Storage system

Abstract

In a storage system, even if the controller's processor or memory stops working due to a failure or other issue, access to data from the host computer is maintained. [Solution] The storage system includes a first processing mode in which a request from a host computer received by a first protocol chip is stored in a first memory included in the same controller as the first protocol chip, and the result of processing the request from the host computer is read from the same first memory; and a second processing mode in which a request from a host computer is stored in a second memory included in a controller different from the first protocol chip, and the response resulting from processing the request from the host computer is read from the second memory.

Description

Technical Field

[0001] The present invention relates to a storage system that stores and outputs data according to requests from a host computer.

Background Art

[0002] In a storage system that is connected to a host computer and stores and outputs data according to requests from the host computer, high reliability and high availability are required to support the processing performed by the host computer. For this reason, in the storage system, in addition to preventing the stored data from being lost due to failures or the like, it is also required to maintain access to the data stored in the storage system from the host computer.

[0003] For example, in Patent Document 1, an individual address conversion unit is provided between a protocol chip and each processor, and even if any one of the processors stops operating, the protocol chip sends the request from the host computer received by the protocol chip to the processor that is still operating, thereby maintaining access to the data from the host computer. An example of a storage system is disclosed. However, in this case, when any one of the processors stops operating, it is necessary to instruct the protocol chip to send the request from the host computer received by the protocol chip to the processor that is still operating. In addition, between each protocol chip and each processor, an individual address conversion unit that converts the address used by each protocol chip into the address used by each processor is required each time, that is, a total of the number of processors is required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] A technology is desired that can maintain access to data from the host computer even if the controller's processor or memory stops working due to a failure, without requiring separate address translation units each time to translate the addresses used by the local router, shared memory, and protocol chip to the addresses used by each processor. [Means for solving the problem]

[0006] One aspect of the present invention is a storage system that connects to a host computer and stores or outputs data in accordance with requests from the host computer, comprising a plurality of controllers, wherein the first controller of the plurality of controllers comprises a first protocol chip connected to the host computer and performing protocol processing for data communication with the host computer, a first processor for controlling the storage system, and a first memory connected to the first processor and storing data necessary for controlling the storage system, wherein the second controller of the plurality of controllers, different from the first controller, comprises a second processor for controlling the storage system, and a second memory connected to the second processor and storing data necessary for controlling the storage system, and the storage system further comprises a mutual address translation unit for mutually converting addresses used by the first processor and addresses used by the second processor, and the processing mode of the storage system is the first The system includes a first processing mode and a second processing mode, wherein in the first processing mode, the first protocol chip stores a request received from the host computer in the first memory, the first processor processes the request from the host computer stored in the first memory and stores the response of the processing result in the first memory, the first protocol chip reads the response of the processing result from the host computer from the first memory and sends the response to the host computer, and in the second processing mode, the first protocol chip stores a request received from the host computer in the second memory through the mutual address translation unit, the second processor processes the request from the host computer stored in the second memory and stores the response of the processing result in the second memory, and the first protocol chip reads the response of the processing result from the host computer from the second memory through the mutual address translation unit and sends it to the host computer. [Effects of the Invention]

[0007] According to the present invention, the protocol chip can process requests from a host computer received by the protocol chip using a second processor and second memory instead of a first processor and first memory, and can continue to respond to requests from the host computer even if the first processor stops processing or the first memory becomes unusable due to a failure. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of a first configuration of the storage system. [Figure 2] Figure 2 shows an example of a processing sequence in which a Read request from the host computer is processed in the first processing mode in an example of the first configuration. [Figure 3] Figure 3 shows an example of a processing sequence in which a Write request from the host computer is processed in the first processing mode in an example of the first configuration. [Figure 4] Figure 4 shows an example of a processing sequence in which a Read request from the host computer is processed in the second processing mode in the first configuration example. [Figure 5] Figure 5 shows an example of a processing sequence in which a Write request from the host computer is processed in the second processing mode in the first configuration example. [Figure 6] Figure 6 shows an example of a second configuration of the storage system. [Figure 7] Figure 7 shows an example of a processing sequence in the second configuration where a Read request from the host computer is processed in the first processing mode. [Figure 8] Figure 8 shows an example of a processing sequence in the second configuration where a Write request from the host computer is processed in the first processing mode. [Figure 9] Figure 9 shows an example of a processing sequence in which a Read request from the host computer is processed in the second processing mode in the second configuration example. [Figure 10] Figure 10 shows an example of a processing sequence in which a Write request from the host computer is processed in the second processing mode in an example of the second configuration. [Figure 11]Figure 11 shows an example of a third configuration of the storage system. [Figure 12] Figure 12 shows an example of a processing sequence in the third configuration where a Read request from the host computer is processed in the first processing mode. [Figure 13] Figure 13 shows an example of a processing sequence in the third configuration where a Write request from the host computer is processed in the first processing mode. [Figure 14] Figure 14 shows an example of a processing sequence in the third configuration where a Read request from the host computer is processed in the second processing mode. [Figure 15] Figure 15 shows an example of a processing sequence in the third configuration where a Write request from the host computer is processed in the second processing mode. [Figure 16] Figure 16 shows an example flowchart of the switching process for switching from the first processing mode to the second processing mode in the second configuration example. [Figure 17] Figure 17 shows an example of the first configuration, illustrating the conversions performed by the memory address translation unit and the mutual address translation unit in the address space. [Figure 18] Figure 18 shows an example flowchart of a switching process in the first configuration example, which switches from the first processing mode to the second processing mode. [Figure 19] Figure 19 is an example flowchart of the process for storing information to notify that a request from the host computer has been interrupted in the first processing mode. [Figure 20] Figure 20 shows an example flowchart of the process for notifying that a request from the host computer has been interrupted in the second processing mode. [Figure 21] Figure 21 shows another example of a processing sequence in the first configuration example, where a Read request from the host computer is processed in the first processing mode. [Figure 22] Figure 22 shows another example of a processing sequence in the first configuration example, where a Write request from the host computer is processed in the first processing mode. [Figure 23] FIG. 23 is another example of a flowchart of a switching process for switching from the first processing mode to the second processing mode in the example of the first configuration. [Figure 24] FIG. 24 is an example of a flowchart for processing requests from the host computer remaining in the first processing mode after switching from the first processing mode to the second processing mode in the example of the first configuration.

MODE FOR CARRYING OUT THE INVENTION

EXAMPLE

[0009] Example 1 will be described with reference to FIGS. 1, 2, 3, 4, 5, 17, and 18.

[0010] FIG. 1 is an example of the configuration of a storage system according to Example 1.

[0011] In FIG. 1, the storage system 1 includes two controllers 110a and 110b, and eight storage devices 107a to 107h.

[0012] Controller 110a includes one protocol chip 101a, a memory address conversion unit 102a, a processor 103a, a memory 104a, a mutual address conversion unit 105a, and a backend switch 106a.

[0013] Controller 110b includes one protocol chip 101b, a memory address conversion unit 102b, a processor 103b, a memory 104b, a mutual address conversion unit 105b, and a backend switch 106b.

[0014] Protocol chips 101a and 101b are connected to a host computer (not shown) and control the data communication protocol between the host computer and the storage system 1. One example of a data communication protocol between the host computer and the storage system 1 is Fibre Channel. Another example of a data communication protocol between the host computer and the storage system 1 is iSCSI (Internet Small Computer System Interface).

[0015] In Figure 1, controllers 110a and 110b are each equipped with one protocol chip 101a and 101b, but the number of protocol chips in a controller is not limited to one and can be arbitrary.

[0016] The memory address translation unit 102a has the function of translating the address of memory 104a, which the protocol chip 101a uses to store requests from the host computer, to an address that points to memory 104b, and also translating the address of memory 104a, which the protocol chip 101a uses to read the response resulting from processing the requests from the host computer, to an address that points to memory 104b.

[0017] Similarly, the memory address translation unit 102b has the function of translating the address of memory 104b, which the protocol chip 101b uses to store requests from the host computer, to an address that points to memory 104a, and also translating the address of memory 104b, which the protocol chip 101b uses to read the response resulting from processing the requests from the host computer, to an address that points to memory 104a.

[0018] In Figure 1, controllers 110a and 110b are each equipped with one memory address translation unit 102a and 102b, but the number of memory address translation units in a controller is not limited to one and can be arbitrary. Furthermore, in Figure 1, memory address translation units 102a and 102b are connected to protocol chips 101a and 101b, respectively, but the number of memory address translation units may be less than the number of protocol chips. If the number of memory address translation units is less than the number of protocol chips, one or more protocol chips may be connected to one memory address translation unit.

[0019] Processors 103a and 103b are connected to memories 104a and 104b, respectively, and control the storage system 1 by executing instruction codes stored in memory 104a or 104b.

[0020] Memory 104a and 104b store instruction codes executed by processors 103a and 103b, respectively, as well as data necessary for executing those instruction codes. They may also temporarily store data sent from the host computer via protocol chip 101a or 101b for storage in memory devices 107a to 107h, or data read from memory devices 107a to 107h and sent to the host computer via protocol chip 101a or 101b.

[0021] In particular, memory 104a or memory 104b stores requests from the host computer, such as data read requests and data write requests to the storage system, which the protocol chip receives from the host computer, and also stores the responses resulting from the processing of requests from the host computer by processor 103a or 103b. An example of memory 104a and 104b is DRAM (Dynamic Random Access Memory).

[0022] In Figure 1, controllers 110a and 110b are each equipped with one processor 103a and 103b, and one memory 104a and 104b, but the number of processors and memory in a controller is not limited to one and can be arbitrary.

[0023] The mutual address translation units 105a and 105b have the function of mutually translating the addresses used by processor 103a and processor 103b. Processor 103a can access any address in memory 104b via the mutual address translation units 105a and 105b. Similarly, processor 103b can access any address in memory 104a via the mutual address translation units 105b and 105a.

[0024] Furthermore, the protocol chip 101a can store requests from the host computer in memory 104b and read responses from memory 104b as a result of processing requests from the host computer, via the memory address translation unit 102a, processor 103a, and mutual address translation units 105a and 105b. Similarly, the protocol chip 101b can store requests from the host computer in memory 104a and read responses from memory 104a as a result of processing requests from the host computer, via the memory address translation unit 102b, processor 103b, and mutual address translation units 105b and 105a.

[0025] In Figure 1, controllers 110a and 110b are each equipped with one mutual address translation unit 105a and 105b, but the number of mutual address translation units in each controller is not limited to one and can be arbitrary. In particular, in Figure 1, mutual address translation units 105a and 105b are provided separately in controllers 110a and 110b, but mutual address translation units 105a and 105b may be combined into a single mutual address translation unit and provided in only one of controllers 110a or 110b.

[0026] The backend switches 106a and 106b connect processors 103a and 103b to eight storage devices 107a to 107h, respectively, and perform switching processing for data communication between processors 103a and 103b and the eight storage devices 107a to 107h according to the data communication protocol between processors 103a and 103b and storage devices 107a to 107h.

[0027] One example of a data communication protocol used between processors 103a and 103b and storage devices 107a to 107h is SAS (Serial Attached Small computer system interface). Another example of a data communication protocol used between processors 103a and 103b and storage devices 107a to 107h is NVMe (Non-Volatile Memory Express). The processing of these data communication protocols may be performed directly by processors 103a and 103b, or a dedicated protocol processing chip (not shown) may be provided between processors 103a and 103b and backend switches 106a and 106b to perform the processing.

[0028] In Figure 1, one backend switch 106a and one 106b are provided in each controller 110a and 110b, but the number of backend switches in a controller is not limited to one and can be arbitrary.

[0029] The storage devices 107a to 107h store and hold the data that the host computer sends to the storage system 1 for storage. One example of storage devices 107a to 107b is an SSD (Solid State Device) that uses flash memory as its memory element. Another example of storage devices 107a to 107b is an HDD (Hard Disk Drive) that uses a magnetic disk as its storage medium. In Figure 1, there are eight storage devices 107a to 107h in the storage system 1, but the number of storage devices is not limited to eight and can be any number.

[0030] An example of address translation by the memory address translation unit 102a or 102b and the mutual address translation unit 105a or 105b will be further explained with reference to Figure 17.

[0031] Figure 17 shows an example of address allocation within controllers 110a and 110b. In the example in Figure 17, within controller 110a, memory 104a has address allocations from 1000(16) (wherein (16) represents a hexadecimal number, and the same applies hereafter) to 4000(16).

[0032] Furthermore, within controller 110a, the memory 104b is allocated an address space of 5000(16) to 9000(16). In this case, since the actual memory 104b resides in controller 110b and not controller 110a, the unit that actually holds the address allocation of 5000(16) to 9000(16) within controller 110a is the mutual address translation unit 105a.

[0033] Similarly, within controller 110b, memory 104b has an address allocation of 1000(16) to 4000(16). Also within controller 110b, memory 104a is allocated an address space of 5000(16) to 9000(16). In this case, since the actual memory 104a is located in controller 110a and not controller 110b, the unit that actually has the address allocation of 5000(16) to 9000(16) within controller 110b is the mutual address translation unit 105b.

[0034] In the example in Figure 17, when the function of the memory address translation unit 102a in the controller 110a to translate the address of memory 104a to the address of memory 104b is enabled, the memory address translation unit 102a translates the access requests for memory 104a addresses 1000(16) to 4000(16) sent from the protocol chip 101a to access requests for memory 104b addresses 5000(16) to 9000(16). The operation of the memory address translation unit 102b in the controller 110b is similar if you read controller 110a as 110b, memory 104a as 104b, and memory address translation unit 102a as 102b.

[0035] Furthermore, when accessing memory 104b from within controller 110a, since the actual memory 104b resides in controller 110a, it is accessed from within controller 110a via the mutual address translation unit 105a. Therefore, when an access request for addresses 5000(16) to 9000(16) is made within controller 110a, the actual access is made to the mutual address translation unit 105a.

[0036] When the mutual address translation unit 105a receives an access request from within the controller 110a for addresses 5000(16) to 9000(16), it translates the addresses 5000(16) to 9000(16) of the access request to addresses 1000(16) to 4000(16) of memory 104b within the controller 110b, and sends the access request to the controller 110b through the mutual address translation unit 105b. In this way, the controller 110a can access memory 104b, which has a physical presence in the controller 110b.

[0037] The same applies when accessing memory 104a, which has a physical location in controller 110a, from within controller 110b; simply replace controller 110a with 110b (and 110b with 110a), memory 104b with 104a, and the mutual address translation unit 105a with 105b (and 105b with 105a).

[0038] In this embodiment, the storage system 1, in the first processing mode, stores Read and Write requests from the host computer received by the protocol chip 101a in memory 104a included in the same controller 110a as the protocol chip 101a, and reads the response resulting from processing the requests from the host computer from memory 104a.

[0039] Furthermore, in the second processing mode, the storage system 1 stores Read and Write requests from the host computer received by the protocol chip 101a in memory 104b, which is included in a controller 110b that is different from the protocol chip 101a, and reads the response resulting from processing the requests from the host computer from the same memory 104b. This operation is illustrated in Figures 2, 3, 4, and 5.

[0040] Figure 2 shows an example of a processing sequence when storage system 1 receives a Read request from the host computer in the first processing mode. In Figure 2, each vertical line indicates the time order of requests and responses sent or received by the part described at the top. Time progresses from top to bottom in the figure (the same applies to Figures 3, 4, and 5 below).

[0041] In Figure 2, when the protocol chip 101a receives a Read request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 102a, specifying the address of memory 104a as the storage destination (201).

[0042] In the first processing mode, by setting the address translation function of the memory address translation unit 102a to disabled, the memory address translation unit 102a sends the request from the host computer, which is sent by the protocol chip 101a and specifies the address of memory 104a as the storage destination, to the processor 103a without performing any address translation.

[0043] The processor 103a stores a request from the host computer, sent from the memory address translation unit 102a, which specifies the address of memory 104a as the storage destination, into memory 104a according to the specified address. This storage process into memory 104a by the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically stores the data into memory 104a according to the specified address.

[0044] Next, processor 103a reads the request from the host computer sent from protocol chip 101a from memory 104a and starts processing it (202). If the request from the host computer read from memory 104a is a Read request, processor 103a determines which of the storage devices 107a to 107h the requested data is located in, generates a data output request for that storage device, storage device 107a in the example of Figure 2, and sends it via backend switch 106a (203).

[0045] The storage device 107a retrieves the requested data from its internal storage element or storage medium and stores it in the memory 104a via the backend switch 106a and processor 103a (204). Furthermore, the storage device 107a generates a data output completion response indicating that the requested data has been correctly stored in the memory 104a and stores it in the memory 104a via the backend switch 106a and processor 103a (205).

[0046] The storage of data from the memory device 107a via the processor 103a, and the storage of the data output completion response into the memory 104a, may be performed by executing some instruction code on the processor 103a, or the processor 103a may be provided with a hardware mechanism that automatically stores the data into the memory 104a.

[0047] Next, processor 103a reads the data output completion response written from memory 107a to memory 104a (206). Processor 103a generates a Read response to send to the host computer according to the read data output completion response and stores it in memory 104a (207). After that, processor 103a generates a response notification to inform protocol chip 101a that the Read response has been stored in memory 104a and sends it to protocol chip 101a via memory address translation unit 102a (208).

[0048] When the protocol chip 101a receives a response notification from the processor 103a, it sends a Read response read request to the memory address translation unit 102a, specifying the address of memory 104a as the read destination. In the first processing mode, by setting the address translation function of the memory address translation unit 102a to be disabled, the memory address translation unit 102a sends the Read response read request sent by the protocol chip 101a, which specifies the address of memory 104a as the read destination, to the processor 103a without address translation (209). When the processor 103a receives the Read response read request from the protocol chip 101a, it reads the Read response from memory 104a (210) and sends it to the protocol chip 101a via the memory address translation unit 102a (211).

[0049] In accordance with the Read response request from the protocol chip 101a, the Read response read from memory 104a by the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically reads from memory 104a.

[0050] When the protocol chip 101a receives a Read response from the processor 103a, it sends a Read data read request to the processor 103a via the memory address translation unit 102a, in accordance with the contents of the response, to retrieve the Read data from the memory 104a (212).

[0051] The processor 103a reads the Read data in accordance with the Read data read request sent (213), and sends the read Read data to the protocol chip 101a via the memory address translation unit 102a (214). This reading of Read data from memory 104a by the processor 103a in accordance with the Read data read request from the protocol chip 101a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically reads from memory 104a. When the protocol chip 101a receives the Read data from the processor 103a, it sends the Read data to a host computer (not shown).

[0052] Figure 3 shows an example of a processing sequence when storage system 1 receives a write request from the host computer in the first processing mode.

[0053] In Figure 3, when the protocol chip 101a receives a Write request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 102a, specifying the address of memory 104a as the storage destination (301). In the first processing mode, by setting the address translation function of the memory address translation unit 102a to be disabled, the memory address translation unit 102a sends the request from the host computer, which is sent by the protocol chip 101a and specifies the address of memory 104a as the storage destination, to the processor 103a without performing any address translation.

[0054] The processor 103a stores a request from the host computer, sent from the memory address translation unit 102a, which specifies the address of memory 104a as the storage destination, into memory 104a according to the specified address. This storage process into memory 104a by the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically stores the data into memory 104a according to the specified address.

[0055] Next, the processor 103a reads the request from the host computer sent from the protocol chip 101a from the memory 104a and starts processing it (302). If the request from the host computer read from the memory 104a is a write request, the processor 103a prepares to receive the write data and sends permission to send the write data to the protocol chip 101a via the memory address translation unit 102a (303).

[0056] Upon receiving permission to send Write data, the protocol chip 101a sends permission to send Write data to the host computer and receives Write data from the host computer. The protocol chip 101a stores the Write data received from the host computer in memory 104a via the memory address translation unit 102a and the processor 103a (304).

[0057] Furthermore, when the protocol chip 101a receives a signal from the host computer indicating the completion of the Write data transmission, it stores the Write data transmission completion in the memory 104a via the memory address translation unit 102a and the processor 103a (305). This process of storing the Write data and the Write data transmission completion in the memory 104a via the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be provided with a hardware mechanism to automatically store the data in the memory 104a.

[0058] Next, processor 103a reads and confirms that the Write data transmission has been completed, which is stored in memory 104a (306). After that, processor 103a reads the Write data from memory 104a (307), and sends it to memory 104b for storage via the mutual address translation units 105a and 105b and processor 103b (308).

[0059] This is to duplicate the write data in memory 104a and memory 104b, so that even if memory 104a or 104b becomes inaccessible due to a failure or power outage, or if processor 103a or 103b stops working, the write data received from the host computer will not be lost.

[0060] Furthermore, the process of storing the write data to memory 104b via processor 103b may be performed by executing some instruction code on processor 103b, or it may be performed by providing processor 103b with a hardware mechanism to automatically store the data in memory 104b.

[0061] Once the processor 103a has finished the process of duplicating the write data, it generates a write response and stores it in memory 104a (309). Subsequently, the processor 103a generates a response notification to inform the protocol chip 101a that the write response has been stored in memory 104a, and sends it to the protocol chip 101a via the memory address translation unit 102a (310).

[0062] When the protocol chip 101a receives a response notification from the processor 103a, it sends a request to read the Write response to the memory address translation unit 102a, specifying the address of memory 104a as the read destination. In the first processing mode, by setting the address translation function of the memory address translation unit 102a to be disabled, the memory address translation unit 102a sends the request to read the Write response sent by the protocol chip 101a, which specifies the address of memory 104a as the read destination, to the processor 103a without address translation (311). When the processor 103a receives the request to read the Write response from the protocol chip 101a, it reads the Write response from memory 104a (312) and sends it to the protocol chip 101a via the memory address translation unit 102a (313).

[0063] The processor 103a's read of the write response from memory 104a in accordance with the write response read request from the protocol chip 101a may be performed by executing some instruction code in the processor 103a, or it may be performed by providing the processor 103a with a hardware mechanism that automatically reads from memory 104a. When the protocol chip 101a receives the write response from the processor 103a, it notifies the host computer that the write process is complete.

[0064] Next, processor 103a determines which storage devices 107a to 107h will store the Write data stored in memory 104a. In Figure 3, it is assumed that processor 103a has decided to store the Write data stored in memory 104a in storage device 107a. Therefore, processor 103a generates a data storage request and sends it to storage device 107a via backend switch 106a (314).

[0065] Upon receiving a data storage request, the storage device 107a sends a request to the processor 103a via the backend switch 106a to read the data of the Write data (315). Upon receiving the data read request, the processor 103a reads the Write data from the memory 104a (316), sends it to the storage device 107a via the backend switch 106a, and stores it (317).

[0066] In response to a data read request for write data from memory device 107a, the processor 103a may read the write data from memory 104a by executing some instruction code, or it may be done by providing the processor 103a with a hardware mechanism that automatically reads the write data from memory 104a in response to a write data read request.

[0067] When the storage device 107a receives write data, it stores the received write data in its internal storage element or storage medium. Once the storage of the write data in its internal storage element or storage medium is complete, the storage device 107a generates a data storage completion response and stores it in the memory 104a via the backend switch 106a and processor 103a (318).

[0068] The process of storing the data storage completion response to memory 104a via processor 103a may be performed by executing some instruction code in processor 103a, or it may be performed by providing processor 103a with a hardware mechanism to automatically store it in memory 104a. Finally, processor 103a reads the data storage completion response from memory 104a and confirms it (319).

[0069] The above describes the operation of the storage system 1 when a Read request or Write request is received from the host computer in the first processing mode, in which requests from the host computer and the responses resulting from processing those requests are stored in memory 104a.

[0070] If memory 104a becomes inaccessible due to a failure or power outage, or if processor 103a stops operating and storage or reading from memory 104a becomes impossible, a second processing mode is applied in which the request from the host computer and the response resulting from processing the request from the host computer are stored in memory 104b instead. By applying the second processing mode, even if memory 104a becomes inaccessible due to a failure or power outage, or if processor 103a stops operating and storage or reading from memory 104a becomes impossible, processing of requests from the host computer can continue.

[0071] Figure 4 shows an example of the processing sequence in storage system 1 when a Read request is received from the host computer, with the second processing mode applied.

[0072] In Figure 4, when the protocol chip 101a receives a Read request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 102a, specifying the address that indicates memory 104a as the storage destination (401). In the second processing mode, by enabling the address translation function of the memory address translation unit 102a, the memory address translation unit 102a translates the address that specifies memory 104a as the storage destination in the request from the host computer sent by the protocol chip 101a to an address that specifies memory 104b, and sends it to the processor 103a.

[0073] Processor 103a receives a request from the host computer, sent from the memory address translation unit 102a, which specifies the address of memory 104b as the storage destination. The request is then stored in memory 104b according to the specified address, via the mutual address translation units 105a and 105b, and processor 103b.

[0074] In the second processing mode, the processor 103a processes a request from a host computer, specifying the address of memory 104b as the storage destination, and stores it in memory 104b via the mutual address translation units 105a, 105b, and processor 103b according to the specified address. However, even if processor 103a has stopped processing requests from the host computer, this process can be carried out by providing processor 103a with a hardware mechanism that automatically sends the request to the mutual address translation unit 105a according to the specified address.

[0075] Next, processor 103b reads the request from the host computer sent from protocol chip 101a from memory 104b and begins processing it (402). If the request from the host computer read from memory 104b is a Read request, processor 103b determines which of the storage devices 107a to 107h the requested data is located in, generates a data output request for that storage device, storage device 107a in the example of Figure 4, and sends it via backend switch 106b (403).

[0076] The storage device 107a retrieves the requested data from its internal storage element or storage medium and stores it in the memory 104b via the backend switch 106b and processor 103b (404). Furthermore, the storage device 107a generates a data output completion response indicating that the requested data has been correctly stored in the memory 104b and stores it in the memory 104b via the backend switch 106b and processor 103b (405).

[0077] The storage of data from the memory device 107a via the processor 103b, and the storage of the data output completion response into the memory 104b, may be performed by executing some instruction code in the processor 103b, or the processor 103b may be provided with a hardware mechanism that automatically stores the data into the memory 104b.

[0078] Next, processor 103b reads the data output completion response written from memory 107a to memory 104b (406). Processor 103b generates a Read response to send to the host computer according to the read data output completion response and stores it in memory 104b (407).

[0079] Subsequently, processor 103b generates a response notification informing protocol chip 101a that the Read response has been stored in memory 104b, and sends it to protocol chip 101a via mutual address translation units 105b, 105a, processor 103a, and memory address translation unit 102a (408).

[0080] When the protocol chip 101a receives a response notification from the processor 103b, it sends a Read response read request to the memory address translation unit 102a, specifying the address that points to memory 104a as the read destination. In the second processing mode, by enabling the address translation function of the memory address translation unit 102a, the memory address translation unit 102a translates the address that specifies memory 104a as the read destination in the Read response read request sent by the protocol chip 101a to an address that specifies memory 104b, and sends it to the processor 103a.

[0081] Processor 103a sends a read request, a Read response sent from memory address translation unit 102a, which specifies the address of memory 104b as the read destination, to processor 103b via mutual address translation units 105a and 105b according to the specified address (409).

[0082] When processor 103b receives a Read response request from protocol chip 101a, it reads the Read response from memory 104b (410) and sends it to protocol chip 101a via mutual address translation units 105b, 105a, processor 103a, and memory address translation unit 102a (411). This reading of the Read response from memory 104b by processor 103b in accordance with the Read response request from protocol chip 101a may be performed by having processor 103b execute some instruction code, or it may be performed by providing processor 103b with a hardware mechanism that automatically reads from memory 104b.

[0083] When the protocol chip 101a receives a Read response from the processor 103b, it sends a Read data read request to the processor 103b via the memory address translation unit 102a, the processor 103a, the mutual address translation units 105a and 105b, in accordance with the contents of the response (412).

[0084] The processor 103b reads the Read data in accordance with the received Read data read request (413), and sends the read Read data to the protocol chip 101a via the mutual address translation units 105b and 105a, the processor 103a, and the memory address translation unit 102a (414).

[0085] In accordance with the Read data read request from the protocol chip 101a, the processor 103b may read the Read data from memory 104b by executing some instruction code in the processor 103b, or it may be done by providing the processor 103b with a hardware mechanism that automatically reads from memory 104b. When the protocol chip 101a receives the Read data from the processor 103b, it sends the Read data to a host computer (not shown).

[0086] Figure 5 shows an example of the processing sequence when storage system 1 receives a write request from the host computer in the second processing mode.

[0087] In Figure 5, when the protocol chip 101a receives a Write request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 102a, specifying the address that indicates memory 104a as the storage destination (501). In the second processing mode, by enabling the address translation function of the memory address translation unit 102a, the memory address translation unit 102a translates the address that specifies memory 104a as the storage destination in the request from the host computer sent by the protocol chip 101a to an address that specifies memory 104b, and sends it to the processor 103a.

[0088] Processor 103a receives a request from the host computer, sent from the memory address translation unit 102a, which specifies the address of memory 104b as the storage destination. The request is then stored in memory 104b according to the specified address, via the mutual address translation units 105a and 105b, and processor 103b.

[0089] In the second processing mode, the processor 103a processes a request from a host computer, specifying the address of memory 104b as the storage destination, and stores it in memory 104b via the mutual address translation units 105a, 105b, and processor 103b according to the specified address. However, even if processor 103a has stopped processing requests from the host computer, this process can be carried out by providing processor 103a with a hardware mechanism that automatically sends the request to the mutual address translation unit 105a according to the specified address.

[0090] Next, processor 103b reads the request from the host computer sent from protocol chip 101a from memory 104b and starts processing it (502). If the request from the host computer read from memory 104b is a write request, processor 103b prepares to receive the write data and sends permission to send the write data to protocol chip 101a via mutual address translation units 105b, 105a, processor 103a, and memory address translation unit 102a (503).

[0091] Upon receiving permission to send Write data, the protocol chip 101a sends permission to send Write data to the host computer and receives Write data from the host computer. The protocol chip 101a stores the Write data received from the host computer in memory 104b via the memory address translation unit 102a, processor 103a, mutual address translation units 105a and 105b, and processor 103b (504).

[0092] Furthermore, when the protocol chip 101a receives a signal from the host computer indicating the completion of the Write data transmission, it stores the Write data transmission completion in memory 104b via the memory address translation unit 102a, processor 103a, mutual address translation units 105a and 105b, and processor 103b (505). This process of storing the Write data and the Write data transmission completion in memory 104b via processor 103b may be performed by executing some instruction code in processor 103b, or it may be performed by providing processor 103b with a hardware mechanism to automatically store it in memory 104b.

[0093] Next, processor 103b reads and confirms that the Write data transmission has been completed, which is stored in memory 104b (506). Then, in the second processing mode, unlike in the first processing mode, the Write data is not duplicated in memory 104a and memory 104b, taking into account the possibility that memory 104a may be inaccessible due to a failure or other reason. Instead, the Write data is stored directly in one of the storage devices 107a to 107h, and a Write response is returned to the host computer.

[0094] Specifically, the next step is for the processor 103b to determine which storage devices 107a to 107h will store the Write data stored in memory 104b. In Figure 5, it is assumed that the processor 103b has decided to store the Write data stored in memory 104b in storage device 107a. Therefore, the processor 103b generates a data storage request and sends it to storage device 107a via the backend switch 106b (507).

[0095] Upon receiving a data storage request, the storage device 107a sends a request to the processor 103b via the backend switch 106b to read the data of the Write data (508). Upon receiving the data read request, the processor 103b reads the Write data from the memory 104b (509) and sends it to the storage device 107a via the backend switch 106b for storage (510).

[0096] In response to a data read request for write data from memory device 107a, the processor 103b may read the write data from memory 104b by executing some instruction code, or the processor 103b may be provided with a hardware mechanism that automatically reads the write data from memory 104b in response to a write data read request.

[0097] When the storage device 107a receives write data, it stores the received write data in its internal storage element or storage medium. Once the storage of the write data in its internal storage element or storage medium is complete, the storage device 107a generates a data storage completion response and stores it in the memory 104b via the backend switch 106b and processor 103b (511).

[0098] The process of storing the data storage completion response to memory 104b via processor 103b may be performed by executing some instruction code on processor 103b, or it may be performed by providing processor 103b with a hardware mechanism to automatically store it in memory 104b.

[0099] Subsequently, processor 103b reads and confirms the data storage completion response from memory 104b (512). After confirming the data storage completion response, processor 103b generates a Write response and stores it in memory 104b (513). Then, processor 103b generates a response notification to inform protocol chip 101a that the Write response has been stored in memory 104b, and sends it to protocol chip 101a via mutual address translation units 105b, 105a, processor 103a, and memory address translation unit 102a (514).

[0100] When the protocol chip 101a receives a response notification from the processor 103b, it sends a read request for the write response to the memory address translation unit 102a, specifying the address that points to memory 104a as the read destination. In the second processing mode, by enabling the address translation function of the memory address translation unit 102a, the memory address translation unit 102a translates the address that specifies memory 104a as the read destination in the read request for the write response sent by the protocol chip 101a to an address that specifies memory 104b, and sends it to the processor 103a.

[0101] Processor 103a sends a read request, a Write response sent from memory address translation unit 102a, which specifies the address of memory 104b as the read destination, to processor 103b via mutual address translation units 105a and 105b according to the specified address (515).

[0102] When processor 103b receives a write response read request from protocol chip 101a, it reads the write response from memory 104b (516) and sends it to protocol chip 101a via mutual address translation units 105b, 105a, processor 103a, and memory address translation unit 102a (517).

[0103] In accordance with the Write response read request from the protocol chip 101a, the processor 103b may read the Write response from memory 104b by executing some instruction code, or it may be done by providing the processor 103b with a hardware mechanism that automatically reads from memory 104b. When the protocol chip 101a receives the Write response from the processor 103b, it notifies the host computer that the Write process is complete.

[0104] The above describes the operation of the storage system 1 when a Read request or Write request is received from the host computer in the second processing mode, in which requests from the host computer and the responses resulting from processing those requests are stored in memory 104b. By applying the second processing mode, even if memory 104a becomes inaccessible due to a failure or power outage, or if processor 103a stops operating and storage to or reading from memory 104a becomes impossible, the processing of requests from the host computer can continue.

[0105] Next, using Figure 18, we will explain an example of the process of switching from the first processing mode to the second processing mode in Example 1.

[0106] Figure 18 shows an example of a process in Embodiment 1 where the protocol chip stores Read and Write requests received from the host computer in memory included in the same controller as the protocol chip, and reads the response resulting from processing the requests from the host computer from the same memory included in the same controller as the protocol chip. The second processing mode is where the protocol chip stores Read and Write requests received from the host computer in memory included in a controller different from the protocol chip, and reads the response resulting from processing the requests from the host computer from the same memory included in the controller different from the protocol chip.

[0107] In Figure 18 below, the storage system 1 is initially in a first processing mode. Requests from the host computer received by the protocol chip 101a are stored in memory 104a, which is included in the same controller 110a as the protocol chip 101a. The response resulting from processing the request from the host computer is also read from memory 104a. For this reason, the protocol chip 101a is configured with an address indicating memory 104a as the storage location for requests from the host computer and the reading location for the response resulting from processing the request from the host computer.

[0108] In Figure 18, when the storage system 1 is in the first processing mode, the processor 103b included in a controller 110b different from the protocol chip 101a periodically obtains the state of the processor 103a included in the same controller 110a as the protocol chip 101a (step 1801).

[0109] Next, in step 1802, processor 103b determines whether processor 103a is stopped. This stopping of processor 103a includes cases where the memory 104a connected to processor 103a has become inaccessible due to a failure or other reason. If the determination shows that processor 103a is operating normally and is not stopped, the process returns to step 1801, and processor 103b periodically acquires the status of processor 103a again, and the determination in step 1802 is repeated.

[0110] If the determination shows that processor 103a is stopped, the process proceeds to step 1803, where processor 103b enables the address translation function of memory address translation unit 102a. By enabling the address translation function of memory address translation unit 102a, the memory address translation unit 102a translates the address indicating memory 104a, which the protocol chip 101a designates as the storage location for requests from the host computer and the reading location for the results of processing those requests, to point to memory 104b of controller 110b, which is different from that of protocol chip 101a.

[0111] As a result, the storage system 1 switches from a first processing mode, where the storage location for requests received from the host computer by the protocol chip 101a and the reading location for responses resulting from processing those requests are the memory 104a of the same controller 110a as the protocol chip 101a, to a second processing mode, where the memory 104b of a different controller 110b is used instead.

[0112] The setting signal to enable the address translation function of the memory address translation unit 102a may be sent from the processor 103b to the memory address translation unit 102a via the mutual address translation units 105b, 105a and processor 103a as shown in Figure 1, or a dedicated signal line may be provided specifically for this purpose between the processor 103b and the memory address translation unit 102a.

[0113] Next, in step 1804, the processor 103b starts processing the request from the host computer that the protocol chip 101a stores in memory 104b, and stores the response resulting from processing the request from the host computer in memory 104b.

[0114] As a result, the system can switch from a first processing mode, in which the protocol chip stores Read and Write requests received from the host computer in memory included in the same controller as the protocol chip, and reads the response resulting from processing the requests from the host computer from the same memory included in the same controller, to a second processing mode, in which the protocol chip stores Read and Write requests received from the host computer in memory included in a controller different from the protocol chip, and reads the response resulting from processing the requests from the host computer from the same memory included in the controller different from the protocol chip.

[0115] As a result, even if the memory in the same controller as the protocol chip becomes inaccessible due to a failure or other reason, or if the processor in the same controller as the protocol chip stops operating as a result, the requests from the host computer can be stored in the memory in a controller different from the protocol chip, and the response resulting from processing the requests from the host computer can be read from the memory in the same controller different from the protocol chip, thus allowing the processing of requests from the host computer to continue. [Examples]

[0116] Next, Example 2 will be described using Figures 6, 7, 8, 9, 10, and 16.

[0117] Figure 6 shows an example of the storage system configuration according to Example 2.

[0118] In Figure 6, the configuration is different from the example storage system configuration shown in Figure 1, with the memory address translation units 102a and 102b removed. Instead, the protocol chips 112a and 112b have translation functionality; in other words, the memory address translation units are included in the protocol chips 112a and 112b, respectively.

[0119] Specifically, the controller 111a comprises a protocol chip (with conversion function) 112a, a processor 103a, memory 104a, a mutual address translation unit 105a, and a backend switch 106a.

[0120] The controller 111b comprises a single protocol chip (with translation function) 112b, a processor 103b, memory 104b, a mutual address translation unit 105b, and a backend switch 106b.

[0121] The protocol chips (with conversion function) 112a and 112b are each connected to a host computer (not shown) and control the protocol for data communication between the host computer and the storage system 2. Furthermore, the protocol chips (with conversion function) 112a and 112b have the function of converting (switching) whether the storage of requests from the host computer and the reading of responses resulting from processing the requests from the host computer are performed by specifying an address that points to memory 104a or an address that points to memory 104b, as set by the processor 103a or 103b. In Figure 6, controllers 111a and 111b are each equipped with one protocol chip (with conversion function) 112a and 112b, but the number of protocol chips (with conversion function) in a controller is not limited to one and can be arbitrary.

[0122] The processors 103a and 103b, memories 104a and 104b, mutual address translation units 105a and 105b, backend switches 106a and 106b, and storage devices 107a to 107h are the same as those in Embodiment 1 shown in Figure 1.

[0123] In this embodiment, the storage system 2, in the first processing mode, stores Read and Write requests from the host computer received by the protocol chip (with conversion function) 112a in memory 104a included in the same controller 111a as the protocol chip (with conversion function) 112a, and reads the response resulting from processing the request from the host computer from memory 104a.

[0124] Furthermore, in the second processing mode, the storage system 2 stores Read and Write requests from the host computer received by the protocol chip (with conversion function) 112a in memory 104b included in a controller 111b that is different from the protocol chip (with conversion function) 112a, and reads the response resulting from processing the requests from the host computer from the same memory 104b. This operation is explained in Figures 7, 8, 9, and 10.

[0125] Figure 7 shows an example of the processing sequence when storage system 2 receives a Read request from the host computer in the first processing mode. In Figure 7, each vertical line indicates the time order of requests and responses sent or received by the part described at the top. Time progresses from top to bottom in the figure (the same applies to Figures 8, 9, and 10 below).

[0126] In Figure 7, when the protocol chip (with conversion function) 112a receives a Read request from a host computer (not shown), it sends the request from the host computer to the processor 103a, specifying the address that points to memory 104a as the storage destination (701). In the first processing mode, the protocol chip (with conversion function) 112a specifies the address that points to memory 104a as the storage destination for the request from the host computer.

[0127] The processor 103a stores a request from a host computer, sent from the protocol chip (with conversion function) 112a, which specifies the address of memory 104a as the storage destination, into memory 104a according to the specified address. This storage process into memory 104a by the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically stores the data into memory 104a according to the specified address.

[0128] Next, processor 103a reads a request from the host computer sent from protocol chip (with conversion function) 112a from memory 104a and starts processing it (702). If the request from the host computer read from memory 104a is a Read request, processor 103a determines which of the storage devices 107a to 107h the requested data is located in, generates a data output request for that storage device, storage device 107a in the example of Figure 7, and sends it via backend switch 106a (703).

[0129] The storage device 107a retrieves the requested data from its internal storage element or storage medium and stores it in the memory 104a via the backend switch 106a and processor 103a (704). Furthermore, the storage device 107a generates a data output completion response indicating that the requested data has been correctly stored in the memory 104a and stores it in the memory 104a via the backend switch 106a and processor 103a (705).

[0130] The storage of data from the memory device 107a via the processor 103a, and the storage of the data output completion response into the memory 104a, may be performed by executing some instruction code on the processor 103a, or the processor 103a may be provided with a hardware mechanism that automatically stores the data into the memory 104a.

[0131] Next, the processor 103a reads the data output completion response written from the storage device 107a to the memory 104a (706). The processor 103a generates a Read response to send to the host computer according to the read data output completion response and stores it in the memory 104a (707). After that, the processor 103a sends a response notification to the protocol chip (with conversion function) 112a informing it that the Read response has been stored in the memory 104a (708).

[0132] When the protocol chip (with conversion function) 112a receives a response notification from the processor 103a, it sends a read request for a Read response to the processor 103a, specifying the address of the memory 104a (709).

[0133] In the first processing mode, the protocol chip (with conversion function) 112a specifies an address indicating memory 104a as the destination for reading the Read response. When the processor 103a receives a Read response read request from the protocol chip (with conversion function) 112a, it reads the Read response from memory 104a (710) and sends it to the protocol chip (with conversion function) 112a (711).

[0134] In accordance with the Read response request from the protocol chip (with conversion function) 112a, the Read response read from memory 104a by the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically reads from memory 104a.

[0135] When the protocol chip (with conversion function) 112a receives a Read response from the processor 103a, it sends a Read data read request to the processor 103a to retrieve the Read data from the memory 104a according to the content of the response (712). The processor 103a reads the Read data according to the sent Read data read request (713) and sends the read Read data to the protocol chip (with conversion function) 112a (714).

[0136] In accordance with the Read data read request from the protocol chip (with conversion function) 112a, the processor 103a may read the Read data from memory 104a by executing some instruction code, or it may be done by providing the processor 103a with a hardware mechanism that automatically reads from memory 104a. When the protocol chip (with conversion function) 112a receives the Read data from the processor 103a, it sends the Read data to a host computer (not shown).

[0137] Figure 8 shows an example of the processing sequence when the storage system 2 receives a Write request from the host computer in the first processing mode.

[0138] In Figure 8, when the protocol chip (with conversion function) 112a receives a Write request from a host computer (not shown), it sends the request from the host computer to the processor 103a, specifying the address that points to memory 104a as the storage destination (801). In the first processing mode, the protocol chip (with conversion function) 112a specifies the address that points to memory 104a as the storage destination for the request from the host computer.

[0139] The processor 103a stores a request from a host computer, sent from the protocol chip (with conversion function) 112a, which specifies the address of memory 104a as the storage destination, into memory 104a according to the specified address. This storage process into memory 104a by the processor 103a may be performed by executing some instruction code in the processor 103a, or the processor 103a may be equipped with a hardware mechanism that automatically stores the data into memory 104a according to the specified address.

[0140] Next, processor 103a reads a request from the host computer sent from protocol chip (with conversion function) 112a from memory 104a and begins processing it (802). If the request from the host computer read from memory 104a is a write request, processor 103a prepares to receive the write data and sends permission to send the write data to protocol chip (with conversion function) 112a (803).

[0141] Upon receiving permission to send Write data, the protocol chip (with conversion function) 112a sends permission to send Write data to the host computer and receives Write data from the host computer. The protocol chip (with conversion function) 112a stores the Write data received from the host computer in memory 104a via processor 103a (804).

[0142] Furthermore, when the protocol chip (with conversion function) 112a receives a signal from the host computer indicating the completion of the Write data transmission, it stores the Write data transmission completion information in the memory 104a, also via the processor 103a (805). This process of storing the Write data and the Write data transmission completion information in the memory 104a via the processor 103a may be performed by executing some instruction code on the processor 103a, or the processor 103a may be provided with a hardware mechanism to automatically store the information in the memory 104a.

[0143] Next, processor 103a reads and confirms that the Write data transmission has been completed, which is stored in memory 104a (806). Then, processor 103a reads the Write data from memory 104a (807), and sends it to memory 104b for storage via the mutual address translation units 105a and 105b and processor 103b (808).

[0144] This is to duplicate the write data in memory 104a and memory 104b, so that even if memory 104a or 104b becomes inaccessible due to a failure or power outage, or if processor 103a or 103b stops working, the write data received from the host computer will not be lost.

[0145] Furthermore, the process of storing the write data to memory 104b via processor 103b may be performed by executing some instruction code on processor 103b, or it may be performed by providing processor 103b with a hardware mechanism to automatically store the data in memory 104b.

[0146] Once the processor 103a has finished the process of duplicating the write data, it generates a write response and stores it in memory 104a (809). Subsequently, the processor 103a sends a response notification to the protocol chip (with conversion function) 112a informing it that the write response has been stored in memory 104a (810).

[0147] When the protocol chip (with conversion function) 112a receives a response notification from the processor 103a, it sends a request to the processor 103a to read the Write response, specifying the address of memory 104a (811). In the first processing mode, the protocol chip (with conversion function) 112a specifies the address of memory 104a as the destination for reading the Write response.

[0148] When processor 103a receives a Write response read request from protocol chip 101a, it reads the Write response from memory 104a (812) and sends it to protocol chip (with conversion function) 112a (813). This reading of the Write response from memory 104a by processor 103a in accordance with the Write response read request from protocol chip (with conversion function) 112a may be performed by having processor 103a execute some instruction code, or it may be performed by providing processor 103a with a hardware mechanism that automatically reads from memory 104a.

[0149] When the protocol chip (with conversion function) 112a receives a write response from the processor 103a, it notifies the host computer that the write process is complete.

[0150] Next, processor 103a determines which storage devices 107a to 107h will store the Write data stored in memory 104a. In Figure 8, it is assumed that processor 103a has decided to store the Write data stored in memory 104a in storage device 107a. Therefore, processor 103a generates a data storage request and sends it to storage device 107a via backend switch 106a (814).

[0151] Upon receiving a data storage request, the storage device 107a sends a request to the processor 103a via the backend switch 106a to read the data of the Write data (815). Upon receiving the data read request, the processor 103a reads the Write data from the memory 104a (816), sends it to the storage device 107a via the backend switch 106a for storage (817).

[0152] In response to a data read request for write data from memory device 107a, the processor 103a may read the write data from memory 104a by executing some instruction code, or it may be done by providing the processor 103a with a hardware mechanism that automatically reads the write data from memory 104a in response to a write data read request.

[0153] When the storage device 107a receives write data, it stores the received write data in its internal storage element or storage medium. Once the storage of the write data in its internal storage element or storage medium is complete, the storage device 107a generates a data storage completion response and stores it in the memory 104a via the backend switch 106a and processor 103a (818).

[0154] The process of storing the data storage completion response to memory 104a via processor 103a may be performed by executing some instruction code in processor 103a, or it may be performed by providing processor 103a with a hardware mechanism to automatically store it in memory 104a. Finally, processor 103a reads the data storage completion response from memory 104a and confirms it (819).

[0155] The above describes the operation of the storage system 2 when a Read request or Write request is received from the host computer in the first processing mode, in which requests from the host computer and the responses resulting from processing those requests are stored in memory 104a.

[0156] If memory 104a becomes inaccessible due to a failure or power outage, or if processor 103a stops operating and storage or reading from memory 104a becomes impossible, a second processing mode is applied in which the request from the host computer and the response resulting from processing the request from the host computer are stored in memory 104b instead. By applying the second processing mode, even if memory 104a becomes inaccessible due to a failure or power outage, or if processor 103a stops operating and storage or reading from memory 104a becomes impossible, processing of requests from the host computer can continue.

[0157] Figure 9 shows an example of the processing sequence in storage system 2 when a Read request is received from the host computer, with the second processing mode applied.

[0158] In Figure 9, when the protocol chip (with conversion function) 112a receives a Read request from a host computer (not shown), it sends the request from the host computer to the processor 103a, specifying the address that points to memory 104b as the storage destination (901). In the second processing mode, the protocol chip (with conversion function) 112a specifies the address that points to memory 104b as the storage destination for the request from the host computer.

[0159] The processor 103a receives a request from the host computer, which has been sent from the protocol chip (with conversion function) 112a and has specified the address of memory 104b as the storage destination, and stores it in memory 104b according to the specified address, via the mutual address translation units 105a, 105b, and processor 103b.

[0160] In the second processing mode, the processor 103a processes a request from a host computer, specifying the address of memory 104b as the storage destination, and stores it in memory 104b via the mutual address translation units 105a, 105b, and processor 103b according to the specified address. However, even if processor 103a has stopped processing requests from the host computer, this process can be carried out by providing processor 103a with a hardware mechanism that automatically sends the request to the mutual address translation unit 105a according to the specified address.

[0161] Next, processor 103b reads a request from the host computer sent from protocol chip (with conversion function) 112a from memory 104b and begins processing it (902). If the request from the host computer read from memory 104b is a Read request, processor 103b determines which of the storage devices 107a to 107h the requested data is located in, generates a data output request for that storage device, storage device 107a in the example of Figure 9, and sends it via backend switch 106b (903).

[0162] The storage device 107a retrieves the requested data from its internal storage element or storage medium and stores it in the memory 104b via the backend switch 106b and processor 103b (904). Furthermore, the storage device 107a generates a data output completion response indicating that the requested data has been correctly stored in the memory 104b and stores it in the memory 104b via the backend switch 106b and processor 103b (905).

[0163] The storage of data from the memory device 107a via the processor 103b, and the storage of the data output completion response into the memory 104b, may be performed by executing some instruction code in the processor 103b, or the processor 103b may be provided with a hardware mechanism that automatically stores the data into the memory 104b.

[0164] Next, processor 103b reads the data output completion response written from memory 107a to memory 104b (906). Processor 103b generates a Read response to send to the host computer according to the read data output completion response and stores it in memory 104b (907). After that, processor 103b generates a response notification to inform protocol chip (with conversion function) 112a that the Read response has been stored in memory 104b and sends it to protocol chip (with conversion function) 112a via mutual address translation units 105b, 105a and processor 103a (908).

[0165] When the protocol chip (with conversion function) 112a receives a response notification from the processor 103b, it sends a read request for the Read response to the processor 103a, specifying the address that points to memory 104b as the read destination. In the second processing mode, the protocol chip (with conversion function) 112a specifies the address that points to memory 104b as the read destination for the Read response.

[0166] Processor 103a sends a read request, a Read response sent from memory address translation unit 102a, which specifies the address of memory 104b as the read destination, to processor 103b via mutual address translation units 105a and 105b according to the specified address (909).

[0167] When processor 103b receives a Read response request from protocol chip (with conversion function) 112a, it reads the Read response from memory 104b (910) and sends it to protocol chip (with conversion function) 112a via mutual address translation units 105b, 105a, and processor 103a (911).

[0168] In accordance with the Read response request from the protocol chip (with conversion function) 112a, the Read response read from memory 104b by the processor 103b may be performed by executing some instruction code on the processor 103b, or the processor 103b may be provided with a hardware mechanism that automatically reads from memory 104b.

[0169] When the protocol chip (with conversion function) 112a receives a Read response from the processor 103b, it sends a Read data read request to the processor 103b via the processor 103a, the mutual address translation unit 105a, and 105b, in accordance with the contents of the response (912).

[0170] The processor 103b reads the Read data in accordance with the received Read data read request (913), and sends the read Read data to the protocol chip (with conversion function) 112a via the mutual address translation units 105b and 105a, and the processor 103a (914).

[0171] In accordance with the Read data read request from the protocol chip (with conversion function) 112a, the processor 103b may read the Read data from memory 104b by executing some instruction code on the processor 103b, or the processor 103b may be equipped with a hardware mechanism to automatically read from memory 104b. When the protocol chip (with conversion function) 112a receives the Read data from the processor 103b, it sends the Read data to a host computer (not shown).

[0172] Figure 10 shows an example of a processing sequence when the storage system 2 receives a Write request from the host computer in the second processing mode.

[0173] In Figure 10, when the protocol chip (with conversion function) 112a receives a Write request from a host computer (not shown), it sends the request from the host computer to the processor 103a, specifying the address that points to memory 104b as the storage destination (1001). In the second processing mode, the protocol chip (with conversion function) 112a specifies the address that points to memory 104b as the storage destination for the request from the host computer.

[0174] The processor 103a receives a request from the host computer, which has been sent from the protocol chip (with conversion function) 112a and has specified the address of memory 104b as the storage destination, and stores it in memory 104b according to the specified address, via the mutual address translation units 105a, 105b, and processor 103b.

[0175] In the second processing mode, the processor 103a processes a request from a host computer, specifying the address of memory 104b as the storage destination, and stores it in memory 104b via the mutual address translation units 105a, 105b, and processor 103b according to the specified address. However, even if processor 103a has stopped processing requests from the host computer, this process can be carried out by providing processor 103a with a hardware mechanism that automatically sends the request to the mutual address translation unit 105a according to the specified address.

[0176] Next, the processor 103b reads a request from the host computer sent from the protocol chip (with conversion function) 112a from the memory 104b and begins processing it (1002). If the request from the host computer read from the memory 104b is a Write request, the processor 103b prepares to receive the Write data and sends permission to send the Write data to the protocol chip (with conversion function) 112a via the mutual address translation units 105b, 105a, and the processor 103a (1003).

[0177] Upon receiving permission to send Write data, the protocol chip (with conversion function) 112a sends permission to send Write data to the host computer and receives Write data from the host computer. The protocol chip (with conversion function) 112a stores the Write data received from the host computer in memory 104b via processor 103a, mutual address translation units 105a and 105b, and processor 103b (1004).

[0178] Furthermore, when the protocol chip (with conversion function) 112a receives a signal from the host computer indicating the completion of the Write data transmission, it stores the completion of the Write data transmission in memory 104b via processor 103a, mutual address translation units 105a and 105b, and processor 103b (1005).

[0179] The process of writing data to memory 104b via processor 103b and storing the completion of the write data transmission may be performed by executing some instruction code on processor 103b, or it may be performed by providing processor 103b with a hardware mechanism to automatically store the data in memory 104b.

[0180] Next, processor 103b reads and confirms that the Write data transmission has been completed, which is stored in memory 104b (1006). Subsequently, in the second processing mode, unlike in the first processing mode, the Write data is not duplicated in memory 104a and memory 104b, taking into account the possibility that memory 104a may be inaccessible due to a failure or other reason.

[0181] Instead, the Write data is stored directly in one of the memory devices 107a to 107h, and a Write response is returned to the host computer. That is, the processor 103b then decides which memory device 107a to 107h to store the Write data stored in memory 104b. In Figure 10, it is assumed that the processor 103b has decided to store the Write data stored in memory 104b in memory device 107a.

[0182] Therefore, the processor 103b generates a data storage request and sends it to the storage device 107a via the backend switch 106b (1007). The storage device 107a, having received the data storage request, sends a request to read the data of the written data to the processor 103b via the backend switch 106b (1008).

[0183] Upon receiving a data read request, processor 103b reads the write data from memory 104b (1009), sends it to storage device 107a via backend switch 106b, and stores it (1010).

[0184] In response to a data read request for write data from memory device 107a, the processor 103b may read the write data from memory 104b by executing some instruction code, or the processor 103b may be provided with a hardware mechanism that automatically reads the write data from memory 104b in response to a write data read request.

[0185] When the storage device 107a receives write data, it stores the received write data in its internal storage element or storage medium. Once the storage of the write data in its internal storage element or storage medium is complete, the storage device 107a generates a data storage completion response and stores it in the memory 104b via the backend switch 106b and processor 103b (1011).

[0186] The process of storing the data storage completion response to memory 104b via processor 103b may be performed by executing some instruction code on processor 103b, or it may be performed by providing processor 103b with a hardware mechanism to automatically store it in memory 104b.

[0187] Subsequently, processor 103b reads and confirms the data storage completion response from memory 104b (1012). After confirming the data storage completion response, processor 103b generates a Write response and stores it in memory 104b (1013). Then, processor 103b generates a response notification to inform protocol chip (with conversion function) 112a that the Write response has been stored in memory 104b, and sends it to protocol chip (with conversion function) 112a via mutual address translation units 105b, 105a, and processor 103a (1014).

[0188] When the protocol chip (with conversion function) 112a receives a response notification from the processor 103b, it sends a request to the processor 103a to read the write response, specifying the address of memory 104b as the read destination. In the second processing mode, the protocol chip (with conversion function) 112a specifies the address of memory 104b as the read destination for the write response.

[0189] The processor 103a sends a read request, a Write response sent from the protocol chip (with conversion function) 112a, which specifies the address of memory 104b as the read destination, to the processor 103b via the mutual address conversion units 105a and 105b according to the specified address (1015).

[0190] When processor 103b receives a Write response read request from protocol chip (with conversion function) 112a, it reads the Write response from memory 104b (1016) and sends it to protocol chip (with conversion function) 112a via mutual address translation units 105b, 105a, and processor 103a (1017).

[0191] In accordance with the Write response read request from the protocol chip (with conversion function) 112a, the processor 103b may perform the Write response read from memory 104b by executing some instruction code, or it may be performed by providing the processor 103b with a hardware mechanism that automatically reads from memory 104b.

[0192] When the protocol chip (with conversion function) 112a receives a write response from the processor 103b, it notifies the host computer that the write process is complete.

[0193] The above describes the operation of the storage system 2 when a Read request or Write request is received from the host computer in the second processing mode, in which requests from the host computer and the responses resulting from processing those requests are stored in memory 104b. By applying the second processing mode, even if memory 104a becomes inaccessible due to a failure or power outage, or if processor 103a stops operating and storage to or reading from memory 104a becomes impossible, the processing of requests from the host computer can continue.

[0194] Next, using Figure 16, we will explain an example of the process of switching from the first processing mode to the second processing mode in Example 2.

[0195] Figure 16 shows an example of a process in Embodiment 2 of the present invention, which switches from a first processing mode in which Read and Write requests received from a host computer by the protocol chip are stored in memory included in the same controller as the protocol chip, and the response resulting from processing the requests from the host computer is read from the same memory included in the same controller as the protocol chip, to a second processing mode in which Read and Write requests received from a host computer by the protocol chip are stored in memory included in a controller different from the protocol chip, and the response resulting from processing the requests from the host computer is read from the same memory included in a controller different from the protocol chip.

[0196] In Example 2, the destination for requests from the host computer is set in the protocol chip (with conversion function) 112. However, if the destination for requests is changed while the protocol chip (with conversion function) 112 is in the process of storing requests from the host computer, a malfunction may occur. Alternatively, to avoid such a malfunction, the protocol chip (with conversion function) 112 could be designed not to accept changes to the destination for requests from the host computer while it is in the process of storing requests from the host computer.

[0197] In such cases, prior to setting the storage location for requests from the host computer, it is necessary to instruct the protocol chip (with conversion function) 112 to stop the operation of storing requests from the host computer. This embodiment will describe such a case.

[0198] In Figure 16 below, the storage system 2 is initially in the first processing mode, and the protocol chip (with conversion function) 112a stores requests from the host computer by specifying an address that points to memory 104a, which is included in the same controller 111a as the protocol chip (with conversion function) 112a, and reads the response resulting from processing the requests from the host computer by similarly specifying an address that points to memory 104a.

[0199] That is, when the storage system 2 is in the first processing mode, the processor 103b included in a controller 111b different from the protocol chip (with conversion function) 112a periodically obtains the state of the processor 103a included in the same controller 111a as the protocol chip (with conversion function) 112a (step 1601).

[0200] Next, in step 1602, processor 103b determines whether processor 103a is stopped. This stopping of processor 103a includes cases where the memory 104a connected to processor 103a has become inaccessible due to a failure or other reason. If the determination shows that processor 103a is operating normally and is not stopped, the process returns to step 1601, and processor 103b periodically acquires the status of processor 103a again, and the determination in step 1602 is repeated.

[0201] If the determination shows that processor 103a is stopped, the process proceeds to step 1603, where processor 103b sends an instruction to protocol chip (with conversion function) 112a to temporarily suspend the storage of requests from the host computer into memory 104a, thereby temporarily suspending the storage of requests from the host computer into memory 104a.

[0202] The instruction to the protocol chip (with conversion function) 112a of the processor 103b to temporarily suspend the storage of requests from the host computer into memory 104a may be sent via the mutual address translation units 105b, 105a and processor 103a as shown in Figure 6, or a dedicated signal line may be provided between the processor 103b and the protocol chip (with conversion function) 112a specifically for this purpose.

[0203] Next, in step 1604, processor 103b changes the setting for the storage location of requests from the host computer of protocol chip (with conversion function) 112a from memory 104a included in the same controller 111a as protocol chip (with conversion function) 112a to memory 104b included in a different controller 111b than protocol chip (with conversion function) 112a.

[0204] This setting change can be performed, for example, by providing a destination address register in the protocol chip (with conversion function) 112a that specifies the address where requests from the host computer are stored, and rewriting its contents from the address pointing to memory 104a to the address pointing to memory 104b. This rewriting of the destination address register can also be performed by the processor 103b via the mutual address conversion units 105b, 105a and processor 103a shown in Figure 6, or by providing a dedicated signal line specifically for this purpose between the processor 103b and the protocol chip (with conversion function) 112a.

[0205] Next, in step 1605, the processor 103b changes the setting for the source from which the response resulting from processing the request from the host computer of the protocol chip (with conversion function) 112a is read, from memory 104a included in the same controller 111a as the protocol chip (with conversion function) 112a, to memory 104b included in a different controller 111b.

[0206] This setting change can also be performed, for example, by providing a source address register in the protocol chip (with conversion function) 112a that specifies the address from which the response resulting from processing a request from the host computer is read, and rewriting its contents from the address pointing to memory 104a to the address pointing to memory 104b. This rewriting of the source address register can also be performed by the processor 103b via the mutual address translation units 105b, 105a and processor 103a shown in Figure 6, or by providing a dedicated signal line specifically for this purpose between the processor 103b and the protocol chip (with conversion function) 112a.

[0207] As described above, by executing steps 1604 and 1605, the protocol chip (with conversion function) 112a stores requests from the host computer in memory 104b included in a controller 111b different from the protocol chip (with conversion function) 112a, and reads the response resulting from processing the requests from the host computer from memory 104b included in the controller 111b different from the protocol chip (with conversion function) 112a. Thus, the storage system 2 switches from the first processing mode to the second processing mode.

[0208] Therefore, in step 1606, the processor 103b sends an instruction to the protocol chip (with conversion function) 112a to resume storing the request from the host computer, and resumes storing the request from the host computer. However, in this case, the storage destination is memory 104b, as it was changed from memory 104a to memory 104b in step 1604.

[0209] Furthermore, the instruction to resume storing requests from the host computer to the protocol chip (with conversion function) 112a of the processor 103b may be sent via the mutual address translation units 105b, 105a and the processor 103a, as shown in Figure 6, or a dedicated signal line may be provided specifically for this purpose between the processor 103b and the protocol chip (with conversion function) 112a.

[0210] Finally, in step 1607, the processor 103b begins processing the request from the host computer that the protocol chip (with conversion function) 112a stores in memory 104b.

[0211] As a result, the system can switch from a first processing mode, in which the protocol chip stores Read and Write requests received from the host computer in memory included in the same controller as the protocol chip, and reads the response resulting from processing the requests from the host computer from the same memory included in the same controller, to a second processing mode, in which the protocol chip stores Read and Write requests received from the host computer in memory included in a controller different from the protocol chip, and reads the response resulting from processing the requests from the host computer from the same memory included in the controller different from the protocol chip.

[0212] As a result, even if the memory in the same controller as the protocol chip becomes inaccessible due to a failure or other reason, or if the processor in the same controller as the protocol chip stops operating as a result, the requests from the host computer can be stored in the memory in a controller different from the protocol chip, and the response resulting from processing the requests from the host computer can be read from the memory in the same controller different from the protocol chip, thus allowing the processing of requests from the host computer to continue.

[0213] Furthermore, by temporarily suspending the storage of requests from the host computer in the protocol chip before changing the setting of the request storage location in the protocol chip, it is possible to avoid the protocol chip malfunctioning or becoming unresponsive to changes in the request storage location setting from the host computer. [Examples]

[0214] Example 3 will be explained using Figures 11, 12, 13, 14, and 15.

[0215] Figure 11 shows an example of the storage system configuration according to Example 3.

[0216] In Figure 11, the storage system 3 includes two interface units 120a and 120b, two processor board units 130a and 130b, and one drive box unit 140. The processor board units 130a and 130b and the interface units 120a and 120b are independently interchangeable.

[0217] The interface unit 120a comprises a protocol chip 121a, a memory address translation unit 122a, and a mutual address translation unit 123a.

[0218] The interface unit 120b comprises a protocol chip 121b, a memory address translation unit 122b, and a mutual address translation unit 123b.

[0219] Although Figure 11 shows two interface units, 120a and 120b, the number of interface units in a storage system is not limited to two; it can be one or more.

[0220] Protocol chips 121a and 121b are connected to a host computer (not shown) and control the protocol for data communication between the host computer and the storage system 3. In Figure 11, one protocol chip 121a and one protocol chip 121b are provided in the interface units 120a and 120b, but the number of protocol chips in the interface unit is not limited to one and can be arbitrary.

[0221] The processor board section 130a includes a processor 131a, memory 132a, and a mutual address translation unit 133a.

[0222] The processor board section 130b includes a processor 131b, memory 132b, and a mutual address translation unit 133b.

[0223] The memory address translation unit 122a has the function of translating the address of memory 132a, which the protocol chip 121a uses to store requests from the host computer, to an address that points to memory 132b, and also translating the address of memory 132a, which the protocol chip 121a uses to read the response resulting from processing the requests from the host computer, to an address that points to memory 132b.

[0224] Furthermore, in Figure 11, when the address translation function that translates to an address indicating memory 132b is enabled, the memory address translation unit 122a does not send the request from the host computer to the processor 131a for storage, or the response resulting from processing the request from the host computer for reading, but instead sends it to the mutual address translation unit 123a, which then sends it to the processor 131b via the mutual address translation units 123a and 123b and the memory address translation unit 122b, causing it to be stored in memory 132b or read from memory 132b.

[0225] Similarly, the memory address translation unit 122b has the function of translating the address of memory 132b, which the protocol chip 121b uses to store requests from the host computer, to an address that points to memory 132a, and also translating the address of memory 132b, which the protocol chip 121b uses to read the response resulting from processing the requests from the host computer, to an address that points to memory 132a.

[0226] Furthermore, in Figure 11, when the address translation function that translates to an address pointing to memory 132a is enabled, the memory address translation unit 122b does not send the request from the host computer to the processor 131b for storage, or the response resulting from processing the request from the host computer for reading, but instead sends it to the mutual address translation unit 123b, which then sends it to the processor 131a via the mutual address translation units 123b and 123a and the memory address translation unit 122a, causing it to be stored in memory 132a or read from memory 132a.

[0227] In Figure 11, the interface units 120a and 120b are each provided with one memory address translation unit 122a and 122b, but the number of memory address translation units in the interface unit is not limited to one and can be arbitrary. Furthermore, in Figure 11, the memory address translation units 122a and 122b are connected to protocol chips 121a and 121b, respectively, but the number of memory address translation units may be less than the number of protocol chips. If the number of memory address translation units is less than the number of protocol chips, one or more protocol chips may be connected to one memory address translation unit.

[0228] The mutual address translation units 123a and 123b have the function of mutually translating the addresses used by processor 131a and processor 131b. The protocol chip 121a can store requests from the host computer in memory 132b connected to processor 131b, and read responses from memory 132b as a result of processing requests from the host computer, via the memory address translation unit 122a and the mutual address translation units 123a and 123b.

[0229] Similarly, the protocol chip 121b can store requests from the host computer in the memory 132a and read responses from the memory 132a as a result of processing requests from the host computer, via the memory address translation unit 122b, and the mutual address translation units 123b and 123a.

[0230] In Figure 11, interface sections 120a and 120b are each provided with one mutual address translation unit 123a and 123b, but the number of mutual address translation units in each interface section is not limited to one and can be arbitrary. In particular, in Figure 11, mutual address translation units 123a and 123b are provided separately in interface sections 120a and 120b, but mutual address translation units 123a and 123b may be combined into a single mutual address translation unit and provided in only one of interface sections 120a or 120b.

[0231] Processors 131a and 131b are connected to memories 132a and 132b, respectively, and control the storage system 3 by executing instruction codes stored in memory 132a or 132b.

[0232] Memory 132a and 132b store instruction codes executed by processors 131a and 131b, respectively, as well as data necessary for executing those instruction codes. They may also temporarily store data sent from the host computer via protocol chip 121a or 121b, or data sent to the host computer via protocol chip 121a or 121b. In particular, memory 132a or memory 132b stores requests from the host computer, such as data read and data write requests to the storage system, which are received by the protocol chip from the host computer, and also stores the responses resulting from the processing of requests from the host computer by processor 131a or 131b.

[0233] In Figure 1, the processor boards 130a and 130b are each equipped with one processor 131a and 131b, and one memory 132a and 132b, respectively. However, the number of processors and memory in the processor board is not limited to one, but can be any number.

[0234] The mutual address translation units 133a and 133b have the function of mutually translating the addresses used by processor 131a and processor 131b. Processor 131a can access any address in memory 132b via the mutual address translation units 133a and 133b. Similarly, processor 131b can access any address in memory 132a via the mutual address translation units 133b and 133a.

[0235] In Figure 11, the processor board sections 130a and 130b are each provided with one mutual address translation unit 133a and 133b, but the number of mutual address translation units in the processor board section is not limited to one and can be arbitrary. In particular, in Figure 11, the mutual address translation units 133a and 133b are provided separately in the processor board sections 130a and 130b, but the mutual address translation units 133a and 133b may be combined into a single mutual address translation unit and provided in only one of the processor board sections 130a or 130b.

[0236] The drive box unit 140 comprises two backend switches 141a and 141b and eight storage devices 142a to 142b. In Figure 11, the storage system 3 comprises one drive box unit 140, but the number of drive box units in the storage system is not limited to one and can be arbitrary.

[0237] Backend switches 141a and 141b connect processors 131a and 131b to eight storage devices 142a to 142h, respectively, and perform switching processing for data communication between processors 131a and 131b and the eight storage devices 142a to 142h according to the data communication protocol between processors 131a and 131b and storage devices 142a to 142h. In Figure 11, two backend switches 141a and 141b are provided in the drive box section 140, but the number of backend switches in the drive box section is not limited to two and can be arbitrary.

[0238] The storage devices 142a to 142h store and hold the data that the host computer sends to the storage system 3 for storage. In Figure 11, eight storage devices 142a to 142h are provided in the drive box section, but the number of storage devices in the drive box section is not limited to eight and can be any number.

[0239] As shown in Figure 11, by providing mutual address translation units 123a and 123b in interface units 120a and 120b, respectively, even if either processor board unit 130a or 130b becomes unusable due to failure or replacement, the protocol chips 121a and 121b of either interface unit 120a or 120b can access the memory 132a or 132b of the operational processor board unit 130a or 130b, and continue to communicate with the host computer.

[0240] In Figure 11, the storage system 3, in the first processing mode, stores Read and Write requests from the host computer received by the protocol chip 121a in the memory 132a of the processor board section 130a to which the interface section 120a containing the protocol chip 121a is connected, and reads the response resulting from processing the requests from the host computer from the same memory 132a.

[0241] Furthermore, in the second processing mode, the storage system 3 stores Read and Write requests from the host computer received by the protocol chip 121a in memory 132b included in the processor board section 130b, which is connected to the interface section 120a containing the protocol chip through a different interface section 120b, and reads the response resulting from processing the request from the host computer from the same memory 132b.

[0242] This process is explained in Figures 12, 13, 14, and 15.

[0243] Figure 12 shows an example of a processing sequence when the storage system 3 receives a Read request from the host computer in the first processing mode. In Figure 12, each vertical line indicates the time order of requests and responses sent or received by the part described at the top. Time progresses from top to bottom in the figure (the same applies to Figures 13, 14, and 15 below).

[0244] In Figure 12, when the protocol chip 121a of the interface unit 120a receives a Read request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 122a, specifying the address that indicates memory 132a as the storage destination (1201).

[0245] In the first processing mode, by setting the address translation function of the memory address translation unit 122a to disabled, the memory address translation unit 122a sends the request from the host computer, which is sent by the protocol chip 121a and specifies the address of memory 132a as the storage destination, to the processor 131a of the processor board unit 130a without performing any address translation.

[0246] The processor 131a stores a request from the host computer, which has been sent from the memory address translation unit 122a and specifies the address of memory 132a as the storage destination, into memory 132a according to the specified address. This storage process into memory 132a by the processor 131a may be performed by executing some instruction code in the processor 131a, or the processor 131a may be equipped with a hardware mechanism that automatically stores the data into memory 132a according to the specified address.

[0247] Next, processor 131a reads the request from the host computer sent from protocol chip 121a from memory 132a and starts processing it (1202). If the request from the host computer read from memory 132a is a Read request, processor 131a determines which of the storage devices 142a to 142h the requested data is located in, generates a data output request for that storage device, storage device 142a in the example of Figure 12, and sends it via backend switch 141a (1203).

[0248] The storage device 142a retrieves the requested data from its internal storage element or storage medium and stores it in the memory 132a via the backend switch 141a and processor 131a (1204). Furthermore, the storage device 142a generates a data output completion response indicating that the requested data has been correctly stored in the memory 132a and stores it in the memory 132a via the backend switch 141a and processor 131a (1205).

[0249] This process of storing data from the memory device 142a via the processor 131a, and storing the data output completion response in the memory 132a, may be performed by executing some instruction code in the processor 131a, or the processor 131a may be provided with a hardware mechanism to automatically store the data in the memory 132a.

[0250] Next, the processor 131a reads the data output completion response written to the memory 132a from the storage device 142a (1206). The processor 131a generates a Read response to send to the host computer according to the read data output completion response and stores it in the memory 132a (1207). Subsequently, the processor 131a generates a response notification to inform the protocol chip 121a that the Read response has been stored in the memory 132a and sends it to the protocol chip 121a via the memory address translation unit 122a (1208).

[0251] When the protocol chip 121a receives a response notification from the processor 131a, it sends a Read response read request to the memory address translation unit 122a, specifying the address of memory 132a as the read destination. In the first processing mode, by setting the address translation function of the memory address translation unit 122a to disabled, the memory address translation unit 122a sends the Read response read request sent by the protocol chip 121a, which specifies the address of memory 132a as the read destination, to the processor 131a without address translation (1209). When the processor 131a receives the Read response read request from the protocol chip 121a, it reads the Read response from memory 132a (1210) and sends it back to the protocol chip 121a via the memory address translation unit 122a (1211).

[0252] In accordance with the Read response request from the protocol chip 121a, the Read response read from memory 132a by the processor 131a may be performed by executing some instruction code in the processor 131a, or the processor 131a may be equipped with a hardware mechanism that automatically reads from memory 132a.

[0253] When the protocol chip 121a receives a Read response from the processor 131a, it sends a Read data read request to the processor 131a via the memory address translation unit 122a, in accordance with the contents of the response (1212). The processor 131a reads the Read data in accordance with the sent Read data read request (1213), and sends the read Read data back to the protocol chip 121a via the memory address translation unit 122a (1214).

[0254] In accordance with the Read data read request from the protocol chip 121a, the processor 131a may read the Read data from memory 132a by executing some instruction code in the processor 131a, or it may be done by providing the processor 131a with a hardware mechanism that automatically reads from memory 132a. When the protocol chip 121a receives the Read data from the processor 131a, it sends the Read data to a host computer (not shown).

[0255] Figure 13 shows an example of a processing sequence when the storage system 3 receives a Write request from the host computer in the first processing mode.

[0256] In Figure 13, when the protocol chip 121a receives a Write request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 122a, specifying the address of memory 132a as the storage destination (1301). In the first processing mode, by setting the address translation function of the memory address translation unit 122a to disabled, the memory address translation unit 122a sends the request from the host computer, which is sent by the protocol chip 121a and specifies the address of memory 132a as the storage destination, to the processor 131a without performing any address translation.

[0257] The processor 131a stores a request from the host computer, which has been sent from the memory address translation unit 122a and specifies the address of memory 132a as the storage destination, into memory 132a according to the specified address. This storage process into memory 132a by the processor 131a may be performed by executing some instruction code in the processor 131a, or the processor 131a may be equipped with a hardware mechanism that automatically stores the data into memory 132a according to the specified address.

[0258] Next, the processor 131a reads the request from the host computer sent from the protocol chip 121a from the memory 132a and starts processing it (1302). If the request from the host computer read from the memory 132a is a write request, the processor 131a prepares to receive the write data and sends permission to send the write data to the protocol chip 121a via the memory address translation unit 122a (1303).

[0259] Upon receiving permission to send Write data, the protocol chip 121a sends permission to send Write data to the host computer and receives Write data from the host computer. The protocol chip 121a stores the Write data received from the host computer in memory 132a via the memory address translation unit 122a and the processor 131a (1304).

[0260] Furthermore, when the protocol chip 121a receives a signal from the host computer indicating the completion of the Write data transmission, it stores the Write data transmission completion in the memory 132a via the memory address translation unit 102a and the processor 103a (1305). This process of storing the Write data and the Write data transmission completion in the memory 132a via the processor 131a may be performed by executing some instruction code in the processor 131a, or the processor 131a may be provided with a hardware mechanism to automatically store the data in the memory 132a.

[0261] Next, processor 131a reads and confirms that the Write data transmission has been completed, which is stored in memory 132a (1306). After that, processor 131a reads the Write data from memory 132a (1307), and sends it to memory 132b for storage via the mutual address translation units 133a and 133b and processor 131b (1308).

[0262] This is to duplicate the write data in memory 132a and memory 132b, so that even if memory 132a or 132b becomes inaccessible due to a failure or power outage, or if processor 131a or 131b stops working, the write data received from the host computer will not be lost.

[0263] Furthermore, the process of storing the write data to memory 132b via processor 131b may be performed by executing some instruction code on processor 131b, or it may be performed by providing processor 131b with a hardware mechanism to automatically store the data in memory 132b.

[0264] Once the processor 131a has finished the process of duplicating the write data, it generates a write response and stores it in memory 132a (1309). Subsequently, the processor 131a generates a response notification to inform the protocol chip 121a that the write response has been stored in memory 132a, and sends it to the protocol chip 121a via the memory address translation unit 122a (1310).

[0265] When the protocol chip 121a receives a response notification from the processor 131a, it sends a request to read the Write response to the memory address translation unit 122a, specifying the address of memory 132a as the read destination. In the first processing mode, by setting the address translation function of the memory address translation unit 122a to be disabled, the memory address translation unit 122a sends the request to read the Write response sent by the protocol chip 121a, which specifies the address of memory 132a as the read destination, to the processor 131a without address translation (1311). When the processor 131a receives the request to read the Write response from the protocol chip 121a, it reads the Write response from memory 132a (1312) and sends it back to the protocol chip 121a via the memory address translation unit 122a (1313).

[0266] In accordance with the Write response read request from the protocol chip 121a, the processor 131a may perform the Write response read from memory 132a by executing some instruction code, or it may be performed by providing the processor 131a with a hardware mechanism that automatically reads from memory 132a.

[0267] When the protocol chip 121a receives a write response from the processor 131a, it notifies the host computer that the write process is complete.

[0268] Next, processor 131a determines which storage devices 142a to 142h will store the Write data stored in memory 132a. In Figure 13, it is assumed that processor 131a has decided to store the Write data stored in memory 132a in storage device 142a. Therefore, processor 131a generates a data storage request and sends it to storage device 142a via backend switch 141a (1314).

[0269] Upon receiving a data storage request, the storage device 142a sends a request to read the data of the Write data to the processor 131a via the backend switch 141a (1315). Upon receiving the data read request, the processor 131a reads the Write data from memory 132a (1316) and sends it to the storage device 142a via the backend switch 141a for storage (1317).

[0270] In response to a data read request for write data from memory 142a, the processor 131a may read the write data from memory 132a by executing some instruction code, or the processor 131a may be equipped with a hardware mechanism that automatically reads the write data from memory 132a in response to a write data read request.

[0271] When the memory device 142a receives Write data, it stores the received Write data in an internal memory element or a storage medium. When the storage of the Write data in the internal memory element or the storage medium is completed, the memory device 142a generates a data storage completion response and stores it in the memory 132a via the backend switch 141a and the processor 131a (1318).

[0272] The process of storing the data storage completion response in the memory 132a via this processor 131a may be performed by causing the processor 131a to execute some instruction code, or a hardware mechanism for automatically storing in the memory 132a may be provided to the processor 131a. Finally, the processor 131a reads out the data storage completion response from the memory 132a for confirmation (1319).

[0273] The above is the operation in the storage system 3 when there is a Read request or a Write request from the host computer in the first processing mode of storing the request from the host computer and the response of the result of processing the request from the host computer in the memory 132a. If the memory 132a becomes inaccessible due to a failure or a power outage, or the processor 131a stops operating and storage or reading to / from the memory 132a becomes impossible, or even if the entire processor board unit 130a becomes unusable due to a failure or replacement, the second processing mode of storing the request from the host computer and the response of the result of processing the request from the host computer in the memory 132b instead of the memory 132a is applied.

[0274] By applying the second processing mode, even if the memory 132a becomes inaccessible due to a failure or a power outage, or the processor 131a stops operating and storage or reading to / from the memory 132a becomes impossible, or even if the entire processor board unit 130a becomes unusable due to a failure or replacement, it is possible to continue processing the requests from the host computer.

[0275] FIG. 14 is an example of a processing sequence in the storage system 3 when a Read request is received from a host computer when the second processing mode is applied.

[0276] In FIG. 14, when the protocol chip 121a receives a Read request from a host computer (not shown), the protocol chip 121a sends the request from the host computer to the memory address translation unit 122a by designating an address indicating the memory 132a as the storage destination (1401).

[0277] In the second processing mode, by setting the address translation function of the memory address translation unit 122a to be valid, the memory address translation unit 122a converts the address designating the memory 132a as the storage destination in the request from the host computer sent by the protocol chip 121a into an address designating the memory 132b. After further performing address translation so as to designate the memory 132b, the request from the host computer is not sent to the processor 131a, but is sent to the processor 131b via the mutual address translation units 123a and 123b and the memory address translation unit 122b, and is stored in the memory 132b.

[0278] This storage process to the memory 132b by the processor 131b may be performed by causing the processor 131b to execute some instruction code, or may be performed by providing the processor 131b with a hardware mechanism that automatically stores data in the memory 132b according to the designated address.

[0279] Next, the processor 131b reads the request from the host computer sent from the protocol chip 121a from the memory 132b and starts processing (1402). If the request from the host computer read from the memory 132b by the processor 131b is a Read request, the processor 131b determines in which of the storage devices 142a to 142h the requested data is stored, and generates a data output request for the storage device, which is the storage device 142a in the example of FIG. 14, and sends it via the back-end switch 141b (1403).

[0280] The storage device 142a retrieves the requested data from its internal storage element or storage medium and stores it in the memory 132b via the backend switch 141b and processor 131b (1404). Furthermore, the storage device 142a generates a data output completion response indicating that the requested data has been correctly stored in the memory 132b and also stores it in the memory 132b via the backend switch 141b and processor 131b (1405).

[0281] The storage of data from the memory device 142a via the processor 131b, and the storage of the data output completion response into the memory 132b, may be performed by executing some instruction code in the processor 131b, or the processor 131b may be provided with a hardware mechanism that automatically stores the data into the memory 132b.

[0282] Next, the processor 131b reads the data output completion response written from the storage device 142a to the memory 132b (1406). The processor 131b generates a Read response to send to the host computer according to the read data output completion response and stores it in the memory 132b (1407).

[0283] Subsequently, the processor 131b generates a response notification informing the protocol chip 121a that the Read response has been stored in the memory 132b, and sends it to the protocol chip 121a via the memory address translation unit 122b, the mutual address translation units 123b and 123a, and the memory address translation unit 122a (1408).

[0284] When the protocol chip 121a receives a response notification from the processor 131b, it sends a read request in the Read response to the memory address translation unit 122a, specifying the address of memory 132a as the read destination.

[0285] In the second processing mode, by enabling the address translation function of the memory address translation unit 122a, the memory address translation unit 122a translates the address specifying memory 132a as the read destination in the Read response read request sent by the protocol chip 121a to an address specifying memory 132b. After further address translation to specify memory 132b, the Read response read request is not sent to the processor 131a, but is sent to the processor 131b via the mutual address translation units 123a, 123b, and the memory address translation unit 122b (1409).

[0286] When processor 131b receives a Read response request from protocol chip 121a, it reads the Read response from memory 132b (1410) and sends it to protocol chip 121a via memory address translation unit 122b, mutual address translation units 123b and 123a, and memory address translation unit 122a (1411).

[0287] In accordance with the Read response request from the protocol chip 121a, the Read response read from memory 132b by the processor 131b may be performed by executing some instruction code on the processor 131b, or the processor 131b may be provided with a hardware mechanism to automatically read from memory 132b.

[0288] When the protocol chip 121a receives a Read response from the processor 131b, it generates a Read data read request that specifies the address of memory 132a as the read destination according to the content of the response, and sends it to the memory address translation unit 122a.

[0289] In the second processing mode, by enabling the address translation function of the memory address translation unit 122a, the memory address translation unit 122a translates the address specifying memory 132a as the read destination in the Read data read request sent by the protocol chip 121a to an address specifying memory 132b. After further address translation to specify memory 132b, the Read data read request is not sent to the processor 131a, but is sent to the processor 131b via the mutual address translation units 123a, 123b, and the memory address translation unit 122b (1412).

[0290] The processor 131b reads the Read data in accordance with the received Read data read request (1413), and sends the read Read data to the protocol chip 121a via the memory address translation unit 122b, the mutual address translation units 123b and 123a, and the memory address translation unit 122a (1414).

[0291] In accordance with the Read data read request from the protocol chip 121a, the processor 131b may read the Read data from memory 132b by executing some instruction code in the processor 131b, or it may be done by providing the processor 131b with a hardware mechanism that automatically reads from memory 132b. When the protocol chip 121a receives the Read data from the processor 131b, it sends the Read data to a host computer (not shown).

[0292] Figure 15 shows an example of a processing sequence when the storage system 3 receives a Write request from the host computer in the second processing mode.

[0293] In Figure 15, when the protocol chip 121a receives a write request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 122a, specifying the address of memory 132a as the storage destination (1501).

[0294] In the second processing mode, by enabling the address translation function of the memory address translation unit 122a, the memory address translation unit 122a translates the address specifying memory 132a as the storage destination in the request from the host computer sent by the protocol chip 121a to an address specifying memory 132b. After further address translation to specify memory 132b, the request from the host computer is not sent to the processor 131a, but is sent to the processor 131b via the mutual address translation units 123a and 123b and the memory address translation unit 122b, and stored in memory 132b.

[0295] The process of storing data in memory 132b by processor 131b may be performed by executing some instruction code on processor 131b, or it may be performed by providing processor 131b with a hardware mechanism that automatically stores data in memory 132b according to a specified address.

[0296] Next, processor 131b reads the request from the host computer sent from protocol chip 121a from memory 132b and begins processing it (1502). If the request from the host computer read from memory 132b is a write request, processor 131b prepares to receive the write data and sends permission to send the write data to protocol chip 121a via memory address translation unit 122b, mutual address translation units 123b, 123a, and memory address translation unit 122a (1503).

[0297] Upon receiving permission to send Write data, the protocol chip 121a sends permission to send Write data to the host computer and receives Write data from the host computer. The protocol chip 121a stores the Write data received from the host computer in memory 132b via the memory address translation unit 122a, the mutual address translation units 123a and 123b, the memory address translation unit 122b, and the processor 131b (1504).

[0298] Furthermore, when the protocol chip 121a receives a signal indicating the completion of Write data transmission from the host computer, it also stores the completion of Write data transmission in the memory 132b via the memory address conversion unit 122a, the mutual address conversion units 123a and 123b, the memory address conversion unit 122b, and the processor 131b (1505).

[0299] The process of storing the Write data and the completion of Write data transmission in the memory 132b via the processor 131b may be performed by causing the processor 131b to execute some instruction code, or a hardware mechanism for automatically storing in the memory 132b may be provided in the processor 131b.

[0300] Next, the processor 131b reads and checks the completion of Write data transmission stored in the memory 132b (1506). After that, in the second processing mode, considering the possibility that the memory 132a may not be accessible due to a failure or the like, the Write data is not duplicated between the memory 132a and the memory 132b as in the first processing mode.

[0301] Instead, the Write data is directly stored in any one of the storage devices 142a to 142h of the storage device, and a Write response is returned to the host computer. That is, next, the processor 131b determines the storage devices 142a to 142h that store the Write data stored in the memory 132b.

[0302] In FIG. 15, assume that the processor 131b determines to store the Write data stored in the memory 132b in the storage device 142a. Therefore, the processor 131b generates a data storage request and sends it to the storage device 142a via the backend switch 141b (1507). The storage device 142a that has received the data storage request sends a request for reading the Write data to the processor 131b via the backend switch 141b (1508).

[0303] Upon receiving a data read request, processor 131b reads the Write data from memory 132b (1509), sends it to storage device 142a via backend switch 141b, and stores it (1510). This reading of Write data from memory 132b by processor 131b in response to a data read request for Write data from storage device 142a may be performed by executing some instruction code in processor 131b, or processor 131b may be provided with a hardware mechanism that automatically reads Write data from memory 132b in response to a Write data read request.

[0304] When the storage device 142a receives write data, it stores the received write data in its internal storage element or storage medium. Once the storage of the write data in its internal storage element or storage medium is complete, the storage device 142a generates a data storage completion response and stores it in the memory 132b via the backend switch 141b and processor 131b (1511).

[0305] The process of storing the data storage completion response to memory 132b via processor 131b may be performed by executing some instruction code on processor 131b, or it may be performed by providing processor 131b with a hardware mechanism to automatically store it in memory 132b.

[0306] Subsequently, processor 131b reads and confirms a data storage completion response from memory 132b (1512). After confirming the data storage completion response, processor 131b generates a Write response and stores it in memory 132b (1513). Then, processor 131b generates a response notification to inform protocol chip 121a that the Write response has been stored in memory 132b, and sends it to protocol chip 121a via memory address translation unit 122b, mutual address translation units 123b and 123a, and memory address translation unit 122a (1514).

[0307] When the protocol chip 121a receives a response notification from the processor 131b, it sends a read request for the write response to the memory address translation unit 122a, specifying the address of memory 132a as the read destination.

[0308] In the second processing mode, by enabling the address translation function of the memory address translation unit 122a, the memory address translation unit 122a translates the address specifying memory 132a as the read destination for the write response read request sent by the protocol chip 121a to an address specifying memory 132b, and sends it to the processor 131b via the mutual address translation units 105a, 105b and the memory address translation unit 122b (1515).

[0309] When processor 131b receives a write response read request from protocol chip 121a, it reads the write response from memory 132b (1516) and sends it to protocol chip 121a via memory address translation unit 122b, mutual address translation units 123b and 123a, and memory address translation unit 122a (1517).

[0310] In accordance with the Write response read request from the protocol chip 121a, the processor 131b may read the Write response from memory 132b by executing some instruction code, or it may be done by providing the processor 131b with a hardware mechanism to automatically read from memory 132b. When the protocol chip 121a receives the Write response from the processor 131b, it notifies the host computer that the Write process is complete.

[0311] The above describes the operation of the storage system 3 when a Read request or Write request is received from the host computer in the second processing mode, in which requests from the host computer and the responses resulting from processing those requests are stored in memory 132b. By applying the second processing mode, it is possible to continue processing requests from the host computer even if memory 132a becomes inaccessible due to a failure or power outage, if the processor 131a stops operating and storage to or reading from memory 132a becomes impossible, or even if the entire processor board 130a becomes unusable due to a failure or replacement. [Examples]

[0312] Embodiment 4 will be described using Figures 1, 19, and 20. In Embodiment 4, the configuration of the storage system, the processing of requests from the host computer, and the response of the processing results are the same as in Embodiment 1. This embodiment can be applied to the configuration example shown in Figure 6 or 11. In Embodiment 4, if the processor 103a does not complete processing a request from the host computer while in the first processing mode, the processor 103b notifies the host computer in the second processing mode that the processing of the request has been interrupted.

[0313] In this way, by notifying the host computer that the processing of a request has been interrupted, the host computer can quickly understand that processing has been interrupted without having to detect that a response has not been received from the storage system within a certain period of time, and can re-request the processing if necessary. This ensures that the host computer's processing proceeds smoothly. It also prevents the host computer from mistakenly assuming that the storage system is down and stopping its own processing.

[0314] In Example 4, the configuration of the storage system 1 is as shown in Figure 1.

[0315] Figure 19 shows the processing performed by processor 103a when storage system 1 is in the first processing mode in Embodiment 4. In Figure 19, processor 103a retrieves a request from the host computer, which has been sent from protocol chip 101a and stored in memory 104a, from memory 104a (step 1901).

[0316] Next, the processor 103a extracts information from the request retrieved from the memory 104a to notify the host computer that it has interrupted processing of the request (step 1902). This information to notify the host computer that it has interrupted processing of the request includes, for example, the host computer's hostname (identifier), the volume number or logical address number within the volume that identifies the storage area in the storage system that is the target of the request, the type of request (read or write), the tag number assigned by the host computer to distinguish the request from other requests, or the session number used by the protocol chip 101a to identify a series of communications with the host computer.

[0317] Next, processor 103a stores the extracted information for notifying that it has interrupted processing of the request from the host computer into memory 104b of processor 103b via the mutual address translation units 105a and 105b (step 1903). After that, processor 103a processes the request from the host computer (step 1904).

[0318] Once the processor 103a has finished processing the request from the host computer, it stores the response resulting from processing the request from the host computer in the memory 104a (step 1905). Next, the processor 103a notifies the protocol chip 101a that it has stored the response resulting from processing the request from the host computer in the memory 104a, and causes the protocol chip 101a to send the response resulting from processing back to the host computer (step 1906).

[0319] Finally, if the processor 103a can complete the processing up to step 1906 without stopping, in step 1907, it stores the response of the result of processing the request from the host computer in the memory 104a and records in the memory 104b of the processor 103b, via the mutual address translation units 105a and 105b, that it has sent the protocol chip 101a back to the host computer.

[0320] Recording in memory 104b may be done by marking the request from the host computer in question, or by adding information indicating that the protocol chip 101a has sent a response to the host computer indicating that the processing of the request from the host computer has been interrupted to the information stored in step 1903, or by erasing the information stored in step 1903 indicating that the processing of the request from the host computer has been interrupted from memory 104b.

[0321] Figure 20 shows the process in the second processing mode in which processor 103b retrieves information stored in memory 104b by processor 103a to notify that the processing of a request from the host computer has been interrupted, and notifies the host computer that the processing of the request has been interrupted.

[0322] In Figure 20, in the second processing mode, processor 103b searches memory 104b to see if there is any information stored in memory 104b by processor 103a to notify that the processing of a request from the host computer has been interrupted (step 2001). If the search does not find such information in memory 104b (step 2002: NO), then in the second processing mode, the process proceeds to retrieve the request from the host computer stored in memory 104b by the protocol chip 101a, store the response resulting from processing the request from the host computer in memory 104b, notify the protocol chip 101a, and have the host computer return the response resulting from processing the request (step 2006).

[0323] If memory 104b contains information to notify that the processing of a request from the host computer has been interrupted (Step 2002: YES), proceed to Step 2003 and search memory 104b for a record of processor 103a storing a response in memory 104b as a result of processing the request from the host computer. If such a record is found (Step 2004: YES), return to Step 2001 and continue searching memory 104b for any other information stored by processor 103a to notify that the processing of a request from the host computer has been interrupted.

[0324] If the search does not find the record in question (Step 2004: NO), the process proceeds to Step 2005, where the information stored in memory 104b for notifying that the processing of the request from the host computer has been interrupted is used to notify the host computer that the processing of the request has been interrupted. After that, the process returns to Step 2001 and continues searching memory 104b for any other information stored by processor 103a for notifying that the processing of the request from the host computer has been interrupted.

[0325] As a result, the host computer can be notified that the processing of a request has been interrupted. This allows the host computer to quickly understand that processing has been interrupted without having to detect that no response has been received from the storage system within a certain period of time. If necessary, it can re-request the processing, and the host computer's processing can proceed smoothly. Furthermore, it is possible to prevent the host computer from mistakenly determining that the storage system is down and stopping its own processing. [Examples]

[0326] Embodiment 5 will be explained using Figures 1, 21, 22, 23, and 24. In Embodiment 5, in the first processing mode, the memory address translation unit 102a stores the request from the host computer in the memory 104a of the processor 103a that processes in the first processing mode, and stores a copy thereof in the memory 104b of the processor 103b that processes in the second processing mode. The processor 103a also stores the response resulting from processing the requests from the host computers in the memory 104a, and stores a copy thereof in the memory 104b.

[0327] In this way, when transitioning from the first processing mode to the second processing mode, processor 103b can identify requests from the host computer that processor 103a has not completed by comparing the requests from the host computer stored in processor 103b's memory 104b with the response resulting from processing the requests from the host computer. If the response resulting from processing the requests from the host computer is not stored, processor 103b can then process the requests from the host computer again.

[0328] In Example 5, the configuration of the storage system is the same as that of Storage System 1 shown in Figure 1 in Example 1. This example can also be applied to the configuration examples shown in Figures 6 or 11.

[0329] In Embodiment 5, in the first processing mode, the memory address translation unit 102a is set to disable the memory address translation function. Therefore, it sends the request from the host computer, which is sent by the protocol chip specifying the address of memory 104a as the storage destination, to the processor 103a without address translation, and stores it in memory 104a.

[0330] In Embodiment 5, the memory address translation unit 102a then replicates the request from the host computer, and if the memory address translation function is enabled, assigns the address of the memory 104b to be translated and sends it to the processor 103a, which then sends it to the processor 103b via the mutual address translation units 105a and 105b, and stores it in the memory 104b.

[0331] Furthermore, processor 103a processes requests from the host computer, generates a response based on the processing results, stores it in memory 104a, then duplicates the response and sends it to processor 103b via mutual address translation units 105a and 105b, causing it to be stored in memory 104b.

[0332] Below, an example of the processing sequence in Embodiment 5 of the present invention in the first processing mode will be described in Figures 21 and 22.

[0333] Figure 21 shows an example of the processing sequence when the storage system 1 receives a Read request from the host computer in the first processing mode in Embodiment 5. In Figure 21, each vertical line indicates the time order of requests and responses sent or received by the part described at the top. Time progresses from the top to the bottom of the figure (the same applies to Figure 22 below).

[0334] In Figure 21, when the protocol chip 101a receives a Read request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 102a, specifying the address of memory 104a as the storage destination (2101). In the first processing mode, by setting the address translation function of the memory address translation unit 102a to disabled, the memory address translation unit 102a sends the request from the host computer, which is sent by the protocol chip 101a and specifies the address of memory 104a as the storage destination, to the processor 103a without performing any address translation.

[0335] In Embodiment 5, the memory address translation unit 102a then replicates the request from the host computer that was sent to the processor 103a specifying the address of memory 104a as the storage destination, and, if the address translation function is enabled, specifies the address of memory 104b that will be translated as the new storage destination address and sends it to the processor 103a as well (2102).

[0336] Processor 103a stores requests from the host computer, where the address of memory 104a is specified as the storage destination, into memory 104a. This storage process into memory 104a by processor 103a may be performed by executing some instruction code on processor 103a, or it may be performed by providing processor 103a with a hardware mechanism that automatically stores the data into memory 104a according to the specified address.

[0337] Furthermore, processor 103a sends a request from a host computer that specifies the address of memory 104b as the storage destination, following a request from a host computer that specifies the address of memory 104a as the storage destination, to the mutual address translation unit 105a, which then transmits the request to memory 104b via the mutual address translation unit 105b and processor 103b.

[0338] The process by which processor 103a receives a request from a host computer, specifying the address of memory 104b as the storage destination, and stores it in memory 104b via the mutual address translation units 105a, 105b, and processor 103b according to the specified address, may be performed by having processor 103a execute some instruction code, or a hardware mechanism may be provided in processor 103a that automatically sends the request to the mutual address translation unit 105a according to the specified address.

[0339] Next, the processor 103a reads the request from the host computer sent from the protocol chip 101a from the memory 104a and begins processing it (2103). The processing flow from this sequence 2103 to sequence 2108, in which the processor 103a generates a Read response to send to the host computer and stores it in the memory 104a, is the same as the processing flow from sequence 202 to sequence 207 in Figure 2 of Embodiment 1.

[0340] In Example 5, in sequence 2108, processor 103a generates a Read response to send to the host computer and stores it in memory 104a. Then, it duplicates the Read response and sends it to processor 103b via the mutual address translation units 105a and 105b, causing it to be stored in memory 104b (2109).

[0341] By doing so, after later transitioning to the second processing mode, processor 103b can retrieve the contents of memory 104b to identify whether a Read request from the host computer sent by processor 103a from protocol chip 101a is stored, but the Read response resulting from processing the request from the host computer is not stored.

[0342] Processor 103a duplicates the Read response in sequence 2109, stores it in memory 104b of processor 103b, and then generates a response notification to inform protocol chip 101a that the Read response has been stored in memory 104a, and sends it to protocol chip 101a via memory address translation unit 102a (2110).

[0343] The processing from sequence 2110 to sequence 2116, which sends the Read data to the protocol chip 101a and then sends it back to the host computer, is the same as the processing flow from sequence 208 to sequence 214 in Figure 2 of Embodiment 1. This processing flow completes the processing sequence in Embodiment 5 when a Read request is received from the host computer.

[0344] Figure 22 shows an example of a processing sequence in this embodiment 5 when the storage system 1 receives a write request from the host computer in the first processing mode.

[0345] In Figure 22, when the protocol chip 101a receives a write request from a host computer (not shown), it sends the request from the host computer to the memory address translation unit 102a, specifying the address of memory 104a as the storage destination (2201).

[0346] In the first processing mode, by setting the address translation function of the memory address translation unit 102a to disabled, the memory address translation unit 102a sends the request from the host computer, which is sent by the protocol chip 101a and specifies the address of memory 104a as the storage destination, to the processor 103a without performing any address translation.

[0347] In Embodiment 5, the memory address translation unit 102a then replicates the request from the host computer that was sent to the processor 103a specifying the address of memory 104a as the storage destination, and, if the address translation function is enabled, specifies the address of memory 104b that will be translated as the new storage destination address and sends it to the processor 103a as well (2202).

[0348] Processor 103a stores requests from the host computer, where the address of memory 104a is specified as the storage destination, into memory 104a. This storage process into memory 104a by processor 103a may be performed by executing some instruction code on processor 103a, or it may be performed by providing processor 103a with a hardware mechanism that automatically stores the data into memory 104a according to the specified address.

[0349] Furthermore, processor 103a sends a request from a host computer that specifies the address of memory 104b as the storage destination, following a request from a host computer that specifies the address of memory 104a as the storage destination, to the mutual address translation unit 105a, which then transmits the request to memory 104b via the mutual address translation unit 105b and processor 103b.

[0350] The process by which processor 103a receives a request from a host computer, specifying the address of memory 104b as the storage destination, and stores it in memory 104b via the mutual address translation units 105a, 105b, and processor 103b according to the specified address, may be performed by having processor 103a execute some instruction code, or a hardware mechanism may be provided in processor 103a that automatically sends the request to the mutual address translation unit 105a according to the specified address.

[0351] Next, the processor 103a reads the request from the host computer sent from the protocol chip 101a from the memory 104a and begins processing it (2203). The processing flow from this sequence 2203 to sequence 2210, in which the processor 103a generates a write response and stores it in the memory 104a, is the same as the processing flow from sequence 302 to sequence 309 in Figure 3 of Embodiment 1.

[0352] In Example 5, processor 103a generates a write response in sequence 2210 and stores it in memory 104a. After that, it duplicates the write response and sends it to processor 103b via the mutual address translation units 105a and 105b, causing it to be stored in memory 104b (2211).

[0353] By doing so, after transitioning to the second processing mode, processor 103b can retrieve the contents of memory 104b to identify whether a Write request from the host computer sent by the protocol chip 101a to processor 103a has been stored, but whether a Write response resulting from processing the request from the host computer has not been stored.

[0354] Processor 103a duplicates the Write response in sequence 2211, stores it in memory 104b of processor 103b, and then generates a response notification to inform protocol chip 101a that the Write response has been stored in memory 104a, and sends it to protocol chip 101a via memory address translation unit 102a (2212).

[0355] The processing flow from sequence 2212 to sequence 2221, in which processor 103a reads and confirms the data storage completion response stored in storage device 107a from memory 104a, is the same as the processing flow from sequence 310 to sequence 319 in Figure 3 of Embodiment 1. With this processing flow, the processing sequence when a Write request is received from the host computer is completed in Embodiment 5.

[0356] Next, using Figure 23, we will explain an example of the process of switching from the first processing mode to the second processing mode in Example 5.

[0357] Figure 23 shows an example of the process in Embodiment 5, which switches from a first processing mode in which Read and Write requests received by the protocol chip from the host computer are processed by a processor included in the same controller as the protocol chip, to a second processing mode in which Read and Write requests received by the protocol chip from the host computer are processed by a processor included in a different controller than the protocol chip.

[0358] In Embodiment 5, in the first processing mode, the processor 103a, which is included in the same controller 110a as the protocol chip 101a, stores the request from the host computer and the response resulting from processing the request from the host computer in the memory 104a of the processor 103a, and also stores copies of them in the memory 104b of the processor 103b, which is included in a different controller 110b from the protocol chip 101a.

[0359] In the second processing mode, processor 103b performs processing by referencing memory 104b. Therefore, the process of storing the copy in memory 104b by processor 103a, as described above, must be completely stopped. In other words, it is necessary that the processing of processor 103a is completely stopped. If the operation of processor 103a is not completely stopped and the process of storing the copy in memory 104b continues, a conflict will occur with processor 103b, which also references memory 104b and performs processing, and processor 103b may malfunction.

[0360] Therefore, in the example of switching from the first processing mode to the second processing mode described in Figure 23, it is confirmed that the operation of processor 103a has completely stopped. To this end, processor 103b generates a specially defined processing stop signal and sends it to processor 103a. After sending the processing stop signal to processor 103a, it checks for a certain period of time whether processor 103a has entered a processing stop state, and then activates the address translation function of memory address translation unit 102a and transitions to the second processing mode.

[0361] In Figure 23 below, the storage system 1 is initially in a first processing mode, and requests from the host computer received by the protocol chip 101a are processed by the processor 103a, which is included in the same controller 110a as the protocol chip 101a.

[0362] In Figure 23, when the storage system 1 is in the first processing mode, the processor 103b included in a controller 110b different from the protocol chip 101a periodically obtains the state of the processor 103a included in the same controller 110a as the protocol chip 101a (step 2301).

[0363] Next, in step 2302, processor 103b determines whether processor 103a is stopped. This stopping of processor 103a includes cases where the memory 104a connected to processor 103a has become inaccessible due to a failure or other reason. If the determination shows that processor 103a is operating normally and is not stopped, the process returns to step 2301, and processor 103b periodically acquires the status of processor 103a again, and the determination in step 2302 is repeated.

[0364] If the determination shows that processor 103a has stopped, the process proceeds to step 2303, where processor 103b sends a processing stop signal to processor 103a. This processing stop signal may be sent by providing a dedicated signal line between processor 103b and processor 103a, or it may be sent from processor 103b through the mutual address translation units 105b and 105a.

[0365] In this embodiment 5, when the processor 103a receives a processing stop signal, there is a processing stop state in which the execution of the processor's instructions is stopped, and the processor transitions to this processing stop state within a certain period of time. For this reason, the processor 103a has a function that automatically transitions to the processing stop state by hardware when it receives a processing stop signal. Furthermore, even if the processor 103a cannot transition to the processing stop state within a certain period of time when it receives a processing stop signal due to a failure or the like, it can be assumed that the execution of the processor's instructions has stopped after a certain period of time has elapsed.

[0366] In Figure 23, in step 2304, processor 103b obtains whether the state of processor 103a has entered a processing stop state. In step 2305, processor 103b determines whether the obtained state of processor 103a is in a processing stop state. If the determination is that it is in a processing stop state, the process proceeds to step 2307.

[0367] If the determination shows that the processing is not stopped, the process proceeds to step 2306 to determine if a predetermined period of time has elapsed since the processing stop signal was sent. If the predetermined period of time has not elapsed, the process returns to step 2304 to determine again whether the state of the processor 103a has entered the processing stop state.

[0368] In step 2305, if it is determined that the processor 103a is in a stopped processing state, or if it is determined that a certain amount of time has elapsed since the stop processing signal was sent in step 2306, the process proceeds to step 2307, where the processor 103b enables the address translation function of the memory address translation unit 102a and transitions the storage system 1 to the second processing mode.

[0369] The setting signal to enable the address translation function of the memory address translation unit 102a may be sent from the processor 103b to the memory address translation unit 102a via the mutual address translation units 105b, 105a and processor 103a as shown in Figure 1, or a dedicated signal line may be provided specifically for this purpose between the processor 103b and the memory address translation unit 102a.

[0370] Next, in step 2308, the processor 103b starts processing the request from the host computer stored in memory 104b, and stores the response resulting from processing the request from the host computer in memory 104b.

[0371] Finally, in this embodiment 5, an example in which, after the storage system 1 transitions to the second processing mode, the processor 103b processes a copy of the request from the host computer that the processor 103a stored in the memory 104b of the processor 103b will be explained using Figure 24.

[0372] In Figure 24, when processor 103b transitions to the second processing mode, it searches memory 104b for a copy of the request from the host computer that processor 103a stored in the first processing mode (step 2401).

[0373] Next, in step 2402, it is determined whether the search results show any copies of the requests from the host computer that the processor 103a stored in the first processing mode. If the determination shows that there are no copies of the requests from the host computer that the processor 103a stored in the first processing mode, the process proceeds to step 2408, and in a new second processing mode, the processing of the requests from the host computer stored in the memory 104b of the processor 103b is started from the protocol chip 101a, through the memory address translation unit 102a, the processor 103a, and the mutual address translation units 105a and 105b. The processing sequence for requests from the host computer in this second processing mode is the same as the processing sequence described in Figures 4 and 5 of Embodiment 1.

[0374] In step 2402, if it is determined that there is a copy of the request from the host computer stored by processor 103a in the first processing mode, the process proceeds to step 2403, where processor 103b searches memory 104b for a copy of the response resulting from processing the request from the host computer, which processor 103a stored in the first processing mode. In step 2404, if a copy of the response resulting from processing the request from the host computer is found, the process returns to step 2401, and the search continues to determine if there are any other requests from the host computer stored by processor 103a in the first processing mode in memory 104b.

[0375] In step 2404, if there is no copy of the response resulting from processing the request from the host computer, the process proceeds to step 2405, where the processor 103b processes the request from the host computer. Furthermore, in step 2406, the processor 103b stores the response resulting from processing the request from the host computer in memory 104b, and in step 2407, it notifies the protocol chip 101a that the response resulting from processing the request from the host computer has been stored in memory 104b, and instructs the protocol chip 101a to send it back to the host computer.

[0376] The processing sequence from step 2405 to step 2407, which processes the request from the host computer and sends the response of the processing result back to the host computer from the protocol chip 101a, is the same as the processing sequence described in Figures 4 and 5 in Embodiment 1, except that it starts with the request from the host computer being stored in memory 104b. That is, if the request from the host computer is a Read request, it is the same as sequence 402 onwards in Figure 4 of Embodiment 1, and if the request from the host computer is a Write request, it is the same as sequence 502 onwards in Figure 5 of Embodiment 1.

[0377] In step 2407, after processing the request from the host computer is completed and the response of the processing result is notified to the protocol chip 101a and sent back to the host computer, the process returns to step 2401 and continues searching for any other requests from the host computer stored by the processor 103a in the first processing mode in memory 104b.

[0378] As described above, when the storage system 1 transitions from the first processing mode to the second processing mode, if the processor 103a stores the request from the host computer sent from the protocol chip 101a in the memory 104a, but the processing of the request from the host computer is not completed and the response resulting from processing the request from the host computer cannot be stored in the memory 104a, the processor 103b processes the request from the host computer by copying the request from the host computer stored in the memory 104b, notifies the protocol chip 101a of the response resulting from the processing, has it sent back to the host computer, and the processing can be completed.

[0379] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations.

[0380] Furthermore, some or all of the above configurations, functions, and processing units may be implemented in hardware, for example, by designing them as integrated circuits. Alternatively, the above configurations and functions may be implemented in software by having the processor interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD, or a recording medium such as an IC card or SD card.

[0381] Furthermore, the control lines and information lines shown are those deemed necessary for explanatory purposes, and not all control lines and information lines are necessarily shown in the actual product. In practice, it is reasonable to assume that almost all components are interconnected. [Explanation of Symbols]

[0382] 1,2,3: Storage Systems 101a, 101b, 121a, 121b: Protocol chip 102a, 102b, 122a, 121b: Memory address translation section 103a, 103b, 131a, 131b: Processors 104a, 104b, 132a, 132b: Memory 105a, 105b, 123a, 123b: Mutual address conversion section 106a, 106b, 141a, 142b: Backend switches 107a, 107b, 107c, 107d, 107e, 107f, 107g, 107h, 142a, 142b, 142c, 142d, 142e, 142f, 142g, 142h: Memory devices 110a, 110b, 111a, 111b: Controller 112a, 112b: Protocol chip (with conversion function) 120a, 120b: Interface section 130a, 130b: Processor board section 140: Drive Box Section

Claims

1. A storage system that connects to a host computer and stores or outputs data according to requests from the host computer, Includes multiple controllers, The first controller among the plurality of controllers is A first protocol chip that connects to the host computer and performs protocol processing for data communication with the host computer, A first processor that controls the storage system, Includes a first memory connected to the first processor and storing data necessary for controlling the storage system, The second controller, which is different from the first controller among the plurality of controllers, A second processor that controls the storage system, It includes a second memory connected to the second processor and storing data necessary for controlling the storage system, The storage system further includes a mutual address translation unit that converts between addresses used by the first processor and addresses used by the second processor. The processing mode of the storage system includes a first processing mode and a second processing mode. In the first processing mode, The first protocol chip stores the request received from the host computer in the first memory. The first processor processes the request from the host computer stored in the first memory, and stores the response of the processing result in the first memory. The first protocol chip reads the response from the first memory as a result of processing the request from the host computer and sends the response to the host computer. In the second processing mode, The first protocol chip stores the request received from the host computer in the second memory via the mutual address translation unit. The second processor processes the request from the host computer stored in the second memory, and stores the response of the processing result in the second memory. The first protocol chip reads the response resulting from processing the request from the host computer from the second memory via the mutual address translation unit and sends it to the host computer. Storage system.

2. A storage system according to claim 1, The first protocol chip stores requests from the host computer in the first memory and reads responses from the first memory as a result of processing the requests from the host computer, using an address that indicates the first memory among the addresses used by the first processor. The first controller includes a first memory address translation unit, The first memory address translation unit translates an address indicating the first memory among the addresses used by the first processor used by the first protocol chip to an address indicating the second memory among the addresses used by the first processor, so that in the second processing mode, it stores a request from the host computer in the second memory through the mutual address translation unit and reads the response resulting from processing the request from the host computer from the second memory through the mutual address translation unit. Storage system.

3. A storage system according to claim 2, The second controller includes a second protocol chip that connects to the host computer and performs protocol processing for data communication with the host computer. The processing modes of the storage system include a third processing mode and a fourth processing mode. In the third processing mode described above, The second protocol chip stores the request received from the host computer in the second memory. The second processor processes the request from the host computer stored in the second memory, and stores the response of the processing result in the second memory. The second protocol chip reads the response from the second memory as a result of processing the request from the host computer and sends the response to the host computer. In the aforementioned fourth processing mode, The second protocol chip stores the request received from the host computer in the first memory via the mutual address translation unit. The first processor processes the request from the host computer stored in the first memory, and stores the response of the processing result in the first memory. The second protocol chip reads the response resulting from processing the request from the host computer from the first memory via the mutual address translation unit and sends it to the host computer. The second protocol chip stores requests from the host computer in the second memory and reads responses from the second memory as a result of processing the requests from the host computer, using an address that indicates the second memory among the addresses used by the second processor. The second controller includes a second memory address translation unit, The second memory address translation unit, in the fourth processing mode, translates an address indicating the second memory among the addresses used by the second processor used by the second protocol chip to an address indicating the first memory among the addresses used by the second processor, so as to store the request from the host computer in the first memory through the mutual address translation unit and read the response resulting from processing the request from the host computer from the first memory through the mutual address translation unit. The aforementioned mutual address translation unit is a storage system connected to the first memory address translation unit and the second memory address translation unit.

4. A storage system according to claim 1, In the first processing mode, the first protocol chip uses an address that indicates the first memory among the addresses used by the first processor to store a request from the host computer in the first memory and read a response from the first memory as a result of processing the request from the host computer. In the second processing mode, the first protocol chip uses an address that indicates the second memory among the addresses used by the first processor, such that it stores the request from the host computer in the second memory through the mutual address translation unit and reads the response resulting from processing the request from the host computer from the second memory through the mutual address translation unit. Storage system.

5. A storage system according to claim 4, In the first processing mode, the second processor, An instruction is sent to the first protocol chip to stop storing requests from the host computer in the first memory. In the first protocol chip, the storage location for requests from the host computer and the source from which responses resulting from processing requests from the host computer are read are changed from the first memory to the second memory. By sending an instruction to the first protocol chip to begin storing the request from the host computer in the second memory, The process transitions to the second processing mode described above. Storage system.

6. A storage system according to claim 1, In the first processing mode, the first processor, The request from the host computer is read from the first memory, When processing a request from the host computer is interrupted, information to inform the host computer that processing of the request from the host computer has been interrupted is stored in the second memory via the mutual address translation unit. If the processing of the request from the host computer is not interrupted, The response resulting from the processing is stored in the first memory. Information indicating that the response resulting from processing the request from the host computer has been stored in the first memory is stored in the second memory via the mutual address translation unit. In the second processing mode, the second processor interrupts processing of a request from the host computer, Information to inform the host computer that the processing of the request from the host computer has been interrupted is read from the second memory. The first protocol chip sends an instruction to the host computer to send information to the host computer that indicates that the processing of the request from the host computer has been interrupted. Storage system.

7. A storage system according to claim 2, The first memory address translation unit, in the first processing mode, The first protocol chip replicates the requests from the host computer to be stored in the first memory. The replicated request is stored in the second memory through the mutual address translation unit. Storage system.

8. A storage system according to claim 7, The second processor detects that the processing of the first processor has completely stopped, The second processor changes the processing of the storage system from the first processing mode to the second processing mode. Storage system.

9. A storage system according to claim 3, The first controller includes a first interface unit and a first processor board unit. The first interface unit includes the first protocol chip and the first memory address translation unit. The first processor board includes the first processor and the first memory. The second controller includes a second interface section and a second processor board section. The second interface unit includes the second protocol chip and the second memory address translation unit. The second processor board includes the second processor and the second memory. The first processor board is configured to be replaceable independently of the first interface section. During the replacement of the first processor board, in the second processing mode, requests received by the first protocol chip from the host computer are stored in the second memory, and the response resulting from processing the requests received by the first protocol chip from the host computer is read from the second memory by the first protocol chip. The second processor board is configured to be replaceable independently of the second interface section. During the replacement of the second processor board, in the fourth processing mode, requests received by the second protocol chip from the host computer are stored in the first memory, and the response resulting from processing the requests received by the second protocol chip from the host computer is read from the first memory by the second protocol chip. Storage system.

Images