Semiconductor equipment

Abstract

To provide a semiconductor device that enables miniaturization of diodes. [Solution] The semiconductor device according to the embodiment includes a semiconductor layer and a diode. The semiconductor layer includes an element region on which a semiconductor element is provided and an outer peripheral region located around the element region along a first surface. The diode is provided on the outer peripheral region via an insulating layer and contains polysilicon. The diode includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region includes a first extension portion extending in a first direction parallel to the first surface and a plurality of first protrusions projecting from the first extension portion in a second direction parallel to the first surface and perpendicular to the first direction. The second semiconductor region includes a second extension portion extending in a first direction and a plurality of second protrusions projecting from the second extension portion in a second direction. The second semiconductor region is in contact with the first semiconductor region. The plurality of first protrusions and the plurality of second protrusions are arranged alternately in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device.

Background Art

[0002] There is a semiconductor device incorporating a diode. For this semiconductor device, a technology capable of miniaturizing the diode is required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the embodiments of the present invention is to provide a semiconductor device capable of miniaturizing a diode.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor layer and a diode. The semiconductor layer includes an element region provided with a semiconductor element and an outer peripheral region located around the element region along a first surface. The diode is provided on the outer peripheral region via an insulating layer and contains polysilicon. The diode includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first semiconductor region includes a first extending portion extending in a first direction parallel to the first surface and a plurality of first protruding portions protruding from the first extending portion in a second direction parallel to the first surface and perpendicular to the first direction. The second semiconductor region includes a second extending portion extending in the first direction and a plurality of second protruding portions protruding from the second extending portion in the second direction. The second semiconductor region is in contact with the first semiconductor region. The plurality of first protruding portions and the plurality of second protruding portions are alternately provided in the first direction. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] Figure 2 is an enlarged plan view of part II of Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along line III-III in Figure 2. [Figure 4] Figure 4(a) is a plan view showing a diode in a semiconductor device according to a reference example. Figure 4(b) is a schematic graph showing the electric field strength along the BB line in Figure 4(a). [Figure 5] Figure 5(a) is a plan view showing a diode in a semiconductor device according to the embodiment. Figure 5(b) is a schematic graph showing the electric field strength along line BB in Figure 5(a). [Figure 6] Figure 6 is a plan view showing a diode in a semiconductor device according to the embodiment. [Figure 7] Figure 7 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. [Figure 8] Figure 8(a) is a plan view showing a semiconductor device according to an embodiment. Figure 8(b) is a bottom view showing a semiconductor device according to an embodiment. [Figure 9] Figure 9 is an electrical circuit diagram of a semiconductor device according to an embodiment. [Figure 10] Figure 10 is a magnified plan view of the cathode electrode in Figure 8(a). [Figure 11] Figure 11(a) is an enlarged plan view of section XA in Figure 10. Figure 11(b) is an enlarged plan view of section XB in Figure 10. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of reality. Furthermore, even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each drawing, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] Figure 1 is a plan view showing a semiconductor device according to an embodiment. As shown in Figure 1, the semiconductor device 1 according to the embodiment includes a semiconductor layer 100 and a diode 200.

[0009] In describing the embodiments, the XYZ Cartesian coordinate system is used. Two directions parallel to the surface of the semiconductor layer 100 and mutually orthogonal are defined as the X direction (an example of a first direction) and the Y direction (an example of a second direction). The direction perpendicular to the X and Y directions is defined as the Z direction. For the sake of explanation, the direction from one surface of the semiconductor layer 100 to the other surface is referred to as "up," and the opposite direction is referred to as "down." These directions are unrelated to the direction of gravity.

[0010] The semiconductor layer 100 includes an element region R1 and an outer peripheral region R2. In the drawing, the element region R1 and the outer peripheral region R2 are shown by dashed lines. A semiconductor element is provided in the element region R1. The semiconductor element is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), etc. The semiconductor element may be a vertical element with electrodes provided on the top and bottom surfaces of the semiconductor layer, respectively. Alternatively, the semiconductor element may be a horizontal element with electrodes provided only on the top surface of the semiconductor layer.

[0011] In the illustrated example, the element region R1 includes a vertical MOSFET or IGBT. An upper electrode 101, electrically connected to the semiconductor element, is provided above the element region R1. A lower electrode (not shown), electrically connected to the semiconductor element, is provided below the element region R1.

[0012] The outer peripheral region R2 is located around the element region R1 in the X-Y plane (the first plane). The diode 200 is provided on the outer peripheral region R2. The diode 200 may be electrically connected to the semiconductor element or may be electrically separated from the semiconductor element.

[0013] Figure 2 is an enlarged plan view of part II of Figure 1. Figure 3 is a cross-sectional view taken along the line III-III of Figure 2. As shown in Figure 2, the diode 200 includes a first semiconductor region 210 and a second semiconductor region 220. The first semiconductor region 210 has one of the conductivity types of n-type and p-type. The second semiconductor region 220 has the other conductivity type of n-type and p-type. In the illustrated example, the conductivity type of the first semiconductor region 210 is n-type (an example of the first conductivity type), and the conductivity type of the second semiconductor region 220 is p-type (an example of the second conductivity type).

[0014] The first semiconductor region 210 and the second semiconductor region 220 are in contact with each other, and a pn junction is formed between the first semiconductor region 210 and the second semiconductor region 220. As shown in Figure 3, the first semiconductor region 210 and the second semiconductor region 220 are provided on the semiconductor layer 100 via an insulating layer 105. Also, a lower electrode 102 electrically connected to the semiconductor element in the element region R1 is provided under the semiconductor layer 100. As shown in Figure 3, the lower electrode 102 may be provided not only in the region under the element region R1 but also in the region under the outer peripheral region R2.

[0015] As shown in Figure 2, the first semiconductor region 210 includes a first extending portion 211 and a plurality of first protruding portions 212. In Figure 2, the first extending portion 211 and the first protruding portions 212 are indicated by a two-dot chain line. The first extending portion 211 extends in the X direction. That is, the length of the first extending portion 211 in the X direction is longer than the length of the first extending portion 211 in the Y direction. The plurality of first protruding portions 212 are separated from each other in the X direction. Each first protruding portion 212 protrudes from the first extending portion 211 in the Y direction.

[0016] The second semiconductor region 220 includes a second extension 221 and a plurality of second protrusions 222. In the drawing, the second extension 221 and the second protrusions 222 are shown by dashed lines. The second extension 221 extends in the X direction. The plurality of second protrusions 222 are spaced apart from each other in the X direction. Each second protrusion 222 protrudes from the second extension 221 in the Y direction. The plurality of first protrusions 212 and the plurality of second protrusions 222 are arranged alternately in the X direction.

[0017] As shown in Figures 2 and 3, the first semiconductor region 210 and the second semiconductor region 220 may be arranged alternately in the Y direction. In this case, the first semiconductor region 210 includes a plurality of first protrusions 212a projecting to one side in the Y direction and a plurality of first protrusions 212b projecting to the other side in the Y direction. The first extension 211 is located between the plurality of first protrusions 212a and the plurality of first protrusions 212b.

[0018] Similarly, the second semiconductor region 220 includes a plurality of second protrusions 222a projecting to one side in the Y direction and a plurality of second protrusions 222b projecting to the other side in the Y direction. The second extension 221 is located between the plurality of second protrusions 222a and the plurality of second protrusions 222b.

[0019] The position of each first projection 212a in the X direction is different from the position of each first projection 212b in the X direction. When viewed from the Y direction, the multiple first projections 212a and multiple first projections 212b are arranged alternately in the X direction. Similarly, the position of each second projection 222a in the X direction is different from the position of each second projection 222b in the X direction. When viewed from the Y direction, the multiple second projections 222a and multiple second projections 222b are arranged alternately in the X direction.

[0020] The semiconductor layer 100 contains a semiconductor material such as silicon, silicon carbide, or gallium nitride. The upper electrode 101 contains a metallic material such as aluminum, titanium, or tungsten. The insulating layer 105 contains an insulating material such as silicon oxide or silicon nitride. The first semiconductor region 210 and the second semiconductor region 220 contain polysilicon. Arsenic, phosphorus, or antimony can be used as n-type impurities. Boron or aluminum can be used as p-type impurities. The first semiconductor region 210 and the second semiconductor region 220 can be formed by ion implanting n-type and p-type impurities into the polysilicon layer, respectively.

[0021] The n-type impurity concentration in the first semiconductor region 210 may be the same as the p-type impurity concentration in the second semiconductor region 220, or it may be different from the p-type impurity concentration in the second semiconductor region 220. For example, p-type impurities are ion-implanted across the entire region where the diode 200 is formed, and then n-type impurities are ion-implanted into a portion of that region. In this case, the n-type impurity concentration in the first semiconductor region 210 will be higher than the p-type impurity concentration in the second semiconductor region 220. For example, the n-type impurity concentration in the first semiconductor region 210 may be 6.0 × 10⁻⁶. 14 cm -3 The above 3.0 × 10 16 cm -3 The following is true: The p-type impurity concentration in the second semiconductor region 220 is 1.0 × 10⁻⁶. 14 cm -3 The above 7.0 x 10 15 cm -3 The following applies:

[0022] The advantages of the embodiment will be explained. Diodes may be incorporated into semiconductor devices. For example, as shown in Figure 1, a semiconductor device such as a MOSFET or IGBT is provided in the element region R1, and a diode 200 is provided on the outer region R2. In this case, the outer region R2 is an inactive region that does not directly contribute to the operation of the semiconductor device. For miniaturization of semiconductor devices, it is preferable that the inactive region be small. In order to reduce the inactive region, it is preferable that the diode 200 be small.

[0023] Figure 4(a) is a plan view showing a diode in a semiconductor device according to a reference example. Figure 4(b) is a schematic graph showing the electric field strength along the BB line in Figure 4(a). In the diode 200r shown in Figure 4(a), the first semiconductor region 210r and the second semiconductor region 220r extend in the X direction. The first semiconductor region 210r and the second semiconductor region 220r do not contain any portions that protrude in the Y direction. The pn junction between the first semiconductor region 210r and the second semiconductor region 220r is parallel to the X direction.

[0024] When a reverse voltage is applied to diode 200r, a depletion layer extends in the Y direction from the pn junction between the first semiconductor region 210r and the second semiconductor region 220r. The electric field strength at this time is as shown in Figure 4(b). In Figure 4(b), the horizontal axis represents the position P in the Y direction, and the vertical axis represents the electric field strength E. In the diode 200r according to the reference example, the electric field strength E decreases as it moves away from the pn junction.

[0025] Figure 5(a) is a plan view showing a diode in a semiconductor device according to the embodiment. Figure 5(b) is a schematic graph showing the electric field strength along line BB in Figure 5(a). In this embodiment, the first semiconductor region 210 includes a plurality of first protrusions 212, and the second semiconductor region 220 includes a plurality of second protrusions 222. The plurality of first protrusions 212 and the plurality of second protrusions 222 are arranged alternately in the X direction. The diode 200 includes a pn junction J1 between a first extension 211 and a second protrusion 222, a pn junction J2 between a first protrusion 212 and a second extension 221, and a pn junction J3 between a first protrusion 212 and a second protrusion 222.

[0026] When a reverse voltage is applied to diode 200, the depletion layer expands in the Y direction from pn junctions J1 and J2, and also expands in the X direction from pn junction J3. The electric field strength at this time is as shown in Figure 5(b). In Figure 5(b), the horizontal axis represents the position P in the Y direction, and the vertical axis represents the electric field strength E. With diode 200, the expansion of the depletion layer in the X direction from pn junction J3 makes it possible to keep the electric field strength at the first protrusion 212 approximately constant in the Y direction.

[0027] The breakdown voltage is expressed as the value obtained by integrating the electric field strength E with respect to position P. In the semiconductor device according to the reference example, the electric field strength E in the diode decreases as it moves away from the pn junction. In contrast, in the semiconductor device according to the embodiment, the electric field strength at the first protrusion 212 and the electric field strength at the second protrusion 222 are substantially constant in the Y direction. The breakdown voltage of the diode 200 can be improved by the amount by which these electric field strengths are improved.

[0028] If the diode area is the same, according to this embodiment, the diode's breakdown voltage can be increased compared to the reference example. Alternatively, according to this embodiment, the diode area required to obtain a specific breakdown voltage can be reduced compared to the reference example. As a result, the inactive region in the semiconductor device 1 can be reduced, and the semiconductor device 1 can be miniaturized.

[0029] Figure 6 is a plan view showing a diode in a semiconductor device according to the embodiment. Referring to Figure 6, a preferred structure of the embodiment will be described. For example, the ratio of length L2y to length L3y, which is the sum of length L1y of the first extension 211 in the Y direction and length L2y of one first projection 212 in the Y direction, is 0.1 or more and 0.9 or less. The larger the ratio (L2y / L3y), the greater the proportion of the area with high electric field strength, and the higher the breakdown voltage of the diode 200. For this reason, the ratio (L2y / L3y) is preferably 0.2 or more, and more preferably 0.3 or more. On the other hand, if the ratio (L2y / L3y) is excessively large, the forward voltage Vf will be large. For this reason, the ratio (L2y / L3y) is preferably 0.8 or less, and more preferably 0.7 or less.

[0030] Similarly, the ratio of length L5y to length L6y, which is the sum of length L4y of the second extension portion 221 in the Y direction and length L5y of one second projection portion 222 in the Y direction, is, for example, 0.1 or more and 0.9 or less. From the viewpoint of improving withstand voltage, the ratio (L5y / L6y) is preferably 0.2 or more, and more preferably 0.3 or more. In order to suppress the increase in forward voltage Vf, the ratio (L5y / L6y) is preferably 0.8 or less, and more preferably 0.7 or less.

[0031] Lengths L2y and L5y are specifically designed to be 0.2 μm or longer. From the viewpoint of improving pressure resistance, lengths L2y and L5y are preferably 0.5 μm or longer, and more preferably 1.0 μm or longer.

[0032] The ratio (L5x / L2x) of the length L5x of one second protrusion 222 in the X direction to the length L2x of one first protrusion 212 in the X direction is 0.1 or more and 10 or less. The difference between the effective n-type impurity concentration in the first semiconductor region 210 and the effective p-type impurity concentration in the second semiconductor region 220 is preferably small, and more preferably substantially the same. "Effective impurity concentration" refers to the impurity concentration after compensation when both n-type and p-type impurities are contained in one region. When only either n-type or p-type impurities are contained in one region, that n-type or p-type impurity concentration can be considered the effective impurity concentration. When the difference between the effective n-type impurity concentration in the first semiconductor region 210 and the effective p-type impurity concentration in the second semiconductor region 220 is small, the ratio (L5x / L2x) is preferably as close to 1 as possible. Therefore, the ratio (L5x / L2x) is preferably 0.2 or more and 9 or less, and more preferably 0.3 or more and 8 or less.

[0033] The ratio (L2y / L2x) of the length L2y of one first protrusion 212 in the Y direction to the length L2x of one first protrusion 212 in the X direction is, for example, 0.1 or more and 10 or less. The shorter the length L2x, the more first protrusions 212 can be placed per unit area, thereby improving the breakdown voltage of the diode 200. Also, the longer the length L2y, the more the proportion of the area with high electric field strength can be increased, thereby improving the breakdown voltage of the diode 200. For this reason, the ratio (L2y / L2x) is preferably 0.2 or more, and more preferably 0.3 or more. On the other hand, if the ratio (L2y / L3y) is excessively large, the forward voltage Vf will be large. For this reason, the ratio (L2y / L2x) is preferably 9 or less, and more preferably 8 or less.

[0034] Similarly, the ratio (L5y / L5x) of the length L5y of one second protrusion 222 in the Y direction to the length L5x of one second protrusion 222 in the X direction is, for example, 0.1 or more and 10 or less. From the viewpoint of improving withstand voltage, the ratio (L5y / L5x) is preferably 0.2 or more, and more preferably 0.3 or more. In addition, in order to suppress the increase in the forward voltage Vf, the ratio (L5y / L5x) is preferably 9 or less, and more preferably 8 or less.

[0035] Embodiments of the present invention are particularly suitable for semiconductor devices 1 that use a silicon carbide semiconductor layer 100. The silicon carbide semiconductor layer 100 is significantly more expensive than silicon or gallium nitride. According to the embodiment, the diode 200 can be miniaturized, and the peripheral region R2 can be reduced. By reducing the peripheral region R2, the semiconductor layer 100 can be made smaller, and as a result, the cost of the semiconductor device 1 can be reduced.

[0036] (modified version) Figure 7 is a plan view showing a part of a semiconductor device according to a modified example of the embodiment. In the examples shown in Figures 2 and 6, the position of the first protrusion 212a in the X direction is different from the position of the first protrusion 212b in the X direction. The position of the second protrusion 222a in the X direction is different from the position of the second protrusion 222b in the X direction. In the example shown in Figure 7, the position of the first protrusion 212a in the X direction is the same as the position of the first protrusion 212b in the X direction. Also, the position of the second protrusion 222a in the X direction is the same as the position of the second protrusion 222b in the X direction. Thus, the positional relationship between the first protrusion 212a and the first protrusion 212b, and the positional relationship between the second protrusion 222a and the second protrusion 222b can be changed as appropriate.

[0037] (Examples) Figure 8(a) is a plan view showing a semiconductor device according to an embodiment. Figure 8(b) is a bottom view showing a semiconductor device according to an embodiment. The semiconductor device 2 according to the embodiment includes an IGBT 110 as a semiconductor element. As shown in Figure 8(a), in the element region R1, a plurality of emitter electrodes 111 are provided on the upper surface of the semiconductor layer 100. As shown in Figure 8(b), in the element region R1 and the outer peripheral region R2, a collector electrode 112 is provided on the lower surface of the semiconductor layer 100.

[0038] A sense diode 120 is further provided above the element region R1. The sense diode 120 is used to measure temperature. The sense diode 120 is located between the emitter electrodes 111.

[0039] An anode electrode 121, a cathode electrode 122, and a gate pad 123 are provided on the outer peripheral region R2. The anode electrode 121, cathode electrode 122, and gate pad 123 are spaced apart from each other.

[0040] The anode electrode 121 is electrically connected to the anode side of the sense diode 120, and the cathode electrode 122 is electrically connected to the cathode side of the sense diode 120. In semiconductor device 2, diode 200 is provided in the same location as cathode electrode 122. The gate pad 123 is electrically connected to the gate electrode of IGBT 110.

[0041] Figure 9 is an electrical circuit diagram of a semiconductor device according to an embodiment. As shown in Figure 9, in semiconductor device 2, diode 200 is connected between the emitter electrode 111 of IGBT 110 and the cathode side of sense diode 120. Diode 200 functions as a Zener diode.

[0042] Figure 10 is a magnified plan view of the cathode electrode in Figure 8(a). As shown in Figure 10, the first semiconductor region 210 and the second semiconductor region 220 are provided along the outer circumference of the cathode electrode 122. The first semiconductor region 210 and the second semiconductor region 220 are arranged alternately in the direction away from the cathode electrode 122. By providing the first semiconductor region 210 and the second semiconductor region 220 around the cathode electrode 122, the area of ​​the pn junction between the first semiconductor region 210 and the second semiconductor region 220 can be increased. An electrode layer 230 electrically connected to the emitter electrode 111 is provided on the outer circumference of the multiple first semiconductor regions 210 and the multiple second semiconductor regions 220.

[0043] Figure 11(a) is an enlarged plan view of section XA in Figure 10. Figure 11(b) is an enlarged plan view of section XB in Figure 10. In section XA, as shown in Figure 11(a), the first extension portion 211 and the second extension portion 221 extend in the X direction. The first projection portion 212 protrudes from the first extension portion 211 in the Y direction, and the second projection portion 222 protrudes from the second extension portion 221 in the Y direction.

[0044] In section XB, as shown in Figure 11(b), the first extension portion 211 and the second extension portion 221 extend in the Y direction. The first projection portion 212 protrudes from the first extension portion 211 in the X direction, and the second projection portion 222 protrudes from the second extension portion 221 in the X direction.

[0045] As shown in Figures 11(a) and 11(b), the first semiconductor region 210 and the second semiconductor region 220 each include an extended portion that extends in one direction and a protruding portion that projects orthogonally from the extended portion. This improves the breakdown voltage of the diode 200. Alternatively, it is possible to reduce the area of ​​the diode 200 while maintaining the breakdown voltage of the diode 200. In the embodiment, the modified structure shown in Figure 7 may be applied instead of the structure shown in Figures 10(a) and 10(b).

[0046] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0047] 1,2: Semiconductor device, 100: Semiconductor layer, 101: Upper electrode, 102: Lower electrode, 105: Insulating layer, 110: IGBT, 111: Emitter electrode, 112: Collector electrode, 120: Sense diode, 121: Anode electrode, 122: Cathode electrode, 123: Gate pad, 200: Diode, 200r: Diode, 210,210r: First semiconductor region, 211: First extension, 212,212a,212b: First protrusion, 220,220r: Second semiconductor region, 221: Second extension, 222,222a,222b: Second protrusion, 230: Electrode layer, E: Electric field strength, J1~J3: pn junction, R1: Element region, R2: Outer periphery region

Claims

1. A semiconductor layer comprising an element region on which a semiconductor element is provided, and an outer peripheral region located around the element region along a first surface, A diode containing polysilicon is provided on the outer peripheral region via an insulating layer, A first semiconductor region of a first conductivity type, including a first extending portion extending in a first direction parallel to the first surface, and a plurality of first protruding portions projecting from the first extending portion in a second direction parallel to the first surface and perpendicular to the first direction, A second semiconductor region having a second conductivity type and in contact with the first semiconductor region, comprising a second extending portion extending in the first direction and a plurality of second protruding portions protruding from the second extending portion in the second direction, The diode includes, wherein the plurality of first protrusions and the plurality of second protrusions are arranged alternately in the first direction, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region are arranged alternately in the second direction.

3. The semiconductor device according to claim 1, wherein the ratio of the length of one of the plurality of first protrusions to the sum of the length of the first extension in the second direction and the length of one of the plurality of first protrusions in the second direction is 0.1 or more and 0.9 or less.

4. The semiconductor device according to claim 1, wherein the ratio of the length of one of the plurality of second protrusions in one of the first directions to the length of one of the plurality of first protrusions in one of the first directions is 0.1 or more and 10 or less.

5. The semiconductor device according to claim 1, wherein the ratio of the length of the plurality of first protrusions in one second direction to the length of one of the plurality of first protrusions in one first direction is 0.1 or more and 10 or less.

6. The semiconductor device according to claim 1, wherein the length of one of the plurality of first protrusions in the second direction and the length of one of the plurality of second protrusions in the second direction are 0.2 μm or more.

7. The first semiconductor region includes a plurality of other first protrusions that protrude from the first extension in the second direction. The first extension is located between the plurality of first protrusions and the other plurality of first protrusions, The second semiconductor region includes a plurality of other second protrusions that protrude from the second extension in the second direction. The semiconductor device according to claim 1, wherein the second extension portion is located between the plurality of second protrusions and the other plurality of second protrusions.

8. The semiconductor device according to claim 1, wherein the semiconductor element includes a MOSFET or an IGBT.

9. The electrode is further provided on the outer peripheral region via the insulating layer, The semiconductor device according to claim 8, wherein the diode is electrically connected between the semiconductor element and the electrode.

10. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor layer contains silicon carbide.

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