Semiconductor device and its manufacturing method

Abstract

This invention provides a technology to improve the reliability of semiconductor devices that have residual stress. [Solution] A semiconductor device comprising a semiconductor substrate formed by bonding a single crystal substrate and a polycrystalline substrate, having a front surface made of the single crystal substrate and a back surface made of the polycrystalline substrate, wherein the residual stress generated at the first corner between the front surface and the side surface of the semiconductor substrate is smaller than the residual stress generated at the second corner between the back surface and the side surface. In the above semiconductor device, a higher residual stress is generated at the second corner than at the first corner, making it easier for degradation cracks to occur at the second corner. In a polycrystalline substrate with a second corner, degradation cracks are less likely to propagate than in a single crystal substrate. Therefore, even if a degradation crack occurs at the second corner, the propagation of the degradation crack can be suppressed. For this reason, this structure enables high reliability of the semiconductor device.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] Patent Document 1 describes a technique for dividing a substrate. In this technique, a crack is formed by pressing a pressing member against the back surface of a semiconductor substrate. Next, the semiconductor substrate is divided starting from the crack by pressing a dividing member against the front surface of the semiconductor substrate. Hereinafter, the crack used as the starting point for dividing the semiconductor substrate may be referred to as a starting crack.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, the semiconductor substrate is divided starting from the starting crack, but there are also cases where the semiconductor substrate is divided starting from a groove. When forming the starting crack or groove, stress remains around the starting crack or groove. Cracks may occur during the use of the semiconductor device at the location where the residual stress exists. Hereinafter, the crack that occurs during the use of the semiconductor device may be referred to as a degradation crack. The reliability of the semiconductor device is reduced due to the degradation crack. This specification provides a technique for improving the reliability of a semiconductor device having residual stress.

Means for Solving the Problems

[0005] The semiconductor device disclosed herein is constructed by bonding a single crystal substrate and a polycrystalline substrate, and comprises a semiconductor substrate having a front surface made of the single crystal substrate and a back surface made of the polycrystalline substrate, wherein the residual stress occurring at the first corner between the front surface and the side surface of the semiconductor substrate is smaller than the residual stress occurring at the second corner between the back surface and the side surface.

[0006] In the semiconductor device described above, the second corner generates higher residual stress than the first corner, making it prone to degradation cracks. In a polycrystalline substrate with a second corner, degradation cracks are less likely to propagate than in a single-crystal substrate. Therefore, even if a degradation crack occurs in the second corner, its propagation can be suppressed. As a result, this structure enables high reliability in semiconductor devices.

[0007] A method for manufacturing a semiconductor device disclosed herein comprises the steps of forming a weak portion, consisting of cracks or grooves, on the back surface of a semiconductor substrate having a front surface made of the single crystal substrate and a back surface made of the polycrystal substrate, wherein the semiconductor substrate is constructed by bonding a single crystal substrate and a polycrystal substrate together.

[0008] In this manufacturing method, residual stress is generated around the weak area when it is formed. Therefore, semiconductor devices manufactured using this method have high residual stress at the corners between the back and side surfaces of the semiconductor substrate. These corners are located within the polycrystalline substrate. Therefore, even if degradation cracks occur at these corners, their propagation can be suppressed. Consequently, this manufacturing method enables high reliability in semiconductor devices. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram of the semiconductor device of the embodiment. [Figure 2] This describes a method for manufacturing a semiconductor device of an example. [Figure 3] This describes a method for manufacturing a semiconductor device of an example. [Figure 4] This describes a method for manufacturing a semiconductor device of an example. [Figure 5] This describes a method for manufacturing a semiconductor device of an example. [Figure 6] This describes a method for manufacturing a semiconductor device of an example. [Figure 7] This describes a method for manufacturing a semiconductor device of an example. [Figure 8] This describes a method for manufacturing a semiconductor device of an example. [Figure 9] This describes a method for manufacturing a semiconductor device of an example. [Figure 10] This describes a method for manufacturing a semiconductor device of an example. [Figure 11] This describes a method for manufacturing a semiconductor device of an example. [Figure 12] This is a schematic diagram of the semiconductor device of the embodiment. [Figure 13] This describes a method for manufacturing a semiconductor device of an example. [Figure 14] This describes a method for manufacturing a semiconductor device of an example.

[0010] (Structure of semiconductor device 100) The semiconductor device 100 shown in Figure 1 is a MOSFET (metal oxide semiconductor field effect transistor). The semiconductor device 100 has a semiconductor substrate 2. The semiconductor substrate 2 is made of SiC.

[0011] The semiconductor substrate 2 has a single crystal substrate 10 and a polycrystalline substrate 30. The single crystal substrate 10 is composed of single crystal SiC. The polycrystalline substrate 30 is composed of polycrystalline SiC. The upper surface of the polycrystalline substrate 30 is bonded to the lower surface of the single crystal substrate 10. That is, the semiconductor substrate 2 is configured by bonding the single crystal substrate 10 and the polycrystalline substrate 30 together. The thickness of the single crystal substrate 10 is several μm. The thickness of the polycrystalline substrate 30 is several tens of μm. Hereinafter, the upper surface of the semiconductor substrate 2 is referred to as the front surface 2a, and the lower surface of the semiconductor substrate 2 is referred to as the back surface 2b. One main surface of the semiconductor substrate 2 is the front surface 2a, and the other main surface is the back surface 2b. The back surface 2b is the surface on the opposite side of the front surface 2a. The front surface 2a is constituted by the single crystal substrate 10, and the back surface 2b is constituted by the polycrystalline substrate 30.

[0012] A plurality of trenches 12 are provided on the front surface 2a. A gate insulating film 14, a gate electrode 16, and an interlayer insulating film 18 are provided in each trench 12. The gate insulating film 14 covers the inner surface of the trench 12. The gate electrode 16 is provided inside the gate insulating film 14. The gate electrode 16 is insulated from the single crystal substrate 10 by the gate insulating film 14. The interlayer insulating film 18 covers the upper surface of the gate electrode 16.

[0013] An n-type source layer 20, a p-type body layer 22, and an n-type drift layer 24 are provided in the single crystal substrate 10. The source layer 20 is disposed in a range partially including the front surface 2a. Also, the source layer 20 is in contact with the gate insulating film 14 on the side surface of the corresponding trench 12.

[0014] The body layer 22 is disposed in a range partially including the front surface 2a. Also, the body layer 22 extends from the side of the source layer 20 to the lower side and is in contact with the source layer 20. Also, the body layer 22 is in contact with the gate insulating film 14 on the side surface of the trench 12 below the source layer 20.

[0015] The drift layer 24 is in contact with the body layer 22. The drift layer 24 is in contact with the gate insulating film 14 on the side surface and the bottom surface of the trench 12 below the body layer 22. Further, the drift layer 24 is disposed in a range including the lower surface of the single crystal substrate 10. The n-type impurity concentration of the drift layer 24 is lower than the n-type impurity concentration of the source layer 20.

[0016] An upper electrode 40 is provided on the front surface 2a. The upper electrode 40 is in contact with the front surface 2a in a range straddling a plurality of trenches 12. The upper electrode 40 makes an ohmic contact with the source layer 20 and the body layer 22. The upper electrode 40 is insulated from each gate electrode 16 by the interlayer insulating film 18.

[0017] Hereinafter, the trench 12, the gate insulating film 14, the gate electrode 16, the interlayer insulating film 18, the source layer 20, the body layer 22, and the upper electrode 40 are referred to as an element structure 26. In the element structure 26, pn junctions are formed at the interfaces between the source layer 20 and the body layer 22 and between the body layer 22 and the drift layer 24.

[0018] An n-type drain layer 32 is provided on the polycrystalline substrate 30. The drain layer 32 is in contact with the lower surface of the drift layer 24. Further, the drain layer 32 is disposed in a range including the back surface 2b. The n-type impurity concentration of the drain layer 32 is higher than the n-type impurity concentration of the drift layer 24.

[0019] A lower electrode 42 is provided on the back surface 2b. The lower electrode 42 is composed of Ti, Ni, Au, or the like. The lower electrode 42 is in contact with the back surface 2b. The lower electrode 42 makes an ohmic contact with the drain layer 32.

[0020] (Method of manufacturing the semiconductor device 100) Next, the manufacturing method of the semiconductor device 100 will be described. Figure 2 shows the semiconductor substrate 2 before processing. Multiple semiconductor devices 100 are manufactured from the semiconductor substrate 2 shown in Figure 2. The semiconductor substrate 2 shown in Figure 2 before processing is composed of a single crystal substrate 10 and a polycrystalline substrate 30 bonded together. The single crystal substrate 10 shown in Figure 2 has the drift layer 24 described above. The polycrystalline substrate 30 shown in Figure 2 has the drain layer 32 described above.

[0021] First, the device structure formation process is carried out. As shown in Figure 3, in the device structure formation process, multiple device structures 26 described above are formed in the single crystal substrate 10. Here, as shown in Figure 4, multiple device structures 26 are formed in a matrix on the front surface 2a of the semiconductor substrate 2. In Figure 4, the planned division lines 4 extending in a grid pattern are the points where the semiconductor substrate 2 will be divided in the break process described later. The planned division lines 4 are not actual lines marked on the semiconductor substrate 2, but are virtual lines. The planned division lines 4 extend in a grid pattern along the boundaries between adjacent device structures 26.

[0022] Next, the component bonding process is carried out. As shown in Figure 5, the component bonding process is the process of bonding the support plate 44 to the front surface 2a of the semiconductor substrate 2. Note that in Figures 5 to 7, the semiconductor substrate 2 is depicted with the front surface 2a facing downwards. The support plate 44 is bonded to the front surface 2a via an adhesive 46. In other words, the adhesive 46 adheres the support plate 44 to the front surface 2a of the semiconductor substrate 2. Here, the adhesive 46 is applied so that its thickness is greater than the thickness of the upper electrode 40. The support plate 44 is made of, for example, a glass plate. The adhesive 46 is made of, for example, a silicone-based adhesive.

[0023] Next, the scribing process is performed. As shown in Figure 6, in the scribing process, a scribe wheel 48, which is a pressing member, is pressed against the back surface 2b of the semiconductor substrate 2. The scribe wheel 48 is a disc-shaped member and is pivotally supported by a support device (not shown). The scribe wheel 48 is also rotatable. The scribe wheel 48 has a sharp outer edge, but it does not cut the semiconductor substrate 2. That is, the scribe wheel 48 is simply pressed against the back surface 2b. In the scribing process, the scribe wheel 48 is moved so that it rolls while being pressed against the back surface 2b of the semiconductor substrate 2. In addition, in the scribing process, the scribe wheel 48 is moved along each of the planned division lines 4 shown in Figure 4.

[0024] When the back surface 2b of the semiconductor substrate 2 is pressed by the scribe wheel 48, a crack 50 (i.e., an origin crack) is formed directly beneath the scribe wheel 48 along the thickness direction. The crack 50 is formed on the back surface 2b of the semiconductor substrate 2. In addition, high stress is applied to both sides of the crack 50, so regions 51 where high stress remains are formed on both sides of the crack 50.

[0025] Next, the electrode formation process is carried out. As shown in Figure 7, in the electrode formation process, a lower electrode 42 is formed on the back surface 2b of the semiconductor substrate 2. The lower electrode 42 is composed of a multilayer film made up of, for example, titanium, nickel, and gold.

[0026] Next, the retaining tape application process is carried out. As shown in Figure 8, in the retaining tape application process, the retaining tape 52 is adhered to the surface of the lower electrode 42. Note that in Figures 8 and onward, the semiconductor substrate 2 is depicted with its front surface 2a facing upward. The retaining tape 52 is, for example, a dicing tape. The outer periphery of the retaining tape 52 is fixed by a frame (not shown).

[0027] Next, a component peeling process is performed. As shown in Figure 9, in the component peeling process, the support plate 44 is peeled off from the adhesive 46. The adhesive 46 is also peeled off from the front surface 2a of the semiconductor substrate 2.

[0028] Next, the protective member attachment process is carried out. As shown in Figure 10, the protective member attachment process involves attaching the protective member 53 so that it spans the front surface 2a of the semiconductor substrate 2 and the surface of the upper electrode 40.

[0029] Next, the breaking process is performed. As shown in Figure 11, in the breaking process, the semiconductor substrate 2 is placed on two support bases 54. The semiconductor substrate 2 is placed on the support bases 54 so that the exposed surface of the holding tape 52 (i.e., the surface opposite to the semiconductor substrate 2) is in contact with the support bases 54. The two support bases 54 are spaced apart. When the semiconductor substrate 2 is placed on the support bases 54, the semiconductor substrate 2 is placed so that this spacing is located below the planned dividing line 4. Next, the break bar 56, which is a dividing member, is pressed against the front surface 2a of the semiconductor substrate 2 via the protective member 53. At this time, the break bar 56 is pressed against the front surface 2a of the semiconductor substrate 2 along the planned dividing line 4. The break bar 56 is a plate-shaped member. Although the lower end of the break bar 56 has a sharp structure, it does not cut the semiconductor substrate 2. That is, the break bar 56 is only pressed against the semiconductor substrate 2.

[0030] Since there is no support base 54 below the break bar 56 (i.e., the space between the two support bases 54 is located there), when the break bar 56 is pressed against the front surface 2a, the semiconductor substrate 2 bends so that it fits into the space between the two support bases 54. Here, the crack 50 is formed on the back surface 2b of the semiconductor substrate 2. Therefore, when the break bar 56 is pressed against the front surface 2a of the semiconductor substrate 2, the semiconductor substrate 2 bends around the pressed portion (line) as an axis, and on the back surface 2b, a force is applied in a direction that pulls the two element structures 26 adjacent to the splitting position away from the crack 50. Therefore, when the break bar 56 is pressed against the front surface 2a, the crack 50 extends in the thickness direction of the semiconductor substrate 2, and the semiconductor substrate 2 cleaves along the crystal plane starting from the crack 50. As a result, the semiconductor substrate 2 is split. In the breaking process, the process of pressing the break bar 56 against the front surface 2a along the planned splitting line 4 is repeatedly performed. This allows the semiconductor substrate 2 to be divided along the boundaries of each element structure 26. Then, the retaining tape 52 is peeled off from the back surface 2b of the semiconductor substrate 2. As a result, as shown in Figure 1, the semiconductor substrate 2 is separated into individual semiconductor devices 100.

[0031] In the above manufacturing method, as shown in Figure 6, residual stress is generated in the region 51 adjacent to the crack 50. Therefore, when the semiconductor device 100 is manufactured using the above manufacturing method, as shown in Figure 1, a region 51 with high residual stress is formed around the corner 62 between the back surface 2b and the side surface 2c of the semiconductor substrate 2. Furthermore, since the side surface 2c is formed by cleavage starting from the crack 50, almost no residual stress is generated in the side surface 2c above the region 51 (towards the front surface 2a). Therefore, the residual stress generated at the corner 64 between the front surface 2a and the side surface 2c is smaller than the residual stress generated at the corner 62 between the back surface 2b and the side surface 2c.

[0032] As shown in Figure 12, during use of the semiconductor device 100, cracks C (i.e., degradation cracks) are likely to occur in regions 51 with high residual stress. In this embodiment, regions 51 with high residual stress (i.e., corners 62) are located within the polycrystalline substrate 30. Since numerous crystal interfaces exist within the polycrystalline substrate 30, cracks are less likely to propagate in the polycrystalline substrate 30 compared to the single-crystal substrate 10. Therefore, even if a crack C occurs at a corner 62, it is difficult for the crack C to propagate. Furthermore, the propagation of crack C is also easily stopped at the interface between the polycrystalline substrate 30 and the single-crystal substrate 10. Therefore, in the semiconductor device 100 of this embodiment, crack C is less likely to reach the device structure 26. As a result, even if a crack C occurs, the characteristics of the MOSFET are less likely to deteriorate. Consequently, the performance of the semiconductor device 100 can be maintained.

[0033] In the scribe process of the embodiment described above, a crack 50 (i.e., a weak area) was formed by the scribe wheel 48. However, as shown in Figure 13, in the scribe process, a crack 50 may also be formed within the semiconductor substrate 2 by irradiating the semiconductor substrate 2 with a laser. When a crack 50 is formed by a laser, regions 51 with high stress remain on both sides of the crack 50. In the break process, cleavage occurs starting from the crack 50.

[0034] In addition, during the scribing process, a groove 72 may be formed on the back surface 2b of the semiconductor substrate 2 using the dicing blade 70. As shown in Figure 14, the semiconductor substrate 2 is cut along the planned division line 4 using the dicing blade 70 from the back surface 2b side of the semiconductor substrate 2. At this time, the dicing blade 70 is not passed through from the back surface 2b to the front surface 2a of the semiconductor substrate 2. Therefore, a groove 72 is formed on the back surface 2b of the semiconductor substrate 2 by the dicing blade 70. At this time, regions 51 with high stress remaining are formed on both sides of the groove 72. In the breaking process, cleavage occurs starting from the groove 72.

[0035] In the embodiment described above, the electrode formation step was performed after the scribing step and before the holding tape application step. However, the electrode formation step may be performed before the scribing step. In this case, the scribe wheel 48 is pressed against the back surface 2b of the semiconductor substrate 2 via the lower electrode 42. As a result, the crack 50 is formed inside the lower electrode 42 and the polycrystalline substrate 30.

[0036] In the above-described embodiment, the member attachment step, the retaining tape attachment step, and the protective member attachment step were performed. However, the member attachment step, the retaining tape attachment step, and the protective member attachment step may be omitted.

[0037] In the embodiment described above, the semiconductor device 100 was a MOSFET. However, the semiconductor device 100 may also be a diode.

[0038] Corner 64 in the embodiment is an example of a "first corner". Also, corner 62 in the embodiment is an example of a "second corner".

[0039] The configuration of the semiconductor device and its manufacturing method disclosed herein is described below. (Composition 1) A semiconductor device comprising a semiconductor substrate formed by bonding a single crystal substrate and a polycrystalline substrate, having a front surface made of the single crystal substrate and a back surface made of the polycrystalline substrate, wherein the residual stress generated at the first corner between the front surface and the side surface of the semiconductor substrate is smaller than the residual stress generated at the second corner between the back surface and the side surface. (Configuration 2) The semiconductor device according to configuration 1, wherein the single crystal substrate has a pn junction. (Composition 3) The manufacturing method according to configuration 1 or 2, wherein the semiconductor substrate is made of SiC. (Composition 4) The semiconductor device according to any one of configurations 1 to 3, wherein the thickness of the polycrystalline substrate is greater than the thickness of the single-crystal substrate. (Composition 5) A method for manufacturing a semiconductor device, comprising the steps of: forming a weak portion, consisting of cracks or grooves, on the back surface of a semiconductor substrate having a front surface made of the single crystal substrate and a back surface made of the polycrystal substrate, wherein the semiconductor substrate is constructed by bonding a single crystal substrate and a polycrystal substrate together; and dividing the semiconductor substrate starting from the weak portion by pressing a dividing member against the front surface. (Composition 6) The manufacturing method according to configuration 5, wherein in the step of forming the weak portion, a crack is formed on the back surface by pressing a pressing member against the back surface.

[0040] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0041] 2: Semiconductor substrate, 2a: Front side, 2b: Back side, 2c: Side, 10: Single crystal substrate, 12: Trench, 14: Gate insulating film, 16: Gate electrode, 18: Interlayer insulating film, 20: Source layer, 22: Body layer, 24: Drift layer, 26: Device structure, 30: Polycrystalline substrate, 32: Drain layer, 40: Upper electrode, 42: Lower electrode, 48: Scribe wheel, 50: Crack, 51: Region, 56: Break bar, 62: Corner, 64: Corner, 70: Dicing blade, 72: Groove, 100: Semiconductor device, C: Crack

Claims

1. Semiconductor device (100), The semiconductor substrate (2) is constructed by bonding a single crystal substrate (10) and a polycrystalline substrate (30), and has a front surface (2a) made of the single crystal substrate and a back surface (2b) made of the polycrystalline substrate. The residual stress generated at the first corner (64) between the front surface and the side surface (2c) of the semiconductor substrate is smaller than the residual stress generated at the second corner (62) between the back surface and the side surface. Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the single crystal substrate has a pn junction.

3. The manufacturing method according to claim 1 or 2, wherein the semiconductor substrate is made of SiC.

4. The semiconductor device according to claim 1 or 2, wherein the thickness of the polycrystalline substrate is greater than the thickness of the single-crystal substrate.

5. A method for manufacturing a semiconductor device (100), The semiconductor substrate (2) is constructed by bonding a single crystal substrate (10) and a polycrystalline substrate (30), and has a front surface (2a) made of the single crystal substrate and a back surface (2b) made of the polycrystalline substrate. The process involves forming a weak area on the back surface of the semiconductor substrate (2) by cracks (50) or grooves (72), The process involves pressing the dividing member (56) against the front surface to divide the semiconductor substrate starting from the weak portion, A manufacturing method having the following characteristics.

6. The manufacturing method according to claim 5, wherein in the step of forming the weak portion, the outer peripheral edge of a disc-shaped pressing member (48) is pressed against the back surface to form the crack on the back surface.

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