A method for manufacturing a display panel, a display panel manufactured thereby, and an electronic device equipped therewith.

Abstract

The present invention provides a method for manufacturing a display panel, a display panel manufactured thereby, and an electronic device equipped therewith. [Solution] In order to provide a method for manufacturing a display panel with a low defect rate, a display panel manufactured thereby, and an electronic device equipped therewith, this manufacturing method includes the steps of: forming a display layer on the first surface of a substrate having a first surface and a second surface facing each other; forming a first hole by etching the second surface of the substrate to reduce the thickness of the substrate and removing the portion of the substrate corresponding to the hole-forming region; forming a polarizing layer corresponding to the entire surface of the display layer in the direction opposite to the direction toward the substrate in the display layer; and forming a second hole connected to the first hole by removing the portion of the polarizing layer and the portion of the display layer corresponding to the edge of the hole-forming region.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a display panel, a display panel manufactured thereby, and an electronic device including the same. More specifically, the present invention relates to a method for manufacturing a display panel with a low defect occurrence rate, a display panel manufactured thereby, and an electronic device including the same.

Background Art

[0002] Generally, a display panel includes a display area and a peripheral area outside thereof. In an electronic device including such a display panel, various functions are added to the electronic device while expanding the area occupied by the display area. Accordingly, research has been conducted on a display panel capable of arranging various components in the display area and an electronic device including the same.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, such conventional display panels and electronic devices including the same have a problem in that the frequency of defect occurrence during the manufacturing process or the use process is high.

[0005] The present invention aims to solve a variety of problems, including those mentioned above, and to provide a method for manufacturing display panels with a low defect rate, a display panel manufactured thereby, and an electronic device equipped therewith. However, such problems are illustrative and do not limit the scope of the present invention. [Means for solving the problem]

[0006] According to one aspect of the present invention, a method for manufacturing a display panel is provided, comprising the steps of: forming a display layer on the first surface of a substrate having mutually opposing first and second surfaces; forming a first hole by etching the second surface of the substrate to reduce the thickness of the substrate and removing the portion of the substrate corresponding to a hole-forming region; forming a polarizing layer corresponding to the entire surface of the display layer in the direction opposite to the substrate direction of the display layer; and forming a second hole connected to the first hole by removing the portion of the polarizing layer and the portion of the display layer corresponding to the edge of the hole-forming region.

[0007] The process further includes the step of forming scratches (particularly ring-shaped or cylindrical cuts or fractures, such as those caused by laser irradiation) inside the substrate corresponding to the edge of the hole-forming region, wherein the step of forming the first hole may be a step in which, when etching the second surface of the substrate, the etching solution penetrates the scratches and removes the portion of the substrate corresponding to the hole-forming region.

[0008] The step of forming the second hole may be the step of irradiating the portion of the polarizing layer corresponding to the edge of the hole-forming region with a laser beam to form the second hole.

[0009] The step of forming the second hole may be a step of irradiating the first surface of the substrate corresponding to the edge of the hole-forming region with the laser beam until the first surface is exposed to form the second hole.

[0010] The process may further include the step of forming a lower protective layer that covers the lower surface of the display layer exposed by the first hole, the second surface of the substrate, and the inner surface of the first hole.

[0011] The step of forming the second hole may be a step of irradiating the lower protective layer with the laser beam so as to remove the portion on the inner surface of the first hole, thereby forming the second hole.

[0012] The step of forming the second hole may be the step of irradiating the lower protective layer with the laser beam such that a portion of the second surface of the substrate is removed and the portion of the second surface of the substrate surrounding the first hole is exposed, thereby forming the second hole.

[0013] According to one aspect of the present invention, a display panel is provided comprising a substrate having a first surface and a second surface facing each other and a first hole penetrating the first surface and the second surface, a display layer having a second hole located on the first surface of the substrate and superimposed on the first hole when viewed from a direction perpendicular to the substrate, and a polarizing layer on the display layer, wherein the inner surface of the second hole is a continuous surface without steps until it reaches the first surface of the substrate, and no organic film is present on the first surface of the substrate between the display layer and the first hole.

[0014] The area of ​​the second hole on the lower surface of the polarizing layer in the direction of the display layer may be the same as the area of ​​the second hole on the upper surface of the display layer in the direction of the polarizing layer.

[0015] The second hole can expose a portion of the first surface of the substrate.

[0016] The portion of the first surface of the substrate exposed by the second hole may surround the first hole.

[0017] The substrate may further be provided with a lower protective layer located on the second surface and having a third hole corresponding to the first hole.

[0018] The area of the third hole is larger than the area of the first hole.

[0019] The area of the third hole on the upper surface of the lower protective layer in the substrate direction is the same as the area of the second hole on the lower surface of the display layer in the substrate direction.

[0020] When viewed from a direction perpendicular to the substrate, the edge of the third hole may overlap with the edge of the second hole on the lower surface of the display layer in the substrate direction.

[0021] The edge of the third hole in the lower protective layer may include a thermally deformed portion.

[0022] The edge of the second hole in the polarizing layer may include a thermally deformed portion.

[0023] According to one aspect of the present invention, there is provided an electronic device including a display panel, a camera, and a lower cover. The display panel has a first surface and a second surface facing each other, and includes a substrate having a first hole penetrating through the first surface and the second surface, a display layer located on the first surface of the substrate and having a second hole overlapping with the first hole when viewed from a direction perpendicular to the substrate, and a polarizing layer on the display layer. The inner surface of the second hole is a continuous surface having no step until reaching the first surface of the substrate. There is no organic film on the first surface of the substrate between the display layer and the first hole. The camera is located between the display panel and the lower cover.

[0024] The area of the second hole on the lower surface of the polarizing layer in the display layer direction is the same as the area of the second hole on the upper surface of the display layer in the polarizing layer direction.

[0025] The second hole may expose a part of the first surface of the substrate.

[0026] Among the portions of the first surface of the substrate exposed by the second hole, the first hole can be surrounded.

[0027] A lower protective layer located on the second surface of the substrate and having a third hole corresponding to the first hole can be further provided.

[0028] The area of the third hole is larger than the area of the first hole.

[0029] The area of the third hole is the same as the area of the second hole on the lower surface of the display layer in the substrate direction.

[0030] When viewed from a direction perpendicular to the substrate, the edge of the third hole can overlap with the edge of the second hole on the lower surface of the display layer in the substrate direction.

[0031] The edge of the third hole of the lower protective layer can include a thermally deformed portion.

[0032] The edge of the second hole of the polarizing layer can include a thermally deformed portion.

[0033] Other aspects, features, and advantages will become clear from the specific content, claims, and drawings for implementing the following invention.

Effects of the Invention

[0034] According to an embodiment of the present invention, a method for manufacturing a display panel with a low defect occurrence rate, a display panel manufactured thereby, and an electronic device including the same can be realized. Of course, the scope of the present invention is not limited by such effects.

Brief Description of the Drawings

[0035] [Figure 1] It is a perspective view schematically showing an electronic device according to an embodiment of the present invention. [Figure 2] It is an exploded perspective view schematically showing the electronic device of FIG. 1. [Figure 3] Figure 1 is a block diagram illustrating the electronic device in schematic form. [Figure 4] This is a schematic plan view showing a display panel according to one embodiment of the present invention. [Figure 5] Figure 4 is a schematic side view of the display panel. [Figure 6] This is a schematic cross-sectional view of the display panel shown in Figure 4, taken along the line A-A'. [Figure 7] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 8] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 9] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 10] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 11] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 12] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 13] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 14] Figure 6 is a schematic cross-sectional view showing the steps involved in manufacturing the display panel. [Figure 15] Figure 1 is a schematic plan view showing the display panel included in the electronic device. [Figure 16] Figure 15 is an equivalent circuit diagram of the pixel circuit electrically connected to the light-emitting diodes included in the display panel. [Figure 17] This is a schematic plan view showing a portion of the display panel shown in Figure 15. [Figure 18] This is a schematic cross-sectional view of the display panel shown in Figure 17, taken along the line B-B'. [Figure 19]This is a schematic cross-sectional view showing a portion of a display panel according to one embodiment of the present invention. [Modes for carrying out the invention]

[0036] The present invention can be modified in various ways and may have many different embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and how they are achieved, will become clear when referring to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of forms.

[0037] Embodiments of the present invention will be described in detail below with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and redundant explanations thereof will be omitted.

[0038] In the following embodiment, when various components such as layers, films, regions, and plates are said to be "on top of" other components, this includes not only cases where they are "directly on top of" other components, but also cases where other components are interposed between them. Furthermore, for the sake of explanation, the size of components may be exaggerated or reduced in the drawings. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of explanation, and the present invention is not necessarily limited to what is shown.

[0039] In the following embodiment, the x, y, and z axes are not limited to the three axes on a Cartesian coordinate system, but can be interpreted in a broader sense that includes them. For example, the x, y, and z axes may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0040] In the following embodiment, terms such as "first," "second," etc., are used not in a restrictive sense, but for the purpose of distinguishing one component from another.

[0041] In the following embodiment, terms such as “includes” or “has” mean the presence of the features or components described in the specification, and do not preclude the possibility of adding one or more other features or components.

[0042] In this specification, “A and / or B” means that it is either A, B, or both A and B. And “at least one of A and B” means that it is either A, B, or both A and B.

[0043] In one embodiment described below, when a membrane, region, or component is said to be connected, this includes not only cases where the membrane, region, or component is directly connected, but also cases where it is indirectly connected with another membrane, region, or component interposed between them. For example, in this specification, when a membrane, region, or component is said to be electrically connected, this includes not only cases where the membrane, region, or component is directly electrically connected, but also cases where it is indirectly electrically connected with another membrane, region, or component interposed between them.

[0044] Figure 1 is a schematic perspective view of an electronic device 1 according to one embodiment of the present invention, Figure 2 is a schematic exploded perspective view of the electronic device 1 of Figure 1, and Figure 3 is a schematic block diagram of the electronic device 1 of Figure 1.

[0045] Referring to Figures 1 and 2, the electronic device 1 according to one embodiment of the present invention is a device that displays videos and still images, and can be a portable electronic device such as a mobile phone, smartphone, tablet PC, mobile communication terminal, electronic organizer, e-book, PMP (portable multimedia player), navigation system, or UMPC (Ultra Mobile PC), and can be a variety of products such as a TV, notebook computer, monitor, billboard, or Internet of Things (IoT). Alternatively, the electronic device 1 according to one embodiment of the present invention can be a wearable device such as a smart watch, watch phone, glasses-type display, or head-mounted display (HMD). Alternatively, the electronic device 1 according to one embodiment of the present invention may be an instrument panel of an automobile, a Center Information Display (CID) located on the center fascia or dashboard of an automobile, a room mirror display that replaces the side mirrors of an automobile, or a display located behind the front seats as entertainment for the rear seats of an automobile.

[0046] In Figures 1 and 2, for the sake of explanation, an electronic device 1 according to one embodiment of the present invention is shown as a smartphone. Such an electronic device 1 may include a cover window 70, a display panel 10, a data driver 20, a display circuit board 30, components 40, a bracket 60, a main circuit board 50, a battery 80, and / or a lower cover 90.

[0047] In the plan views of this specification, "left," "right," "up," and "down" indicate directions when viewing the display panel 10 from the vertical direction of the display panel 10. For example, "left" indicates the -x direction, "right" indicates the +x direction, "up" indicates the +y direction, and "down" indicates the -y direction.

[0048] The electronic device 1 is shown to be approximately rectangular in plan view. For example, as shown in Figure 1, the electronic device 1 is shown to have an approximately rectangular shape in the xy-plane, with a shorter side in the x-axis direction and a longer side in the y-axis direction. In this case, the angle where the shorter side in the x-axis direction and the longer side in the y-axis direction meet is a right angle and may have a rounded shape with a predetermined curvature. Of course, in plan view, the electronic device 1 is not limited to a rectangle, but may have other polygons, ellipses, or irregular shapes.

[0049] The cover window 70 may be positioned on the top of the display panel 10 so as to cover the top surface of the display panel 10. Such a cover window 70 can function to protect the top surface of the display panel 10.

[0050] The cover window 70 may include a transparent cover portion DA70 corresponding to the display panel 10 and a light-shielding cover portion NDA70 surrounding the transparent cover portion DA70. The transparent cover portion DA70 may allow light from the display area DA of the display panel 10 to pass through and emit that light to the outside. The light-shielding cover portion NDA70 may include an opaque material that blocks light (for example, a colored opaque material). The light-shielding cover portion NDA70 may include a pattern to show to the user when no image is being displayed.

[0051] Such a cover window 70 may include glass or plastic. If the cover window 70 includes glass, it may include ultra-thin glass. If the cover window 70 includes plastic, it may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0052] The display panel 10 may be positioned below the cover window 70. The display panel 10 may overlap the transparent cover portion DA 70 of the cover window 70. Such a display panel 10 includes a display area DA. The display area DA is the area on which an image is displayed, and the display area DA may include an area (hereinafter referred to as the component area) that transmits light emitted from or directed toward the component 40 or camera 531, which is positioned below the display panel 10. The component 40 may include sensors that use visible light, infrared light, sound, etc.

[0053] An aperture region OA may be located within the display region DA. The aperture region OA may be defined by an opening in the substrate 100 (see Figures 6 and 18) that the display panel 10 contains. As shown in Figure 2, the aperture region OA may be located in the upper center of the display region DA, and the display region DA located outside the aperture region OA may surround it. Of course, the aperture region OA can be located within the display region DA in various ways, such as being located on the upper left side or the upper right side of the display region DA. Although Figure 2 shows one aperture region OA located within the display region DA, the display panel 10 may have multiple aperture regions OA.

[0054] The component region described above can be such an aperture region OA. Figure 2 illustrates that the position of the aperture region OA corresponds to the position of the camera 531 located at the bottom. That is, in a plan view, the aperture region OA may overlap with the camera 531. Of course, if necessary, the position of the aperture region OA may correspond to the position of at least a part of the component 40. That is, in a plan view, the aperture region OA may overlap with at least a part of the first component 41, second component 42, third component 43, and fourth component 44 included in component 40. For convenience, the case in which the position of the aperture region OA corresponds to the position of the camera 531 located at the bottom will be described below.

[0055] Between the display region DA and the aperture region OA, there may be an intermediate region MA, also called the first region. That is, the intermediate region MA, also called the first region, may be located outside the aperture region OA. In a plan view, the intermediate region MA may have a closed loop shape that surrounds the aperture region OA as a whole. The display region DA can also be called the second region outside the first region.

[0056] The display panel 10 may be a light-emitting display panel including light-emitting diodes. The light-emitting diodes may be organic light-emitting diodes (OLEDs) including an organic light-emitting layer, or inorganic light-emitting diodes including inorganic materials. In the case of inorganic light-emitting diodes, they may include PN diodes containing an inorganic semiconductor substrate material. When a forward voltage is applied to a PN junction diode, holes and electrons are injected, and the energy generated by the recombination of these holes and electrons is converted into light energy, emitting light of a predetermined hue. Such inorganic light-emitting diodes may have a width of several millimeters to several hundred millimeters. Inorganic light-emitting diodes are also referred to as microLEDs.

[0057] The display panel 10 may be a rigid display panel that is rigid and does not bend easily, or a flexible display panel that is flexible and can be easily bent, folded, or rolled up. For example, the display panel 10 may be a foldable display panel, a curved display panel with a curved display surface, a bent display panel with a curved area other than the display surface, a rollable display panel that can be rolled up or unrolled, or a stretchable display panel that can be extended.

[0058] The display panel 10 may be a transparent display panel that allows objects or backgrounds placed on the underside of the display panel 10 to be viewed from the top surface of the display panel 10. Alternatively, the display panel 10 may be a reflective display panel that reflects objects or backgrounds on the top surface of the display panel 10.

[0059] The data driver 20 can be implemented on the display panel 10 in the form of an integrated circuit (IC). Of course, the present invention is not limited to this, and for example, the data driver 20 can be implemented on a display circuit board 30.

[0060] The display circuit board 30 may be attached to one side of the display panel 10. The display circuit board 30 may be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is hard and difficult to bend, or a composite printed circuit board that includes both a rigid and a flexible printed circuit board. A touch sensor driver may be mounted on such a display circuit board 30. The touch sensor driver may be formed by an integrated circuit. The touch sensor driver may be electrically connected to the touch electrodes of the touchscreen layer of the display panel 10 via the display circuit board 30.

[0061] The touchscreen layer of the display panel 10 can sense user touch input using at least one of various touch methods, such as resistive or capacitive touch. When the touchscreen layer of the display panel 10 senses user touch input using the capacitive method, the touch sensor drive unit can determine whether or not the user has touched the panel by applying a drive signal to the drive electrode among the touch electrodes and sensing the voltage charged in the mutual capacitance (hereinafter referred to as "mutual capacitance") between the drive electrode and the sensing electrode through the sensing electrode among the touch electrodes.

[0062] User touch can include contact touch and proximity touch. Contact touch means that the user's finger or an object such as a pen directly touches the cover window 70 which is placed on the touchscreen layer. Proximity touch means that the user's finger or an object such as a pen is positioned at a distance so as to be close to the cover window 70, such as hovering. The touch sensor drive unit transmits sensor data to the main processor 510 based on the sensed voltage, and the main processor 510 can calculate the touch coordinates where the touch input occurred by analyzing the sensor data.

[0063] A control unit for supplying drive voltages to drive the pixels, gate drivers, and / or data drivers 20 of the display panel 10 may be located on the display circuit board 30.

[0064] A bracket 60 for supporting the display panel 10 may be positioned at the bottom of the display panel 10. The bracket 60 may include plastic, metal, or a combination of both. The bracket 60 may include a first camera hole CMH1 into which the camera 531 is inserted, a battery hole BH into which the battery 80 is located, a cable hole CAH through which the cable connected to the display circuit board 30 passes, and a component hole CPH corresponding to the component 40. The component hole CPH may overlap with the component 40 of the main circuit board 50 when viewed from a third direction (z-axis direction). For reference, the display area DA of the display panel 10 may overlap with the component 40 of the main circuit board 50 when viewed from a third direction (z-axis direction). Of course, the bracket 60 may not have the component hole CPH if necessary.

[0065] The components 40 included in the electronic device 1 may include a first component 41, a second component 42, a third component 43, and a fourth component 44 superimposed on the display panel 10. Each of the first component 41, second component 42, third component 43, and fourth component 44 may include at least one of a proximity sensor, an illuminance sensor, an iris sensor, a face recognition sensor, and a camera (or image sensor). The infrared proximity sensor can detect an object located close to the top surface of the electronic device 1, and the illuminance sensor can sense the brightness of light incident on the top surface of the electronic device 1. The iris sensor can photograph the iris of a person located on the top surface of the electronic device 1, and the camera can acquire image data of an object placed on the top surface of the electronic device 1. Of course, the components 40 are not limited to the proximity sensor, illuminance sensor, iris sensor, face recognition sensor, and / or camera, and may include other sensors.

[0066] The main circuit board 50 and battery 80 may be located at the bottom of the bracket 60. The main circuit board 50 may be a printed circuit board or a flexible printed circuit board.

[0067] The main circuit board 50 may include a main processor 510, a camera 531, a main connector 55, and components 40. The main processor 510 may be formed as an integrated circuit. If necessary, the electronic device 1 may include a camera 531 located on the top surface of the main circuit board 50, as well as a camera located on the bottom surface of the main circuit board 50. The main processor 510 and the main connector 55 may be located on either the top or bottom surface of the main circuit board 50. Such a main circuit board 50 may be electrically connected to the display circuit board 30 via the main connector 55, etc.

[0068] The main processor 510 can control all functions of the electronic device 1. For example, the main processor 510 can output digital video data to the data driver 20 via the display circuit board 30 so that the display panel 10 displays an image. The main processor 510 can receive sensing data from the touch sensor drive unit. The main processor 510 can determine whether or not the user has touched the device based on the sensing data and perform actions corresponding to the user's direct touch or proximity touch. The main processor 510 may be an application processor, a central processing unit, or a system chip consisting of an integrated circuit.

[0069] The camera 531 processes image frames, such as still images or videos, obtained by the image sensor in camera mode and outputs them to the main processor 510. The camera 531 may include at least one of the following: a camera sensor (e.g., CCD or CMOS), a photosensor (or image sensor), and a laser sensor.

[0070] A cable that has passed through the cable hole CAH of the bracket 60 is connected to the main connector 55, and the main circuit board 50 can be electrically connected to the display circuit board 30 via such a cable.

[0071] The electronic device 1 may be represented by a block diagram as shown in Figure 3. In addition to the main processor 510, the electronic device 1 may include a wireless communication unit 520, an input unit 530, a sensor unit 540, an output unit 550, an interface unit 560, a memory 570, and / or a power supply unit 580, as shown in Figure 3.

[0072] The wireless communication unit 520 may include at least one of the following: a broadcast receiving module 521, a mobile communication module 522, a wireless internet module 523, a short-range communication module 524, and a location information module 525.

[0073] The broadcast receiving module 521 receives broadcast codes and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include satellite channels and terrestrial channels.

[0074] The mobile communication module 522 transmits and receives radio signals to and from at least one of a base station, an external terminal, and a server on a mobile communication network constructed by a technical standard or communication method for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA® (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The radio signals may include various forms of data such as voice call signals, image call signals, or text / multimedia message transmission and reception.

[0075] The wireless internet module 523 indicates a module for wireless internet connectivity. The wireless internet module 523 may be configured to send and receive wireless signals over a communication network using wireless internet technology. Wireless internet technologies may include, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, and / or DLNA (Digital Living Network Alliance).

[0076] The short-range communication module 524 is for short-range communication and uses Bluetooth® (registered trademark). TMThe short-range communication module 524 may support short-range communication using at least one of the following technologies: RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus). The short-range communication module 524 may support wireless communication between the electronic device 1 and a wireless communication system, between the electronic device 1 and other electronic devices, or between the electronic device 1 and a network where other electronic devices (or external servers) are located, via a wireless area network. The wireless area network may be a wireless personal area network. The other electronic devices may be wearable devices that can exchange (or interact with) data with the electronic device 1.

[0077] The location information module 525 is a module for obtaining the location of the electronic device 1, and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0078] The input unit 530 may include a video input unit such as a camera 531 for video signal input, an audio input unit such as a microphone 532 for audio signal input, and an input device 533 for receiving information from the user. The camera 531 processes image frames, such as still images or videos, obtained by the image sensor in video call mode or shooting mode. The processed image frames may be displayed on the display panel 10 or stored in the memory 570. The microphone 532 processes external audio signals as electrical audio data. The processed audio data can be used in various ways by the functions (or applications) being performed by the electronic device 1.

[0079] The main processor 510 can control the operation of the electronic device 1 in response to information input via the input device 533. The input device 533 may include mechanical input means such as buttons, dome switches, jog wheels, or jog switches located on the rear or side of the electronic device 1, or touch input means. The touch input means may consist of the touchscreen layer of the display panel 10.

[0080] The sensor unit 540 may include one or more sensors that sense at least one of the following: information within the electronic device 1, information about the surrounding environment related to the electronic device 1, and user information, and generate a corresponding sensing signal. Based on such sensing signals, the main processor 510 may control the driving or operation of the electronic device 1, or perform data processing, functions, or operations related to the application installed on the electronic device 1. The sensor unit 540 may be a proximity sensor, illumination sensor, or face recognition sensor as described above in relation to component 40. Of course, the sensor unit 540 may include an acceleration sensor, a magnetic sensor, a gravity sensor (G-sensor), a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor), a fingerprint recognition sensor, an ultrasonic sensor, an optical sensor, and / or a battery gauge. In addition, the sensor unit 540 may include environmental sensors and chemical sensors. Environmental sensors may be, for example, a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, and / or a gas detection sensor. Chemical sensors may be, for example, an e-nose, a healthcare sensor, and / or a biorecognition sensor.

[0081] The output unit 550 is for generating outputs related to vision, hearing, or touch, and may include at least one of the display panel 10, the acoustic output unit 551, the haptic module 552, and the optical output unit 553.

[0082] The display panel 10 displays (outputs) information processed by the electronic device 1. For example, the display panel 10 may display execution screen information of an application driven by the electronic device 1, display a UI (User Interface) corresponding to the execution screen information, or display GUI (Graphic User Interface) information. The display panel 10 may include a display layer for displaying images and a touchscreen layer for sensing user touch input. Thus, the display panel 10 may function as one of the input devices 533 that provide an input interface between the electronic device 1 and the user, and as one of the output units 550 that provide an output interface between the electronic device 1 and the user.

[0083] The acoustic output unit 551 can output acoustic data received from the wireless communication unit 520 or stored in the memory 570 in call signal reception, call mode, recording mode, voice recognition mode and / or broadcast reception mode. The acoustic output unit 551 can output acoustic signals related to functions performed by the electronic device 1 (e.g., call signal reception sound, message reception sound, etc.). The acoustic output unit 551 may include a receiver and a speaker. At least one of the receiver and speaker may be an acoustic generator mounted below the display panel 10 that vibrates the display panel 10 to output sound. The acoustic generator may be a piezoelectric element or piezoelectric actuator that contracts and expands in response to an electrical signal, or an exciter that generates a magnetic force using a voice coil to vibrate the display panel 10.

[0084] The haptic module 552 generates a variety of tactile effects that the user experiences. The haptic module 552 can provide vibrations to the user as a tactile effect. The haptic module 552 can transmit tactile effects through direct contact and can be embodied in a way that the user can feel the tactile effects through muscle sensation in their fingers, arms, etc.

[0085] The optical output unit 553 outputs a signal to indicate the occurrence of an event using light from a light source. Examples of events occurring in the electronic device 1 may include message reception, ringing signal reception, answering machine messages, alarms, schedule notifications, email reception, and / or information reception via an application. The signal output by the optical output unit 553 is manifested by the electronic device 1 emitting monochromatic or multi-colored light from its front or back. The signal output may be terminated when the electronic device 1 senses that the user has confirmed the event.

[0086] The interface unit 560 acts as a conduit for various types of external devices connected to the electronic device 1. The interface unit 560 may include at least one of the following: a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (input / output) port, a video I / O (input / output) port, and an earphone port. When an external device is connected to the interface unit 560, the electronic device 1 can perform appropriate control related to the connected external device.

[0087] Memory 570 stores data that supports the various functions of the electronic device 1. Memory 570 can store numerous application programs driven by the electronic device 1, data for the operation of the electronic device 1, and / or instruction words. At least some of these numerous applications may be downloaded from an external server via wireless communication. Memory 570 stores applications for the operation of the main processor 510 and can temporarily store input / output data, such as phonebooks, messages, still images, and / or videos. Memory 570 can also store haptic data for various vibration patterns provided to the haptic module 552 and acoustic data for various sounds provided to the acoustic output unit 551.

[0088] Memory 570 may include at least one recording medium from among flash memory type, hard disk type, SSD type (Solid State Disk type), SDD type (Silicon Disk Drive type), multimedia card micro type, card type memory (e.g., SD or XD memory), RAM (random access memory), SRAM (static random access memory), ROM (read-only memory), EEPROM (electrically erasable programmable read-only memory), PROM (programmable read-only memory), magnetic memory, magnetic disk, and optical disk.

[0089] The power supply unit 580, under the control of the main processor 510, receives power from an external power source and / or an internal power source to supply power to each component included in the electronic device 1. The power supply unit 580 may include a battery 80. The power supply unit 580 may also have a connection port, which is an example of an interface unit 560 to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit 580 may charge the battery 80 wirelessly. The battery 80 may be positioned so as not to overlap with the main circuit board 50 in a third direction (z direction). The battery 80 may overlap with the battery hole BH of the bracket 60.

[0090] The lower cover 90 forms the exterior of the electronic device 1 and has an opening that exposes a portion of the display panel 10. The lower cover 90 has an open shape on the side corresponding to the display panel 10 and can be fastened to the display panel 10. The lower cover 90 may be located on the opposite side of the cover window 70, with the display panel 10 in between. The lower cover 90 may be located below the main circuit board 50 and the battery 80. The lower cover 90 may be fastened and secured to the bracket 60. The lower cover 90 forms the exterior of the bottom surface of the electronic device 1. The lower cover 90 may include plastic, metal, or both plastic and metal.

[0091] A second camera hole CMH2 may be formed in the lower cover 90, through which the lower surface of the camera 531 is exposed. The position of the camera 531, and the positions of the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera 531, are not limited to those shown in Figures 1 and 2, but can be varied in various ways. For example, the camera 531 may be located between the display panel 10 and the lower cover 90. Also, when viewed from a direction perpendicular to the display panel 10, the camera 531 may overlap with the opening area OA of the display area DA.

[0092] Figure 4 is a schematic plan view showing a display panel 10 according to one embodiment of the present invention, and Figure 5 is a schematic side view showing the display panel of Figure 4. The aforementioned electronic device 1 may include a display panel 10 as shown in Figures 4 and 5.

[0093] The display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA is the part that displays the image and may contain multiple pixels. The display area DA can have various shapes, such as a circle, an ellipse, a polygon, or the shape of a specific geometric figure. In Figure 4, the shape of the display area DA is shown as a rounded rectangle.

[0094] The peripheral region PA may be located outside the display region DA. The portion of the peripheral region PA located at the lower edge of the display region DA and extending in the first direction (x-axis direction) has a width in that direction (x-axis direction) that is narrower than the width of the display region DA. At least a portion of the peripheral region PA can be easily folded through such a structure.

[0095] The planar shape of the display panel 10 shown in Figure 4 is substantially identical to the shape of the substrate 100 included in the display panel 10. The fact that the display panel 10 includes a display area DA and a peripheral area PA outside the display area DA means that the substrate 100 also includes a display area DA and a peripheral area PA outside the display area DA. For convenience, in the following explanation, the substrate 100 will be described as having a display area DA and a peripheral area PA.

[0096] The display panel 10 may include a main area MR, a folding area BR outside the main area MR, and a sub-area SR separated from the main area MR by the folding area BR. The main area MR may be located on one side of the folding area BR, and the sub-area SR may be located on the other side of the folding area BR. The display panel 10 is folded at the folding area BR as shown in Figure 5, and when viewed from a third direction (z-axis direction), at least a portion of the sub-area SR may overlap with the main area MR. Figure 5 illustrates the display panel 10 being folded, but the present invention is not limited thereto. The display panel 10 may not be folded if necessary. In that case, the sub-area SR may be directly connected to the main area MR. The sub-area SR may be a non-display area.

[0097] A data driver 20 may be located in the sub-region SR of the display panel 10. The data driver 20 may be located in the display panel 10 in the form of an integrated circuit (IC). For example, the data driver 20 may be a data-driven integrated circuit that generates data signals.

[0098] A display circuit board 30 may be attached to the edge of the sub-region SR of the display panel 10. The display circuit board 30 may be electrically connected to a data driver 20 or the like via pads on the sub-region SR of the display panel 10.

[0099] Of course, the display panel 10 may have an aperture region OA located within the display region DA, as described above with reference to Figure 2. Furthermore, the display panel 10 may have an intermediate region MA located between the display region DA and the aperture region OA.

[0100] Figure 6 is a schematic cross-sectional view showing a section of the display panel 10 cut along the line A-A' in Figure 4, and for convenience, the cover window 70 and camera 531 are shown together outside the display panel 10. As mentioned above, the electronic device 1 may include the display panel 10 and the camera 531 positioned in the opening area OA of the display panel 10.

[0101] The display panel 10 may include a substrate 100 having a first surface and a second surface facing each other and containing glass, a display layer DIL located on the first surface which is the upper surface of the substrate 100 in the (+z direction), a polarizing layer POL located on the display layer DIL, and a lower protective layer BPL located on the second surface which is the lower surface of the substrate 100.

[0102] The display layer (DIL) may include a display element (or light-emitting element) that emits light to display an image. The display element may include a light-emitting diode, for example, an organic light-emitting diode that includes an organic light-emitting layer. Of course, the display element may also be an inorganic light-emitting diode that includes inorganic materials. The inorganic light-emitting diode may include a PN diode that includes an inorganic semiconductor substrate material. When a forward voltage is applied to a PN junction diode, holes and electrons are injected, and the energy generated by the recombination of these holes and electrons is converted into light energy, which can emit light of a predetermined hue. The inorganic light-emitting diodes described above have a width of several to several hundred mm, or several to several hundred nm.

[0103] Of course, the present invention is not limited thereto. For example, the display layer DIL may include a quantum point layer. That is, light of a specific wavelength band generated from the light-emitting layer included in the display layer DIL can be converted into light of a predetermined wavelength by the quantum point layer.

[0104] The display layer (DIL) may include not only the display elements but also a drive circuit for driving the display elements. The drive circuit may include, for example, thin-film transistors and capacitors. The drive circuit may be located beneath the display elements.

[0105] The display layer (DIL) may include a touchscreen layer. The touchscreen layer included in the display layer (DIL) may acquire coordinate information from external inputs, such as touch events. The touchscreen layer may include sensing electrodes (or touch electrodes) and trace lines connected to the sensing electrodes. The touchscreen layer may sense external inputs using a mutual capping method and / or a self-capping method.

[0106] The touchscreen layer included in the display layer DIL may be located on the display element. Such a touchscreen layer may be formed directly on the display element, or it may be formed separately and then attached to the display element via an adhesive layer such as an optically transparent adhesive. In the former case, the touchscreen layer is formed continuously after the process of forming the display element and the sealing layer that protects it, in which case the adhesive layer may not be interposed between the touchscreen layer and the display element.

[0107] The polarizing layer POL can perform an anti-reflective function. For this purpose, a phase delay layer may be interposed between the polarizing layer POL and the display layer DIL as needed. The phase delay layer may be, for example, a λ / 4 wave plate. Such a phase delay layer and the polarizing layer POL can reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the cover window 70. If the display panel 10 includes a phase delay layer, the polarizing layer POL will be considered to include such a phase delay layer below.

[0108] The lower protective layer BPL may be located on the (-z direction) underside of the substrate 100. The lower protective layer BPL may contain materials such as polyethylene terephthalate, polyethylene naphthalate, or polyimide. Such a lower protective layer BPL can serve to protect the underside of the substrate 100. The lower protective layer BPL may also be opaque. This allows the user to clearly see the image generated by the display layer DIL on the substrate 100. For this purpose, the lower protective layer BPL may contain an opaque material, such as carbon black.

[0109] To improve the transmittance of the aperture region OA, the display panel 10 may include through-holes 10H. The through-holes 10H may penetrate the substrate 100, the display layer DIL, the polarizing layer POL, and the lower protective layer BPL. Specifically, the substrate 100 may have a first hole H1, the display layer DIL and the polarizing layer POL may have a second hole H2 that overlaps with the first hole H1 when viewed from a direction perpendicular to the substrate 100, and the lower protective layer BPL may have a third hole H3 that overlaps with the first hole H1 when viewed from a direction perpendicular to the substrate 100, thereby forming through-holes 10H that penetrate the substrate 100, the display layer DIL, the polarizing layer POL, and the lower protective layer BPL. In this case, the inner surfaces of the second hole H2 in the display layer DIL and the polarizing layer POL may be continuous surfaces extending to the upper surface of the substrate 100 in the (+z direction). The fact that the inner surface of the second hole H2 is a continuous surface means that there is no step between the inner surface of the second hole H2 and the top surface of the substrate 100. For reference, a step may exist between the second hole H2 of the display layer DIL and the polarizing layer POL and the first hole H1 of the substrate 100. This will be discussed later. In such a display panel 10, there may be no organic film on the first surface, which is the top surface of the substrate 100, between the display layer DIL and the first hole H1. This will also be discussed later.

[0110] The cover window 70 may be located on the display panel 10. The cover window 70 may be attached to the polarizing layer POL through an adhesive layer such as an optical clear adhesive (OCA). The cover window 70 may cover through-holes 10H contained in the display panel 10.

[0111] The aperture region OA may be the region where the through-hole 10H of the display panel 10 is located. An electronic element, such as a camera 531 or component 40, may be positioned (in the -z direction) corresponding to such an aperture region OA. Figure 6 illustrates the case where the camera 531 is positioned to correspond to the aperture region OA, as described above. If necessary, at least a portion of the camera 531 may be located within the through-hole 10H of the display panel 10.

[0112] Figures 7 to 14 are schematic cross-sectional views illustrating the steps involved in manufacturing the display panel 10 shown in Figure 6.

[0113] A display layer DIL is formed on the first surface (located in the +z direction) of a substrate 100 of sufficient thickness, which has two opposing first and second surfaces. The substrate 100 may be a glass substrate. In this case, a temporary protective layer TPL may be formed on the display layer DIL to protect the upper surface of the display layer DIL in the opposite direction to the substrate 100 (+z direction). The temporary protective layer TPL may be formed by methods such as inkjet printing or spin coating. The temporary protective layer TPL may contain materials such as polyethylene terephthalate, polyethylene naphthalate, or polyimide. Alternatively, a temporary protective layer TPL that has been pre-formed in a flat shape using such materials may be attached to the display layer DIL using an adhesive.

[0114] Next, as shown in Figure 8, scratches are formed inside the substrate 100. In Figure 8, the dotted line indicates that scratches have been formed. The region where the aforementioned first hole H1 is formed is called the hole-forming region. The position of the formed scratches may correspond to the edge of such a hole-forming region. Since Figure 8 is a cross-sectional view, the scratch-forming portion is shown with two dotted lines, but in reality, scratches can be formed almost uniformly inside the substrate 100 corresponding to the edge of the hole-forming region. Such scratches can be formed by irradiating the substrate 100 with a laser beam. That is, after focusing the laser beam to the area inside the substrate 100 where scratches are to be formed, scratches can be formed in that part inside the substrate 100 by irradiating it with the laser beam.

[0115] After forming scratches inside the substrate 100 in this manner, the thickness of the substrate 100 can be reduced by etching the second surface, which is the bottom surface (-z direction) of the substrate 100. To reduce the thickness of the substrate 100, a wet etching method using an etching solution can be used when etching the bottom surface of the substrate 100. Any solution capable of etching glass can be used as the etching solution, but an etching solution containing HF, HCl, phosphoric acid and / or nitric acid can be used. For example, an etching solution containing 10% by weight of HF, 40% by weight of HNO3, 40% by weight of H3PO4, and 10% by weight of ultrapure water (DI water) can be used, or an etching solution containing 20% ​​by weight of HF, 45% by weight of HNO3, 20% by weight of H3PO4, and 15% by weight of ultrapure water can be used.

[0116] When etching the second surface, which is the underside of the substrate 100, using the etching solution in this manner, the etching solution penetrates into the scratches formed within the substrate 100. As a result, the substrate is etched along the scratches formed within the substrate 100. Figure 9 illustrates that the thickness of the substrate 100 is reduced through this method, and that the substrate 100 is etched along the edge of the hole-forming region. As the substrate 100 is etched along the edge of the hole-forming region, the portion of the substrate 100 corresponding to the area where the first hole H1 is formed is separated from the rest of the substrate 100, as shown in Figure 9. As a result, if this portion is removed, the first hole H1 is formed in the substrate 100, as shown in Figure 10. This exposes a portion of the underside of the display layer DIL corresponding to the first hole H1 in the substrate 100.

[0117] Subsequently, as shown in Figure 11, a lower protective layer BPL is formed on the second surface, which is the lower surface of the substrate 100. Specifically, the lower protective layer BPL is formed to cover the lower surface of the display layer DIL exposed by the first hole H1 of the substrate 100, the lower surface of the substrate 100, and the inner surface of the first hole H1. Such a lower protective layer BPL can be formed using an inkjet printing method or a spin coating method. Of course, in order to form the lower protective layer BPL, the display panel 10 under manufacture may be covered so that the lower surface of the substrate 100 is positioned above the upper surface, if necessary. The material for forming the lower protective layer BPL is as described above.

[0118] After forming the lower protective layer BPL, the temporary protective layer TPL on the display layer DIL is removed. Removal of the temporary protective layer TPL can be carried out by various methods. For example, the temporary protective layer TPL can be removed by a wet etching method using an etching solution, by a dry etching method, or simply by physically peeling the temporary protective layer TPL from the display layer DIL. If the temporary protective layer TPL is pre-formed in a flat shape and attached to the display layer DIL with an adhesive, the temporary protective layer TPL can also be removed by causing the adhesive to lose its tackiness. For example, the temporary protective layer TPL can be removed by irradiating the adhesive layer containing the adhesive with ultraviolet light to weaken its tackiness.

[0119] After removing the temporary protective layer TPL, a polarizing layer POL is formed on the upper side of the display layer DIL, i.e., in the direction opposite to the substrate 100 side (+z direction) on the display layer DIL, as shown in Figure 12, covering the entire surface of the display layer DIL. For example, a pre-formed flat polarizing layer POL can be attached to the display layer DIL using an adhesive. Of course, if necessary, a phase delay layer such as a λ / 4 wave plate can be formed on the display layer DIL, and the polarizing layer POL can be formed on this phase delay layer. If the display panel 10 includes a phase delay layer, for convenience, the polarizing layer POL can be considered to include such a phase delay layer as described above.

[0120] Next, as shown in Figure 13, the portions of the polarizing layer POL and the display layer DIL corresponding to the edges of the hole-forming regions are removed. Specifically, the portion of the polarizing layer POL corresponding to the edge of the hole-forming region is irradiated with a laser beam LB to remove the portion of the polarizing layer POL and the display layer DIL. Figure 13 is a cross-sectional view illustrating two laser beams LB, but in reality, the laser beam LB can be irradiated along the edge of the hole-forming region. The laser beam LB can be irradiated until the first surface, which is the upper surface of the substrate 100, corresponding to the edge of the hole-forming region, is exposed.

[0121] As the laser beam LB is irradiated along the edge of the hole-forming region, the portion of the display layer DIL and polarization layer POL corresponding to the area where the second hole H2 is formed is separated from the rest of the display layer DIL and polarization layer POL, as shown in Figure 13. Once this portion is removed, the second hole H2, which is connected to the first hole H1, is formed in the display layer DIL and polarization layer POL, as shown in Figure 14.

[0122] When forming the second hole H2 in this way, the laser beam LB is irradiated onto the polarizing layer POL and the substrate 100. In this process, the portion of the lower protective layer BPL on the inner surface of the first hole H1 may be removed. Also, since the substrate 100 contains glass and is therefore translucent, the laser beam LB passes through the substrate 100, and as shown in Figures 13 and 14, a portion of the lower protective layer BPL on the (-z direction) lower surface of the substrate 100 may also be removed. As a result, the portion of the second surface, which is the lower surface of the substrate 100, that is exposed and surrounds the first hole H1 without being covered by the lower protective layer BPL may appear as a ring shape in plan view. The lower protective layer BPL may have a third hole H3 corresponding to the first hole H1 of the substrate 100.

[0123] Furthermore, when forming the second hole H2 in this manner, the laser beam LB is irradiated onto the polarization layer POL and the substrate 100 until the first surface, which is the upper surface of the substrate 100 corresponding to the edge of the hole formation region, is exposed. Therefore, the organic film can be removed from at least the region of the first surface, which is the upper surface of the substrate 100, that is irradiated with the laser beam LB. In other words, in a display panel 10 manufactured through such a process, there is no organic film, such as an organic insulating film, on the first surface, which is the upper surface of the substrate 100, between the display layer DIL and the first hole H1. For example, in Figure 14, there is no organic film on the first surface, which is the upper surface of the substrate 100, between the portion shown in A1 and the portion shown in A2.

[0124] As described above, the second hole H2 is formed using the laser beam LB, and as a result, the edge of the second hole H2 in the polarizing layer POL may include a thermally deformed portion. Similarly, the edge of the third hole H3 in the lower protective layer BPL may include a thermally deformed portion.

[0125] The second holes H2 in the display layer DIL and the polarizing layer POL are formed by the laser beam LB, and the inner surfaces of the second holes H2 in the display layer DIL and the polarizing layer POL can be continuous cylindrical surfaces extending to the upper surface of the substrate 100 in the (+z direction). The fact that the inner surfaces of the second holes H2 are continuous cylindrical surfaces means that there are no steps on the inner surfaces of the second holes H2 extending to the upper surface of the substrate 100. Consequently, the area of ​​the second holes H2 on the lower surface of the polarizing layer POL on the display layer DISL side can be the same as the area of ​​the second holes H2 on the upper surface of the display layer DIL on the polarizing layer POL side.

[0126] A step may exist between the second hole H2 of the display layer DIL and the polarizing layer POL, and the first hole H1 of the substrate 100. This is because the second hole H2 of the display layer DIL and the polarizing layer POL exposes a portion of the first surface, which is the upper surface of the substrate 100. The portion of the upper surface of the substrate 100 that is not covered by the display layer DIL and is exposed has a shape that surrounds the first hole H1 of the substrate 100, and as a result, this portion appears ring-shaped in plan view. Furthermore, the area A2 of the second hole H2 on the lower surface of the display layer DIL is larger than the area of ​​the first hole H1 of the substrate 100.

[0127] As mentioned above, the laser beam LB irradiated to form the second hole H2 forms the third hole H3 in the lower protective layer BPL. The area of ​​the third hole H3 in the lower protective layer BPL is larger than the area of ​​the first hole H1 in the substrate 100. This is because the substrate 100 contains glass and is translucent, so the laser beam LB passes through the substrate 100 and removes a portion of the lower surface of the substrate 100 in the lower protective layer BPL (in the -z direction), as shown in Figures 13 and 14. Thus, since the third hole H3 is formed simultaneously with the laser beam LB irradiated to form the second hole H2, the area A3 of the third hole H3 on the upper surface of the substrate 100 side in the lower protective layer BPL is the same as the area A2 of the second hole H2 on the lower surface of the substrate 100 side in the display layer DIL. In other words, when viewed from a direction perpendicular to the substrate 100 (in the z-axis direction), the edge (contour) of the third hole H3 on the upper surface of the lower protective layer BPL may overlap with the edge (contour) of the second hole H2 on the lower surface of the display layer DIL.

[0128] Figure 15 is a schematic plan view showing the display panel 10 included in the electronic device of Figure 1. As shown in Figure 15 and as described above, the display panel 10 may include an aperture region OA, an intermediate region MA called the first region, a display region DA called the second region, and a peripheral region PA. For example, the substrate 100 of the display panel 10 can be considered to include a first hole H1 corresponding to the aperture region OA, a display region DA located outside the first hole H1 so as to surround the first hole H1, an intermediate region MA located between the first hole H1 and the display region DA, and a peripheral region PA located outside the display region DA.

[0129] The display panel 10 includes a plurality of pixels P arranged in the display area DA, and the display panel 10 can display an image using light emitted from the pixels P. Each pixel P may emit red, green, or blue light using a light-emitting diode. The pixels P may be electrically connected to scan lines SL and data lines DL.

[0130] The peripheral region PA may include scan drivers 11 and 12 that provide scan signals to each pixel P, a data driver 20 that provides data signals to each pixel P, a first power supply wiring (not shown) for providing a drive voltage to each pixel P, and a second power supply wiring (not shown) for providing a common voltage to each pixel P.

[0131] The intermediate region MA may surround the aperture region OA. Display elements such as light-emitting diodes may not be located in the intermediate region MA. Of course, display elements may be placed in the intermediate region MA as needed, in which case the pixel circuits electrically connected to the display elements may be located either within the intermediate region MA or within the display region DA. Signal lines that provide signals to pixels P located relatively adjacent to the aperture region OA within the display region DA may partially pass through such an intermediate region MA.

[0132] For example, a data line DL crosses the display area DA, but a portion of the data line DL can be bypassed in the intermediate area MA by extending along the edge (contour) of the through-hole 10H of the display panel 10 formed in the opening area OA. Figure 15 illustrates a case where the data line DL crosses the display area DA along the y-axis direction, but a portion of the data line DL bypasses in the intermediate area MA so as to partially surround the opening area OA.

[0133] The scan line SL traverses the display area DA along the x-axis direction, but may include a first and second portion separated from each other by the aperture area OA. In this case, the first portion of the scan line SL, located on one side of the aperture area OA (-x direction), is electrically connected to the scan driver 11 located on the same side, and the second portion of the scan line SL, located on the other side of the aperture area OA (+x direction), may be electrically connected to the scan driver 12 located on the other side. This eliminates the need for the scan line SL to detour in a way that partially surrounds the aperture area OA within the intermediate area MA. Of course, if the display panel 10 has only one scan driver, some of the scan line SL may detour in a way that partially surrounds the aperture area OA within the intermediate area MA.

[0134] For reference, Figure 15 illustrates that the data driver 20 is positioned on the substrate 100 so as to be adjacent to one edge of the substrate 100 in the (-y direction), but the present invention is not limited to this. For example, the data driver 20 may be located on a printed circuit board that is electrically connected to the display panel 10 via a pad located on one edge of the display panel 10. And, as shown in Figure 15, when the data driver 20 is positioned on the substrate 100 so as to be adjacent to one edge of the substrate 100 in the (-y direction), a part of the substrate 100 is bent, as described above with reference to Figure 5, and the part of the substrate 100 where the data driver 20 etc. is located may overlap with the display area DA and be located on the back side of the display area DA.

[0135] Figure 16 is an equivalent circuit diagram of the pixel circuit PC electrically connected to the light-emitting diode LEDs included in the display panel 10 of Figure 15.

[0136] As illustrated in Figure 16, a pixel circuit PC including multiple thin-film transistors and capacitors can be electrically connected to a light-emitting diode (LED). In Figure 16, the pixel circuit PC is shown to include seven thin-film transistors T1 to T7 and a storage capacitor Cst. However, the present invention is not limited thereto, and the number and connection relationships can be varied in various ways.

[0137] Multiple thin-film transistors T1 to T7 and storage capacitor Cst may be connected to signal lines SL, SL-1, SL+1, EL, DL, initialization voltage line VIL, and drive voltage line PL. At least one of these connections, for example, the drive voltage line PL, may be shared by adjacent pixels P.

[0138] The multiple thin-film transistors T1 to T7 may include a drive transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, a light emission control transistor T6, and a second initialization transistor T7.

[0139] Light-emitting diodes (LEDs), such as organic light-emitting diodes, include pixel electrodes and a common electrode. The pixel electrodes of the LED are connected to a drive transistor T1 via a light-emitting control transistor T6 to provide a drive current, and the common electrode may be supplied with a second power supply voltage ELVSS. The LED can generate light with a brightness corresponding to the drive current.

[0140] Figure 16 illustrates that multiple thin-film transistors T1 to T7 are all PMOS (p-channel MOSFETs), but the present invention is not limited to this. For example, multiple thin-film transistors T1 to T7 could all be NMOS (n-channel MOSFETs). Alternatively, some of the multiple thin-film transistors T1 to T7 could be PMOS and the rest could be NMOS. Such multiple thin-film transistors T1 to T7 could include amorphous silicon or polysilicon. Alternatively, at least some of the thin-film transistors could include oxide semiconductors.

[0141] The signal lines may include a scan line SL that transmits a scan signal Sn to the switching transistor T2 and the compensation transistor T3, a pre-stage scan line SL-1 that transmits a pre-stage scan signal Sn-1 to the first initialization transistor T4, a post-stage scan line SL+1 that transmits a post-stage scan signal Sn+1 to the second initialization transistor T7, a light emission control line EL that transmits a light emission control signal En to the operation control transistor T5 and the light emission control transistor T6, and a data line DL that crosses the scan line SL and transmits a data signal Dm.

[0142] The drive voltage line PL transmits the drive voltage ELVDD to the drive transistor T1, and the initialization voltage line VIL transmits the initialization voltage Vint to initialize the drive transistor T1 and initialize the pixel electrodes of the light-emitting diode LED.

[0143] The drive gate electrode of the drive transistor T1 is connected to the first capacitor electrode of the storage capacitor Cst. One of the source and drain regions of the drive transistor T1 is connected to the drive voltage line PL via the operation control transistor T5. The other of the source and drain regions of the drive transistor T1 may be electrically connected to the pixel electrode of the light-emitting diode LED via the light-emitting control transistor T6. The drive transistor T1 can supply drive current to the light-emitting diode LED by receiving a data signal Dm through the switching operation of the switching transistor T2. That is, the drive transistor T1 can control the amount of current flowing to the organic light-emitting diode OLED in response to the voltage that changes with the data signal Dm.

[0144] The switching gate electrode of switching transistor T2 is connected to scan line SL, which transmits the scan signal Sn. One of the source and drain regions of switching transistor T2 is connected to data line DL. The other of the source and drain regions of switching transistor T2 may be connected to the drive voltage line PL via the operation control transistor T5 while being connected to the drive transistor T1. Switching transistor T2 can transmit the data signal Dm from data line DL to drive transistor T1 in response to the voltage applied to scan line SL. That is, switching transistor T2 can perform a switching operation in which it is turned on by the scan signal Sn transmitted via scan line SL and transmits the data signal Dm transmitted to data line DL to drive transistor T1.

[0145] The compensating gate electrode of the compensating transistor T3 is connected to the scan line SL. Either the source region or the drain region of the compensating transistor T3 may be connected to the pixel electrode of the light-emitting diode LED via the light-emitting control transistor T6. The other of the source region or drain region of the compensating transistor T3 may be connected to the first capacitor electrode of the storage capacitor Cst and the drive gate electrode of the drive transistor T1. Such a compensating transistor T3 can be turned on by a scan signal Sn transmitted through the scan line SL to diode-couple the drive transistor T1.

[0146] The first initialization gate electrode of the first initialization transistor T4 may be connected to the preceding scan line SL-1. Either the source region or the drain region of the first initialization transistor T4 may be connected to the initialization voltage line VIL. The other of the source region or drain region of the first initialization transistor T4 may be connected to the first capacitor electrode CE1 of the storage capacitor Cst and the drive gate electrode of the drive transistor T1, etc. The first initialization transistor T4 can be turned on by the preceding scan signal Sn-1 transmitted via the preceding scan line SL-1 and perform an initialization operation in which it transmits the initialization voltage Vint to the drive gate electrode of the drive transistor T1, thereby initializing the voltage of the drive gate electrode of the drive transistor T1.

[0147] The control gate electrode of the control transistor T5 is connected to the light emission control line EL. Either the source region or the drain region of the control transistor T5 is connected to the drive voltage line PL, and the other may be connected to the drive transistor T1 and the switching transistor T2.

[0148] The light emission control gate electrode of the light emission control transistor T6 is connected to the light emission control line EL, and one of the source and drain regions of the light emission control transistor T6 is connected to the drive transistor T1 and the compensation transistor T3, while the other of the source and drain regions of the light emission control transistor T6 may be electrically connected to the pixel electrode of the light-emitting diode LED.

[0149] The operation control transistor T5 and the light emission control transistor T6 are simultaneously turned on by the light emission control signal En transmitted via the light emission control line EL, and the drive voltage ELVDD is transmitted to the light-emitting diode LED via the drive transistor T1, causing a drive current to flow to the light-emitting diode LED.

[0150] The second initialization gate electrode of the second initialization transistor T7 is connected to the subsequent scan line SL+1. Either the source region or drain region of the second initialization transistor T7 is connected to the pixel electrode of the light-emitting diode LED, and the other of the source region or drain region of the second initialization transistor T7 is connected to the initialization voltage line VIL, which can provide the initialization voltage Vint. The second initialization transistor T7 is turned on by the subsequent scan signal Sn+1 transmitted via the subsequent scan line SL+1 to initialize the pixel electrode of the light-emitting diode LED. For reference, the subsequent scan line SL+1 may be the scan line SL of a pixel adjacent to pixel P shown in Figure 4, and electrically connected to the data line DL. That is, the scan line SL can transmit the same electrical signal with a time difference and function as the scan line SL of one pixel or as the subsequent scan line SL+1 of an adjacent pixel.

[0151] The storage capacitor Cst may include a first capacitor electrode and a second capacitor electrode. The first capacitor electrode of the storage capacitor Cst is connected to the drive gate electrode of the drive transistor T1, and the second capacitor electrode of the storage capacitor Cst is connected to the drive voltage line PL. The storage capacitor Cst may store a charge corresponding to the difference between the drive gate electrode voltage of the drive transistor T1 and the drive voltage ELVDD.

[0152] The specific operation of each pixel P in one embodiment is as follows:

[0153] During the initialization period, if the pre-stage scan signal Sn-1 is supplied through the pre-stage scan line SL-1, the first initialization transistor T4 is turned on and the drive transistor T1 is initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0154] During the data programming period, when a scan signal Sn is supplied via scan line SL, the switching transistor T2 and compensation transistor T3 are turned on. At this time, the drive transistor T1 is diode-connected by the turned-on compensation transistor T3 and forward-biased. Then, a compensation voltage (Dm + Vth, where Vth is the negative value) is applied to the drive gate electrode of the drive transistor T1, which is reduced by the threshold voltage (Vth) of the drive transistor T1 from the data signal Dm supplied from data line DL. The drive voltage ELVDD and the compensation voltage (Dm + Vth) are applied across the storage capacitor Cst, and a charge corresponding to the voltage difference across its terminals is stored in the storage capacitor Cst.

[0155] During the light emission period, the operation control transistor T5 and the light emission control transistor T6 are turned on by the light emission control signal En supplied from the light emission control line EL. A drive current is generated by the voltage difference between the voltage of the drive gate electrode of the drive transistor T1 and the drive voltage ELVDD, and this drive current is supplied to the light-emitting diode LED via the light emission control transistor T6.

[0156] Figure 17 is a schematic plan view showing the aperture region OA, the intermediate region MA, and a portion of the display region DA in the display panel 10 of Figure 15. As shown in Figure 17, pixels P are arranged in the display region DA.

[0157] Between the aperture region OA and the second region, the display region DA, there may be a first region, the intermediate region MA. Pixels P adjacent to the aperture region OA may be arranged on a plane, separated from each other with the aperture region OA as the center. That is, pixels P may be arranged separated vertically (in the y-axis direction) from the aperture region OA in Figure 17, or separated horizontally (in the x-axis direction) from the aperture region OA.

[0158] Of the signal lines that supply signals to the pixel circuits connected to the light-emitting diodes of each pixel P, signal lines adjacent to the aperture region OA may bypass the aperture region OA and / or the through-hole 10H. A portion of the data lines DL that pass through the display region DA are located in the same row, but extend (in the y-axis direction) to provide data signals to pixels P located on one side of the aperture region OA (+y direction) and pixels P located on the other side of the aperture region OA (-y direction). However, in the intermediate region MA, they may bypass the aperture region OA and / or the through-hole 10H along their edges.

[0159] Figure 17 illustrates that the first data line DL1 includes a first extension DL-L1 electrically connected to a pixel P located on one side (+y direction) of the aperture region OA, a first extension DL-L1 electrically connected to a pixel P located on the other side (-y direction) of the aperture region OA, and a first bypass DL-C1 that bypasses the aperture region OA and / or through-hole 10H along its edge in the intermediate region MA. The first bypass DL-C1 can electrically connect two mutually separated first extension DL-L1s. The first bypass DL-C1 can generally be located on one side (+x direction) of the aperture region OA, as shown in Figure 17. The first bypass portion DL-C1 is located in a different layer from the layer in which the first extension portion DL-L1 is located, in which case it may be connected to the first extension portion DL-L1 via a contact hole CNT, as shown in Figure 17. Of course, alternatively, the first bypass portion DL-C1 and the first extension portion DL-L1 may be formed as a single unit.

[0160] On the other hand, Figure 17 illustrates that the second data line DL2 includes a second extension portion DL-L2 electrically connected to a pixel P located on one side (+y direction) of the aperture region OA, a second extension portion DL-L2 electrically connected to a pixel P located on the other side (-y direction) of the aperture region OA, and a second bypass portion DL-C2 that bypasses the aperture region OA and / or through-hole 10H along the edge of the aperture region OA and / or through-hole 10H in the intermediate region MA. The second bypass portion DL-C2 can electrically connect two mutually separated second extension portions DL-L2. The second bypass portion DL-C2 can generally be located on one side (-x direction) of the aperture region OA, as illustrated in Figure 17. As illustrated in Figure 17, the second bypass portion DL-C2 and the second extension portion DL-L2 can be formed integrally. Of course, in contrast to this, the second bypass portion DL-C2 may be located in a different layer from the layer in which the second extension portion DL-L2 is located, in which case it may be connected to the second extension portion DL-L2 via a contact hole.

[0161] The scan line SL can be separated or disconnected around the aperture region OA. Figure 17 illustrates that the scan line SL includes two sub-scan lines SL-L separated around the aperture region OA. The sub-scan line SL-L located to the left (-x direction) of the aperture region OA receives signals from the scan driver 11 located to the left (-x direction) of the display region DA, while the sub-scan line SL-L located to the right (+x direction) of the aperture region OA may receive signals from the scan driver 12 located to the right (+x direction) of the display region DA. Of course, these sub-scan lines SL-L may be electrically connected to each other by a bypass portion in the intermediate region MA, and the display panel 10 may have a single scan driver.

[0162] A groove G may be located in the intermediate region MA. Groove G may be located between the region around which the data line DL bypasses and the opening region OA. That is, groove G may be located between the first bypass portion DL-C1 and the second bypass portion DL-C2 and the opening region OA. In a plan view taken from a direction approximately perpendicular to the substrate 100 (z-axis direction), each groove G may have a closed-loop shape surrounding the opening region OA. Such grooves G may be located spaced apart from each other.

[0163] Figure 18 is a schematic cross-sectional view taken along the line B-B' of the display panel 10 in Figure 17.

[0164] A buffer layer 201 may be placed on the substrate 100 to prevent impurities from penetrating the semiconductor layer Act of the thin-film transistor TFT. The buffer layer 201 contains an inorganic insulator such as silicon nitride, silicon oxynitride, and / or silicon oxide, and may have a single-layer or multilayer structure.

[0165] A pixel circuit PC may be arranged on the buffer layer 201. The pixel circuit PC may include a thin-film transistor TFT and a storage capacitor Cst. The thin-film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE and / or a drain electrode DE. The thin-film transistor TFT shown in Figure 18 may be a driving transistor. Of course, in the pixel circuit PC described above based on Figure 16, a light emission control transistor T6 is interposed between the driving transistor T1 and the organic light-emitting diode OLED. In such a case, unlike what is shown in Figure 18, the thin-film transistor TFT, which is the driving transistor, is not connected to the pixel electrode 221 of the organic light-emitting diode via the contact metal layer CM, but is electrically connected to a light emission control transistor (not shown), and that light emission control transistor may be electrically connected to the pixel electrode 221 of the organic light-emitting diode. For convenience, the following describes a structure in which the thin-film transistor TFT of Figure 18 is connected to the pixel electrode 221 of the organic light-emitting diode via the contact metal layer CM.

[0166] Although not shown in Figure 18, the data line DL of the pixel circuit PC can be electrically connected to a switching transistor included in the pixel circuit PC.

[0167] The semiconductor layer Act may contain polysilicon. Alternatively, the semiconductor layer Act may contain amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The gate electrode GE may contain a low-resistance metallic material. For example, the gate electrode GE may contain a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may have a multilayer or monolayer structure. For example, the gate electrode GE may have a three-layer structure of a molybdenum layer, an aluminum layer, and a molybdenum layer (Mo / Al / Mo).

[0168] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may contain inorganic insulators such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The gate insulating layer 203 may have a single-layer or multilayer structure.

[0169] The source electrode SE and drain electrode DE are located on the same layer as the data line DL and may contain the same material as the data line DL. The source electrode SE, drain electrode DE, and data line DL may contain materials with excellent conductivity. The source electrode SE and drain electrode DE contain conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may have a multilayer or monolayer structure. For example, the source electrode SE, drain electrode DE, and data line DL may have a multilayer structure of titanium layers, aluminum layers, and titanium layers (Ti / Al / Ti).

[0170] Figure 18 illustrates that the thin-film transistor TFT includes both a source electrode SE and a drain electrode DE, but the present invention is not limited to this. For example, the drain region of the semiconductor layer Act of the thin-film transistor TFT may be formed integrally with the source region of the semiconductor layer of another thin-film transistor. In this case, the thin-film transistor TFT may not have a drain electrode DE, and the other thin-film transistor may not have a source electrode. In this case, the circuit diagram shows that the drain of the thin-film transistor TFT and the source of the other thin-film transistor are connected. In the pixel circuit PC of Figure 16, it is shown that the drain of the driving transistor T1 and the source of the light emission control transistor T6 are connected. In this case, the driving transistor T1 may not have a drain electrode, and the light emission control transistor T6 may not have a source electrode, and the drain region of the semiconductor layer of the driving transistor T1 and the source region of the light emission control transistor T6 may be formed integrally. Similarly, in the pixel circuit PC of Figure 16, the source of the drive transistor T1 is connected to the drain of the operation control transistor T5. Therefore, the drive transistor T1 does not have a source electrode, and the operation control transistor T5 does not have a drain electrode. The source region of the semiconductor layer of the drive transistor T1 and the drain region of the operation control transistor T5 can be formed integrally. As a result, the drive transistor T1 does not need to have either a source electrode or a drain electrode.

[0171] The storage capacitor Cst may include a first capacitor electrode CE1 and a second capacitor electrode CE2 superimposed on each other with a first interlayer insulating layer 205 in between. The storage capacitor Cst may be superimposed on a thin-film transistor TFT. In Figure 18, the gate electrode GE of the thin-film transistor TFT is shown to be the first capacitor electrode CE1 of the storage capacitor Cst. Of course, the present invention is not limited to this, and the storage capacitor Cst may not be superimposed on a thin-film transistor TFT. The storage capacitor Cst may be covered with a second interlayer insulating layer 207. The second capacitor electrode CE2 of the storage capacitor Cst may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may have a multilayer (laminated) structure or a single-layer structure.

[0172] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may contain inorganic insulators such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or hafnium oxide. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may have a single-layer structure or a multilayer structure.

[0173] The pixel circuit PC, which includes a thin-film transistor TFT and a storage capacitor Cst, may be covered with a first organic insulating layer 209.

[0174] The pixel circuit PC can be electrically connected to the pixel electrode 221. For example, as shown in Figure 18, a contact metal layer CM can be interposed between the thin-film transistor TFT and the pixel electrode 221. The contact metal layer CM is connected to the thin-film transistor TFT via contact holes formed in the first organic insulating layer 209, and the pixel electrode 221 can be connected to the contact metal layer CM via contact holes formed in the second organic insulating layer 211 on the contact metal layer CM. The contact metal layer CM contains a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and can have a multilayer or monolayer structure. For example, the contact metal layer CM can have a multilayer structure of a titanium layer, an aluminum layer, and a titanium layer (Ti / Al / Ti).

[0175] The first organic insulating layer 209 and the second organic insulating layer 211 may contain organic insulators such as acrylic, polystyrene (PS), polymethyl methacrylate (PMMA), BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane). For example, the first organic insulating layer 209 and the second organic insulating layer 211 may contain polyimide. The first organic insulating layer 209 and / or the second organic insulating layer 211 may have a substantially flattened upper surface. That is, the first organic insulating layer 209 and / or the second organic insulating layer 211 may also be called a planarized layer.

[0176] The pixel electrode 221 located on the second organic insulating layer 211 may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode 221 may include a reflective layer containing Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or compounds thereof, and a transparent or translucent electrode layer located on the reflective layer. The transparent or translucent electrode layer may comprise at least one selected from the group including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx:ZnO or ZnO2), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode 221 may have a three-layer structure of ITO / Ag / ITO.

[0177] A pixel definition film 215 may be placed on the second organic insulating layer 211. The pixel definition film 215 covers the edges of the pixel electrodes 221 and increases the distance between the pixel electrodes 221 and the common electrode 223 above the pixel electrodes 221, thereby preventing the generation of arcs at the edges of the pixel electrodes 221. That is, the pixel definition film 215 may have an opening that exposes the central part of the pixel electrodes 221. Such a pixel definition film 215 may be one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin, and may be formed by methods such as spin coating. Alternatively, the pixel definition film 215 may include inorganic insulators such as silicon nitride (SiNx), silicon oxynitride (SiON), or silicon oxide (SiOx).

[0178] The intermediate layer 222 interposed between the pixel electrode 221 and the common electrode 223 may include a light-emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed between the light-emitting layer 222b and the pixel electrode 221, and a second functional layer 222c disposed between the light-emitting layer 222b and the common electrode 223. The light-emitting layer 222b emits light of a predetermined hue and may contain polymers or low-molecular-weight organic materials.

[0179] The first functional layer 222a can be a single layer or a multilayer. For example, if the first functional layer 222a contains a polymeric substance, it may be a single-layer hole transport layer (HTL) containing polyethylenedioxythiophene (PEDOT) or polyaniline (PANI). If the first functional layer 222a contains a low molecular weight substance, it may contain a hole injection layer (HIL) and a hole transport layer (HTL).

[0180] The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0181] On the other hand, unlike the illustration in Figure 18, the intermediate layer 222 may include a first stack containing the light-emitting layer 222b and a functional layer, a second stack containing the light-emitting layer 222b and a functional layer, and a charge generation layer between the first and second stacks. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. In the case of a tandem type light-emitting diode LED having multiple light-emitting layers, the luminous efficiency can be further increased by including a negative charge generation layer and a positive charge generation layer.

[0182] The negative charge generation layer can be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer can contain a host and a dopant. The host can contain organic matter. The dopant can contain metallic matter. The positive charge generation layer can be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer can contain a host and a dopant. The host can contain organic matter. The dopant can contain metallic matter.

[0183] The light-emitting layer 222b may have a patterned shape corresponding to the pixel electrode 221. The layers other than the light-emitting layer 222b included in the intermediate layer 222 can be formed integrally on multiple pixel electrodes 221, and can undergo various other deformations. Furthermore, the layers other than the light-emitting layer 222b included in the intermediate layer 222 may also be located in the intermediate region MA.

[0184] The common electrode 223 can be a translucent electrode or a reflective electrode. For example, the common electrode 223 can also be a transparent or translucent electrode and may include a thin metal film with a low work function containing Li, Ca, Al, Ag, Mg or their compounds (e.g., LiF). The common electrode 223 may further include a TCO (transparent conductive oxide) film such as ITO, IZO, ZnO, ZnO2, or In2O3 located on the thin metal film.

[0185] The common electrode 223 can be integrally formed across the entire surface of the display area DA to cover the display area DA, and can be positioned above the intermediate layer 222 and the pixel definition film 215. That is, each pixel electrode 221 is positioned corresponding to each light-emitting diode LED, and the common electrode 223 can be integrally formed corresponding to multiple organic light-emitting diodes OLEDs. Multiple organic light-emitting diodes OLEDs share the common electrode 223, and the stacked structure of the pixel electrode 221, intermediate layer 222, and common electrode 223 can correspond to an organic light-emitting diode OLED.

[0186] The capping layer 230 may be located on the common electrode 223. For example, the capping layer 230 may contain LiF. Of course, the capping layer 230 may be omitted.

[0187] Spacers 217 may be placed on the pixel definition film 215. The spacers 217 may contain an organic insulator such as polyimide. Alternatively, the spacers 217 may contain an inorganic insulator, or both an organic and an inorganic insulator.

[0188] The spacer 217 may contain a different material from the pixel definition film 215, or it may contain the same material as the pixel definition film 215. For example, both the pixel definition film 215 and the spacer 217 may contain polyimide. If the pixel definition film 215 and the spacer 217 contain the same material, they can be formed simultaneously in a masking process using a halftone mask. The functional layer or common electrode 223 of the aforementioned intermediate layer 222 may cover such a spacer 217.

[0189] The organic light-emitting diode (OLED) is covered with a thin film encapsulation layer 300. The thin film encapsulation layer 300 includes at least one organic encapsulation layer and at least one inorganic encapsulation layer. Figure 18 illustrates that the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 interposed between them. Of course, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be changed.

[0190] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contain one or more inorganic substances selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each have a single-layer or multi-layer structure. The organic encapsulation layer 320 may contain polymer-based materials. Polymer-based materials may include acrylic resins such as polymethyl methacrylate or polyacrylic acid, epoxy resins, polyimides, and / or polyethylene. For example, the organic encapsulation layer 320 may contain acrylate.

[0191] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may contain different materials. For example, the first inorganic encapsulation layer 310 may contain silicon oxynitride, and the second inorganic encapsulation layer 330 may contain silicon nitride.

[0192] An additional planarization layer SPL is located on the thin film encapsulation layer 300, and a polarizing layer POL may be located on the additional planarization layer SPL. The additional planarization layer SPL may contain an organic insulator such as acrylic, polystyrene (PS), polymethyl methacrylate (PMMA), BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane) as part of the display layer DIL described above. Such an additional planarization layer SPL may be formed by an inkjet printing method or a spin coating method. The additional planarization layer SPL has a substantially flat top surface. If the display layer DIL includes a touchscreen layer located on the thin film encapsulation layer 300, the additional planarization layer SPL may be located on such a touchscreen layer.

[0193] As mentioned above, and as illustrated in Figure 18, the inner surface H2S of the second hole H2, which is contained in the display layer DIL and the polarizing layer POL, can be a continuous surface extending to the top surface of the substrate 100. That is, in the polarizing layer POL, the additional planarization layer SPL, the second interlayer insulating layer 207, the first interlayer insulating layer 205, the gate insulating layer 203 and / or the buffer layer 201, the inner surface H2S of the second hole H2 can form a continuous cylindrical surface without any steps.

[0194] The intermediate region MA shown in Figure 18 may include a first sub-intermediate region SMA1 that is relatively far from the opening region OA where the through-hole 10H of the display panel 10 is located, i.e., the opening region OA where the first hole H1 of the substrate 100 is located, and a second sub-intermediate region SMA2 that is relatively close to the opening region OA. Lines and grooves G1, G2, and G that bypass the opening region OA may be arranged in the intermediate region MA.

[0195] A line, for example, data line DL, may be located in the first sub-intermediate region SMA1. The data line DL in the first sub-intermediate region SMA1, as shown in Figure 18, corresponds to the bypass portion of data line DL mentioned above, referring to Figure 17, for example, the first bypass portion DL-C1 and the second bypass portion DL-C2. The first sub-intermediate region SMA1 can also be understood as a line region or bypass region to which a line such as data line DL bypasses.

[0196] In the first sub-intermediate region SMA1, the data lines DL may be arranged alternately with an insulating layer in between. That is, one of adjacent data lines DL may be located below the insulating layer (e.g., the first organic insulating layer) 209, and the other may be located above the insulating layer (e.g., the first organic insulating layer) 209. When the data lines DL are arranged alternately with an insulating layer in between, the distance (Δd, pitch) between data lines shown in the plan view can be reduced. Figure 18 illustrates the data lines DL located in the first sub-intermediate region SMA1, but if necessary, the bypass portion of the scan line SL may also be located in the first sub-intermediate region SMA1.

[0197] Grooves G1, G2, and G may be located in the second sub-intermediate region SMA2. Organic layers contained in the intermediate layer 222, for example, the first functional layer 222a and / or the second functional layer 222c, may be interrupted (or separated) by grooves G1, G2, and G. The second sub-intermediate region SMA2 may be understood as a groove region or as an interrupted (or separated) region of the organic layers.

[0198] Grooves G1, G2, and G can be formed by layers interposed between the substrate 100 and the organic light-emitting diode (OLED), which is the display element. Figure 18 shows that the first organic insulating layer 209, which can be called the upper layer, is located on top of the second interlayer insulating layer 207, which can be called the lower layer, and has grooves G1, G2, and G. Of course, each of grooves G1, G2, and G can be formed across multiple layers.

[0199] Of the grooves G1, G2, and G located in the intermediate region MA, which can be called the first region, the first groove G1, which is the groove closest to the opening region OA where the first hole H1 of the substrate 100 is located, may be formed in the first upper layer 209a located on the second interlayer insulating layer 207, which can be called the lower layer. The first upper layer 209a may be referred to as a part of the first organic insulating layer 209. Alternatively, the first upper layer 209a may be formed simultaneously with the first organic insulating layer 209 in the manufacturing process using the same material, but separated from the first organic insulating layer 209. The first groove G1 may extend along at least a part of the opening region OA, or it may encircle the opening region OA as described above with reference to Figure 17. The materials for forming the intermediate layer 222, the common electrode 223, and the capping layer 230 may be located within the first groove G1. This is also true for the other grooves described later.

[0200] The first-first metal layer M1-1 can be positioned so as to span the second interlayer insulating layer 207, which can be considered a lower layer, and the first upper layer 209a. The first-first metal layer M1-1 can be formed simultaneously with the contact metal layer CM from the same material during the manufacturing process. Such a first-first metal layer M1-1 can be positioned in the direction of the opening region OA (-x direction) where the through hole 10H is located, centered on the first groove G1 of the first upper layer 209a. In this case, the end of the first-first metal layer M1-1 in the direction of the opening region OA (-x direction) is located on the second interlayer insulating layer 207, which can be considered a lower layer, and the end of the first-first metal layer M1-1 in the direction of the first groove G1 may protrude from the first upper layer 209a and be located within the first groove G1.

[0201] On the other hand, the first-second metal layer M1-2, separated from the first-first metal layer M1-1, may be positioned across the second interlayer insulating layer 207, which can be called the lower layer, and the first upper layer 209a, such that it is positioned in the direction of the second region, the display region DA (+x direction), with the center of the first groove G1. In this case, the end (edge) of the first-second metal layer M1-2 on the central side of the first groove G1 may protrude from the first upper layer 209a and be located within the first groove G1.

[0202] Thus, the central end of the first groove G1 of the first-1 metal layer M1-1 protrudes from the first upper layer 209a and is located within the first groove G1, and the central end of the first groove G1 of the first-2 metal layer M1-2 protrudes from the first upper layer 209a and is located within the first groove G1. Considering the set of the first upper layer 209a, the first-1 metal layer M1-1, and the first-2 metal layer M1-2, it can be understood that the first groove G1 has an undercut structure. The end of the first-1 metal layer M1-1 that protrudes from the first upper layer 209a is called the protruding tip, and the length of the protrusion from the first upper layer 209a is approximately 0.3 μm to 0.5 μm, and for example, it may be 0.4 μm. The protruding length of the portion of the end of the first-second metal layer M1-2 that protrudes from the first upper layer 209a is also the same.

[0203] As described above, the functional layer included in the intermediate layer 222 is formed to substantially cover the entire surface of the substrate 100, and thereafter, a part of the substrate 100 can be removed to form through-holes 10H in the display panel 10. As a result, moisture from the outside that has penetrated into the functional layer through the through-holes 10H may move along the functional layer to the display area DA, causing defects. However, in the case of the display panel 10 and the electronic device 1 equipped therewith according to this embodiment, as described above, it has a first groove G1 with an undercut structure, and such a first groove G1 with an undercut structure may be formed in the manufacturing process before the intermediate layer 222 is formed. Therefore, as shown in Figure 18, the functional layer included in the intermediate layer 222 is discontinuous due to the first groove G1 with an undercut structure, and as a result, even if moisture penetrates into the functional layer through the through-holes 10H, it is possible to effectively prevent or minimize the movement of that moisture in the direction of the display area DA.

[0204] Of course, as mentioned above, in the case of the display panel 10 according to this embodiment, there is no organic film such as an organic insulating film on the first surface, which is the upper surface of the substrate 100, between the display layer DIL and the opening region OA, that is, between the first hole H1 of the display layer DIL. For example, Figure 18 also shows that there is no organic film such as an organic insulating film on the first surface, which is the upper surface of the substrate 100, between the inner surface H2S of the second hole H2 and the opening region OA. This effectively prevents or minimizes the penetration of moisture and other substances from the outside that have penetrated through the through-hole 10H into the functional layer.

[0205] As mentioned above, in the case of the first-first metal layer M1-1 located in the direction of the opening region OA (-x direction) centered on the first groove G1, which is the groove closest to the opening region OA, the end in the direction of the opening region OA (-x direction) may be located on the second interlayer insulating layer 207, which can be considered the lower layer. The bonding force between the first-first metal layer M1-1 containing metal and the inorganic insulating material is stronger than the bonding force between the first-first metal layer M1-1 containing metal and the organic insulating material. As mentioned above, since the second interlayer insulating layer 207 contains an inorganic insulating material, the end of the first-first metal layer M1-1 in the direction of the opening region OA (-x direction) can be strongly bonded to the second interlayer insulating layer 207. This can prevent or minimize defects such as delamination between layers near the opening region OA.

[0206] Of the grooves G1, G2, and G located in the intermediate region MA, which can be called the first region, the second groove G2, which is the second closest groove to the opening region OA where the through-hole of the substrate 100 is located, may be formed on the second upper layer 209b located on the second interlayer insulating layer 207, which can be called the lower layer. The second upper layer 209b may be referred to as part of the first organic insulating layer 209. Alternatively, the second upper layer 209b may be formed simultaneously with the first organic insulating layer 209 from the same material during the manufacturing process, but separated from the first organic insulating layer 209 so as to be located between the display region DA and the first upper layer 209a. The second upper layer 209b may be separated from the first upper layer 209a. The second groove G2 may extend along at least a portion of the opening region OA, or it may encircle the opening region OA as described above with reference to Figure 17.

[0207] The second-first metal layer M2-1 may be positioned so as to span the second interlayer insulating layer 207, which can be called the lower layer, and the second upper layer 209b. The second-first metal layer M2-1 may be formed simultaneously with the contact metal layer CM from the same material during the manufacturing process. Such a second-first metal layer M2-1 may be positioned in the direction of the opening region OA (-x direction) where the through hole 10H is located, centered on the second groove G2 of the second upper layer 209b. In this case, the end of the second-first metal layer M2-1 in the direction of the second groove G2 may protrude from the second upper layer 209b and be located within the second groove G2.

[0208] On the other hand, the second-second metal layer M2-2, separated from the second-first metal layer M2-1, may be positioned over the second interlayer insulating layer 207 and the second upper layer 209b, which can be called the lower layer, such that it is located in the DA direction (+x direction), which is the second region of the display area, with the center of the second groove G2 at its center. In this case, the end of the second-second metal layer M2-2 in the direction of the center of the second groove G2 may protrude from the second upper layer 209b and be located within the second groove G2.

[0209] Thus, the central end of the second groove G2 of the second-first metal layer M2-1 protrudes from the second upper layer 209b and is located within the second groove G2, and the central end of the second groove G2 of the second-second metal layer M2-2 protrudes from the second upper layer 209b and is located within the second groove G2. Considering the set of the second upper layer 209b, the second-first metal layer M2-1, and the second-second metal layer M2-2, it can be understood that the second groove G2 has an undercut structure. The end of the second-first metal layer M2-1 that protrudes from the second upper layer 209b is called the protruding tip, and the length of the protrusion from the second upper layer 209b may be, for example, about 1.7 μm. The protrusion length of the end of the second-second metal layer M2-2 that protrudes from the second upper layer 209b is similar.

[0210] As mentioned above, the functional layer contained in the intermediate layer 222 is discontinuous due to the first groove G1 of the undercut structure, and similarly, it can also be discontinuous due to the second groove G2 of the undercut structure. This effectively prevents or minimizes the movement of moisture in the display area DA direction even if moisture penetrates the functional layer exposed to the outside on the inner surface of the through-hole 10H.

[0211] As shown in Figure 18, the first-second metal layer M1-2 and the second-first metal layer M2-1 can be formed integrally. Therefore, the integral first-second metal layer M1-2 and the second-first metal layer M2-1 can contact the lower layer, the second interlayer insulating layer 207, between the first upper layer 209a and the second upper layer 209b. The metal layer and the second interlayer insulating layer 207, which are in contact with each other between the first upper layer 209a and the second upper layer 209b, can form an inorganic contact region ICR with strong bonding force. Of course, as mentioned above, the end of the opening region OA side (-x direction) of the first-first metal layer M1-1 can also contact the second interlayer insulating layer 207, forming an inorganic contact region ICR with strong bonding force.

[0212] Similar to the functional layer, the common electrode 223 can also be interrupted by the first groove G1 and the second groove G2. The capping layer 230, which may contain LiF or the like, can also be interrupted by the first groove G1 and the second groove G2. If the capping layer 230 contains an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride, the capping layer 230 may not be interrupted by the first groove G1 and the second groove G2, but may be formed continuously. For convenience, the case in which the capping layer 230 is interrupted by the first groove G1 and the second groove G2 will be described below.

[0213] A first partition wall PW1 and a second partition wall PW2 may be arranged in the intermediate region MA. Figure 18 shows that the first partition wall PW1 and the second partition wall PW2 are arranged in the intermediate region MA, but the present invention is not limited to this. For example, three partition walls may be arranged in the intermediate region MA. The first partition wall PW1 may be located more adjacent to the display region DA than the second partition wall PW2. The first partition wall PW1 and the second partition wall PW2 may each have a shape that encircles the opening region OA.

[0214] The first partition PW1 and the second partition PW2 may each include a plurality of organic insulating layers that are sequentially stacked. For example, the first partition PW1 may have a structure in which a part of the first organic insulating layer 209 (209P), a part of the second organic insulating layer 211 (211P), a part of the pixel definition film 215 (215P), and a part of the spacer 217 (217P) are sequentially stacked. In this case, the part of the first organic insulating layer 209 (209P) may be connected to the first organic insulating layer 209 and separated from the first organic insulating layer 209. The second partition PW2 may have a structure in which a part of the first organic insulating layer 209, a part of the second organic insulating layer 211, and a part of the pixel definition film 215 are sequentially stacked.

[0215] As shown in Figure 18, parts of the functional layer and the common electrode 223 can also be located on the first partition PW1 and the second partition PW2, respectively.

[0216] The thin film encapsulation layer 300, which prevents the organic light-emitting diode (OLED) from being damaged or degraded by external impurities, may include at least one organic encapsulation layer and at least one inorganic encapsulation layer, as described above.

[0217] The first inorganic encapsulation layer 310, formed by chemical vapor deposition or the like, has relatively better step coverage than the functional layer and / or common electrode 223. Therefore, as shown in Figure 18, the first inorganic encapsulation layer 310 is not interrupted by the first groove G1 and the second groove G2, and can cover the inner surfaces of the first groove G1 and the second groove G2.

[0218] The organic encapsulation layer 320 can be formed by coating a monomer onto the substrate 100 and curing it. Alternatively, the organic encapsulation layer 320 can be formed by coating a polymer. The first partition wall PW1 and the second partition wall PW2 can block the flow of the monomer or polymer onto the substrate 100 in the direction of the opening region OA. In Figure 18, the formation region of the organic encapsulation layer 320 is shown as being limited by the first partition wall PW1. If the first partition wall PW1 and the second partition wall PW2, etc., were not present and the material for forming the organic encapsulation layer 320 was coated over the entire surface of the substrate 100, then when a through-hole 10H was formed in the display panel 10, the organic encapsulation layer 320 would be exposed on the inner surface of the through-hole 10H. In that case, the organic encapsulation layer 320 would become a penetration path for moisture and other substances from the outside on the inner surface of the through-hole 10H, potentially causing defects such as damage to the organic light-emitting diode OLED in the display region DA. However, in the case of the display panel 10 and the electronic device 1 equipped therewith according to this embodiment, since there is a first partition wall PW1 and a second partition wall PW2, the occurrence of such defects can be effectively prevented or minimized. For reference, even if an excess of the organic sealing layer 320 forming material is applied during the formation process of the organic sealing layer 320 and the material flows to the outside of the first partition wall PW1, the second partition wall PW2 can prevent the material from flowing any further towards the opening area OA.

[0219] The second inorganic encapsulation layer 330 is located on the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 may be in direct contact with the first inorganic encapsulation layer 310 in a portion of the intermediate region MA. For example, as shown in Figure 18, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be in contact with each other in a portion of the intermediate region MA adjacent to the opening region OA.

[0220] The first groove G1 and the second groove G2 may be located between the second partition wall PW2 and the opening region OA. As shown in Figure 18, a groove G identical or similar in form to the second groove G2 may also be located between the first partition wall PW1 and the second partition wall PW2, and a groove G identical or similar in form to the second groove G2 may also be located between the first partition wall PW1 and the second region, the display region DA. In the groove G, there is a metal layer 210 located on the first organic insulating layer 209 that has a shape similar to the integrated first-second metal layers M1-2 and second-first metal layer M2-1, and can form a chip (shelf-shaped protrusion) that protrudes into the groove G.

[0221] Figure 18 illustrates that there are two grooves G located between the display area DA and the first partition wall PW1, two grooves G located between the first partition wall PW1 and the second partition wall PW2, and two grooves G1 and G2 located between the second partition wall PW2 and the opening area OA, resulting in a total of 12 chips. Of course, the number of chips can vary as needed.

[0222] The cross-sectional view of the display panel 10 shown in Figure 18 can be understood as a structure surrounding the first region OA. For example, as mentioned above, the grooves G1, G2, and G in Figure 18 can each be ring-shaped surrounding the opening region OA when viewed from a direction perpendicular to the upper surface of the substrate 100, as shown in Figure 17. Similarly, the first partition wall PW1 and the second partition wall PW2 can also be ring-shaped surrounding the opening region OA when viewed from a direction perpendicular to the upper surface of the substrate 100. Likewise, the first-first metal layer M1-1 and the first-second metal layer M1-2 can also have a ring shape surrounding the opening region OA when viewed from a direction perpendicular to the upper surface of the substrate 100.

[0223] Figure 19 is a schematic cross-sectional view showing a part of a display panel 10 according to one embodiment of the present invention. In the case of the display panel 10 according to this embodiment, the buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207, which are included in the display layer DIL located on the substrate 100, have additional grooves AG. The buffer layer 201, gate insulating layer 203, first interlayer insulating layer 205, and second interlayer insulating layer 207 can be collectively referred to as the inorganic layer. By having the inorganic layer located on the substrate 100 as the inorganic layer included in the display layer DIL in this way, even if moisture penetrates through the inner surface of the through-hole 10H, the movement of that moisture to the display area DA can be effectively prevented or minimized.

[0224] For reference, Figure 18 shows that the first groove G1 and the second groove G2 are located between the second partition wall PW2 and the opening region OA, and that the number of protruding tips projecting towards the center of the first groove G1 is 2, and the number of protruding tips projecting towards the center of the second groove G2 is 2. In other words, Figure 18 shows that there are 4 protruding tips located between the second partition wall PW2 and the opening region OA. Then, Figure 19 shows that there are 2 protruding tips projecting towards the center of one groove G located between the second partition wall PW2 and the opening region OA, and 1 protruding tip projecting in the direction from groove G toward the opening region OA. In other words, Figure 19 shows that there are 3 protruding tips located between the second partition wall PW2 and the opening region OA.

[0225] In the case of the display panel 10 as shown in Figure 19, as mentioned above, by having an additional groove AG in the inorganic layer located on the substrate 100 as an inorganic layer included in the display layer DIL, it is possible to effectively prevent or minimize the movement of moisture to the display area DA even if moisture penetrates through the inner surface of the through-hole 10H. Taking this into consideration, in the case of the display panel 10 as shown in Figure 19, the number of protruding chips can be reduced.

[0226] For reference, Figures 18 and 19 both illustrate that there are two grooves G between the first partition wall PW1 and the second partition wall PW2, and two protruding chips that project outwards from the center (center line) of each groove G. That is, both Figures 18 and 19 illustrate that there are four protruding chips between the first partition wall PW1 and the second partition wall PW2. However, the present invention is not limited to this. As illustrated in Figure 19, if the inorganic layer located on the substrate 100 as an inorganic layer included in the display layer DIL has additional grooves AG, then there may be fewer than four protruding chips between the first partition wall PW1 and the second partition wall PW2. For example, if the inorganic layer located on the substrate 100 as an inorganic layer included in the display layer DIL has additional grooves AG, then there may be three protruding chips between the first partition wall PW1 and the second partition wall PW2.

[0227] Although the present invention has been described above based on the embodiments illustrated in the drawings, these are merely illustrative examples, and a person with ordinary skill in the art will understand that a variety of modifications and equivalent other embodiments are possible therefrom. Therefore, the true scope of technical protection of the present invention must be determined by the technical idea of ​​the claims.

[0228] A preferred specific embodiment is as follows:

[0229] The background and issues of this matter are as follows (i) to (v).

[0230] (i) Display panels in which light-emitting elements (LEDs) or subpixels such as organic light-emitting elements (OLEDs) are arranged, and pixel circuits are arranged for each light-emitting element (LED) or subpixel, are widely used in smartphones, tablet PCs, smartwatches, and various mobile devices.

[0231] (ii) In smartphones and the like, a display area is formed over the entire or nearly entire front surface, and through-holes (10H) are formed in a part of the display area for a camera (531) and sensors, passing through the display panel (10) (see Figure 6 of this application).

[0232] (iii) The display panel is typically formed from a substrate (100) made of a resin film such as polyimide or a thin tempered glass plate, a "display layer (100)" formed on the substrate as a pixel formation area, and a touch panel and / or polarizing layer (POL). The back surface of the substrate (100) is usually covered with a bottom protective layer (BPL). In addition, a cover window (70) is generally placed over the front surface of the display panel (10).

[0233] (iv) The "display layer (100)" generally includes a circuit layer on which pixel circuits, peripheral drive circuits, and various wirings are formed, a light-emitting element layer on which light-emitting display elements (LEDs) are formed or arranged, and a sealing layer covering the same. The "display layer (100)" includes a metal film, an inorganic insulating film, and an organic resin layer.

[0234] (v) There is a need for a manufacturing method that can efficiently form through-holes in such a laminated display panel.

[0235] In a particularly preferred specific embodiment, it can be manufactured as shown in A1 to A7 below, and further as shown in A8 to A9 below.

[0236] A1 A glass plate is used as the substrate (100). After forming the "display layer (DIL)" on this substrate (100), a temporary protective layer (TPL) is attached.

[0237] In a display panel in which a substrate (100), a "display layer (DIL)," and a temporary protective layer (TPL) are laminated, a ring-shaped or cylindrical "scratch" (cut or fractured portion) is formed by laser irradiation along the contour of the location where a through-hole (10H) is formed. This "scratch" is formed so as to reach the front surface of the substrate (100). (Figure 8 of this application)

[0238] A3 The back side of the substrate (100) is brought into contact with the etching solution to reduce the thickness of the substrate (100). At this time, the etching solution seeps in through the "scratch" and forms a ring-shaped groove that penetrates the substrate (100). (Figure 9 of this application)

[0239] The cylindrical or truncated cone-shaped portion inside the ring-shaped groove of the A4 substrate (100) is removed. (Figure 10 of this application)

[0240] A lower protective layer (BPL) is formed on the back surface by applying a coating using methods such as A5 inkjet printing or spin coating. In this way, the inner surface of the first hole (H1) is also covered by the lower protective layer (BPL). (Figure 11 of this application)

[0241] A6 After peeling off the temporary protective layer (TPL), apply the polarizing layer (POL). (Figure 12 of this application)

[0242] A7 By irradiating from the front side with a laser, a through-hole (10H) is formed by cutting the "display layer (DIL)" and the polarizing layer (POL) in a ring shape at the location corresponding to the first hole (H1). At this time, the lower protective layer (BPL) is also removed near the through-hole (10H) by the laser irradiation. (Figure 13 of this application)

[0243] A8 Within the "Display Layer (DIL)", a laminated film of inorganic and metal layers is formed extending into and near the through-hole (10H), and can function as an etching stopper during etching as shown in Figure 9 of this application. Furthermore, an additional planarization layer (SPL) made of resin material is provided near the through-hole (10H).

[0244] A9 In the "Display Layer (DIL)," multiple ring-shaped grooves (G1, G2, G) are provided surrounding the through-hole (10H) and the opening area (OA). This interrupts the metal layer, preventing adverse effects on the display area even if etching solution seeps into the metal layer. To achieve this, the metal layers (M1-1, M1-2, M2-1, M2-2) are designed to form "protruding tips (tips)" along the edges of the grooves (G1, G2, G). (Figures 17-18 of this application) [Explanation of Symbols]

[0245] 1 Electronic equipment 10 Display Panels 100 circuit boards 100H Through Hole DIL Display Layer POL polarizing layer 70 Cover window H1, Hall 1 H2, Hall 2 H3, Hall 3 OA opening area MA intermediate area DA display area G1 Group 1 G2 2nd Group G Groove M1-1 1st-1st metal layer M1-2 1st-2nd metal layer M2-1 2nd-1st metal layer M2-2 2nd-2nd metal layer PW1 1st bulkhead PW2 2nd bulkhead SPL additional planarization layer AG Additional Grooves

Claims

1. A step of forming a display layer on the first surface of a substrate having a first surface and a second surface that are opposite to each other, The steps include: etching the second surface of the substrate to reduce the thickness of the substrate while removing the portion of the substrate corresponding to the hole formation region to form a first hole; The steps include forming a polarizing layer in the display layer in the direction opposite to the direction toward the substrate, corresponding to the entire surface of the display layer, A method for manufacturing a display panel, comprising the step of forming a second hole connected to the first hole by removing a portion of the polarizing layer and a portion of the display layer corresponding to the edge of the hole-forming region.

2. The process further includes the step of forming a scratch inside the substrate corresponding to the edge of the hole-forming region, The method for manufacturing a display panel according to claim 1, wherein the step of forming the first hole is a step in which, when etching the second surface of the substrate, the etching solution penetrates the scratch and removes the portion of the substrate corresponding to the hole-forming region.

3. The method for manufacturing a display panel according to claim 1, wherein the step of forming the second hole is to irradiate a portion of the polarizing layer corresponding to the edge of the hole-forming region with a laser beam to form the second hole.

4. The method for manufacturing a display panel according to claim 3, wherein the step of forming the second hole is to irradiate the first surface of the substrate corresponding to the edge of the hole-forming region with the laser beam until the second hole is formed.

5. The method for manufacturing a display panel according to claim 3, further comprising the step of forming a lower protective layer so as to cover the lower surface of the display layer exposed by the first hole, the second surface of the substrate, and the inner surface of the first hole.

6. The method for manufacturing a display panel according to claim 5, wherein the step of forming the second hole is to form the second hole by irradiating the lower protective layer with the laser beam such that the portion on the inner surface of the first hole is removed.

7. The method for manufacturing a display panel according to claim 6, wherein the step of forming the second hole is to form the second hole by irradiating the laser beam such that a portion of the second surface of the substrate in the lower protective layer is removed and the portion of the second surface of the substrate surrounding the first hole is exposed.

8. A substrate having a first surface and a second surface facing each other, and a first hole penetrating the first surface and the second surface, The substrate comprises a display layer and a polarizing layer on the display layer, having a second hole located on the first surface of the substrate and superimposed on the first hole when viewed from a direction perpendicular to the substrate, The inner surface of the second hole is a continuous surface without steps until it reaches the first surface of the substrate, and there is no organic film on the first surface of the substrate between the display layer and the first hole, in a display panel.

9. The display panel according to claim 8, wherein the area of ​​the second hole on the lower surface of the polarizing layer on the display layer side is the same as the area of ​​the second hole on the upper surface of the display layer on the polarizing layer side.

10. The display panel according to claim 8, wherein the second hole exposes a portion of the first surface of the substrate.

11. The display panel according to claim 10, wherein the portion of the first surface of the substrate exposed by the second hole surrounds the first hole.

12. The display panel according to claim 8, further comprising a lower protective layer located on the second surface of the substrate and having a third hole corresponding to the first hole.

13. The display panel according to claim 12, wherein the area of ​​the third hole is larger than the area of ​​the first hole.

14. The display panel according to claim 13, wherein the area of ​​the third hole on the upper surface in the substrate direction of the lower protective layer is the same as the area of ​​the second hole on the lower surface in the substrate direction of the display layer.

15. The display panel according to claim 13, wherein, when viewed from a direction perpendicular to the substrate, the edge of the third hole overlaps with the edge of the second hole on the lower surface of the display layer on the substrate side.

16. The display panel according to claim 12, wherein the edge of the third hole in the lower protective layer includes a thermally deformed portion.

17. The display panel according to claim 8, wherein the edge of the second hole in the polarizing layer includes a thermally deformed portion.

18. Display panel and Camera and, Including the bottom cover, The aforementioned display panel is A substrate having a first surface and a second surface facing each other, and a first hole penetrating the first surface and the second surface, The substrate comprises a display layer and a polarizing layer on the display layer, the first surface of the substrate having a second hole that overlaps with the first hole when viewed from a direction perpendicular to the substrate, The inner surface of the second hole is a continuous surface without any steps until it reaches the first surface of the substrate. Between the display layer and the first hole, there is no organic film on the first surface of the substrate. An electronic device in which the camera is located between the display panel and the lower cover.

19. The electronic device according to claim 18, wherein the area of ​​the second hole on the lower surface of the polarizing layer on the display layer side is the same as the area of ​​the second hole on the upper surface of the display layer on the polarizing layer side.

20. The electronic device according to claim 18, wherein the second hole exposes a portion of the first surface of the substrate.

21. The electronic device according to claim 20, wherein the portion of the first surface of the substrate exposed by the second hole surrounds the first hole.

22. The electronic device according to claim 18, further comprising a lower protective layer located on the second surface of the substrate and having a third hole corresponding to the first hole.

23. The electronic device according to claim 22, wherein the area of ​​the third hole is larger than the area of ​​the first hole.

24. The electronic device according to claim 23, wherein the area of ​​the third hole is the same as the area of ​​the second hole on the lower surface of the substrate side in the display layer.

25. The electronic device according to claim 23, wherein, when viewed from a direction perpendicular to the substrate, the edge of the third hole overlaps with the edge of the second hole on the lower surface of the display layer on the substrate side.

26. The electronic device according to claim 22, wherein the edge of the third hole in the lower protective layer includes a thermally deformed portion.

27. The electronic device according to claim 18, wherein the edge of the second hole in the polarizing layer includes a thermally deformed portion.

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