Imaging device and camera system

Abstract

The present invention provides an imaging device, etc., that can suppress changes in the potential of the charge storage region that exceed a predetermined level, and can also improve the signal-to-noise ratio. [Solution] The imaging device comprises a pixel electrode 12a, a light intensity detection electrode 12d positioned at a different location from the pixel electrode 12a in a plan view, a photoelectric conversion layer 12b that converts light into signal charge, a counter electrode 12c that faces the pixel electrode 12a and the light intensity detection electrode 12d via the photoelectric conversion layer 12b, a charge storage node FD connected to the pixel electrode 12a and accumulating signal charge, and an overflow transistor 28 whose source and drain are connected to the charge storage node FD and whose gate is connected to the light intensity detection electrode 12d.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a camera system.

Background Art

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used. These imaging devices have, for example, a photodiode formed on a semiconductor substrate as a photoelectric conversion section. In addition, an imaging device having a structure in which a photoelectric conversion section having a photoelectric conversion layer is disposed on the light incident side of a semiconductor substrate instead of a photodiode has been proposed. An imaging device having such a structure may be called a stacked imaging device. In a stacked imaging device, signal charges generated in the photoelectric conversion section by photoelectric conversion are accumulated in a charge storage region, and a signal corresponding to the amount of charge accumulated in the charge storage region is read out.

[0003] In an imaging device in which signal charges are accumulated in a charge storage region, a transistor for suppressing a change in the potential of the charge storage region exceeding a predetermined value may be connected to the charge storage region.

[0004] For example, a technique for expanding the dynamic range by providing a transistor that can conduct the charge storage region and a capacitance element when the potential of the charge storage region exceeds a predetermined potential is known (see, for example, Patent Document 1 and Patent Document 2).

[0005] In addition, for example, a technique for suppressing damage to a transistor or the like connected to a charge storage region by clipping the potential of the charge storage region at a predetermined potential by a transistor connected to the charge storage region is known (see, for example, Patent Document 3).

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] International Publication No. 2022 / 153628 [Patent Document 2] International Publication No. 2022 / 196155 [Patent Document 3] Japanese Patent Publication No. 2012-209342 [Overview of the project] [Problems that the invention aims to solve]

[0007] This disclosure provides an imaging device, etc., that can suppress changes in the potential of the charge storage region that exceed a predetermined level and can improve the signal-to-noise ratio. [Means for solving the problem]

[0008] An imaging device according to one aspect of the present disclosure includes: a first electrode; a second electrode positioned at a different location from the first electrode in a plan view; a photoelectric conversion layer that converts light into signal charge; a third electrode facing the first electrode and the second electrode via the photoelectric conversion layer; a charge storage region connected to the first electrode for accumulating the signal charge; and a first transistor whose source or drain is connected to the charge storage region and whose gate is connected to the second electrode.

[0009] A camera system relating to one aspect of this disclosure includes the above-mentioned imaging device. [Effects of the Invention]

[0010] According to this disclosure, it is possible to suppress changes in the potential of the charge storage region that exceed a predetermined level, and to improve the signal-to-noise ratio. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a diagram showing the configuration of the imaging device according to Embodiment 1. [Figure 2] Figure 2 is a diagram showing the circuit configuration of a pixel according to Embodiment 1. [Figure 3]FIG. 3 is a schematic cross-sectional view of the device structure of a pixel according to Embodiment 1. [Figure 4] FIG. 4 is a timing chart for explaining an example of the operation of the imaging device according to Embodiment 1. [Figure 5] FIG. 5 is a diagram showing the potential dependence of the charge storage node of the gate overlap capacitance and the pn junction capacitance in the charge storage node. [Figure 6] FIG. 6 is a plan view showing the layout of the pixel electrode and the light amount detection electrode of the imaging device according to Embodiment 1. [Figure 7] FIG. 7 is a schematic cross-sectional view showing the structure near the pixel electrode and the light amount detection electrode of the imaging device according to Embodiment 1. [Figure 8] FIG. 8 is a diagram showing the circuit configuration of a pixel according to Modification 1 of Embodiment 1. [Figure 9] FIG. 9 is a schematic cross-sectional view of the device structure of a pixel according to Modification 1 of Embodiment 1. [Figure 10] FIG. 10 is a diagram showing the circuit configuration of a pixel according to Modification 2 of Embodiment 1. [Figure 11] FIG. 11 is a schematic cross-sectional view of the device structure of a pixel according to Modification 2 of Embodiment 1. [Figure 12] FIG. 12 is a diagram showing the circuit configuration of a pixel according to Modification 3 of Embodiment 1. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a first alternative example of the device structure of a pixel according to Embodiment 1. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a first alternative example of the device structure of a pixel according to Modification 1 of Embodiment 1. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a second alternative example of the device structure of a pixel according to Embodiment 1. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a second alternative example of the device structure of a pixel according to Modification 1 of Embodiment 1. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a third alternative example of the device structure of a pixel according to Embodiment 1. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a third alternative example of the device structure of pixels according to Modification 1 of Embodiment 1. [Figure 19] FIG. 19 is a block diagram showing an example of the configuration of a camera system according to Embodiment 2. Embodiments for Carrying Out the Invention

[0012] (Background Leading to One Aspect of the Present Disclosure) Before specifically describing the embodiments of the present disclosure, the background leading to one aspect of the present disclosure will be described.

[0013] In an imaging device, when excessive light is incident on a photoelectric conversion unit, signal charges are accumulated in a charge storage region, and the absolute value of the potential of the charge storage region rises excessively. Therefore, the potential of the charge storage region changes beyond the signal output possible range, and it may occur that the dynamic range cannot be widened. Further, when the absolute value of the potential of the charge storage region rises excessively, there is a risk that circuit elements such as transistors electrically connected to the charge storage region deteriorate or are damaged. Therefore, in the techniques disclosed in Patent Documents 1 to Patent Documents 3, by providing a transistor in which one of the gate, source, and drain is connected to the charge storage region, a change in the potential of the charge storage region above a predetermined level is suppressed.

[0014] On the other hand, in such a technique, since the gate of the transistor for suppressing a change in the potential of the charge storage region above a predetermined level is connected to the charge storage region, the gate functions as a capacitance for accumulating signal charges. As a result, even when the amount of signal charges accumulated in the charge storage region is the same, the potential of the charge storage region is less likely to change. Therefore, in a situation where the amount of signal charges accumulated in the charge storage region is small, there arises a problem that the conversion gain by photoelectric conversion decreases and the ratio of noise to the signal increases.

[0015] This disclosure is based on the inventor's focus on these issues and provides an imaging device, etc., that can suppress changes in the potential of the charge storage region beyond a predetermined level and improve the signal-to-noise ratio.

[0016] (Summary of this disclosure) As an overview of one aspect of this disclosure, an example of an imaging device and camera system related to this disclosure is shown below.

[0017] For example, an imaging device according to a first aspect of the present disclosure includes a first electrode, a second electrode positioned at a different location from the first electrode in a plan view, a photoelectric conversion layer that converts light into signal charge, a third electrode facing the first electrode and the second electrode via the photoelectric conversion layer, a charge storage region connected to the first electrode for storing the signal charge, and a first transistor whose source or drain is connected to the charge storage region and whose gate is connected to the second electrode.

[0018] As a result, when the signal charge is collected by the second electrode, the potential of the gate of the first transistor connected to the second electrode reaches a threshold potential that depends on the threshold voltage of the first transistor, and the first transistor turns on. Consequently, the signal charge accumulated in the charge storage region can flow to the other side of the source and drain of the first transistor, and changes in the potential of the charge storage region beyond a predetermined level can be suppressed.

[0019] Furthermore, since the gate of the first transistor is connected to the second electrode rather than the first electrode connected to the charge storage region, the capacitance of the gate of the first transistor is not added to the capacitance of the charge storage region. Therefore, it is possible to increase the conversion gain of photoelectric conversion when the gate of the first transistor is in the off state, which increases sensitivity and thus improves the signal-to-noise ratio.

[0020] Based on the above, the imaging device according to this embodiment can suppress changes in the potential of the charge storage region that exceed a predetermined level, and can also improve the signal-to-noise ratio.

[0021] Furthermore, for example, an imaging apparatus according to a second aspect of the present disclosure is an imaging apparatus according to a first aspect, further comprising a second transistor whose source and drain are connected to the gate and second electrode of the first transistor.

[0022] This allows for easy resetting of the potentials of the gate and second electrode of the first transistor.

[0023] Furthermore, for example, an imaging apparatus according to a third aspect of the present disclosure is an imaging apparatus according to a second aspect, wherein the first transistor includes an impurity region of a first conductivity type as one of its source and drain, and the second transistor includes an impurity region of a second conductivity type different from the first conductivity type as one of its source and drain.

[0024] This makes it possible to configure the system so that if an excessive signal charge accumulates between the second electrode and the second transistor, the signal charge can be discharged into the well region from either the source or the drain of the second transistor.

[0025] Furthermore, for example, the imaging device according to the fourth aspect of this disclosure is the imaging device according to the third aspect, wherein the first conductivity type is n type and the second conductivity type is p type.

[0026] This makes it possible to configure the system so that, when the signal charge is a hole, if an excessive amount of signal charge accumulates between the second electrode and the second transistor, the signal charge can be discharged into the well region from either the source or the drain of the second transistor.

[0027] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, further comprising a third transistor whose source and drain are connected to the other source and drain of the first transistor.

[0028] As a result, when the first transistor turns on, the signal charge accumulates not only in the charge storage region but also between the first and third transistors. This increases the capacitance for storing the signal charge, making it more difficult for the potential of the charge storage region to rise. Therefore, once the potential of the gate of the first transistor reaches the threshold potential, the conversion gain due to photoelectric conversion decreases. This allows for a wider dynamic range.

[0029] Furthermore, for example, an imaging apparatus according to a sixth aspect of the present disclosure is an imaging apparatus according to a fifth aspect, wherein the first transistor includes an impurity region of a first conductivity type as one of its source and drain, and the third transistor includes an impurity region of a second conductivity type different from the first conductivity type as one of its source and drain.

[0030] This makes it possible to configure the system so that if an excess of signal charge accumulates between the first and third transistors, the signal charge can be discharged into the well region from either the source or the drain of the third transistor.

[0031] Furthermore, for example, the imaging device according to the seventh aspect of this disclosure is the imaging device according to the sixth aspect, wherein the first conductivity type is n type and the second conductivity type is p type.

[0032] This makes it possible to configure the system so that, when the signal charge is a hole, if an excess of signal charge accumulates between the first and third transistors, the signal charge can be discharged into the well region from either the source or the drain of the third transistor.

[0033] Furthermore, for example, an imaging device according to the eighth aspect of the present disclosure is an imaging device according to any one of the first to seventh aspects, further comprising a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to the other of the source and drain of the first transistor, and a first voltage is applied to the second terminal.

[0034] As a result, when the first transistor is turned on, signal charge accumulates in the capacitive element, which reduces the gain of photoelectric conversion when the first transistor is on, thus widening the dynamic range.

[0035] Furthermore, for example, an imaging device according to the ninth aspect of the present disclosure is an imaging device according to any one of the fifth to seventh aspects, further comprising a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to one of the source and drain of the third transistor, and the second terminal is connected to the other of the source and drain of the third transistor.

[0036] As a result, when the first transistor is turned on, signal charge accumulates not only between the first and third transistors but also in the capacitive element. This further reduces the gain of photoelectric conversion when the first transistor is turned on, allowing for an even wider dynamic range.

[0037] Furthermore, for example, the imaging device according to the tenth aspect of this disclosure is an imaging device according to any one of the first to ninth aspects, wherein, in a plan view, the area of ​​the second electrode is smaller than the area of ​​the first electrode.

[0038] This makes it more difficult for the second electrode to collect signal charge, and the potential range of the charge storage node FD, where the first transistor is in the off state, can be broadened.

[0039] Furthermore, for example, an imaging apparatus according to an eleventh aspect of the present disclosure is an imaging apparatus according to any one of the second to fourth aspects, comprising a first pixel and a second pixel, each including a first electrode, a second electrode, a photoelectric conversion layer, a third electrode, a charge storage region, and a first transistor, wherein the second transistor is shared by the first and second pixels, and one of the sources and drains of the second transistor of the first pixel is connected to the second electrode of the first pixel, the second electrode of the second pixel, the gate of the first transistor of the first pixel, and the gate of the first transistor of the second pixel.

[0040] This means that the first and second pixels share the second transistor, allowing for a reduction in the number of transistors and thus miniaturization of the imaging device.

[0041] Furthermore, for example, an imaging device according to the twelfth aspect of this disclosure is an imaging device according to any one of the fifth to seventh aspects and the ninth aspect, wherein a voltage for resetting the potential of the charge storage region is supplied to the charge storage region via the third transistor and the first transistor.

[0042] As a result, the first and third transistors, which widen the dynamic range, also have the function of resetting the potential of the charge storage region. Therefore, there is no need to provide a dedicated transistor for resetting the potential of the charge storage region, and the number of transistors can be reduced, allowing for miniaturization of the imaging device. In addition, since the number of transistors connected to the charge storage region is reduced, the leakage current flowing through the charge storage region can be reduced.

[0043] Furthermore, for example, an imaging apparatus according to a 13th aspect of the present disclosure is an imaging apparatus according to any one of the 2nd to 4th aspects and the 11th aspect, comprising a first semiconductor substrate and a second semiconductor substrate laminated on the first semiconductor substrate, wherein the first semiconductor substrate is located between the first electrode and the second semiconductor substrate, the first transistor is disposed on the first semiconductor substrate and the second transistor is disposed on the second semiconductor substrate.

[0044] This allows the first and second transistors to be placed on separate semiconductor substrates, the first and second semiconductor substrates, thus reducing the area of ​​the imaging device. Furthermore, since the first transistor is placed on the first semiconductor substrate between the first electrode and the second semiconductor substrate, the wiring connecting the first electrode and the first transistor can be shortened.

[0045] Furthermore, for example, an imaging apparatus according to a 14th aspect of the present disclosure is an imaging apparatus according to any one of the 5th to 7th aspects and the 9th aspect, comprising a first semiconductor substrate and a second semiconductor substrate laminated on the first semiconductor substrate, wherein the first semiconductor substrate is located between the first electrode and the second semiconductor substrate, the first transistor is arranged on the first semiconductor substrate and the third transistor is arranged on the second semiconductor substrate.

[0046] This allows the first and third transistors to be placed on separate semiconductor substrates, the first and second semiconductor substrates, thus reducing the area of ​​the imaging device. Furthermore, since the first transistor is placed on the first semiconductor substrate between the first electrode and the second semiconductor substrate, the wiring connecting the first electrode and the first transistor can be shortened.

[0047] Furthermore, for example, a camera system according to the 15th aspect of this disclosure comprises an imaging device according to any one of the 1st to 14th aspects.

[0048] As a result, the camera system according to this embodiment, equipped with the above-mentioned imaging device, can suppress changes in the potential of the charge storage region that exceed a predetermined level, and can also improve the signal-to-noise ratio.

[0049] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0050] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0051] Furthermore, in this specification, terms indicating relationships between elements, such as parallel or coincident, terms indicating the shape of elements, such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0052] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." It should be noted that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0053] Furthermore, in this specification, "planar view" refers to a view of the semiconductor substrate from a direction perpendicular to the main surface (in other words, in the thickness direction of the semiconductor substrate).

[0054] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified, and refers to a state of being electrically connected at all times. Also, in this specification, the term "node" means an electrical connection point between multiple elements in an electrical circuit, and is a concept that includes wiring and the like that which are responsible for the electrical connection between those multiple elements.

[0055] Furthermore, in this specification, when a transistor is said to be placed on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are placed on either side of that surface.

[0056] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not refer to the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0057] (Embodiment 1) The imaging device according to Embodiment 1 will now be described.

[0058] [Overall structure] First, the overall configuration of the imaging device according to this embodiment will be described.

[0059] Figure 1 is a diagram showing the configuration of an imaging device according to this embodiment. As shown in Figure 1, the imaging device 100 according to this embodiment comprises a plurality of pixels 10 and peripheral circuits formed on a semiconductor substrate 60. Each pixel 10 includes a photoelectric conversion unit 12 located above the semiconductor substrate 60. In other words, a stacked type imaging device 100 will be described as an example of an imaging device according to this disclosure.

[0060] In the example shown in Figure 1, multiple pixels 10 are arranged in an m x n matrix, where m and n are integers greater than or equal to 2. The multiple pixels 10 are arranged, for example, in two dimensions on the semiconductor substrate 60 to form an imaging region R1. In this embodiment, the photoelectric conversion unit 12 is a photoelectric conversion structure including a photoelectric conversion layer positioned above the semiconductor substrate 60. The imaging region R1 is defined as the area of ​​the semiconductor substrate 60 covered by the photoelectric conversion unit 12. In Figure 1, the photoelectric conversion unit 12 of each pixel 10 is shown spatially separated from each other for ease of explanation, but the photoelectric conversion units 12 of multiple pixels 10 can be arranged above the semiconductor substrate 60 without spacing between them. The photoelectric conversion unit 12 may also be a photodiode formed on the semiconductor substrate 60.

[0061] The number and arrangement of pixels 10 are not limited to the illustrated example. For example, the imaging device 100 may contain only one pixel 10. Also, in this example, the center of each pixel 10 is located on a grid point of a square grid, but the arrangement of pixels 10 does not have to be so. For example, multiple pixels 10 may be arranged such that each center is located on a grid point of a triangular grid, a hexagonal grid, or the like. Furthermore, if the pixels 10 are arranged in one dimension, the imaging device 100 can be used as a line sensor.

[0062] In the example shown in Figure 1, the peripheral circuit includes a vertical scanning circuit 42 and a horizontal signal readout circuit 44. In addition, in the example shown in Figure 1, the peripheral circuit may also include a control circuit 46 and a voltage supply circuit 48. As schematically shown in Figure 1, the peripheral circuit is located in the peripheral region R2 outside the imaging region R1. The peripheral circuit is connected to a plurality of pixels 10 and is a circuit for acquiring signals from each pixel 10. The peripheral circuit may further include a load circuit, a signal processing circuit, an output circuit, and a power supply that supplies a predetermined voltage to each pixel 10. The peripheral circuit is located on the semiconductor substrate 60, but at least a portion of the peripheral circuit may be located on one or more other semiconductor substrates different from the semiconductor substrate 60 on which the pixels 10 are formed. In other words, at least a portion of the peripheral circuit does not have to be located in the peripheral region R2 of the semiconductor substrate 60. In this case, one or more other semiconductor substrates may be stacked on the semiconductor substrate 60. Also, some of the circuits of the pixels 10 may be located on one or more other semiconductor substrates.

[0063] The vertical scanning circuit 42, also called a row scanning circuit, has connections to address signal lines 34 provided for each row of the multiple pixels 10. As will be described later, the signal lines provided for each row of the multiple pixels 10 are not limited to address signal lines 34. Multiple types of signal lines may be connected to the vertical scanning circuit 42 for each row of the multiple pixels 10.

[0064] The horizontal signal readout circuit 44, also called a column scanning circuit, has connections to vertical signal lines 35 provided corresponding to each column of the multiple pixels 10.

[0065] The control circuit 46 receives command data, a clock, etc., from an external source, for example, and controls the entire imaging device 100. The control circuit 46 includes, for example, a timing generator. The control circuit 46 supplies drive signals to the vertical scanning circuit 42, the horizontal signal readout circuit 44, and the voltage supply circuit 48, etc. In Figure 1, the arrows extending from the control circuit 46 schematically represent the flow of output signals from the control circuit 46. The control circuit 46 can be implemented, for example, by a microcontroller or one or more processors. The microcontroller may include one or more processors. The functions of the control circuit 46 may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing.

[0066] The voltage supply circuit 48 supplies a predetermined voltage to each pixel 10 via the storage control line 31. The voltage supply circuit 48 is not limited to a specific power supply circuit. The voltage supply circuit 48 may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or it may be a circuit that generates a predetermined voltage. The voltage supply circuit 48 may also be part of the vertical scanning circuit 42 or control circuit 46 described above.

[0067] [Pixel configuration] Next, the configuration of the pixels 10 of the imaging device 100 according to this embodiment will be described.

[0068] First, the circuit configuration of the pixel 10 according to this embodiment will be described. Figure 2 is a diagram showing the circuit configuration of the pixel 10 according to this embodiment. Each of the plurality of pixels 10 has, for example, the circuit configuration shown in Figure 2. As shown in Figure 2, the imaging device 100 further includes a voltage supply circuit 49.

[0069] As described above, the pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges upon the incidence of light. In other words, the photoelectric conversion unit 12 converts light into electric charge. Positive and negative charges are typically hole-electron pairs. The photoelectric conversion unit 12 includes a pixel electrode 12a, a photoelectric conversion layer 12b, a counter electrode 12c, and a light intensity detection electrode 12d. The pixel electrode 12a is an example of a first electrode. The light intensity detection electrode 12d is an example of a second electrode. The counter electrode 12c is an example of a third electrode.

[0070] The pixel electrode 12a of the photoelectric conversion unit 12 is connected to the charge storage node FD. The light intensity detection electrode 12d of the photoelectric conversion unit 12 is connected to node N0. The counter electrode 12c of the photoelectric conversion unit 12 is connected to the storage control line 31, and a predetermined storage control voltage VITO is applied to the storage control line 31 by the voltage supply circuit 48 when the imaging device 100 is operating. By the voltage supply circuit 48 applying the predetermined storage control voltage VITO to the storage control line 31, one of the positive and negative charges generated by photoelectric conversion can be selectively stored as a signal charge in the charge storage node FD. In addition, a portion of the signal charge generated by photoelectric conversion is also stored in node N0. In the following description, unless otherwise specified, the case in which positive charges, i.e., holes, are used as signal charges from among the positive and negative charges generated by photoelectric conversion will be illustrated.

[0071] Pixel 10 is electrically connected to the photoelectric conversion unit 12 and includes a signal detection circuit that detects a signal based on the signal charge generated by the photoelectric conversion unit 12. In the example shown in Figure 2, the signal detection circuit includes an amplifying transistor 22 and an addressing transistor 24. The amplifying transistor 22 is also called a readout transistor. The addressing transistor 24 is also called a row selection transistor. Pixel 10 also includes a first reset transistor 26, an overflow transistor 28, a second reset transistor 30, and a capacitive element 21.

[0072] As will be explained in detail later with reference to the drawings, the amplification transistor 22, address transistor 24, first reset transistor 26, overflow transistor 28, and second reset transistor 30 are, for example, field-effect transistors (FETs) formed on the semiconductor substrate 60 supporting the photoelectric conversion unit 12. In the example shown in Figure 2, N-channel MOSFETs (Metal Oxide Semiconductor FETs) are used for each of the amplification transistor 22, address transistor 24, and overflow transistor 28. P-channel MOSFETs are used for each of the first reset transistor 26 and second reset transistor 30. Note that which of the two diffusion regions of the FET corresponds to the source and which corresponds to the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and which is the drain can vary depending on the operating state of the FET. In other words, the source and drain of each transistor described below may be reversed depending on the operating state of the FET.

[0073] As schematically shown in Figure 2, the gate of the amplification transistor 22 is connected to the charge storage node FD, which in turn is connected to the pixel electrode 12a. The signal charge generated by the photoelectric conversion unit 12 is stored as signal charge in the charge storage node FD between the photoelectric conversion unit 12 and the amplification transistor 22. In other words, the charge storage node FD functions as at least part of the charge storage region where signal charge is stored, and the potential of the charge storage node FD corresponds to the amount of signal charge stored in the charge storage region.

[0074] One of the sources and drains of the amplification transistor 22 is connected to a power supply wiring 32 that supplies a power supply voltage Vdd to each pixel 10 when the imaging device 100 is operating. The power supply voltage Vdd is, for example, about 3.3V, but is not limited to this. The amplification transistor 22 outputs a signal voltage corresponding to the amount of signal charge accumulated in the charge storage region from the signal charge generated by the photoelectric conversion unit 12. The other of the sources and drains of the amplification transistor 22 is connected to one of the sources and drains of the address transistor 24.

[0075] A vertical signal line 35 is connected to the source and the other drain of the address transistor 24. A load circuit that forms a source follower circuit together with the amplifying transistor 22, and a column signal processing circuit are connected to the vertical signal line 35, for example.

[0076] An address signal line 34 is connected to the gate of the address transistor 24. An address signal line 34 is provided for each row of multiple pixels 10. The address signal line 34 is connected to a vertical scanning circuit 42, which applies a row selection signal SEL to the address signal line 34 to control the on and off states of the address transistor 24. This causes the row to be read to be scanned vertically (i.e., in the column direction) and the row to be read to be selected. By controlling the on and off states of the address transistor 24 via the address signal line 34, the vertical scanning circuit 42 can read the output of the amplification transistor 22 of the selected pixel 10 to the corresponding vertical signal line 35. The arrangement of the address transistor 24 is not limited to the example shown in Figure 2, and may be between one of the source and drain of the amplification transistor 22 and the power supply wiring 32.

[0077] The signal voltage from the pixel 10, output to the vertical signal line 35 via the address transistor 24, is subjected to noise suppression signal processing and analog-to-digital conversion in a column signal processing circuit, for example, and then input to the horizontal signal readout circuit 44.

[0078] One of the sources and drains of the first reset transistor 26 is connected to the gate of the light intensity detection electrode 12d and the overflow transistor 28 via node N0. The gate of the first reset transistor 26 is connected to a first reset signal line 36, which has a connection to the vertical scanning circuit 42. The first reset signal line 36 is provided for each row of multiple pixels 10, similar to the address signal line 34. The vertical scanning circuit 42 applies a first reset signal RST1 to the gate of the first reset transistor 26 via the first reset signal line 36 to control the on and off states of the first reset transistor 26. When the first reset transistor 26 is turned on, the potential of node N0 is reset. The first reset transistor 26 is an example of a second transistor.

[0079] In the example shown in Figure 2, the source and drain of the first reset transistor 26 are connected via the first reset voltage line 53 to a voltage supply circuit 49 that supplies the first reset voltage VR1.

[0080] The voltage supply circuit 49 supplies a first reset voltage VR1 to the first reset voltage line 53. The first reset voltage VR1 is applied to node N0 via the first reset voltage line 53 when the first reset transistor 26 is turned on. The magnitude of the first reset voltage VR1 applied by the voltage supply circuit 49 is controlled, for example, by the control circuit 46. The voltage supply circuit 49 may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or it may be a circuit that generates a predetermined voltage. The voltage supply circuit 49 may be part of the vertical scanning circuit 42 or the control circuit 46 described above.

[0081] One of the sources and drains of the overflow transistor 28 is connected to the charge storage node FD. The other of the sources and drains of the overflow transistor 28 is connected via node N1 to one of the sources and drains of the second reset transistor 30, as well as to one end of the capacitive element 21. The gate of the overflow transistor 28 is connected via node N0 to the light intensity detection electrode 12d and one of the sources and drains of the first reset transistor 26. The gate of the overflow transistor 28 is electrically isolated from the charge storage node FD. The overflow transistor 28 is an example of a first transistor.

[0082] With the first reset transistor 26 turned off, as the signal charge accumulated at node N0 increases, the potential of node N0 reaches the threshold potential Vof, causing the overflow transistor 28 to turn on. As a result, a portion of the signal charge accumulated at the charge storage node FD flows to node N1 and the capacitive element 21, where it is stored. The threshold potential Vof is a potential that depends on the threshold voltage of the overflow transistor 28. Here, the threshold voltage refers to the gate-source voltage of the transistor when drain current begins to flow through the transistor.

[0083] Furthermore, when the first reset transistor 26 is ON, the first reset voltage VR1 is applied to the gate of the overflow transistor 28. When the first reset transistor 26 is ON, the ON and OFF states of the overflow transistor 28 are controlled by the first reset voltage VR1.

[0084] In the example shown in Figure 2, the gate of the amplification transistor 22 connected to the charge storage node FD, and one of the source and drain of the overflow transistor 28, are part of a charge storage region that stores the signal charge generated by the photoelectric conversion unit 12. In this specification, the expressions that an element is connected to the charge storage node FD and that an element is connected to a charge storage region may also include the expressions that an element is part of the charge storage node FD and an element is part of a charge storage region, respectively.

[0085] One of the sources and drains of the second reset transistor 30 is connected to node N1. The gate of the second reset transistor 30 is connected to a second reset signal line 37, which has a connection to the vertical scanning circuit 42. The second reset signal line 37 is provided for each row of multiple pixels 10, similar to the address signal line 34. The vertical scanning circuit 42 applies a second reset signal RST2 to the gate of the second reset transistor 30 via the second reset signal line 37 to control the on and off states of the second reset transistor 30. When the second reset transistor 30 is turned on, the potential of node N1 is reset. Also, when the second reset transistor 30 is turned on, the charge accumulated in the capacitive element 21 together with node N1 is reset. Furthermore, when the second reset transistor 30 is turned on and the overflow transistor 28 is turned on, the potential of the charge storage node FD is reset. The second reset transistor 30 is an example of a third transistor.

[0086] In the example shown in Figure 2, the source and the other drain of the second reset transistor 30 are connected to a second reset voltage line 54 that supplies a predetermined second reset voltage VR2 to the pixel 10 when the pixel 10 is reset. That is, in this example, the second reset voltage VR2 that initializes the signal charge flowing out from the charge storage node FD by the overflow transistor 28 is supplied to node N1 via the second reset transistor 30. In addition, the second reset voltage VR2 for initializing the potential of the charge storage node FD is supplied to the charge storage node FD via the second reset transistor 30 and the overflow transistor 28. The second reset voltage VR2 may be a fixed voltage.

[0087] One end of the capacitive element 21 is connected via node N1 to the other source and drain of the overflow transistor 28, and to one source and drain of the second reset transistor 30. The other end of the capacitive element 21 is connected to a power supply wiring 38 that supplies a power supply voltage Vss to each pixel 10 when the imaging device 100 is operating. The power supply voltage Vss is, for example, the ground voltage. The power supply voltage Vss is supplied to the other end of the capacitive element 21 via the power supply wiring 38. One end of the capacitive element 21 is an example of a first terminal of the capacitive element 21, and the other end of the capacitive element 21 is an example of a second terminal of the capacitive element 21.

[0088] The capacitive element 21 is, for example, a MOM (Metal-Oxide-Metal) capacitor, a MIM (Metal-Insulator-Metal) capacitor, a MOS (Metal Oxide Semiconductor) capacitor, or a trench capacitor.

[0089] Next, the device structure of the pixel 10 according to this embodiment will be described. Figure 3 is a schematic cross-sectional view of the device structure of the pixel 10 according to this embodiment. In Figure 3, a portion of the electrical connections of the transistor and impurity region formed on the semiconductor substrate 60 is schematically shown. In Figure 3, the photoelectric conversion unit 12 is shown in a simplified manner, and detailed structural illustration is omitted. This is also the case in the schematic cross-sectional views described later.

[0090] As shown in Figure 3, the pixel 10 schematically includes a semiconductor substrate 60 and a photoelectric conversion unit 12 positioned above the semiconductor substrate 60. An interlayer insulating layer (not shown) is placed between the semiconductor substrate 60 and the photoelectric conversion unit 12, and various wirings and capacitive elements 21 are formed within the interlayer insulating layer. The semiconductor substrate 60 is formed continuously, for example, over at least the entire imaging region R1 and is shared by multiple pixels 10.

[0091] The semiconductor substrate 60 has a main surface 81 on which various transistors of the pixel 10 are arranged. Specifically, a first reset transistor 26, an overflow transistor 28, and a second reset transistor 30 are arranged on the main surface 81. Although not shown in Figure 3, an amplification transistor 22 and an address transistor 24 are also arranged on the main surface 81. The main surface 81 is a surface perpendicular to the thickness direction of the semiconductor substrate 60. In the example shown in Figure 3, the photoelectric conversion unit 12 is arranged on the main surface 81 side of the semiconductor substrate 60.

[0092] The semiconductor substrate 60 includes a support substrate 61p and a p-type semiconductor layer 62p and an n-type semiconductor layer 63n on which transistors are formed. Here, a p-type silicon (Si) substrate is given as an example of the support substrate 61p. The p-type semiconductor layer 62p is a p-type well region in the semiconductor substrate 60. The n-type semiconductor layer 63n is an n-type well region in the semiconductor substrate 60. The p-type semiconductor layer 62p is provided on the support substrate 61p, and the n-type semiconductor layer 63n is provided in a region on the support substrate 61p different from the p-type semiconductor layer 62p. The p-type semiconductor layer 62p and the n-type semiconductor layer 63n are semiconductor layers on which the main surface 81 of the semiconductor layers included in the semiconductor substrate 60 is located.

[0093] The p-type semiconductor layer 62p is a semiconductor layer containing p-type impurities, which are of the second conductivity type. The n-type semiconductor layer 63n is a semiconductor layer containing n-type impurities, which are of the first conductivity type. Each of the p-type semiconductor layer 62p and the n-type semiconductor layer 63n is formed, for example, by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. In this embodiment, the p-type impurity is, for example, boron, and the n-type impurity is, for example, arsenic or phosphorus.

[0094] As shown in Figure 3, the semiconductor substrate 60 includes n-type impurity regions 65n, 66n, and 75n, p-type impurity regions 67p, 71p, 72p, 73p, and 74p, and an element isolation region 69. The n-type impurity regions 65n, 66n, and 75n are impurity regions where n-type impurities have diffused. The p-type impurity regions 67p, 71p, 72p, 73p, and 74p are impurity regions where p-type impurities have diffused.

[0095] The n-type impurity regions 65n and 66n are located in the p-type semiconductor layer 62p. The n-type impurity regions 65n and 66n are formed by impurities being injected into the p-type semiconductor layer 62p from the main surface 81 side. The n-type impurity region 75n is located in the n-type semiconductor layer 63n. The n-type impurity region 75n is formed by impurities being injected into the n-type semiconductor layer 63n from the main surface 81 side.

[0096] The p-type impurity region 67p is located within the p-type semiconductor layer 62p. The p-type impurity region 67p is formed by impurities being injected into the p-type semiconductor layer 62p from the main surface 81 side. The p-type impurity regions 71p, 72p, 73p, and 74p are located within the n-type semiconductor layer 63n. The p-type impurity regions 71p, 72p, 73p, and 74p are formed by impurities being injected into the n-type semiconductor layer 63n from the main surface 81 side.

[0097] The semiconductor substrate 60 has an amplifying transistor 22 (not shown in Figure 3), an addressing transistor 24 (not shown in Figure 3), a first reset transistor 26, an overflow transistor 28, and a second reset transistor 30 formed on it. Each of the amplifying transistor 22 (not shown in Figure 3), the addressing transistor 24 (not shown in Figure 3), and the overflow transistor 28 is an N-channel MOSFET formed on the p-type semiconductor layer 62p. Each of the first reset transistor 26 and the second reset transistor 30 is a P-channel MOSFET formed on the n-type semiconductor layer 63n.

[0098] As shown in Figure 3, the first reset transistor 26 includes a p-type impurity region 71p as one of the source and drain, a p-type impurity region 72p as the other of the source and drain, a gate 26e, a channel region 26c, and a gate insulating film 26i.

[0099] The overflow transistor 28 includes an n-type impurity region 65n as one of the source and drain, an n-type impurity region 66n as the other of the source and drain, a gate 28e, a channel region 28c, and a gate insulating film 28i.

[0100] The second reset transistor 30 includes a p-type impurity region 73p as one of the source and drain, a p-type impurity region 74p as the other of the source and drain, a gate 30e, a channel region 30c, and a gate insulating film 30i.

[0101] Although not shown in Figure 3, each of the amplifying transistor 22 and the addressing transistor 24 includes an n-type impurity region as the source and drain, a gate, a channel region, and a gate insulating film, respectively.

[0102] The area of ​​the gate 28e of the overflow transistor 28 is larger than, for example, the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30. This reduces the variation in the threshold voltage of the overflow transistor 28. Here, the gate area is the effective area, which is the area of ​​the region where the gate and the channel region overlap in a plan view.

[0103] Furthermore, the gate length of the overflow transistor 28 is greater than, for example, the gate length of the first reset transistor 26 and the gate length of the second reset transistor 30. The gate width of the overflow transistor 28 is also greater than, for example, the gate width of the first reset transistor 26 and the gate width of the second reset transistor 30. This reduces variations in the threshold voltage of the overflow transistor 28.

[0104] Furthermore, the thickness of the gate insulating film 28i of the overflow transistor 28 is smaller than, for example, the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30. This reduces variations in the threshold voltage of the overflow transistor 28.

[0105] The concentration of p-type impurities in the channel region 28c of the overflow transistor 28 is higher than, for example, the concentration of n-type impurities in the channel region 26c of the first reset transistor 26 and the concentration of n-type impurities in the channel region 30c of the second reset transistor 30. This suppresses depletion of the channel region 28c when the overflow transistor 28 is off, and reduces the leakage current when the overflow transistor 28 is off. As will be described in detail later, the photoelectric conversion gain is high when the overflow transistor 28 is off. Therefore, reducing the leakage current flowing through the charge storage region when the overflow transistor 28 is off is useful from the viewpoint of noise reduction. Leakage current is also called dark current because it is a current that flows even in the dark when no light is irradiated. Note that the relationship of the impurity concentrations in the channel region described above is not limited to the above relationship.

[0106] Gates 26e, 28e, and 30e are gate electrodes formed from, for example, impurity-doped polysilicon. Gates 26e, 28e, and 30e are doped with, for example, p-type impurities. By doping gate 28e of the overflow transistor 28 with p-type impurities, the threshold voltage of the overflow transistor 28 can be increased without increasing the channel dose of the overflow transistor 28. As a result, the increase in the electric field around the n-type impurity region 65n is suppressed, and leakage current can be reduced. The gates of the amplification transistor 22 and address transistor 24, which are not shown in Figure 3, are also gate electrodes formed from, for example, impurity-doped polysilicon. The gates of the amplification transistor 22 and address transistor 24 are doped with, for example, n-type impurities.

[0107] The gate insulating films 26i, 28i, and 30i of the first reset transistor 26, the overflow transistor 28, and the second reset transistor 30, respectively, are insulating films such as silicon oxide films formed on the main surface 81 of the semiconductor substrate 60.

[0108] The element isolation region 69 is arranged, for example, in a plan view to surround the first reset transistor 26, the overflow transistor 28, the second reset transistor 30, the p-type impurity region 67p, and the n-type impurity region 75n, thereby electrically isolating them from each other. The element isolation region 69 is, for example, an STI (Shallow Trench Isolation) structure. The STI structure is formed on the semiconductor substrate 60 by an STI process. At least a portion of the element isolation region 69 may be an implanted isolation region in which impurities are implanted at a high concentration.

[0109] The p-type impurity region 67p functions as a well contact region of the p-type semiconductor layer 62p. A p-well voltage Vp is applied to the p-type semiconductor layer 62p via the p-type impurity region 67p. This makes it possible to control the potential of the p-type semiconductor layer 62p via the p-type impurity region 67p when the imaging device 100 is in operation. The n-type impurity region 75n functions as a well contact region of the n-type semiconductor layer 63n. An n-well voltage Vn is applied to the n-type semiconductor layer 63n via the n-type impurity region 75n. This makes it possible to control the potential of the n-type semiconductor layer 63n via the n-type impurity region 75n when the imaging device 100 is in operation. Note that the p-type impurity region 67p and the n-type impurity region 75n do not necessarily have to be located in the region where the pixel 10 is formed. For example, at least one of the p-type impurity region 67p and the n-type impurity region 75n may be located in the peripheral region R2 of the semiconductor substrate 60. Furthermore, the potentials of the p-type semiconductor layer 62p and the n-type semiconductor layer 63n may be controlled from sources other than the p-type impurity region 67p and the n-type impurity region 75n, without the formation of the p-type impurity region 67p and the n-type impurity region 75n. For example, the potential of at least one of the p-type semiconductor layer 62p and the n-type semiconductor layer 63n may be controlled via the support substrate 61p or another semiconductor layer disposed between the support substrate 61p and the p-type semiconductor layer 62p and the n-type semiconductor layer 63n.

[0110] The n-well voltage Vn is a higher voltage than the p-well voltage Vp. The n-well voltage Vn is, for example, 7V or less, and may be 5V or less. Alternatively, the n-well voltage Vn may be the power supply voltage Vdd. This allows a portion of the power supply wiring for supplying the n-well voltage Vn to be shared with the power supply wiring for the power supply voltage Vdd, enabling miniaturization of the pixel 10 and lower resistance of the power supply wiring by making the power supply wiring thicker. The p-well voltage Vp is, for example, 0V or more and 1V or less. Alternatively, the p-well voltage Vp may be the power supply voltage Vss. This allows a portion of the power supply wiring for supplying the p-well voltage Vp to be shared with the power supply wiring for the power supply voltage Vss, enabling miniaturization of the pixel 10 and lower resistance of the power supply wiring by making the power supply wiring thicker.

[0111] Furthermore, during exposure by the imaging device 100, the n-well voltage Vn is the voltage between the accumulation control voltage VITO, the first reset voltage VR1 used to reset the potential of node N0, and the second reset voltage VR2 used to reset the potentials of charge accumulation node FD and node N1. When the signal charge is a hole, the n-well voltage Vn is higher than the first reset voltage VR1 used to reset the potential of node N0 and the second reset voltage VR2 used to reset the potentials of charge accumulation node FD and node N1, and lower than the accumulation control voltage VITO.

[0112] As shown in Figure 3, the photoelectric conversion unit 12 includes a pixel electrode 12a, a light intensity detection electrode 12d positioned differently from the pixel electrode 12a in a plan view, a photoelectric conversion layer 12b, and a counter electrode 12c facing the pixel electrode 12a and the light intensity detection electrode 12d via the photoelectric conversion layer 12b. The pixel electrode 12a, the photoelectric conversion layer 12b, and the counter electrode 12c are stacked in this order from the semiconductor substrate 60 side. The pixel electrode 12a and the light intensity detection electrode 12d are located on the same plane.

[0113] The photoelectric conversion layer 12b of the photoelectric conversion unit 12 converts light into signal charges. Specifically, the photoelectric conversion layer 12b is formed from an organic material or an inorganic material such as amorphous silicon, and receives light incident via the counter electrode 12c to generate positive and negative charges through photoelectric conversion. The photoelectric conversion layer 12b is formed continuously, for example, across a plurality of pixels 10. In other words, the photoelectric conversion layer 12b is shared by a plurality of pixels 10. The photoelectric conversion layer 12b may also include a layer made of organic material and a layer made of inorganic material. Alternatively, the photoelectric conversion layer 12b may be provided separately for each pixel 10.

[0114] The counter electrode 12c is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving side of the photoelectric conversion layer 12b. The counter electrode 12c is a film-like electrode and, for example, is formed continuously across multiple pixels 10, similar to the photoelectric conversion layer 12b. In other words, the counter electrode 12c is shared by multiple pixels 10. The counter electrode 12c may also be provided separately for each pixel 10.

[0115] Although not shown in Figure 3, the counter electrode 12c has a connection to the accumulation control line 31 described above. When the imaging device 100 is in operation, the potential of the accumulation control line 31 is controlled to make the potential of the counter electrode 12c different from the potentials of the pixel electrode 12a and the light intensity detection electrode 12d, thereby allowing the signal charge generated by photoelectric conversion to be collected by the pixel electrode 12a and the light intensity detection electrode 12d. For example, the potential of the accumulation control line 31 is controlled so that the potential of the counter electrode 12c is higher than the potentials of the pixel electrode 12a and the light intensity detection electrode 12d. Specifically, when the imaging device 100 is in operation, an accumulation control voltage VITO different from the first reset voltage VR1 used to reset the potential of node N0 and the second reset voltage VR2 used to reset the potential of charge accumulation node FD is applied to the counter electrode 12c via the accumulation control line 31. The accumulation control voltage VITO is, for example, a positive voltage of about 10V. As a result, holes from the hole-electron pairs generated in the photoelectric conversion layer 12b can be collected by the pixel electrode 12a and the light intensity detection electrode 12d. The n-type impurity region 65n is electrically connected to the pixel electrode 12a, and the signal charge collected by the pixel electrode 12a is accumulated in the n-type impurity region 65n. The p-type impurity region 71p is electrically connected to the light intensity detection electrode 12d, and the signal charge collected by the light intensity detection electrode 12d is accumulated in the p-type impurity region 71p. When electrons are used as the signal charge, an accumulation control voltage VITO is applied to the counter electrode 12c such that the potential of the counter electrode 12c is lower than the potentials of the pixel electrode 12a and the light intensity detection electrode 12d.

[0116] The pixel electrode 12a and the light intensity detection electrode 12d are film-like electrodes formed from metals such as aluminum and copper, metal nitrides, or polysilicon that has been doped with impurities to impart conductivity. A pixel 10 includes one pixel electrode 12a and one light intensity detection electrode 12d. In a pixel 10, the pixel electrode 12a and the light intensity detection electrode 12d are electrically isolated by spatial separation. Furthermore, the pixel electrode 12a and the light intensity detection electrode 12d are electrically isolated from the pixel electrodes 12a and light intensity detection electrodes 12d of other adjacent pixels 10 by spatial separation.

[0117] [Operation of the imaging device] Next, the operation of the imaging device 100 will be described. Figure 4 is a timing chart illustrating an example of the operation of the imaging device 100 according to this embodiment.

[0118] In Figure 4, "VR1" indicates the change in the voltage level of the first reset voltage VR1 supplied to the first reset voltage line 53. In Figure 4, "RST1" indicates the change in the voltage level of the first reset signal RST1 supplied to the gate 26e of the first reset transistor 26. In Figure 4, "VR2" indicates the voltage level of the second reset voltage VR2 supplied to the second reset voltage line 54. In Figure 4, "RST2" indicates the change in the voltage level of the second reset signal RST2 supplied to the gate 30e of the second reset transistor 30. In Figure 4, high-level voltages are denoted as "High" and low-level voltages are denoted as "Low". In the example shown in Figure 4, the second reset voltage VR2 is constant at a low level. Note that the high-level voltages of the first reset voltage VR1, first reset signal RST1, second reset voltage VR2, and second reset signal RST2 may be the same magnitude, or two or more of these high-level voltages may be different magnitudes. Furthermore, the low-level voltages of the first reset voltage VR1, first reset signal RST1, second reset voltage VR2, and second reset signal RST2 may be the same magnitude, or two or more of these low-level voltages may be of different magnitudes.

[0119] First, at time t1, the first reset signal RST1 becomes low, and the first reset transistor 26 is turned on. At this time, since the first reset voltage VR1 is high, a high voltage is applied to the gate of the overflow transistor 28, and the overflow transistor 28 is also turned on. Also at time t1, the second reset signal RST2 becomes low, and the second reset transistor 30 is turned on. As a result, the potential of the charge storage node FD, the potential of node N1, and the potential of one end of the capacitive element 21 are reset to the second reset voltage VR2. As a result, the overflow transistor 28 and the second reset transistor 30 take over the function of the transistors that reset the potential of the charge storage node FD, so the number of transistors can be reduced and the imaging device 100 can be miniaturized. In addition, since the number of transistors connected to the charge storage node FD is reduced, the leakage current flowing through the charge storage node FD can be reduced.

[0120] Next, at time t2, with the first reset transistor 26 turned on, the first reset voltage VR1 becomes low, and the overflow transistor 28 is turned off. Hereafter, the period from when the overflow transistor 28 is turned on until it is turned off, with the first reset transistor 26 and the second reset transistor 30 turned on, may be referred to as the "reset period". The reset period is the period for resetting the potential of the charge storage node FD. In the example shown in Figure 4, the reset period ("reset" in the figure) is the period from time t1 to time t2. Also in Figure 4, the period labeled "OF-Tr off" is the period during which the overflow transistor 28 is turned off by applying a low-level first reset voltage VR1 to the gate of the overflow transistor 28.

[0121] Furthermore, in the example shown in Figure 4, the potential of node N1 and the potential of one end of the capacitive element 21 are also reset during the reset period. Note that the potential of node N1 and the potential of one end of the capacitive element 21 may be reset after the reset period in which the potential of the charge storage node FD is reset. In this case, for example, the second reset transistor 30 remains ON for a predetermined period even after time t3, as described later, and the potential of node N1 and the potential of one end of the capacitive element 21 are reset even after time t3. In this case, the second reset voltage VR2 when resetting the potential of the charge storage node FD and the second reset voltage VR2 when resetting the potential of node N1 and the potential of one end of the capacitive element 21 may be at different levels. For example, during the period in which the potential of node N1 and the potential of one end of the capacitive element 21 are reset, the second reset voltage VR2 may be a voltage at an intermediate level between a high level and a low level.

[0122] Furthermore, at time t2, with the first reset transistor 26 turned on, the first reset voltage VR1 becomes low, and the potential of node N0 is reset by the low level of the first reset voltage VR1.

[0123] Furthermore, at time t2, the imaging device 100 starts exposure. In the example shown in Figure 4, the imaging device 100 starts exposure simultaneously with time t2, when the reset period ends, but exposure may start later than the end of the reset period. The imaging device 100 may also perform exposure using a rolling shutter method or a global shutter method. Upon the start of exposure, the signal charge generated by the photoelectric conversion unit 12 is accumulated in the charge storage node FD, and the potentials of the charge storage node FD and node N0 rise in accordance with the amount of light incident on the photoelectric conversion unit 12 (exposure amount). The exposure period starting from time t2 is the storage period for accumulating signal charge in the charge storage node FD.

[0124] Next, at time t3, the first reset signal RST1 and the second reset signal RST become high, and the first reset transistor 26 and the second reset transistor 30 are turned off. As a result, nodes N0 and N1 become floating, and are able to accumulate signal charge. Time t3 is the time before exposure ends. Also at time t3, the first reset voltage VR1 becomes high. However, the first reset voltage VR1 may remain low at time t3 instead of becoming high.

[0125] After the storage period ends, the output signal of the pixel 10, corresponding to the potential of the charge storage node FD, is read out to the vertical signal line 35 by the amplification transistor 22 and the address transistor 24.

[0126] Here, the changes in the potentials of the charge storage node FD and node N0 during exposure will be explained with reference to Figure 2. At the start of exposure, the potential of the charge storage node FD is the initial potential Vr1 reset by the second reset voltage VR2. Also at the start of exposure, the potential of node N0 is the initial potential Vr2 reset by the first reset voltage VR1. The signal charge generated in the photoelectric conversion layer 12b by exposure is collected by the pixel electrode 12a and stored in the charge storage node FD, so the potential of the charge storage node FD rises. Furthermore, from time t3 onward, a portion of the signal charge generated in the photoelectric conversion layer 12b by exposure is collected by the light intensity detection electrode 12d and stored in node N0, so the potential of node N0 rises. Both the pixel electrode 12a and the light intensity detection electrode 12d are configured to collect the signal charge generated in the photoelectric conversion layer 12b, and the signal charge generated in the photoelectric conversion layer 12b is collected by the pixel electrode 12a and the light intensity detection electrode 12d in a predetermined ratio. Therefore, the potential of node N0 increases in response to the increase in the potential of charge storage node FD.

[0127] When exposure causes the potential of node N0 to rise and reach the threshold potential Vof, the gate-source voltage of the overflow transistor 28 becomes the threshold voltage of the overflow transistor 28, and the overflow transistor 28 turns on. As a result, the charge storage node FD is electrically connected to node N1 and the capacitive element 21, and works together with node N1 and the capacitive element 21 to store signal charge. In other words, the capacitance for storing signal charge increases, so after the potential of node N0 reaches the threshold potential Vof, the potential of the charge storage node FD will not rise as easily as before, even if the same amount of signal charge is generated. Therefore, at the point when the potential of node N0 reaches the threshold potential Vof, the conversion gain by photoelectric conversion at pixel 10 switches to a lower level. Since the potential of node N0 rises in response to the rise in the potential of the charge storage node FD, when the potential of node N0 reaches the threshold potential Vof, the potential of the charge storage node FD has also risen to a potential corresponding to the threshold potential Vof. Therefore, when the potential of the charge storage node FD rises from the initial potential Vr1 to a predetermined potential, the overflow transistor 28 turns on, and the conversion gain by photoelectric conversion is switched to a lower level. This allows the dynamic range to be widened. In addition, since the signal charge is also stored in the capacitive element 21, the conversion gain can be lowered even further, thus widening the dynamic range even more.

[0128] In the following, the exposure mode before the potential of node N0 reaches the threshold potential Vof (i.e., before the conversion gain due to photoelectric conversion switches) may be referred to as the "high sensitivity mode." The exposure mode after the potential of node N0 reaches the threshold potential Vof (i.e., after the conversion gain due to photoelectric conversion switches) may be referred to as the "high saturation mode." In the imaging device 100, imaging can be performed in high sensitivity mode when the exposure amount is small, thus improving the signal-to-noise ratio (S / N) even when imaging in low-light environments. On the other hand, when the exposure amount increases, the device switches from high sensitivity mode to high saturation mode, thereby widening the dynamic range.

[0129] In the imaging device 100, the gate of the overflow transistor 28 is not connected to the charge storage node FD, but is connected to node N0, and is electrically isolated from the charge storage node FD. Therefore, the capacitance of the gate of the overflow transistor 28 (gate overlap capacitance) is not added to the capacitance of the charge storage node FD. Here, the effect of reducing the capacitance of the charge storage node FD will be explained using Figure 5. Figure 5 is a diagram showing the potential dependence of the gate overlap capacitance and pn junction capacitance of the charge storage node FD. In Figure 5, the vertical axis shows the sum of the gate overlap capacitance and pn junction capacitance of the charge storage node FD, and the horizontal axis shows the potential of the charge storage node FD. Figure 5 also shows the results of capacitance measurement using a TEG (Test Element Group). Figure 5(a) shows the capacitance measurement results in a conventional configuration (hereinafter, "configuration (a)") in which the gate of the overflow transistor 28 is connected to the charge storage node FD. Figure 5(b) shows the capacitance measurement results for a configuration in which the overflow transistor 28 is removed from the configuration according to this embodiment (hereinafter referred to as "configuration (b)"). Figure 5(c) shows the capacitance measurement results for a configuration according to this embodiment (hereinafter referred to as "configuration (c)").

[0130] As shown in Figure 5, configuration (c) has a significantly reduced capacitance compared to configuration (a). This is due to the fact that the gate of the overflow transistor 28 is not connected to the charge storage node FD, as described above. Furthermore, configuration (c) has almost no difference in capacitance compared to configuration (b), in which the overflow transistor 28 is not formed. The difference between configuration (b) and configuration (c) is mainly due to the gate-drain overlap capacitance of the overflow transistor 28, and the proportion of the capacitance of the charge storage node FD is small.

[0131] From the above, in the imaging device 100 according to this embodiment, the increase in the capacitance of the charge storage node FD can be suppressed in high-sensitivity mode, making it possible to increase the conversion gain in high-sensitivity mode compared to conventional devices. Therefore, sensitivity is further increased and the signal-to-noise ratio can be improved in high-sensitivity mode.

[0132] In the imaging device 100, the absolute value of the threshold voltage of the overflow transistor 28 may be greater than the absolute value of the threshold voltage of the first reset transistor 26 and the absolute value of the threshold voltage of the second reset transistor 30. This increases the absolute value of the threshold potential Vof, thereby widening the range of the potential of the charge storage node FD corresponding to the high-sensitivity mode.

[0133] After the potential of node N0 reaches the threshold potential Vof, exposure continues, causing the potential of node N0 and the potential of charge storage node FD to rise further. At this time, since the charge storage node FD and node N1 are electrically connected, the potential of node N1 also rises to the same potential as the charge storage node FD. When the potential of node N1 reaches a limiting potential Vlim that exceeds the n-well voltage Vn, a forward bias voltage is applied to the pn junction between the p-type impurity region 73p, which is one of the source and drain of the second reset transistor 30, and the n-type semiconductor layer 63n. As a result, signal charge is discharged from the p-type impurity region 73p to the n-type semiconductor layer 63n, and the potentials of node N1 and the charge storage node FD, which is electrically connected to node N1, are clipped at the limiting potential Vlim. Similarly, when the potential of node N0 reaches a limiting potential Vlim that exceeds the n-well voltage Vn, a forward bias voltage is applied to the pn junction between the p-type impurity region 71p, which is one of the source and drain of the first reset transistor 26, and the n-type semiconductor layer 63n. As a result, signal charge is discharged from the p-type impurity region 71p to the n-type semiconductor layer 63n, and the potential of node N0 is clipped at the limiting potential Vlim. Therefore, even when a large amount of light is incident on the photoelectric conversion unit 12, the rise in the potentials of the charge storage node FD, node N0, and node N1 is suppressed to the limiting potential Vlim. Thus, damage to transistors to which at least one of the gate, source, and drain is connected (for example, damage to the gate insulating film or pn junction in the transistor) can be suppressed. Furthermore, by arranging the p-type impurity region 73p and the p-type impurity region 71p in electrically isolated n-well regions, it is also possible to make the clipping potentials for the charge storage nodes FD and N1 different from the clipping potential for node N0.

[0134] Furthermore, since the potential of the charge storage node FD is clipped at the limiting potential Vlim, the lower the second reset voltage VR2 corresponding to the initial potential Vr1 of the charge storage node FD, the wider the dynamic range can be. In other words, the larger the difference between the n-well voltage Vn and the second reset voltage VR2 at the time of resetting the charge storage node FD, the wider the dynamic range can be. In the imaging device 100, the n-type impurity region 65n, which is one of the source and drain of the overflow transistor 28 connected to the charge storage node FD, is formed in the p-type semiconductor layer 62p. Therefore, since a p-well voltage Vp, which is lower than the n-well voltage Vn, is applied to the p-type semiconductor layer 62p, even if the second reset voltage VR2 applied to the n-type impurity region 65n during the reset period is lower, the potential difference between the p-type semiconductor layer 62p and the n-type impurity region 65n can be reduced. As a result, the leakage current between the n-type impurity region 65n and the p-type semiconductor layer 62p can be reduced.

[0135] In the above example, the signal charge is described as a hole, but the signal charge may also be an electron. In this case, the potential clipping effect described above can be obtained by swapping the p-type and n-type configurations of each component in the semiconductor substrate 60. In this case, the first conductivity type is p-type and the second conductivity type is n-type. For example, in the semiconductor substrate 60, the n-type semiconductor layer 63n to which the n-well voltage Vn is applied via the n-type impurity region 75n is replaced with a p-type semiconductor layer to which the p-well voltage Vp is applied via the p-type impurity region, and the p-type impurity regions 71p, 72p, 73p, and 74p are replaced with n-type impurity regions. In this case, a P-channel MOSFET is used for each of the amplifying transistor 22, the addressing transistor 24, and the overflow transistor 28, and an N-channel MOSFET is used for each of the first reset transistor 26 and the second reset transistor 30. Furthermore, when the signal charge is electrons, the p-well voltage Vp is lower than the first reset voltage VR1 used to reset the potential of node N0 and the second reset voltage VR2 used to reset the potentials of charge storage node FD and node N1, but higher than the storage control voltage VITO.

[0136] [Layout of pixel electrodes and light intensity detection electrodes] Next, an example of the layout of the pixel electrode 12a and the light intensity detection electrode 12d will be described.

[0137] Figure 6 is a plan view showing the layout of the pixel electrode 12a and light intensity detection electrode 12d of the imaging device 100 according to this embodiment. Figure 7 is a schematic cross-sectional view showing the structure near the pixel electrode 12a and light intensity detection electrode 12d of the imaging device 100 according to this embodiment. Figure 6 is a plan view of the plane on which the pixel electrode 12a and light intensity detection electrode 12d are arranged (the upper surface of the interlayer insulating layer 90 in Figure 7). Figure 7 also shows the cross-section along line VII-VII in Figure 6. In Figure 6, for clarity, the pixel electrode 12a, light intensity detection electrode 12d, and shield electrode 13 are shaded. In Figure 6, electrodes of the same type are shaded with the same type of shading. Also in Figure 6, the outlines of the vias 14 covered by the pixel electrode 12a and light intensity detection electrode 12d are shown with dashed lines. Also in Figure 7, for clarity, the shading showing the cross-section of the interlayer insulating layer 90 is omitted.

[0138] As shown in Figures 6 and 7, the imaging device 100 may also include, in addition to the configuration described above, a shield electrode 13, a via 14, insulating films 91 and 93, a color filter 92, and a microlens 94.

[0139] In the example shown in Figure 6, the pixel electrodes 12a are arranged in an array in a plan view, with their centers forming a square grid at predetermined intervals. Similarly, the light intensity detection electrodes 12d are arranged in an array in a plan view, with their centers forming a square grid at the same intervals as the pixel electrodes 12a. The pixel electrodes 12a and light intensity detection electrodes 12d are adjacent to each other in a plan view, separated by a shield electrode 13. In the example shown in Figure 6, the plan view shape of the pixel electrodes 12a is a regular octagon, but is not particularly limited. Also, in the example shown in Figure 6, the plan view shape of the light intensity detection electrodes 12d is a square, but is not particularly limited.

[0140] In the examples shown in Figures 6 and 7, the area of ​​the light intensity detection electrode 12d is smaller than the area of ​​the pixel electrode 12a in a plan view. As a result, the light intensity detection electrode 12d has difficulty collecting signal charge, making it less likely for the potential of node N0 to rise above the potential of charge storage node FD, thus widening the range of the potential of charge storage node FD that corresponds to the high-sensitivity mode. Therefore, exposure can be performed stably in high-sensitivity mode even in low-light environments where the exposure amount is small.

[0141] The shield electrode 13 is a film-like electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to impure conductivity. The shield electrode 13 is located between the pixel electrode 12a and the light intensity detection electrode 12d. This suppresses capacitive coupling between the pixel electrode 12a and the light intensity detection electrode 12d, thereby suppressing electrical color mixing. In the example shown in Figure 6, the shield electrode 13 is also placed between adjacent pixel electrodes 12a and between adjacent light intensity detection electrodes 12d. The shield electrode 13 may be formed integrally over the entire imaging region R1, or it may be formed separately for each of the two or more regions in which the imaging region R1 is divided.

[0142] The shield electrode 13 is connected to, for example, a voltage supply circuit or power supply voltage (not shown) and maintained at a predetermined potential. The shield electrode 13, the pixel electrode 12a, and the light intensity detection electrode 12d are formed on the interlayer insulating layer 90. The shield electrode 13, the pixel electrode 12a, and the light intensity detection electrode 12d are electrically isolated by a portion of the interlayer insulating layer 90 being placed between them.

[0143] Via 14 is at least part of a wiring structure connected to the pixel electrode 12a and the light intensity detection electrode 12d. Via 14 is a plug formed by embedding a metal such as aluminum or copper in the interlayer insulating layer 90.

[0144] As shown in Figure 7, the counter electrode 12c faces the pixel electrode 12a, the light intensity detection electrode 12d, and the shield electrode 13 via the photoelectric conversion layer 12b. Furthermore, an insulating film 91, a color filter 92, and an insulating film 93 are stacked on the upper surface of the counter electrode 12c in this order. The insulating film 91, color filter 92, and insulating film 93 are provided for each pixel 10. A microlens 94 is positioned on the upper surface of the insulating film 93 in a one-to-one correspondence with the pixel electrode 12a. In a plan view, the microlens 94 overlaps with the pixel electrode 12a but does not overlap with the light intensity detection electrode 12d. This makes it easier to concentrate light at a position overlapping with the pixel electrode 12a in a plan view, thereby increasing sensitivity. Note that the microlens 94 may overlap with a portion of the light intensity detection electrode 12d in a plan view. Also, the imaging device 100 may include a microlens other than the microlens 94 that overlaps with the light intensity detection electrode 12d in a plan view.

[0145] [Example 1] Next, we will describe a modified example of Embodiment 1. In the following, we will focus on the differences from Embodiment 1 described above, and omit or simplify the explanation of the common points.

[0146] Figure 8 shows the circuit configuration of the pixel according to this modified example. Figure 9 is a schematic cross-sectional view of the device structure of the pixel according to this modified example. In Figure 9, some of the electrical connections of the transistors and impurity regions formed on the semiconductor substrate 60 are schematically shown. Note that in Figure 9, the amplification transistor 22 and the address transistor 24 are not shown, as in Figure 3.

[0147] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are replaced with a plurality of pixels 10A. Furthermore, the imaging device according to this modified example further includes a voltage supply circuit 49A.

[0148] As shown in Figures 8 and 9, the pixel 10A in this modified example differs from the pixel 10 in Embodiment 1 mainly in that it includes a capacitive element 21A instead of the capacitive element 21, and the source and drain of the second reset transistor 30 are connected to the voltage supply circuit 49A via the gain switching control line 55.

[0149] One end of the capacitive element 21A is connected to the other source and drain of the overflow transistor 28, and to one source and drain of the second reset transistor 30. The other end of the capacitive element 21A is connected to the other source and drain of the second reset transistor 30, and to the gain switching control line 55. One end of the capacitive element 21A is an example of a first terminal of the capacitive element 21A, and the other end of the capacitive element 21A is an example of a second terminal of the capacitive element 21A. The capacitive element 21A is, for example, a MOM capacitor, a MIM capacitor, a MOS capacitor, or a trench capacitor.

[0150] The voltage supply circuit 49A supplies a control voltage VF to the gain switching control line 55. The control voltage VF is applied to one end of the capacitive element 21A and node N1 via the gain switching control line 55 when the second reset transistor 30 is turned on. This resets the potential of one end of the capacitive element 21A and node N1 to the control voltage VF at that time. The control voltage VF is also applied to the charge storage node FD when the second reset transistor 30 and overflow transistor 28 are turned on. This resets the potential of the charge storage node FD to the control voltage VF at that time. After the second reset transistor 30 and overflow transistor 28 are turned on, the overflow transistor 28 is turned off without the second reset transistor 30 being turned off, and the magnitude of the control voltage VF is changed, making it possible to make the potential of the charge storage node FD at the time of reset different from the potential of one end of the capacitive element 21A and node N1 at the time of reset. In other words, by changing the magnitude of the control voltage VF during the period from time t1 to time t2 and the period from time t2 to time t3 as shown in Figure 4, it is possible to make the potential of the charge storage node FD at the time of reset and the potential of one end of the capacitive element 21A and node N1 at the time of reset different.

[0151] The magnitude of the control voltage VF applied by the voltage supply circuit 49A is controlled, for example, by the control circuit 46. The voltage supply circuit 49A may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or it may be a circuit that generates a predetermined voltage. The voltage supply circuit 49A may also be part of the vertical scanning circuit 42 or the control circuit 46 described above.

[0152] In this modified example, by controlling the control voltage VF, the reset potential of node N1 connected to the other end of the source and drain of the overflow transistor 28 is controlled, so that the threshold potential Vof at which the overflow transistor 28 turns on can be changed. Furthermore, by setting the control voltage VF to a height above a predetermined level, a state in which the overflow transistor 28 does not turn on can also be achieved. The control circuit 46 has, for example, a gain switching ON mode in which the gain of photoelectric conversion switches when the potential of the charge storage node FD reaches the threshold potential Vof, and a gain switching OFF mode in which the gain of photoelectric conversion does not switch even when the potential of the charge storage node FD reaches a predetermined potential.

[0153] In the imaging device according to this modified example, changing the control voltage VF is not essential. For example, similar to the pixel 10, the source and drain of the second reset transistor 30 may be connected to the second reset voltage line 54 that supplies the second reset voltage VR2.

[0154] [Differentiation 2] Next, a modified example of Embodiment 1, Part 2, will be described. In the following, the differences between Embodiment 1 and Modified Example 1 of Embodiment 1 will be the main focus of the explanation, and the explanation of the common points will be omitted or simplified.

[0155] Figure 10 shows the circuit configuration of the pixel according to this modified example. Figure 11 is a schematic cross-sectional view of the device structure of the pixel according to this modified example. In Figure 11, some of the electrical connections of the transistors and impurity regions formed on the semiconductor substrate 60 are schematically shown. Note that in Figure 11, the amplification transistor 22 and the address transistor 24 are not shown, as in Figure 3.

[0156] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are changed to a plurality of pixels 10B.

[0157] As shown in Figures 10 and 11, the pixel 10B according to this modified example differs from the pixel 10 according to Embodiment 1 mainly in that it does not have a capacitive element 21 and a second reset transistor 30, and the source and drain of the overflow transistor 28 are connected to the second reset voltage line 54.

[0158] In this modified example, when exposure causes the potential of node N0 to rise and reach the threshold potential Vof, turning on the overflow transistor 28, the charge storage node FD is electrically connected to the second reset voltage line 54. Therefore, even when a large amount of light is incident on the photoelectric conversion unit 12, the second reset voltage VR2 is supplied to the charge storage node FD when the potential of node N0 reaches the threshold potential Vof, thereby suppressing an excessive rise in the potential of the charge storage node FD. As a result, damage to the transistor (for example, damage to the gate insulating film or pn junction in the transistor) to which at least one of the gate, source, and drain is connected can be suppressed.

[0159] [Difference 3] Next, we will describe a modified example of Embodiment 1, Part 3. In the following, we will focus on the differences between Embodiment 1 and Modified Examples 1 and 2 of Embodiment 1, and will omit or simplify the explanation of the common points.

[0160] Figure 12 is a diagram showing the circuit configuration of a pixel according to this modified example. The imaging device according to this modified example has a configuration in which some of the multiple pixels 10 of the imaging device 100 according to Embodiment 1 are changed to pixels 10C, and the remaining part of the pixels 10 are changed to pixels 10D. Pixel 10C is an example of a first pixel, and pixel 10D is an example of a second pixel.

[0161] As shown in Figure 12, pixel 10C differs from pixel 10 according to Embodiment 1 mainly in that one of the sources and drains of the first reset transistor 26 is connected not only to its own light intensity detection electrode 12d and the gate of the overflow transistor 28, but also to the light intensity detection electrode 12d and the gate of the overflow transistor 28 of pixel 10D. Furthermore, pixel 10D differs from pixel 10 according to Embodiment 1 mainly in that it does not include the first reset transistor 26.

[0162] In pixel 10D, the light intensity detection electrode 12d and the gate of the overflow transistor 28 are connected to either the source or drain of the first reset transistor 26 of pixel 10C via node N0 of pixel 10D and node N0 of pixel 10C. Node N0 of pixel 10C and node N0 of pixel 10D are electrically connected. The first reset voltage VR1 is supplied to node N0 of pixel 10C and node N0 of pixel 10D from the voltage supply circuit 49 via the first reset transistor 26 of pixel 10C. Therefore, the imaging device according to this modified example can also be said to have a configuration in which two pixels 10 share one first reset transistor 26 in the imaging device 100 according to Embodiment 1. This makes it possible to reduce the number of first reset transistors 26 and miniaturize the imaging device. Furthermore, if one first reset transistor 26 is shared between pixel 10C and pixel 10D, then pixel 10C and pixel 10D may not each have their own first reset transistor 26, and the first reset transistor 26 located in a region other than the region in which pixels 10C and pixel 10D are provided may be shared between pixel 10C and pixel 10D.

[0163] The imaging device according to this modified example includes a predetermined ratio of pixels 10C and pixels 10D. For example, the imaging device according to this modified example includes pixels 10C and pixels 10D in a ratio of 1:X, where X is an integer greater than or equal to 1. In other words, the imaging device according to this modified example has a configuration in which 2 (=1+X) or more pixels 10 share one first reset transistor 26. For example, X is between 1 and 15. In the example shown in Figure 12, pixels 10C and pixels 10D are arranged adjacent to each other, and X is 1. X may also be 3. When X is 3, one pixel 10C and three pixels 10D adjacent to that pixel 10C are, for example, R (red) pixels, Gr (green) pixels, Gb (green) pixels, and B (blue) pixels.

[0164] In addition, although the above describes an example in which two or more pixels 10 share one first reset transistor 26, two or more pixels 10A or two or more pixels 10B may share one first reset transistor 26 instead of one pixel 10.

[0165] [Another example of a pixel device structure] Next, another example of the device structure of pixel 10 according to Embodiment 1 and pixel 10A according to Modification 1 of Embodiment 1 described above will be explained. In the following, the differences between the device structures of pixel 10 according to Embodiment 1 and pixel 10A according to Modification 1 of Embodiment 1 described above, as well as the differences between other examples of device structures, will be explained, and the explanation of common points will be omitted or simplified. Note that for pixels 10B, 10C, and 10D, the circuit configuration of pixel 10 or pixel 10A may be changed to that of pixels 10B, 10C, and 10D, and the device structure described below may be applied.

[0166] First, let's describe another example of the pixel device structure. Figure 13 is a schematic cross-sectional view showing another example of the pixel device structure according to Embodiment 1. Figure 14 is a schematic cross-sectional view showing another example of the pixel device structure according to Modification 1 of Embodiment 1. The circuit configuration of pixel 111 shown in Figure 13 is the same as that of pixel 10 shown in Figure 2. The circuit configuration of pixel 111A shown in Figure 14 is the same as that of pixel 10A shown in Figure 8.

[0167] The pixel 111 shown in Figure 13 differs from the pixel 10 shown in Figure 3 mainly in that the photoelectric conversion unit 12 is located on the side opposite to the main surface 81 of the semiconductor substrate 60. Similarly, the pixel 111A shown in Figure 14 differs from the pixel 10A shown in Figure 9 mainly in that the photoelectric conversion unit 12 is located on the side opposite to the main surface 81 of the semiconductor substrate 60.

[0168] As shown in Figures 13 and 14, in pixels 111 and 111A, light is incident from the side opposite to the main surface 81 of the semiconductor substrate 60. In pixels 111 and 111A, the pixel electrode 12a and the n-type impurity region 65n are connected via a through-electrode (not shown) that penetrates the semiconductor substrate 60. Also, the light intensity detection electrode 12d, the p-type impurity region 71p, and the gate 28e are connected via a through-electrode (not shown) that penetrates the semiconductor substrate 60. In pixels 111 and 111A, the capacitive elements 21 and 21A are located on the side of the semiconductor substrate 60 opposite to the photoelectric conversion section 12.

[0169] In pixels 111 and 111A, the main surface 81 on which the transistors are located is on the opposite side of the semiconductor substrate 60 from the photoelectric conversion section 12. Therefore, when at least a portion of the peripheral circuitry is formed on another semiconductor substrate stacked on the semiconductor substrate 60, it becomes easier to connect the transistors located on the main surface 81 to the peripheral circuitry.

[0170] Next, a second example of the pixel device structure will be described. Figure 15 is a schematic cross-sectional view showing a second example of the pixel device structure according to Embodiment 1. Figure 16 is a schematic cross-sectional view showing a second example of the pixel device structure according to Modification 1 of Embodiment 1. The circuit configuration of the pixel 112 shown in Figure 15 is the same as that of the pixel 10 shown in Figure 2. The circuit configuration of the pixel 112A shown in Figure 16 is the same as that of the pixel 10A shown in Figure 8.

[0171] The pixel 112 shown in Figure 15 differs from the pixel 10 shown in Figure 3 mainly in that it includes semiconductor substrates 60A and 60B instead of semiconductor substrate 60. Similarly, the pixel 112A shown in Figure 16 differs from the pixel 10A shown in Figure 9 mainly in that it includes semiconductor substrates 60A and 60B instead of semiconductor substrate 60. In pixels 112 and 112A, the p-type semiconductor layer 62p and the n-type semiconductor layer 63n are arranged separately on semiconductor substrates 60A and 60B. Semiconductor substrate 60A is an example of a first semiconductor substrate, and semiconductor substrate 60B is an example of a second semiconductor substrate.

[0172] As shown in Figures 15 and 16, in pixels 112 and 112A, the semiconductor substrate 60A is located between the photoelectric conversion unit 12 and the semiconductor substrate 60B. The semiconductor substrates 60A and 60B are stacked on top of each other with an interlayer insulating layer in between. Similarly, the semiconductor substrate 60A and the photoelectric conversion unit 12 are stacked on top of each other with an interlayer insulating layer in between. In pixels 112 and 112A, the capacitive elements 21 and 21A are formed within the interlayer insulating layer between the semiconductor substrates 60A and 60B.

[0173] As shown in Figures 15 and 16, the semiconductor substrate 60A has a main surface 82 on which an amplifying transistor 22 (not shown), an addressing transistor 24 (not shown), and an overflow transistor 28 are arranged. The main surface 82 is a surface perpendicular to the thickness direction of the semiconductor substrate 60A. In pixels 112 and 112A, the photoelectric conversion unit 12 is arranged on the side of the main surface 82 of the semiconductor substrate 60A, and the semiconductor substrate 60B is arranged on the side of the semiconductor substrate 60A opposite to the main surface 82. The semiconductor substrate 60A includes a support substrate 61p and a p-type semiconductor layer 62p. The p-type semiconductor layer 62p is provided on the support substrate 61p. The p-type semiconductor layer 62p is the semiconductor layer on which the main surface 82 is arranged among the semiconductor layers included in the semiconductor substrate 60A.

[0174] The semiconductor substrate 60B has a main surface 83 on which the first reset transistor 26 and the second reset transistor 30 are arranged. The main surface 83 is a surface perpendicular to the thickness direction of the semiconductor substrate 60B. In pixels 112 and 112A, the semiconductor substrate 60A and the photoelectric conversion unit 12 are arranged on the side of the main surface 83 of the semiconductor substrate 60B. The semiconductor substrate 60B includes a support substrate 61n and an n-type semiconductor layer 63n. Here, an n-type silicon (Si) substrate is given as an example of the support substrate 61n. The n-type semiconductor layer 63n is provided on the support substrate 61n. The n-type semiconductor layer 63n is the semiconductor layer on which the main surface 83 is arranged among the semiconductor layers included in the semiconductor substrate 60B.

[0175] In pixels 112 and 112A, semiconductor substrates 60A and 60B are stacked so that their main surfaces 82 and 83 face in the same direction. The side of semiconductor substrate 60A opposite to semiconductor substrate 60B is the main surface 82, and the side of semiconductor substrate 60B facing semiconductor substrate 60A is the main surface 83.

[0176] In pixels 112 and 112A, the transistors are separated and arranged on semiconductor substrates 60A and 60B, allowing for a smaller pixel size. Furthermore, since the n-type impurity region 65n is located on the main surface 82 of semiconductor substrate 60A on the photoelectric conversion unit 12 side between the photoelectric conversion unit 12 and semiconductor substrate 60B, the wiring connecting the pixel electrode 12a and the n-type impurity region 65n can be shortened. This wiring functions as a charge storage region that accumulates signal charge in high-sensitivity mode, thus reducing the capacitance of the charge storage region in high-sensitivity mode and increasing the gain of photoelectric conversion.

[0177] Furthermore, the semiconductor substrates 60A and 60B may be swapped in position while maintaining their vertical orientation. In other words, semiconductor substrate 60B may be located between the photoelectric conversion unit 12 and semiconductor substrate 60A. As a result, the n-type impurity region 65n, which accumulates signal charge in high-sensitivity mode, is located in semiconductor substrate 60A, which is further from the photoelectric conversion unit 12 than semiconductor substrate 60B. Therefore, the generation of charge caused by light not absorbed by the photoelectric conversion unit 12 entering the n-type impurity region 65n is suppressed. Consequently, in high-sensitivity mode, noise caused by the generation of charge unrelated to photoelectric conversion by the photoelectric conversion unit 12 is suppressed.

[0178] Next, a third example of the pixel device structure will be described. Figure 17 is a schematic cross-sectional view showing a third example of the pixel device structure according to Embodiment 1. Figure 18 is a schematic cross-sectional view showing a third example of the pixel device structure according to Modification 1 of Embodiment 1. The circuit configuration of the pixel 113 shown in Figure 17 is the same as that of the pixel 10 shown in Figure 2. The circuit configuration of the pixel 113A shown in Figure 18 is the same as that of the pixel 10A shown in Figure 8.

[0179] Pixel 113 shown in Figure 17 differs from pixel 112 shown in Figure 15 mainly in that the top and bottom of the semiconductor substrate 60A are inverted. Similarly, pixel 113A shown in Figure 18 differs from pixel 112A shown in Figure 16 mainly in that the top and bottom of the semiconductor substrate 60A are inverted.

[0180] As shown in Figures 17 and 18, in pixels 113 and 113A, the semiconductor substrate 60A is located between the photoelectric conversion unit 12 and the semiconductor substrate 60B. The semiconductor substrates 60A and 60B are stacked on top of each other with an interlayer insulating layer in between. In pixels 113 and 113A, the capacitive elements 21 and 21A are formed within the interlayer insulating layer between the semiconductor substrates 60A and 60B. Furthermore, the capacitive elements 21 and 21A are positioned, for example, closer to the semiconductor substrate 60B than to the semiconductor substrate 60A.

[0181] In pixels 113 and 113A, the photoelectric conversion unit 12 is positioned on the side of the semiconductor substrate 60A opposite to the main surface 82, while the semiconductor substrate 60B is positioned on the main surface 82 side of the semiconductor substrate 60A. Furthermore, the semiconductor substrate 60A and the photoelectric conversion unit 12 are positioned on the main surface 83 side of the semiconductor substrate 60B.

[0182] In pixels 113 and 113A, semiconductor substrates 60A and 60B are stacked such that their main surfaces 82 and 83 face each other. The surface of semiconductor substrate 60A facing semiconductor substrate 60B is the main surface 82, and the surface of semiconductor substrate 60B facing semiconductor substrate 60A is the main surface 83.

[0183] In pixels 113 and 113A, the transistors are arranged separately on semiconductor substrates 60A and 60B, allowing for a smaller pixel size (area). Furthermore, since the n-type impurity region 65n is located on semiconductor substrate 60A between the photoelectric conversion unit 12 and semiconductor substrate 60B, the wiring connecting the pixel electrode 12a and the n-type impurity region 65n can be shortened. This wiring functions as a charge storage region that accumulates signal charge in high-sensitivity mode, thus reducing the capacitance of the charge storage region in high-sensitivity mode and increasing the photoelectric conversion gain. Additionally, in pixels 113 and 113A, the main surfaces 82 and 83 on which the transistors are located face each other, facilitating wiring connections between pixels. Moreover, high capacitance is easily achieved when using the wiring between main surfaces 82 and 83 to form capacitive elements 21 and 21A.

[0184] Furthermore, the semiconductor substrates 60A and 60B may be swapped in position while maintaining the orientation so that their main surfaces 82 and 83 face each other. In other words, semiconductor substrate 60B may be located between the photoelectric conversion unit 12 and semiconductor substrate 60A. As a result, the n-type impurity region 65n, which accumulates signal charge in high-sensitivity mode, is located in semiconductor substrate 60A, which is further from the photoelectric conversion unit 12 than semiconductor substrate 60B. Therefore, the generation of charge caused by light not absorbed by the photoelectric conversion unit 12 entering the n-type impurity region 65n is suppressed. Consequently, in high-sensitivity mode, noise caused by the generation of charge unrelated to photoelectric conversion by the photoelectric conversion unit 12 is suppressed.

[0185] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 describes a camera system equipped with an imaging device according to the present disclosure.

[0186] Figure 19 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0187] As shown in Figure 19, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0188] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to any of the above-described embodiments 1 and 1 to 3 of embodiment 1 is used.

[0189] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0190] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data such as differential digital signals from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 602 as part can be made smaller.

[0191] (Other embodiments) The imaging apparatus and camera system relating to this disclosure have been described above based on embodiments, but this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to the embodiments that a person skilled in the art could conceive, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of this disclosure.

[0192] For example, in the above embodiment, the potential of the charge storage node FD was reset by a second reset voltage VR2 supplied to the charge storage node FD via a second reset transistor 30 and an overflow transistor 28, but this is not limited to this. For example, the potential of the charge storage node FD may be reset via the photoelectric conversion unit 12 by a voltage applied to the counter electrode 12c. Furthermore, the pixel may be further provided with a transistor to which one of the source and drain is connected to the charge storage node FD, and to which a voltage for resetting the potential of the charge storage node FD is supplied to the other source and drain.

[0193] Furthermore, in the above embodiment, the potential of node N0 was reset by a first reset voltage VR1 supplied to node N0 via the first reset transistor 26, but this is not limited to this. For example, the potential of node N0 may be reset via the photoelectric conversion unit 12 by a voltage applied to the counter electrode 12c. In this case, the imaging device does not need to be equipped with the first reset transistor 26.

[0194] Furthermore, in the above embodiment, for example, N-channel MOSFETs were used for each of the amplification transistor 22, address transistor 24, and overflow transistor 28, and P-channel MOSFETs were used for each of the first reset transistor 26 and second reset transistor 30, but this is not limited to this. N-channel MOSFETs or P-channel MOSFETs may be used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, overflow transistor 28, and second reset transistor 30. For example, N-channel MOSFETs may be used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, overflow transistor 28, and second reset transistor 30.

[0195] Furthermore, for example, in the above embodiment, each pixel is equipped with a capacitive element 21 or 21A, but this is not limited to this. Each pixel does not need to be equipped with capacitive elements 21 and 21A.

[0196] Furthermore, in the above embodiment, for example, the area of ​​the gate 28e of the overflow transistor 28 was larger than the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30, respectively. However, this is not limited to this, and any relationship between the areas is acceptable. For example, the area of ​​the gate 28e of the overflow transistor 28 may be the same as the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30, respectively.

[0197] Furthermore, for example, in the above embodiment, the thickness of the gate insulating film 28i of the overflow transistor 28 was smaller than the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30, respectively. However, this is not limited to this, and any thickness relationship is possible. For example, the thickness of the gate insulating film 28i of the overflow transistor 28 may be the same as the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30, respectively.

[0198] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0199] The imaging device relating to this disclosure is useful for, for example, image sensors and digital cameras. The imaging device relating to this disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like. [Explanation of Symbols]

[0200] 10, 10A, 10B, 10C, 10D, 111, 111A, 112, 112A, 113, 113A pixels 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c counter electrode 12d Light intensity detection electrode 13 Shielding electrodes 14 Beer 21, 21A Capacitive element 22 Amplifying Transistors 26e, 28e, 30e gates 24 Address Transistors 26. First Reset Transistor 26c, 28c, 30c channel regions 26i, 28i, 30i gate insulator 28 Overflow Transistors 30. Second reset transistor 31. Accumulation control line 32, 38 Power wiring 34 Address signal line 35 Vertical signal lines 36. First reset signal line 37. Second reset signal line 42 Vertical scanning circuit 44 Horizontal signal readout circuit 46 Control circuits 48, 49, 49A voltage supply circuit 53 First reset voltage line 54 Second reset voltage line 55 Gain switching control line 60, 60A, 60B Semiconductor Substrates 61n, 61p support board 62p p-type semiconductor layer 63n n-type semiconductor layer 65n, 66n, 75n n-type impurity region 67p, 71p, 72p, 73p, 74p p-type impurity region 69 Element Isolation Region 81, 82, 83 Main surface 91, 93 Insulating film 92 Color Filters 100, 602 Imaging device 400 Camera System 601 Lens Optics 603 System Controller 604 Camera signal processing circuit FD charge storage node N0, N1 nodes

Claims

1. First electrode and In a plan view, a second electrode is positioned at a different location from the first electrode, A photoelectric conversion layer that converts light into signal charges, A third electrode facing the first electrode and the second electrode is connected via the photoelectric conversion layer, A charge storage region connected to the first electrode and accumulating the signal charge, A first transistor having one of its source and drain connected to the charge storage region and its gate connected to the second electrode, Equipped with, Imaging device.

2. The system further comprises a second transistor, the source and drain of which are connected to the gate and second electrode of the first transistor. The imaging apparatus according to claim 1.

3. The first transistor includes an impurity region of a first conductivity type as either the source or the drain. The second transistor includes an impurity region of a second conductivity type different from the first conductivity type as either the source or the drain. The imaging apparatus according to claim 2.

4. The first conductivity type is n-type, and the second conductivity type is p-type. The imaging device according to claim 3.

5. The system further comprises a third transistor, the source of which one of the drains is connected to the other of the source and drain of the first transistor. The imaging apparatus according to claim 1.

6. The first transistor includes an impurity region of a first conductivity type as either the source or the drain. The third transistor includes an impurity region of a second conductivity type different from the first conductivity type as either the source or the drain. The imaging apparatus according to claim 5.

7. The first conductivity type is n-type, and the second conductivity type is p-type. The imaging device according to claim 6.

8. The present invention further comprises a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to the other of the source and drain of the first transistor, and a first voltage is applied to the second terminal. The imaging apparatus according to claim 1.

9. The present invention further comprises a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to one of the source and drain of the third transistor, and the second terminal is connected to the other of the source and drain of the third transistor. The imaging apparatus according to claim 5.

10. In a plan view, the area of ​​the second electrode is smaller than the area of ​​the first electrode. The imaging apparatus according to claim 1.

11. Each comprises a first pixel and a second pixel, each including the first electrode, the second electrode, the photoelectric conversion layer, the third electrode, the charge storage region, and the first transistor, The second transistor is shared by the first pixel and the second pixel, The source and drain of the second transistor of the first pixel are connected to the second electrode of the first pixel, the second electrode of the second pixel, the gate of the first transistor of the first pixel, and the gate of the first transistor of the second pixel. The imaging apparatus according to claim 2.

12. A voltage for resetting the potential of the charge storage region is supplied to the charge storage region via the third transistor and the first transistor. The imaging apparatus according to claim 5.

13. First semiconductor substrate and The invention comprises a second semiconductor substrate laminated on the first semiconductor substrate, The first semiconductor substrate is located between the first electrode and the second semiconductor substrate. The first transistor is arranged on the first semiconductor substrate. The second transistor is located on the second semiconductor substrate. The imaging apparatus according to claim 4.

14. First semiconductor substrate and The invention comprises a second semiconductor substrate laminated on the first semiconductor substrate, The first semiconductor substrate is located between the first electrode and the second semiconductor substrate. The first transistor is arranged on the first semiconductor substrate. The third transistor is located on the second semiconductor substrate. The imaging device according to claim 6.

15. The imaging device comprises the imaging device described in any one of claims 1 to 14. Camera system.

Images