Imaging device and camera system

Abstract

The present invention provides an imaging device that can widen the dynamic range and suppress variations in the output signal. [Solution] The imaging device comprises a photoelectric conversion unit 12 that converts light into signal charge, a charge storage region connected to the photoelectric conversion unit 12 for accumulating signal charge, a gain switching transistor 28 whose source and drain and gate 28e are connected to the charge storage region, and a second reset transistor 30 whose source and drain are connected to the other source and drain of the gain switching transistor 28. In a plan view, at least one of the following is satisfied: (ii) the area of ​​the gate 28e of the gain switching transistor 28 is larger than the area of ​​the gate 30e of the second reset transistor 30, and (ii) the thickness of the gate insulating film 28i of the gain switching transistor 28 is smaller than the thickness of the gate insulating film 30i of the second reset transistor 30.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a camera system.

Background Art

[0002] In digital cameras and the like, imaging devices such as CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used. These imaging devices have, for example, a photodiode formed on a semiconductor substrate as a photoelectric conversion section. Further, an imaging device having a structure in which a photoelectric conversion section having a photoelectric conversion layer is disposed on the light incident side of a semiconductor substrate instead of a photodiode has been proposed. An imaging device having such a structure may be called a stacked imaging device.

[0003] Also, in an imaging device, a technique for expanding the dynamic range of light and shade is known (see, for example, Patent Document 1 and Patent Document 2).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present disclosure provides an imaging device and the like that can expand the dynamic range and suppress variations in output signals.

Means for Solving the Problems

[0006] An imaging device according to one aspect of the present disclosure includes: a photoelectric conversion unit that converts light into signal charge; a charge storage region connected to the photoelectric conversion unit for storing the signal charge; a first transistor whose source and drain and gate are connected to the charge storage region; and a second transistor whose source and drain are connected to the other source and drain of the first transistor, wherein at least one of the following is satisfied: (i) in a plan view, the area of ​​the gate of the first transistor is larger than the area of ​​the gate of the second transistor; and (ii) the thickness of the gate insulating film of the first transistor is smaller than the thickness of the gate insulating film of the second transistor.

[0007] A camera system relating to one aspect of this disclosure includes the above-mentioned imaging device. [Effects of the Invention]

[0008] According to this disclosure, the dynamic range can be widened and variations in the output signal can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a diagram showing the configuration of the imaging device according to Embodiment 1. [Figure 2] Figure 2 is a diagram showing the circuit configuration of a pixel according to Embodiment 1. [Figure 3] Figure 3 is a plan view showing an example of the layout within a pixel according to Embodiment 1. [Figure 4] Figure 4 is a schematic cross-sectional view of the pixel device structure according to Embodiment 1. [Figure 5] Figure 5 is a timing chart illustrating an example of the operation of the imaging device according to Embodiment 1. [Figure 6] Figure 6 schematically shows the relationship between exposure time and the potential of the charge storage node. [Figure 7] Figure 7 shows the circuit configuration of a pixel according to a modified example of Embodiment 1. [Figure 8]FIG. 8 is a schematic cross-sectional view of the device structure of a pixel according to a modification of Embodiment 1. [Figure 9] FIG. 9 is a diagram showing the relationship between the exposure amount and the output signal level in a pixel according to a modification of Embodiment 1. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a first alternative example of the device structure of a pixel according to Embodiment 1. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a first alternative example of the device structure of a pixel according to a modification of Embodiment 1. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a second alternative example of the device structure of a pixel according to Embodiment 1. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a second alternative example of the device structure of a pixel according to a modification of Embodiment 1. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a third alternative example of the device structure of a pixel according to Embodiment 1. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a third alternative example of the device structure of a pixel according to a modification of Embodiment 1. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a fourth alternative example of the device structure of a pixel according to Embodiment 1. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a fourth alternative example of the device structure of a pixel according to a modification of Embodiment 1. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a fifth alternative example of the device structure of a pixel according to Embodiment 1. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a fifth alternative example of the device structure of a pixel according to a modification of Embodiment 1. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of a camera system according to Embodiment 2.

BEST MODE FOR CARRYING OUT THE INVENTION

[0010] (SUMMARY OF THE DISCLOSURE) As an overview of one aspect of the present disclosure, examples of an imaging device and a camera system according to the present disclosure are shown below.

[0011] For example, an imaging device according to a first aspect of the present disclosure includes a photoelectric conversion unit that converts light into signal charges, a charge storage region connected to the photoelectric conversion unit that stores the signal charges, a first transistor having one of a source and a drain and a gate connected to the charge storage region, and a second transistor having one of a source and a drain connected to the other of the source and the drain of the first transistor. At least one of (i) in a plan view, the area of the gate of the first transistor is larger than the area of the gate of the second transistor, and (ii) the thickness of the gate insulating film of the first transistor is smaller than the thickness of the gate insulating film of the second transistor is satisfied.

[0012] As a result, when the potential of the charge storage region reaches a threshold potential that depends on the threshold voltage of the first transistor as the signal charges accumulated in the charge storage region increase, the first transistor turns on. As a result, the signal charges accumulate not only in the charge storage region but also between the first transistor and the second transistor, increasing the capacitance for storing the signal charges and making it difficult for the potential of the charge storage region to rise. Therefore, the conversion gain by photoelectric conversion decreases at the point when the potential of the charge storage region reaches the threshold potential. As a result, the dynamic range can be expanded.

[0013] Further, if the threshold voltage of the first transistor varies, the above-mentioned threshold potential at which the gain of photoelectric conversion switches varies, and the output signal of the imaging device also varies. However, in this aspect, since at least one of (i) and (ii) above is satisfied, the variation in the threshold voltage of the first transistor is suppressed, and the variation in the output signal of the imaging device can be suppressed.

[0014] From the above, according to the imaging device according to this aspect, the dynamic range can be expanded and the variation in the output signal can be suppressed.

[0015] Furthermore, for example, the imaging apparatus according to the second aspect of this disclosure is the imaging apparatus according to the first aspect, wherein the gate width of the first transistor is greater than the gate width of the second transistor.

[0016] This makes it possible to suppress variations in the threshold voltage of the first transistor.

[0017] Furthermore, for example, an imaging device according to a third aspect of this disclosure is an imaging device according to the first or second aspect, wherein the gate length of the first transistor is greater than the gate length of the second transistor.

[0018] This makes it possible to suppress variations in the threshold voltage of the first transistor.

[0019] Furthermore, for example, an imaging device according to a fourth aspect of this disclosure is an imaging device according to any one of the first to third aspects, wherein, in a plan view, the area of ​​the channel region of the first transistor is larger than the area of ​​the channel region of the second transistor.

[0020] This makes it possible to suppress variations in the threshold voltage of the first transistor.

[0021] Furthermore, for example, an imaging device according to a fifth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, further comprising a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to the other of the source and drain of the first transistor, and a first voltage is applied to the second terminal.

[0022] As a result, when the first transistor is turned on, signal charge accumulates in the capacitive element as well, further reducing the gain of photoelectric conversion when the first transistor is on, thus widening the dynamic range even further.

[0023] Furthermore, for example, an imaging device according to a sixth aspect of the present disclosure is an imaging device according to any one of the first to fourth aspects, further comprising a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to one of the source and drain of the second transistor, and the second terminal is connected to the other of the source and drain of the second transistor.

[0024] As a result, when the first transistor is turned on, signal charge accumulates in the capacitive element as well, further reducing the gain of photoelectric conversion when the first transistor is on, thus widening the dynamic range even further.

[0025] Furthermore, for example, an imaging apparatus according to the seventh aspect of the present disclosure is an imaging apparatus according to any one of the first to sixth aspects, wherein the first transistor includes an impurity region of a first conductivity type as one of the source and drain, and the second transistor includes an impurity region of a second conductivity type different from the first conductivity type as one of the source and drain.

[0026] This makes it possible to configure the system so that if an excess of signal charge accumulates in the charge storage region, the signal charge can be discharged from either the source or drain of the second transistor into the well region.

[0027] Furthermore, for example, the imaging apparatus according to the eighth aspect of this disclosure is the imaging apparatus according to the seventh aspect, wherein the concentration of the impurity of the second conductivity type in the channel region of the first transistor is higher than the concentration of the impurity of the first conductivity type in the channel region of the second transistor.

[0028] This suppresses depletion of the channel region when the first transistor is off, and reduces the leakage current when the first transistor is off.

[0029] Furthermore, for example, the imaging device according to the ninth aspect of this disclosure is an imaging device according to the seventh or eighth aspect, wherein the first conductivity type is n type and the second conductivity type is p type.

[0030] This makes it possible to configure the system so that, when the signal charge is a hole, if an excess of signal charge accumulates in the charge storage region, the signal charge can be discharged from either the source or drain of the second transistor into the well region.

[0031] Furthermore, for example, an imaging apparatus according to a tenth aspect of the present disclosure is an imaging apparatus according to a ninth aspect, further comprising a third transistor which includes the impurity region of the first conductivity type as one of its source and drain, and one of the source and drain is connected to the charge storage region, wherein the voltage applied to the other of the source and drain of the third transistor is smaller than the voltage applied to the other of the source and drain of the second transistor.

[0032] This reduces the potential difference between the first transistor, which is reset by the second transistor, and the second transistor, and the well region where the second transistor is formed, thereby reducing leakage current. Furthermore, it reduces the potential difference between the charge storage region, which is reset by the third transistor, and the well region where the third transistor is formed, thereby reducing leakage current.

[0033] Furthermore, for example, the imaging apparatus according to the 11th aspect of this disclosure is the imaging apparatus according to the 10th aspect, wherein the voltage applied to the gate of the third transistor during the storage period in which the signal charge is stored in the charge storage region is a negative voltage.

[0034] This suppresses depletion of the channel region of the third transistor during the storage period, thereby reducing the leakage current of the third transistor.

[0035] Furthermore, for example, an imaging apparatus according to the twelfth aspect of this disclosure is an imaging apparatus according to the tenth or eleventh aspect, wherein the concentration of the second conductivity type impurity in the channel region of the third transistor is higher than the concentration of the first conductivity type impurity in the channel region of the second transistor.

[0036] This suppresses depletion of the channel region when the third transistor is off, and reduces the leakage current when the third transistor is off.

[0037] Furthermore, for example, the imaging device according to the 13th aspect of this disclosure is an imaging device according to any one of the 10th to 12th aspects, wherein the gate width of the first transistor is greater than the gate width of the third transistor.

[0038] This makes it possible to suppress variations in the threshold voltage of the first transistor.

[0039] Furthermore, for example, the imaging device according to the 14th aspect of this disclosure is an imaging device according to any one of the 10th to 13th aspects, wherein the gate length of the first transistor is greater than the gate length of the third transistor.

[0040] This makes it possible to suppress variations in the threshold voltage of the first transistor.

[0041] Furthermore, for example, an imaging apparatus according to a 15th aspect of the present disclosure is an imaging apparatus according to any one of the 10th to 14th aspects, wherein the photoelectric conversion unit includes a first electrode connected to the charge storage region, a second electrode facing the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode, the second transistor located in a well region of the first conductivity type, and the voltage applied to the well region is the voltage between the voltage applied to the second electrode and the voltage applied to the other of the source and drain of the third transistor.

[0042] As a result, if the potential of the charge storage region rises excessively, a forward bias condition is created between one of the source and drain of the second transistor and the well region. Consequently, signal charge can be discharged from one of the source and drain of the second transistor to the well region, clipping the potential of the charge storage region. Therefore, damage to the imaging device due to an excessive rise in the potential of the charge storage region can be suppressed.

[0043] Furthermore, for example, an imaging apparatus according to the 16th aspect of the present disclosure is an imaging apparatus according to any one of the 1st to 15th aspects, comprising a first semiconductor substrate and a second semiconductor substrate laminated on the first semiconductor substrate, wherein the first semiconductor substrate is located between the photoelectric conversion unit and the second semiconductor substrate, the first transistor is arranged on the first semiconductor substrate, and the second transistor is arranged on the second semiconductor substrate.

[0044] This allows the first and second transistors to be placed on separate semiconductor substrates, the first and second semiconductor substrates, thus reducing the area of ​​the imaging device. Furthermore, since the first transistor is placed on the first semiconductor substrate between the photoelectric conversion unit and the second semiconductor substrate, the wiring connecting the photoelectric conversion unit and the first transistor can be shortened.

[0045] Furthermore, for example, a camera system according to the 17th aspect of this disclosure comprises an imaging device according to any one of the 1st to 16th aspects.

[0046] As a result, the camera system according to this embodiment, equipped with the above-mentioned imaging device, can widen the dynamic range and suppress variations in the output signal.

[0047] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0048] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0049] Furthermore, in this specification, terms indicating relationships between elements, such as parallel or coincident, terms indicating the shape of elements, such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0050] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." It should be noted that terms such as "upper" and "lower" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0051] Furthermore, in this specification, "planar view" refers to a view of the semiconductor substrate from a direction perpendicular to the main surface (in other words, in the thickness direction of the semiconductor substrate).

[0052] Furthermore, in this specification, "connection" means an electrical connection unless otherwise specified, and refers to a state of being electrically connected at all times. Also, in this specification, the term "node" means an electrical connection point between multiple elements in an electrical circuit, and is a concept that includes wiring and the like that which are responsible for the electrical connection between those multiple elements.

[0053] Furthermore, in this specification, when a transistor is said to be placed on a certain surface of a semiconductor substrate, it means that the gate, source, and drain of the transistor are placed on either side of that surface.

[0054] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not mean the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0055] (Embodiment 1) The imaging device according to Embodiment 1 will now be described.

[0056] [Overall structure] First, the overall configuration of the imaging device according to this embodiment will be described.

[0057] Figure 1 is a diagram showing the configuration of an imaging device according to this embodiment. As shown in Figure 1, the imaging device 100 according to this embodiment comprises a plurality of pixels 10 and peripheral circuits formed on a semiconductor substrate 60. Each pixel 10 includes a photoelectric conversion unit 12 located above the semiconductor substrate 60. In other words, a stacked type imaging device 100 will be described as an example of an imaging device according to this disclosure.

[0058] In the example shown in Figure 1, multiple pixels 10 are arranged in an m x n matrix, where m and n are integers greater than or equal to 2. The multiple pixels 10 are arranged, for example, in two dimensions on the semiconductor substrate 60 to form an imaging region R1. In this embodiment, the photoelectric conversion unit 12 is a photoelectric conversion structure including a photoelectric conversion layer positioned above the semiconductor substrate 60. The imaging region R1 is defined as the area of ​​the semiconductor substrate 60 covered by the photoelectric conversion unit 12. In Figure 1, the photoelectric conversion unit 12 of each pixel 10 is shown spatially separated from each other for ease of explanation, but the photoelectric conversion units 12 of multiple pixels 10 can be arranged above the semiconductor substrate 60 without spacing between them. The photoelectric conversion unit 12 may also be a photodiode formed on the semiconductor substrate 60.

[0059] The number and arrangement of pixels 10 are not limited to the illustrated example. For example, the imaging device 100 may contain only one pixel 10. Also, in this example, the center of each pixel 10 is located on a grid point of a square grid, but the arrangement of pixels 10 does not have to be so. For example, multiple pixels 10 may be arranged such that each center is located on a grid point of a triangular grid, a hexagonal grid, or the like. Furthermore, if the pixels 10 are arranged in one dimension, the imaging device 100 can be used as a line sensor.

[0060] In the example shown in Figure 1, the peripheral circuit includes a vertical scanning circuit 42 and a horizontal signal readout circuit 44. In addition, in the example shown in Figure 1, the peripheral circuit may also include a control circuit 46 and a voltage supply circuit 48. As schematically shown in Figure 1, the peripheral circuit is located in the peripheral region R2 outside the imaging region R1. The peripheral circuit is connected to a plurality of pixels 10 and is a circuit for acquiring signals from each pixel 10. The peripheral circuit may further include a load circuit, a signal processing circuit, an output circuit, and a power supply that supplies a predetermined voltage to each pixel 10. The peripheral circuit is located on the semiconductor substrate 60, but at least a portion of the peripheral circuit may be located on one or more other semiconductor substrates different from the semiconductor substrate 60 on which the pixels 10 are formed. In other words, at least a portion of the peripheral circuit does not have to be located in the peripheral region R2 of the semiconductor substrate 60. In this case, one or more other semiconductor substrates may be stacked on the semiconductor substrate 60. Also, some of the circuits of the pixels 10 may be located on one or more other semiconductor substrates.

[0061] The vertical scanning circuit 42, also called a row scanning circuit, has connections to address signal lines 34 provided for each row of the multiple pixels 10. As will be described later, the signal lines provided for each row of the multiple pixels 10 are not limited to address signal lines 34. Multiple types of signal lines may be connected to the vertical scanning circuit 42 for each row of the multiple pixels 10.

[0062] The horizontal signal readout circuit 44, also called a column scanning circuit, has connections to vertical signal lines 35 provided corresponding to each column of the multiple pixels 10.

[0063] The control circuit 46 receives command data, a clock, etc., from an external source, for example, and controls the entire imaging device 100. The control circuit 46 includes, for example, a timing generator. The control circuit 46 supplies drive signals to the vertical scanning circuit 42, the horizontal signal readout circuit 44, and the voltage supply circuit 48, etc. In Figure 1, the arrows extending from the control circuit 46 schematically represent the flow of output signals from the control circuit 46. The control circuit 46 can be implemented, for example, by a microcontroller or one or more processors. The microcontroller may include one or more processors. The functions of the control circuit 46 may be implemented by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing.

[0064] The voltage supply circuit 48 supplies a predetermined voltage to each pixel 10 via the storage control line 31. The voltage supply circuit 48 is not limited to a specific power supply circuit. The voltage supply circuit 48 may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or it may be a circuit that generates a predetermined voltage. The voltage supply circuit 48 may also be part of the vertical scanning circuit 42 or control circuit 46 described above.

[0065] [Pixel configuration] Next, the configuration of the pixels 10 of the imaging device 100 according to this embodiment will be described.

[0066] First, the circuit configuration of the pixel 10 according to this embodiment will be described. Figure 2 is a diagram showing the circuit configuration of the pixel 10 according to this embodiment. Each of the multiple pixels 10 has, for example, the circuit configuration shown in Figure 2.

[0067] As described above, the pixel 10 includes a photoelectric conversion unit 12. The photoelectric conversion unit 12 generates positive and negative charges upon incident light. In other words, the photoelectric conversion unit 12 converts light into charge. Positive and negative charges are typically hole-electron pairs. The photoelectric conversion unit 12 includes a pixel electrode 12a, a photoelectric conversion layer 12b, and a counter electrode 12c. The pixel electrode 12a is an example of a first electrode. The counter electrode 12c is an example of a second electrode. The pixel electrode 12a of the photoelectric conversion unit 12 is connected to a charge storage node FD. The counter electrode 12c of the photoelectric conversion unit 12 is also connected to a storage control line 31, and a predetermined storage control voltage VITO is applied to the storage control line 31 by a voltage supply circuit 48 when the imaging device 100 is operating. By applying a predetermined storage control voltage VITO to the storage control line 31, the voltage supply circuit 48 can selectively store one of the positive and negative charges generated by photoelectric conversion as a signal charge in the charge storage node FD. In the following description, unless otherwise specified, the example given is the case in which the positive charge, i.e., a hole, is used as the signal charge from among the positive and negative charges generated by photoelectric conversion.

[0068] Pixel 10 is electrically connected to the photoelectric conversion unit 12 and includes a signal detection circuit that detects a signal based on the signal charge generated by the photoelectric conversion unit 12. In the example shown in Figure 2, the signal detection circuit includes an amplifying transistor 22 and an addressing transistor 24. The amplifying transistor 22 is also called a readout transistor. The addressing transistor 24 is also called a row selection transistor. Pixel 10 also includes a first reset transistor 26, a gain switching transistor 28, a second reset transistor 30, and a capacitive element 21.

[0069] As will be explained in detail later with reference to the drawings, the amplification transistor 22, address transistor 24, first reset transistor 26, gain switching transistor 28, and second reset transistor 30 are, for example, field-effect transistors (FETs) formed on the semiconductor substrate 60 supporting the photoelectric conversion unit 12. In the example shown in Figure 2, N-channel MOSFETs (Metal Oxide Semiconductor FETs) are used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, and gain switching transistor 28. A P-channel MOSFET is used for the second reset transistor 30. Note that which of the two diffusion regions of the FET corresponds to the source and which corresponds to the drain is determined by the polarity of the FET and the potential level at that time. Therefore, which is the source and which is the drain can vary depending on the operating state of the FET. In other words, the source and drain of each transistor described below may be reversed depending on the operating state of the FET.

[0070] As schematically shown in Figure 2, the gate of the amplification transistor 22 is connected to the charge storage node FD, which in turn is connected to the photoelectric conversion unit 12. The signal charge generated by the photoelectric conversion unit 12 is stored as signal charge in the charge storage node FD between the photoelectric conversion unit 12 and the amplification transistor 22. In other words, the charge storage node FD functions as at least part of the charge storage region where signal charge is stored, and the potential of the charge storage node FD corresponds to the amount of signal charge stored in the charge storage region.

[0071] One of the sources and drains of the amplification transistor 22 is connected to a power supply wiring 32 that supplies a power supply voltage Vdd to each pixel 10 when the imaging device 100 is operating. The power supply voltage Vdd is, for example, about 3.3V, but is not limited to this. The amplification transistor 22 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion unit 12. The other of the sources and drains of the amplification transistor 22 is connected to one of the sources and drains of the address transistor 24.

[0072] A vertical signal line 35 is connected to the source and the other drain of the address transistor 24. A load circuit that forms a source follower circuit together with the amplifying transistor 22, and a column signal processing circuit are connected to the vertical signal line 35, for example.

[0073] An address signal line 34 is connected to the gate of the address transistor 24. An address signal line 34 is provided for each row of multiple pixels 10. The address signal line 34 is connected to a vertical scanning circuit 42, which applies a row selection signal SEL to the address signal line 34 to control the on and off states of the address transistor 24. This causes the row to be read to be scanned vertically (i.e., in the column direction) and the row to be read to be selected. By controlling the on and off states of the address transistor 24 via the address signal line 34, the vertical scanning circuit 42 can read the output of the amplification transistor 22 of the selected pixel 10 to the corresponding vertical signal line 35. The arrangement of the address transistor 24 is not limited to the example shown in Figure 2, and may be between one of the source and drain of the amplification transistor 22 and the power supply wiring 32.

[0074] The signal voltage from the pixel 10, output to the vertical signal line 35 via the address transistor 24, is subjected to noise suppression signal processing and analog-to-digital conversion in a column signal processing circuit, for example, and then input to the horizontal signal readout circuit 44.

[0075] One of the sources and drains of the first reset transistor 26 is connected to the charge storage node FD. The gate of the first reset transistor 26 is connected to a first reset signal line 36, which has a connection to the vertical scanning circuit 42. The first reset signal line 36 is provided for each row of multiple pixels 10, similar to the address signal line 34. The vertical scanning circuit 42 applies a first reset signal RST1 to the gate of the first reset transistor 26 via the first reset signal line 36 to control the on and off states of the first reset transistor 26. When the first reset transistor 26 is turned on, the potential of the charge storage node FD is reset. The first reset transistor 26 is an example of a third transistor.

[0076] In the example shown in Figure 2, the source and the other drain of the first reset transistor 26 are connected to a first reset voltage line 53 that supplies a predetermined first reset voltage VR1 to the pixel 10 when the pixel 10 is reset. That is, in this example, the first reset voltage VR1 that initializes the signal charge generated by the photoelectric conversion unit 12 is supplied to the charge storage node FD via the first reset transistor 26. The first reset voltage VR1 may be a fixed voltage. Note that the source and the other drain of the first reset transistor 26 are not limited to being connected to the first reset voltage line 53, but may also be connected to a feedback line connected to the output of a feedback amplifier that feeds back the output from the pixel 10, for example, as in Patent Document 2.

[0077] One of the source and drain ends, as well as the gate, of the gain switching transistor 28 are connected to the charge storage node FD. The other of the source and drain ends of the gain switching transistor 28 is connected via node N1 to one of the source and drain ends of the second reset transistor 30, as well as to one end of the capacitive element 21. The gain switching transistor 28 is an example of a first transistor.

[0078] As the signal charge accumulated in the charge storage region, which includes at least a portion of the charge storage node FD, increases, the potential of the charge storage node FD reaches the threshold potential Vof, causing the gain switching transistor 28 to turn on. As a result, a portion of the signal charge accumulated in the charge storage node FD flows to node N1 and the capacitive element 21, where it is stored. The threshold potential Vof is a potential that depends on the threshold voltage of the gain switching transistor 28. Here, the threshold voltage refers to the gate-source voltage of the transistor when drain current begins to flow through the transistor.

[0079] In the example shown in Figure 2, the gate of the amplification transistor 22 connected to the charge storage node FD, one of the source and drain of the first reset transistor 26, one of the source and drain of the gain switching transistor 28, and the gate of the gain switching transistor 28 are part of the charge storage region that stores the signal charge generated by the photoelectric conversion unit 12. In this specification, the expressions that an element is connected to the charge storage node FD and that an element is connected to the charge storage region may also include the expressions that an element is part of the charge storage node FD and an element is part of the charge storage region, respectively.

[0080] One of the sources and drains of the second reset transistor 30 is connected to node N1. The gate of the second reset transistor 30 is connected to a second reset signal line 37, which has a connection to the vertical scanning circuit 42. The second reset signal line 37 is provided for each row of pixels 10, similar to the address signal line 34. The vertical scanning circuit 42 applies a second reset signal RST2 to the gate of the second reset transistor 30 via the second reset signal line 37 to control the on and off states of the second reset transistor 30. When the second reset transistor 30 is turned on, the potential of node N1 is reset. Also, when the second reset transistor 30 is turned on, the charge accumulated in the capacitive element 21 together with node N1 is reset. The second reset transistor 30 is an example of a second transistor.

[0081] In the example shown in Figure 2, the source and the other drain of the second reset transistor 30 are connected to a second reset voltage line 54, which supplies a predetermined second reset voltage VR2 to the pixel 10 when the pixel 10 is reset. That is, in this example, the second reset voltage VR2, which initializes the signal charge that has flowed out from the charge storage node FD by the gain switching transistor 28, is supplied to node N1 via the second reset transistor 30. The second reset voltage VR2 may be a fixed voltage. Note that the configuration in which the source and the other drain of the second reset transistor 30 are connected to the second reset voltage line 54 is not limited to this configuration; for example, they may be connected to the first reset voltage line 53, and the same voltage may be supplied to the other source and drain of the first reset transistor 26 and the other source and drain of the second reset transistor 30.

[0082] One end of the capacitive element 21 is connected via node N1 to the other source and drain of the gain switching transistor 28, and to one source and drain of the second reset transistor 30. The other end of the capacitive element 21 is connected to a power supply wiring 38 that supplies a power supply voltage Vss to each pixel 10 when the imaging device 100 is operating. The power supply voltage Vss is, for example, the ground voltage. The power supply voltage Vss is supplied to the other end of the capacitive element 21 via the power supply wiring 38. One end of the capacitive element 21 is an example of a first terminal of the capacitive element 21, and the other end of the capacitive element 21 is an example of a second terminal of the capacitive element 21. The power supply voltage Vss is also an example of a first voltage.

[0083] The capacitive element 21 is, for example, a MOM (Metal-Oxide-Metal) capacitor, a MIM (Metal-Insulator-Metal) capacitor, a MOS (Metal Oxide Semiconductor) capacitor, or a trench capacitor.

[0084] Next, the device structure of the pixel 10 according to this embodiment will be described. Figure 3 is a plan view showing an example of the layout within the pixel 10 according to this embodiment. Figure 4 is a schematic cross-sectional view of the device structure of the pixel 10 according to this embodiment. Figure 4 is a cross-sectional view when the pixel 10 is cut along the line IV-IV in Figure 3 and unfolded in the direction of the arrow. Figure 3 schematically shows the arrangement of transistors and impurity regions on the main surface 81 of the semiconductor substrate 60 when the pixel 10 shown in Figure 4 is viewed from a direction perpendicular to the semiconductor substrate 60, and other details are omitted from the illustration. Also, in Figures 3 and 4, some of the electrical connections of transistors and impurity regions formed on the semiconductor substrate 60 are schematically shown. Note that in Figure 3, the gates of the transistors are shaded for clarity. Also, in Figure 4, the photoelectric conversion unit 12 is shown in a simplified manner, and the detailed structure is omitted from the illustration. This is also the case in the schematic cross-sectional view described later.

[0085] As shown in Figure 4, the pixel 10 schematically includes a semiconductor substrate 60 and a photoelectric conversion unit 12 positioned above the semiconductor substrate 60. An interlayer insulating layer (not shown) is placed between the semiconductor substrate 60 and the photoelectric conversion unit 12, and various wirings and capacitive elements 21 are formed within the interlayer insulating layer. The semiconductor substrate 60 is formed continuously, for example, over at least the entire imaging region R1 and is shared by multiple pixels 10.

[0086] The semiconductor substrate 60 has a main surface 81 on which various transistors of the pixel 10 are arranged. Specifically, an amplification transistor 22, an address transistor 24, a first reset transistor 26, a gain switching transistor 28, and a second reset transistor 30 are arranged on the main surface 81. The main surface 81 is a surface perpendicular to the thickness direction of the semiconductor substrate 60. In the example shown in Figure 4, the photoelectric conversion unit 12 is arranged on the main surface 81 side of the semiconductor substrate 60.

[0087] The semiconductor substrate 60 includes a support substrate 61p and a p-type semiconductor layer 62p and an n-type semiconductor layer 63n on which transistors are formed. Here, a p-type silicon (Si) substrate is given as an example of the support substrate 61p. The p-type semiconductor layer 62p is a p-type well region in the semiconductor substrate 60. The n-type semiconductor layer 63n is an n-type well region in the semiconductor substrate 60. The p-type semiconductor layer 62p is provided on the support substrate 61p, and the n-type semiconductor layer 63n is provided in a region on the support substrate 61p different from the p-type semiconductor layer 62p. The p-type semiconductor layer 62p and the n-type semiconductor layer 63n are semiconductor layers on which the main surface 81 of the semiconductor layers included in the semiconductor substrate 60 is located.

[0088] The p-type semiconductor layer 62p is a semiconductor layer containing p-type impurities, which are of the second conductivity type. The n-type semiconductor layer 63n is a semiconductor layer containing n-type impurities, which are of the first conductivity type. Each of the p-type semiconductor layer 62p and the n-type semiconductor layer 63n is formed, for example, by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. In this embodiment, the p-type impurity is, for example, boron, and the n-type impurity is, for example, arsenic or phosphorus.

[0089] As shown in Figures 3 and 4, the semiconductor substrate 60 includes n-type impurity regions 65n, 66n, 67n, 73n, 75n, 76n, and 77n, p-type impurity regions 68p, 71p, and 72p, and an element isolation region 69. The n-type impurity regions 65n, 66n, 67n, 73n, 75n, 76n, and 77n are impurity regions where n-type impurities have diffused. The p-type impurity regions 68p, 71p, and 72p are impurity regions where p-type impurities have diffused.

[0090] The n-type impurity regions 65n, 66n, 67n, 75n, 76n, and 77n are located in the p-type semiconductor layer 62p. The n-type impurity regions 65n, 66n, 67n, 75n, 76n, and 77n are formed by impurities being injected into the p-type semiconductor layer 62p from the main surface 81 side. The n-type impurity region 73n is located in the n-type semiconductor layer 63n. The n-type impurity region 73n is formed by impurities being injected into the n-type semiconductor layer 63n from the main surface 81 side.

[0091] The p-type impurity region 68p is located within the p-type semiconductor layer 62p. The p-type impurity region 68p is formed by impurities being injected into the p-type semiconductor layer 62p from the main surface 81 side. The p-type impurity regions 71p and 72p are located within the n-type semiconductor layer 63n. The p-type impurity regions 71p and 72p are formed by impurities being injected into the n-type semiconductor layer 63n from the main surface 81 side.

[0092] As shown in Figures 3 and 4, an amplification transistor 22, an address transistor 24, a first reset transistor 26, a gain switching transistor 28, and a second reset transistor 30 are formed on the semiconductor substrate 60. Each of the amplification transistor 22, the address transistor 24, the first reset transistor 26, and the overflow transistor 28 is an N-channel MOSFET formed on the p-type semiconductor layer 62p. The second reset transistor 30 is a P-channel MOSFET formed on the n-type semiconductor layer 63n.

[0093] The amplifying transistor 22 includes an n-type impurity region 75n as one of the source and drain, an n-type impurity region 76n as the other of the source and drain, a gate 22e, a gate insulating film (not shown), and a channel region (not shown).

[0094] The address transistor 24 includes an n-type impurity region 76n as one source and drain, an n-type impurity region 77n as the other source and drain, a gate 24e, a channel region (not shown), and a gate insulating film (not shown). In the example shown in Figure 3, the address transistor 24 is electrically connected to the amplifier transistor 22 by sharing the n-type impurity region 76n with the amplifier transistor 22.

[0095] The first reset transistor 26 includes an n-type impurity region 65n as one of the source and drain, an n-type impurity region 66n as the other of the source and drain, a gate 26e, a channel region 26c, and a gate insulating film 26i.

[0096] The gain switching transistor 28 includes an n-type impurity region 65n as one of the source and drain, an n-type impurity region 67n as the other of the source and drain, a gate 28e, a channel region 28c, and a gate insulating film 28i. In the example shown in Figures 3 and 4, the gain switching transistor 28 is electrically connected to the first reset transistor 26 by sharing the n-type impurity region 65n with the first reset transistor 26.

[0097] The second reset transistor 30 includes a p-type impurity region 71p as one of the source and drain, a p-type impurity region 72p as the other of the source and drain, a gate 30e, a channel region 30c, and a gate insulating film 30i.

[0098] As shown in Figure 3, in a plan view, the area of ​​the gate 28e of the gain switching transistor 28 is larger than the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30. This reduces the variation in the threshold voltage of the gain switching transistor 28. In the example shown in Figure 3, in a plan view, the area of ​​the gate and the area of ​​the channel region of each transistor included in the pixel 10 are equal. Therefore, in a plan view, the area of ​​the channel region 28c of the gain switching transistor 28 is larger than the area of ​​the channel region 26c of the first reset transistor 26 and the channel region 30c of the second reset transistor 30. Note that in a plan view, the area of ​​the gate and the area of ​​the channel region of at least one of the transistors included in the pixel 10 may be different.

[0099] Furthermore, the gate length L1 of the gain switching transistor 28 is greater than the gate length L2 of the first reset transistor 26 and the gate length L3 of the second reset transistor 30. The gate width W1 of the gain switching transistor 28 is greater than the gate width W2 of the first reset transistor 26 and the gate width W3 of the second reset transistor 30. This reduces variations in the threshold voltage of the gain switching transistor 28.

[0100] Furthermore, as shown in Figure 4, the thickness of the gate insulating film 28i of the gain switching transistor 28 is smaller than the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30. This reduces variations in the threshold voltage of the gain switching transistor 28.

[0101] The concentration of p-type impurities in the channel region 28c of the gain switching transistor 28 is higher than, for example, the concentration of n-type impurities in the channel region 30c of the second reset transistor 30. This suppresses depletion of the channel region 28c when the gain switching transistor 28 is off, thereby reducing the leakage current when the gain switching transistor 28 is off. Similarly, the concentration of p-type impurities in the channel region 26c of the first reset transistor 26 is higher than, for example, the concentration of n-type impurities in the channel region 30c of the second reset transistor 30. This suppresses depletion of the channel region 26c when the first reset transistor 26 is off, thereby reducing the leakage current when the first reset transistor 26 is off. As will be described in detail later, the gain of photoelectric conversion is high when the gain switching transistor 28 is off. Therefore, reducing the leakage current flowing through the charge storage region when the first reset transistor 26 and the gain switching transistor 28 are off is useful from the viewpoint of noise reduction. Leakage current is also called dark current because it is a current that flows even in the dark when no light is irradiated. Note that the relationship between the impurity concentrations in the channel region described above is not limited to the relationship described above.

[0102] Gates 22e, 24e, 26e, 28e, and 30e are gate electrodes formed from, for example, impurity-doped polysilicon. Gates 22e, 24e, and 26e are doped with, for example, n-type impurities. Gates 28e and 30e are doped with, for example, p-type impurities. By doping gate 28e of the gain switching transistor 28 with p-type impurities, the threshold voltage of the gain switching transistor 28 can be increased without increasing the channel dose of the gain switching transistor 28. As a result, the electric field around the n-type impurity region 65n is suppressed, and leakage current can be reduced.

[0103] The gate insulating films of the amplification transistor 22, address transistor 24, first reset transistor 26, gain switching transistor 28, and second reset transistor 30 are insulating films such as silicon oxide films formed on the main surface 81 of the semiconductor substrate 60.

[0104] The element isolation region 69 is arranged, for example, in a plan view, to surround the set of the first reset transistor 26 and the gain switching transistor 28, the set of the second reset transistor 30, the amplification transistor 22 and the address transistor 24, the p-type impurity region 68p, and the n-type impurity region 73n, thereby electrically isolating them from each other. The element isolation region 69 is, for example, an STI (Shallow Trench Isolation) structure. The STI structure is formed on the semiconductor substrate 60 by an STI process. At least a portion of the element isolation region 69 may be an implanted isolation region in which impurities are implanted at a high concentration.

[0105] The p-type impurity region 68p functions as a well contact region of the p-type semiconductor layer 62p. A p-well voltage Vp is applied to the p-type semiconductor layer 62p via the p-type impurity region 68p. This makes it possible to control the potential of the p-type semiconductor layer 62p via the p-type impurity region 68p when the imaging device 100 is in operation. The n-type impurity region 73n functions as a well contact region of the n-type semiconductor layer 63n. An n-well voltage Vn is applied to the n-type semiconductor layer 63n via the n-type impurity region 73n. This makes it possible to control the potential of the n-type semiconductor layer 63n via the n-type impurity region 73n when the imaging device 100 is in operation. Note that the p-type impurity region 68p and the n-type impurity region 73n do not necessarily have to be located in the region where the pixel 10 is formed. For example, at least one of the p-type impurity region 68p and the n-type impurity region 73n may be located in the peripheral region R2 of the semiconductor substrate 60. Furthermore, the potentials of the p-type semiconductor layer 62p and the n-type semiconductor layer 63n may be controlled from sources other than the p-type impurity region 68p and the n-type impurity region 73n, without the formation of the p-type impurity region 68p and the n-type impurity region 73n. For example, the potential of at least one of the p-type semiconductor layer 62p and the n-type semiconductor layer 63n may be controlled via the support substrate 61p or another semiconductor layer disposed between the support substrate 61p and the p-type semiconductor layer 62p and the n-type semiconductor layer 63n.

[0106] The n-well voltage Vn is a higher voltage than the p-well voltage Vp. The n-well voltage Vn is, for example, 7V or less, and may be 5V or less. Alternatively, the n-well voltage Vn may be the power supply voltage Vdd. This allows a portion of the power supply wiring for supplying the n-well voltage Vn to be shared with the power supply wiring for the power supply voltage Vdd, enabling miniaturization of the pixel 10 and lower resistance of the power supply wiring by making the power supply wiring thicker. The p-well voltage Vp is, for example, 0V or more and 1V or less. Alternatively, the p-well voltage Vp may be the power supply voltage Vss. This allows a portion of the power supply wiring for supplying the p-well voltage Vp to be shared with the power supply wiring for the power supply voltage Vss, enabling miniaturization of the pixel 10 and lower resistance of the power supply wiring by making the power supply wiring thicker.

[0107] Furthermore, during exposure of the imaging device 100, the n-well voltage Vn is the voltage between the storage control voltage VITO and the first reset voltage VR1. When the signal charge is a hole, the n-well voltage Vn is higher than the first reset voltage VR1 and lower than the storage control voltage VITO.

[0108] As shown in Figure 4, the photoelectric conversion unit 12 includes a pixel electrode 12a, a counter electrode 12c facing the pixel electrode 12a, and a photoelectric conversion layer 12b located between the pixel electrode 12a and the counter electrode 12c. The pixel electrode 12a, the photoelectric conversion layer 12b, and the counter electrode 12c are stacked in this order from the semiconductor substrate 60 side. The photoelectric conversion layer 12b of the photoelectric conversion unit 12 converts light into signal charges. Specifically, the photoelectric conversion layer 12b is formed from an organic material or an inorganic material such as amorphous silicon, and receives light incident via the counter electrode 12c to generate positive and negative charges through photoelectric conversion. The photoelectric conversion layer 12b is formed continuously, for example, across a plurality of pixels 10. That is, the photoelectric conversion layer 12b is shared by a plurality of pixels 10. The photoelectric conversion layer 12b may also include a layer made of an organic material and a layer made of an inorganic material. Furthermore, the photoelectric conversion layer 12b may be provided separately for each pixel 10.

[0109] The counter electrode 12c is formed from a transparent conductive material such as ITO (Indium Tin Oxide) and is positioned on the light-receiving side of the photoelectric conversion layer 12b. The counter electrode 12c is a film-like electrode and, for example, is formed continuously across multiple pixels 10, similar to the photoelectric conversion layer 12b. In other words, the counter electrode 12c is shared by multiple pixels 10. The counter electrode 12c may also be provided separately for each pixel 10.

[0110] Although not shown in Figure 4, the counter electrode 12c is connected to the accumulation control line 31 described above. When the imaging device 100 is in operation, the potential of the accumulation control line 31 is controlled to make the potential of the counter electrode 12c different from the potential of the pixel electrode 12a, thereby allowing the signal charge generated by photoelectric conversion to be collected by the pixel electrode 12a. For example, the potential of the accumulation control line 31 is controlled so that the potential of the counter electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, when the imaging device 100 is in operation, an accumulation control voltage VITO different from the first reset voltage VR1 is applied to the counter electrode 12c via the accumulation control line 31. The accumulation control voltage VITO is, for example, a positive voltage of about 10V. As a result, among the hole-electron pairs generated in the photoelectric conversion layer 12b, the holes can be collected as signal charges by the pixel electrode 12a. The n-type impurity region 65n is electrically connected to the pixel electrode 12a, and the signal charge collected by the pixel electrode 12a is accumulated in the n-type impurity region 65n. When electrons are used as the signal charge, an accumulation control voltage VITO is applied to the counter electrode 12c such that the potential of the counter electrode 12c is lower than the potential of the pixel electrode 12a.

[0111] The pixel electrode 12a is a film-like electrode formed from a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to impure conductivity. The pixel electrode 12a is electrically isolated from the pixel electrodes 12a of other adjacent pixels 10 by being spatially separated from them.

[0112] [Operation of the imaging device] Next, the operation of the imaging device 100 will be described. Figure 5 is a timing chart illustrating an example of the operation of the imaging device 100 according to this embodiment. In Figure 5, "RST1" indicates the change in the voltage level of the first reset signal RST1 supplied to the gate 26e of the first reset transistor 26. In Figure 5, "RST2" indicates the change in the voltage level of the second reset signal RST2 supplied to the gate 30e of the second reset transistor 30. In Figure 5, high-level voltages are denoted as "High" and low-level voltages are denoted as "Low". Note that the high-level voltages of the first reset signal RST1 and the second reset signal RST2 may be the same magnitude or different magnitudes. Also, the low-level voltages of the first reset signal RST1 and the second reset signal RST2 may be the same magnitude or different magnitudes.

[0113] First, at time t1, the first reset signal RST1 becomes high, and the first reset transistor 26 is turned on. This resets the potential of the charge storage node FD to the first reset voltage VR1. Also at time t1, the second reset signal RST2 becomes low, and the second reset transistor 30 is turned on. This resets the potential of node N1 and the potential of one end of the capacitive element 21 to the second reset voltage VR2.

[0114] In this case, the first reset voltage VR1 may be the same as or lower than the second reset voltage VR2. The p-well voltage Vp applied to the p-type semiconductor layer 62p, where the n-type impurity region 65n (which is one of the source and drain of the first reset transistor 26) is formed, is lower than the n-well voltage Vn applied to the n-type semiconductor layer 63n, where the p-type impurity region 71p (which is one of the source and drain of the second reset transistor 30) is formed, as described above. Therefore, by making the first reset voltage VR1 the same as or lower than the second reset voltage VR2, the potential difference between the n-type impurity region 65n and the p-type semiconductor layer 62p, and the potential difference between the p-type impurity region 71p and the n-type semiconductor layer 63n after the reset can be reduced. As a result, the leakage current between the n-type impurity region 65n and the p-type semiconductor layer 62p, and between the p-type impurity region 71p and the n-type semiconductor layer 63n can be reduced.

[0115] Next, at time t2, the first reset signal RST1 becomes low level, and the first reset transistor 26 is turned off. Also at time t2, the second reset signal RST2 becomes high level, and the second reset transistor 30 is turned off. Hereafter, the period from when the first reset transistor 26 and the second reset transistor 30 are turned on until they are turned off may be referred to as the "reset period". The reset period is the period for resetting the potential of the charge storage node FD. In the example shown in Figure 5, the reset period (referred to as "reset" in the figure) is the period from time t1 to time t2. Also, in the example shown in Figure 5, the potential of node N1 and the potential of one end of the capacitive element 21 are reset during the reset period.

[0116] Next, at time t3, the imaging device 100 starts exposure. In the example shown in Figure 3, the imaging device 100 starts exposure after time t2 when the reset period ends, but exposure may start simultaneously with the end of the reset period. The imaging device 100 may also perform exposure using a rolling shutter method or a global shutter method. Upon the start of exposure, the signal charge generated by the photoelectric conversion unit 12 is accumulated in the charge storage node FD, and the potential of the charge storage node FD increases in accordance with the amount of light incident on the photoelectric conversion unit 12 (exposure amount). The exposure period starting from time t3 is the accumulation period for accumulating signal charge in the charge storage node FD.

[0117] During the storage period, the low-level voltage applied to the gate 26e of the first reset transistor 26 may be a negative voltage (for example, -1V). This suppresses depletion of the channel region 26c of the first reset transistor 26 during the storage period and reduces the leakage current of the first reset transistor 26.

[0118] After the storage period ends, the output signal of the pixel 10, corresponding to the potential of the charge storage node FD, is read out to the vertical signal line 35 by the amplification transistor 22 and the address transistor 24.

[0119] Next, the change in the potential of the charge storage node FD during exposure will be explained with reference to Figure 6. Figure 6 is a schematic diagram showing the relationship between exposure time and the potential of the charge storage node FD. In Figure 6, the vertical axis represents the potential of the charge storage node FD, and the horizontal axis represents the exposure time from the start of exposure. Figure 6 shows the change in the potential of the charge storage node FD when the photoelectric conversion unit 12 is irradiated with light at a constant illuminance.

[0120] As shown in Figure 6, at the start of exposure, the potential of the charge storage node FD is the initial potential Vr reset by the first reset voltage VR1. As the signal charge generated by the photoelectric conversion unit 12 during exposure accumulates in the charge storage node FD, the potential of the charge storage node FD rises.

[0121] When exposure causes the potential of the charge storage node FD to rise and reach the threshold potential Vof, the gate-source voltage of the gain switching transistor 28 becomes the threshold voltage of the gain switching transistor 28, and the gain switching transistor 28 turns on. As a result, the charge storage node FD is electrically connected to node N1 and the capacitive element 21, and works together with node N1 and the capacitive element 21 to store signal charge. In other words, the capacitance for storing signal charge increases, so after the potential of the charge storage node FD reaches the threshold potential Vof, the potential of the charge storage node FD will not rise as easily as before, even if the same amount of signal charge is generated. Therefore, at the point when the potential of the charge storage node FD reaches the threshold potential Vof, the conversion gain by photoelectric conversion at pixel 10 switches to a lower level. This allows the dynamic range to be widened. Furthermore, since signal charge is also stored in the capacitive element 21, the conversion gain can be made even lower, further widening the dynamic range.

[0122] In the following, the exposure mode before the potential of the charge storage node FD reaches the threshold potential Vof (i.e., before the conversion gain due to photoelectric conversion switches) may be referred to as the "high sensitivity mode." The exposure mode after the potential of the charge storage node FD reaches the threshold potential Vof (i.e., after the conversion gain due to photoelectric conversion switches) may be referred to as the "high saturation mode." In the imaging device 100, imaging can be performed in high sensitivity mode when the exposure amount is small, thus improving the signal-to-noise ratio even when imaging in low-light environments. On the other hand, when the exposure amount increases, the device switches from high sensitivity mode to high saturation mode, thereby widening the dynamic range.

[0123] Here, the threshold potential Vof depends on the threshold voltage of the gain switching transistor 28. Therefore, if the threshold voltage of the gain switching transistor 28 varies among multiple pixels 10 and between manufacturing lots of the imaging device 100, the threshold potential Vof will also vary. When the threshold potential Vof varies, the potential at which the gain of photoelectric conversion switches will vary, and the output signal of the pixels 10 will also vary. In the imaging device 100, in a plan view, the area of ​​the gate 28e of the gain switching transistor 28 is larger than the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30. Also, the thickness of the gate insulating film 28i of the gain switching transistor 28 is smaller than the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30. Therefore, variations in the threshold voltage of the gain switching transistor 28 are suppressed, and variations in the output signal of the pixels 10 can be suppressed.

[0124] As shown in Figure 6, after the potential of the charge storage node FD reaches the threshold potential Vof, the potential of the charge storage node FD rises further as exposure continues. At this time, since the charge storage node FD and node N1 are electrically connected, the potential of node N1 also rises to the same potential as the charge storage node FD. When the potential of node N1 reaches a limiting potential Vlim that exceeds the n-well voltage Vn, a forward bias voltage is applied to the pn junction between the p-type impurity region 71p, which is one of the source and drain of the second reset transistor 30, and the n-type semiconductor layer 63n. As a result, signal charge is discharged from the p-type impurity region 71p to the n-type semiconductor layer 63n, and the potentials of node N1 and the charge storage node FD electrically connected to node N1 are clipped at the limiting potential Vlim. Therefore, even when a large amount of light is incident on the photoelectric conversion unit 12, the rise in the potentials of the charge storage node FD and node N1 is suppressed to the limiting potential Vlim. Therefore, damage to transistors in which at least one of the gate, source, and drain is connected to the charge storage node FD and node N1 (for example, damage to the gate insulating film or pn junction in the transistor) can be suppressed.

[0125] Furthermore, since the potential of the charge storage node FD is clipped by the limiting potential Vlim, the lower the first reset voltage VR1 corresponding to the initial potential Vr of the charge storage node FD, the wider the dynamic range can be. In other words, the larger the difference between the n-well voltage Vn and the first reset voltage VR1, the wider the dynamic range can be. In the imaging device 100, the n-type impurity region 65n, which is one of the source and drain of the gain switching transistor 28 connected to the charge storage node FD, is formed in the p-type semiconductor layer 62p. Therefore, since a p-well voltage Vp, which is lower than the n-well voltage Vn, is applied to the p-type semiconductor layer 62p, even if the first reset voltage VR1 applied to the n-type impurity region 65n during the reset period is lower, the potential difference between the p-type semiconductor layer 62p and the n-type impurity region 65n can be reduced. As a result, the leakage current between the n-type impurity region 65n and the p-type semiconductor layer 62p can be reduced.

[0126] In the above example, the signal charge is described as a hole, but the signal charge may also be an electron. In this case, the potential clipping effect described above can be obtained by swapping the p-type and n-type configurations of each component in the semiconductor substrate 60. In this case, the first conductivity type is p-type and the second conductivity type is n-type. For example, in the semiconductor substrate 60, the n-type semiconductor layer 63n to which the n-well voltage Vn is applied via the n-type impurity region 73n is replaced with a p-type semiconductor layer to which the p-well voltage Vp is applied via the p-type impurity region, and the p-type impurity regions 71p and 72p are replaced with n-type impurity regions. In this case, P-channel MOSFETs are used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, and gain switching transistor 28, and an N-channel MOSFET is used for the second reset transistor 30. Also, when the signal charge is an electron, the p-well voltage Vp is lower than the first reset voltage VR1 and higher than the storage control voltage VITO.

[0127] [Differentiation] Next, a modified example of Embodiment 1 will be described. In the following, the differences from Embodiment 1 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0128] Figure 7 shows the circuit configuration of the pixel according to this modified example. Figure 8 is a schematic cross-sectional view of the device structure of the pixel according to this modified example. In Figure 8, some of the electrical connections of the transistors and impurity regions formed on the semiconductor substrate 60 are schematically shown. Note that the layout of the transistors in the pixel 10A shown in Figure 8 is the same as, for example, the layout of the transistors in the pixel 10 shown in Figure 3.

[0129] The imaging device according to this modified example has a configuration in which the plurality of pixels 10 of the imaging device 100 according to Embodiment 1 are replaced with a plurality of pixels 10A. Furthermore, the imaging device according to this modified example further includes a voltage supply circuit 49.

[0130] As shown in Figures 7 and 8, the pixel 10A in this modified example differs from the pixel 10 in Embodiment 1 mainly in that it includes a capacitive element 21A instead of the capacitive element 21, and the source and drain of the second reset transistor 30 are connected to the voltage supply circuit 49 via a gain switching control line 55.

[0131] One end of the capacitive element 21A is connected to the other source and drain of the gain switching transistor 28, and to one source and drain of the second reset transistor 30. The other end of the capacitive element 21A is connected to the other source and drain of the second reset transistor 30, and to the gain switching control line 55. One end of the capacitive element 21A is an example of a first terminal of the capacitive element 21A, and the other end of the capacitive element 21A is an example of a second terminal of the capacitive element 21A. The capacitive element 21A is, for example, a MOM capacitor, a MIM capacitor, a MOS capacitor, or a trench capacitor.

[0132] The voltage supply circuit 49 supplies a control voltage VF to the gain switching control line 55. The control voltage VF is applied to one end of the capacitive element 21A and node N1 via the gain switching control line 55 when the second reset transistor 30 is turned on during the reset period of the pixel 10A. This resets the potential of one end of the capacitive element 21A and node N1 to the control voltage VF at that time. The magnitude of the control voltage VF applied by the voltage supply circuit 49 is controlled, for example, by the control circuit 46. The voltage supply circuit 49 may be a circuit that converts a voltage supplied from a power source such as a battery to a predetermined voltage, or it may be a circuit that generates a predetermined voltage. The voltage supply circuit 49 may be part of the vertical scanning circuit 42 or the control circuit 46 described above.

[0133] In this modified example, by controlling the control voltage VF, the reset potential of node N1 connected to the other end of the source and drain of the gain switching transistor 28 is controlled, so that the threshold potential Vof at which the gain switching transistor 28 turns on can be changed. Furthermore, by setting the control voltage VF to a height above a predetermined level, a state in which the gain switching transistor 28 does not turn on can also be achieved. The control circuit 46 has, for example, a gain switching ON mode in which the gain of photoelectric conversion is switched when the potential of the charge storage node FD reaches the threshold potential Vof, and a gain switching OFF mode in which the gain of photoelectric conversion is not switched even when the potential of the charge storage node FD reaches a predetermined potential.

[0134] Figure 9 shows the relationship between exposure amount and output signal level in pixel 10A according to this modified example. In Figure 9, the vertical axis represents the signal level output from pixel 10A, and the horizontal axis represents the exposure amount of the photoelectric conversion unit 12 of pixel 10A. The exposure amount of the photoelectric conversion unit 12 can also be said to be the amount of light received by the photoelectric conversion unit 12. Figure 9 also shows the relationship between exposure amount and output signal level when the control voltage VF is changed.

[0135] As shown in Figure 9, changing the control voltage VF changes the slope of the signal level with respect to the exposure amount, that is, the exposure amount at which the conversion gain of photoelectric conversion switches. Specifically, the higher the control voltage VF, the greater the exposure amount at which the conversion gain of photoelectric conversion switches, and as the control voltage VF increases further, the conversion gain of photoelectric conversion stops switching. In other words, when the control voltage VF rises above a certain level, the gain switching OFF mode is realized. In the gain switching ON mode, it can be seen that signal charge can be accumulated even when the exposure amount is high, compared to the gain switching OFF mode. Note that in Figure 9, the reason why the output signal level does not rise above a certain level is because it has reached the upper limit of the signal readout range.

[0136] In the imaging device according to this modified example, changing the control voltage VF is not essential. For example, similar to the pixel 10, the source and drain of the second reset transistor 30 may be connected to the second reset voltage line 54 that supplies the second reset voltage VR2.

[0137] [Another example of a pixel device structure] Next, another example of the device structure of the pixel 10 according to Embodiment 1 described above and the pixel 10A according to a modified example of Embodiment 1 will be described. In the following, the differences between the device structure of the pixel 10 according to Embodiment 1 and the pixel 10A according to a modified example of Embodiment 1 described above, as well as the differences between other examples of device structures, will be explained, and the explanation of common points will be omitted or simplified.

[0138] First, let's describe another example of the pixel device structure. Figure 10 is a schematic cross-sectional view showing another example of the pixel device structure according to Embodiment 1. Figure 11 is a schematic cross-sectional view showing another example of the pixel device structure according to a modified example of Embodiment 1. The circuit configuration of pixel 111 shown in Figure 10 is the same as that of pixel 10 shown in Figure 2. The circuit configuration of pixel 111A shown in Figure 11 is the same as that of pixel 10A shown in Figure 7.

[0139] The pixel 111 shown in Figure 10 differs from the pixel 10 shown in Figure 4 mainly in that the photoelectric conversion unit 12 is located on the side opposite to the main surface 81 of the semiconductor substrate 60. Similarly, the pixel 111A shown in Figure 11 differs from the pixel 10A shown in Figure 8 mainly in that the photoelectric conversion unit 12 is located on the side opposite to the main surface 81 of the semiconductor substrate 60.

[0140] As shown in Figures 10 and 11, in pixels 111 and 111A, light is incident from the side opposite to the main surface 81 of the semiconductor substrate 60. In pixels 111 and 111A, the pixel electrode 12a, the n-type impurity region 65n, and the gate 28e are connected via a through-electrode (not shown) that penetrates the semiconductor substrate 60. In pixels 111 and 111A, the capacitive elements 21 and 21A are located on the side of the semiconductor substrate 60 opposite to the photoelectric conversion section 12.

[0141] In pixels 111 and 111A, the main surface 81 on which the transistors are located is on the opposite side of the semiconductor substrate 60 from the photoelectric conversion section 12. Therefore, when at least a portion of the peripheral circuitry is formed on another semiconductor substrate stacked on the semiconductor substrate 60, it becomes easier to connect the transistors located on the main surface 81 to the peripheral circuitry.

[0142] Next, a second example of the pixel device structure will be described. Figure 12 is a schematic cross-sectional view showing a second example of the pixel device structure according to Embodiment 1. Figure 13 is a schematic cross-sectional view showing a second example of the pixel device structure according to a modified version of Embodiment 1. The circuit configuration of the pixel 112 shown in Figure 12 is the same as that of the pixel 10 shown in Figure 2. The circuit configuration of the pixel 112A shown in Figure 13 is the same as that of the pixel 10A shown in Figure 7.

[0143] Pixel 112, shown in Figure 12, differs from pixel 10, shown in Figure 4, mainly in that it includes semiconductor substrates 60A and 60B instead of semiconductor substrate 60. Similarly, pixel 112A, shown in Figure 13, differs from pixel 10A, shown in Figure 8, mainly in that it includes semiconductor substrates 60A and 60B instead of semiconductor substrate 60. In pixels 112 and 112A, the p-type semiconductor layer 62p and the n-type semiconductor layer 63n are arranged separately on semiconductor substrates 60A and 60B. Semiconductor substrate 60A is an example of a first semiconductor substrate, and semiconductor substrate 60B is an example of a second semiconductor substrate.

[0144] As shown in Figures 12 and 13, in pixels 112 and 112A, the semiconductor substrate 60A is located between the photoelectric conversion unit 12 and the semiconductor substrate 60B. The semiconductor substrates 60A and 60B are stacked on top of each other with an interlayer insulating layer in between. Similarly, the semiconductor substrate 60A and the photoelectric conversion unit 12 are stacked on top of each other with an interlayer insulating layer in between. In pixels 112 and 112A, the capacitive elements 21 and 21A are formed within the interlayer insulating layer between the semiconductor substrates 60A and 60B.

[0145] As shown in Figures 12 and 13, the semiconductor substrate 60A has a main surface 82 on which an amplifying transistor 22 (not shown), an address transistor 24 (not shown), a first reset transistor 26, and a gain switching transistor 28 are arranged. The main surface 82 is a surface perpendicular to the thickness direction of the semiconductor substrate 60A. In pixels 112 and 112A, the photoelectric conversion unit 12 is arranged on the side of the main surface 82 of the semiconductor substrate 60A, and the semiconductor substrate 60B is arranged on the side of the semiconductor substrate 60A opposite to the main surface 82. The semiconductor substrate 60A includes a support substrate 61p and a p-type semiconductor layer 62p. The p-type semiconductor layer 62p is provided on the support substrate 61p. The p-type semiconductor layer 62p is the semiconductor layer on which the main surface 82 is arranged among the semiconductor layers included in the semiconductor substrate 60A.

[0146] The semiconductor substrate 60B has a main surface 83 on which the second reset transistor 30 is located. The main surface 83 is a surface perpendicular to the thickness direction of the semiconductor substrate 60B. In pixels 112 and 112A, the semiconductor substrate 60A and the photoelectric conversion unit 12 are located on the side of the main surface 83 of the semiconductor substrate 60B. The semiconductor substrate 60B includes a support substrate 61n and an n-type semiconductor layer 63n. Here, an n-type silicon (Si) substrate is given as an example of the support substrate 61n. The n-type semiconductor layer 63n is provided on the support substrate 61n. The n-type semiconductor layer 63n is the semiconductor layer on which the main surface 83 is located among the semiconductor layers included in the semiconductor substrate 60B.

[0147] In pixels 112 and 112A, semiconductor substrates 60A and 60B are stacked so that their main surfaces 82 and 83 face in the same direction. The side of semiconductor substrate 60A opposite to semiconductor substrate 60B is the main surface 82, and the side of semiconductor substrate 60B facing semiconductor substrate 60A is the main surface 83.

[0148] In pixels 112 and 112A, the transistors are separated and arranged on semiconductor substrates 60A and 60B, allowing for a smaller pixel size. Furthermore, since the n-type impurity region 65n is located on the main surface 82 of semiconductor substrate 60A on the photoelectric conversion unit 12 side between the photoelectric conversion unit 12 and semiconductor substrate 60B, the wiring connecting the pixel electrode 12a and the n-type impurity region 65n can be shortened. This wiring functions as a charge storage region that accumulates signal charge in high-sensitivity mode, thus reducing the capacitance of the charge storage region in high-sensitivity mode and increasing the gain of photoelectric conversion.

[0149] Next, a third example of the pixel device structure will be described. Figure 14 is a schematic cross-sectional view showing a third example of the pixel device structure according to Embodiment 1. Figure 15 is a schematic cross-sectional view showing a third example of the pixel device structure according to a modified example of Embodiment 1. The circuit configuration of the pixel 113 shown in Figure 14 is the same as that of the pixel 10 shown in Figure 2. The circuit configuration of the pixel 113A shown in Figure 15 is the same as that of the pixel 10A shown in Figure 7.

[0150] Pixel 113 shown in Figure 14 differs from pixel 112 shown in Figure 12 mainly in that the top and bottom of the semiconductor substrate 60A are inverted. Similarly, pixel 113A shown in Figure 15 differs from pixel 112A shown in Figure 13 mainly in that the top and bottom of the semiconductor substrate 60A are inverted.

[0151] As shown in Figures 14 and 15, in pixels 113 and 113A, the semiconductor substrate 60A is located between the photoelectric conversion unit 12 and the semiconductor substrate 60B. The semiconductor substrates 60A and 60B are stacked on top of each other with an interlayer insulating layer in between. In pixels 113 and 113A, the capacitive elements 21 and 21A are formed within the interlayer insulating layer between the semiconductor substrates 60A and 60B. Furthermore, the capacitive elements 21 and 21A are positioned, for example, closer to the semiconductor substrate 60B than to the semiconductor substrate 60A.

[0152] In pixels 113 and 113A, the photoelectric conversion unit 12 is positioned on the side of the semiconductor substrate 60A opposite to the main surface 82, while the semiconductor substrate 60B is positioned on the main surface 82 side of the semiconductor substrate 60A. Furthermore, the semiconductor substrate 60A and the photoelectric conversion unit 12 are positioned on the main surface 83 side of the semiconductor substrate 60B.

[0153] In pixels 113 and 113A, semiconductor substrates 60A and 60B are stacked such that their main surfaces 82 and 83 face each other. The surface of semiconductor substrate 60A facing semiconductor substrate 60B is the main surface 82, and the surface of semiconductor substrate 60B facing semiconductor substrate 60A is the main surface 83.

[0154] In pixels 113 and 113A, the transistors are arranged separately on semiconductor substrates 60A and 60B, allowing for a smaller pixel size (area). Furthermore, since the n-type impurity region 65n is located on semiconductor substrate 60A between the photoelectric conversion unit 12 and semiconductor substrate 60B, the wiring connecting the pixel electrode 12a and the n-type impurity region 65n can be shortened. This wiring functions as a charge storage region that accumulates signal charge in high-sensitivity mode, thus reducing the capacitance of the charge storage region in high-sensitivity mode and increasing the photoelectric conversion gain. Additionally, in pixels 113 and 113A, the main surfaces 82 and 83 on which the transistors are located face each other, facilitating wiring connections between pixels. Moreover, high capacitance is easily achieved when using the wiring between main surfaces 82 and 83 to form capacitive elements 21 and 21A.

[0155] Next, a fourth example of the pixel device structure will be described. Figure 16 is a schematic cross-sectional view showing a fourth example of the pixel device structure according to Embodiment 1. Figure 17 is a schematic cross-sectional view showing a fourth example of the pixel device structure according to a modified example of Embodiment 1. The circuit configuration of the pixel 114 shown in Figure 16 is the same as that of the pixel 10 shown in Figure 2. The circuit configuration of the pixel 114A shown in Figure 17 is the same as that of the pixel 10A shown in Figure 7.

[0156] Pixel 114 shown in Figure 16 differs from pixel 112 shown in Figure 12 mainly in that the positions of semiconductor substrate 60A and semiconductor substrate 60B are swapped. Similarly, pixel 114A shown in Figure 17 differs from pixel 112A shown in Figure 13 mainly in that the positions of semiconductor substrate 60A and semiconductor substrate 60B are swapped.

[0157] As shown in Figures 16 and 17, in pixels 114 and 114A, the semiconductor substrate 60B is located between the photoelectric conversion unit 12 and the semiconductor substrate 60A. The semiconductor substrates 60A and 60B are stacked on top of each other with an interlayer insulating layer in between. The semiconductor substrate 60B and the photoelectric conversion unit 12 are also stacked on top of each other with an interlayer insulating layer in between. In pixels 114 and 114A, the capacitive elements 21 and 21A are formed within the interlayer insulating layer between the semiconductor substrate 60B and the photoelectric conversion unit 12.

[0158] In pixels 114 and 114A, the semiconductor substrate 60B and the photoelectric conversion unit 12 are positioned on the main surface 82 side of the semiconductor substrate 60A. The photoelectric conversion unit 12 is positioned on the main surface 83 side of the semiconductor substrate 60B, and the semiconductor substrate 60A is positioned on the side opposite to the main surface 83 side of the semiconductor substrate 60B.

[0159] In pixels 114 and 114A, semiconductor substrates 60A and 60B are stacked so that their main surfaces 82 and 83 face in the same direction. The side of semiconductor substrate 60A facing semiconductor substrate 60B is the main surface 82, and the side of semiconductor substrate 60B opposite to the side facing semiconductor substrate 60A is the main surface 83.

[0160] In pixels 114 and 114A, the transistors are arranged separately on semiconductor substrates 60A and 60B, allowing for a smaller pixel size. Furthermore, in high-sensitivity mode, the n-type impurity region 65n, which accumulates signal charge, is located in semiconductor substrate 60A, which is further from the photoelectric conversion unit 12 than semiconductor substrate 60B. This suppresses the generation of charge caused by light not absorbed by the photoelectric conversion unit 12 entering the n-type impurity region 65n. As a result, in high-sensitivity mode, noise caused by charge generation unrelated to photoelectric conversion by the photoelectric conversion unit 12 is suppressed.

[0161] Next, a fifth example of the pixel device structure will be described. Figure 18 is a schematic cross-sectional view showing a fifth example of the pixel device structure according to Embodiment 1. Figure 19 is a schematic cross-sectional view showing a fifth example of the pixel device structure according to a modified version of Embodiment 1. The circuit configuration of the pixel 115 shown in Figure 18 is the same as that of the pixel 10 shown in Figure 2. The circuit configuration of the pixel 115A shown in Figure 19 is the same as that of the pixel 10A shown in Figure 7.

[0162] Pixel 115 shown in Figure 18 differs from pixel 114 shown in Figure 16 mainly in that the top and bottom of the semiconductor substrate 60B are inverted. Similarly, pixel 115A shown in Figure 19 differs from pixel 114A shown in Figure 17 mainly in that the top and bottom of the semiconductor substrate 60B are inverted.

[0163] As shown in Figures 18 and 19, in pixels 115 and 115A, the semiconductor substrate 60B is located between the photoelectric conversion unit 12 and the semiconductor substrate 60A. The semiconductor substrates 60A and 60B are stacked on top of each other with an interlayer insulating layer in between. In pixels 115 and 115A, the capacitive elements 21 and 21A are formed within the interlayer insulating layer between the semiconductor substrates 60A and 60B. Furthermore, the capacitive elements 21 and 21A are positioned, for example, closer to the semiconductor substrate 60B than to the semiconductor substrate 60A.

[0164] In pixels 115 and 115A, the semiconductor substrate 60B and the photoelectric conversion unit 12 are positioned on the main surface 82 side of the semiconductor substrate 60A. The photoelectric conversion unit 12 is positioned on the side opposite to the main surface 83 side of the semiconductor substrate 60B, and the semiconductor substrate 60A is positioned on the main surface 83 side of the semiconductor substrate 60B.

[0165] In pixels 115 and 115A, semiconductor substrates 60A and 60B are stacked such that their main surfaces 82 and 83 face each other. The surface of semiconductor substrate 60A facing semiconductor substrate 60B is the main surface 82, and the surface of semiconductor substrate 60B facing semiconductor substrate 60A is the main surface 83.

[0166] In pixels 115 and 115A, the transistors are arranged separately on semiconductor substrates 60A and 60B, allowing for a smaller pixel size. Furthermore, in high-sensitivity mode, the n-type impurity region 65n, which accumulates signal charge, is located in semiconductor substrate 60A, which is further from the photoelectric conversion unit 12 than semiconductor substrate 60B. This suppresses the generation of charge by light not absorbed by the photoelectric conversion unit 12 entering the n-type impurity region 65n. Therefore, in high-sensitivity mode, noise caused by charge generation unrelated to photoelectric conversion by the photoelectric conversion unit 12 is suppressed. Additionally, in pixels 115 and 115A, the main surfaces 82 and 83 on which the transistors are located face each other, facilitating wiring connections between pixels. Moreover, high capacitance is easily achieved when forming capacitive elements 21 and 21A using the wiring between main surfaces 82 and 83.

[0167] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 describes a camera system equipped with an imaging device according to the present disclosure.

[0168] Figure 20 is a block diagram showing an example of the configuration of the camera system 400 according to this embodiment.

[0169] As shown in Figure 20, the camera system 400 according to this embodiment comprises a lens optical system 601, an imaging device 602, a system controller 603, and a camera signal processing circuit 604. The camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0170] The lens optical system 601 focuses light onto the imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, an imaging device according to either Embodiment 1 or a modified version thereof described above is used.

[0171] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0172] The camera signal processing circuit 604 has the function of processing the output signal from the imaging device 602. The camera signal processing circuit 604 receives output data such as differential digital signals from the imaging device 602 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The imaging device 602 and the camera signal processing circuit 604 may be realized as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device that includes the imaging device 602 as part can be made smaller.

[0173] (Other embodiments) The imaging apparatus and camera system relating to this disclosure have been described above based on embodiments, but this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to the embodiments that a person skilled in the art could conceive, as well as other forms constructed by combining some of the components of the embodiments, are also included in the scope of this disclosure.

[0174] For example, in the above embodiment, the potential of the charge storage node FD was reset by the first reset transistor 26, but this is not limited to this. For example, the potential of the charge storage node FD may be reset via the photoelectric conversion unit 12 by a voltage applied to the counter electrode 12c. In this case, the imaging device does not need to be equipped with the first reset transistor 26.

[0175] Furthermore, in the above embodiment, for example, N-channel MOSFETs were used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, and gain switching transistor 28, and a P-channel MOSFET was used for the second reset transistor 30, but this is not limited to this. N-channel MOSFETs or P-channel MOSFETs may be used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, gain switching transistor 28, and second reset transistor 30. For example, N-channel MOSFETs may be used for each of the amplification transistor 22, address transistor 24, first reset transistor 26, gain switching transistor 28, and second reset transistor 30.

[0176] Furthermore, for example, in the above embodiment, each pixel is equipped with a capacitive element 21 or 21A, but this is not limited to this. Each pixel does not need to be equipped with capacitive elements 21 and 21A.

[0177] Furthermore, in the above embodiment, for example, in a plan view, the area of ​​the gate 28e of the gain switching transistor 28 was larger than the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30, respectively. However, this is not limited to this, and any area relationship is possible. For example, in a plan view, the area of ​​the gate 28e of the gain switching transistor 28 may be the same as the area of ​​the gate 26e of the first reset transistor 26 and the gate 30e of the second reset transistor 30, respectively.

[0178] Furthermore, in the above embodiment, for example, the thickness of the gate insulating film 28i of the gain switching transistor 28 was smaller than the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30, respectively. However, this is not limited to this, and any thickness relationship is possible. For example, the thickness of the gate insulating film 28i of the gain switching transistor 28 may be the same as the thickness of the gate insulating film 26i of the first reset transistor 26 and the gate insulating film 30i of the second reset transistor 30.

[0179] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. [Industrial applicability]

[0180] The imaging device relating to this disclosure is useful for, for example, image sensors and digital cameras. The imaging device relating to this disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like. [Explanation of Symbols]

[0181] 10, 10A, 111, 111A, 112, 112A, 113, 113A, 114, 114A, 115, 115A pixels 12 Photoelectric conversion unit 12a Pixel electrode 12b Photoelectric conversion layer 12c counter electrode 21, 21A Capacitive element 22 Amplifying Transistors 22e, 24e, 26e, 28e, 30e gates 24 Address Transistors 26. First Reset Transistor 26c, 28c, 30c channel regions 26i, 28i, 30i gate insulator 28 Gain switching transistors 30. Second reset transistor 31. Accumulation control line 32, 38 Power wiring 34 Address signal line 35 Vertical signal lines 36. First reset signal line 37. Second reset signal line 42 Vertical scanning circuit 44 Horizontal signal readout circuit 46 Control circuits 48, 49 Voltage supply circuit 53 First Reset Voltage Line 54 Second reset voltage line 55 Gain switching control line 60, 60A, 60B Semiconductor Substrates 61n, 61p support board 62p p-type semiconductor layer 63n n-type semiconductor layer 65n, 66n, 67n, 73n, 75n, 76n, 77n n-type impurity region 68p, 71p, 72p p-type impurity region 69 Element Isolation Region 100, 602 Imaging device 400 Camera System 601 Lens Optics 603 System Controller 604 Camera signal processing circuit FD charge storage node N1 node

Claims

1. A photoelectric conversion unit that converts light into signal charge, A charge storage region connected to the photoelectric conversion unit for accumulating the signal charge, A first transistor in which one of the source and drain and the gate are connected to the charge storage region, A second transistor, in which one of its source and drain is connected to the other of the source and drain of the first transistor, Equipped with, (i) In a plan view, the gate area of ​​the first transistor is larger than the gate area of ​​the second transistor, and (ii) the thickness of the gate insulating film of the first transistor is smaller than the thickness of the gate insulating film of the second transistor, at least one of these conditions is met. Imaging device.

2. The gate width of the first transistor is greater than the gate width of the second transistor. The imaging apparatus according to claim 1.

3. The gate length of the first transistor is greater than the gate length of the second transistor. The imaging apparatus according to claim 1.

4. In a plan view, the area of ​​the channel region of the first transistor is larger than the area of ​​the channel region of the second transistor. The imaging apparatus according to claim 1.

5. The present invention further comprises a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to the other of the source and drain of the first transistor, and a first voltage is applied to the second terminal. The imaging apparatus according to claim 1.

6. The present invention further comprises a capacitive element having a first terminal and a second terminal, wherein the first terminal is connected to one of the source and drain of the second transistor, and the second terminal is connected to the other of the source and drain of the second transistor. The imaging apparatus according to claim 1.

7. The first transistor includes an impurity region of a first conductivity type as either the source or the drain. The second transistor includes an impurity region of a second conductivity type different from the first conductivity type as either the source or the drain. The imaging apparatus according to claim 1.

8. The concentration of the second conductivity type impurity in the channel region of the first transistor is higher than the concentration of the first conductivity type impurity in the channel region of the second transistor. The imaging apparatus according to claim 7.

9. The first conductivity type is n-type, and the second conductivity type is p-type. The imaging apparatus according to claim 7.

10. The third transistor further comprises the impurity region of the first conductivity type as one of the source and drain, and one of the source and drain is connected to the charge storage region. The voltage applied to the other of the source and drain of the third transistor is smaller than the voltage applied to the other of the source and drain of the second transistor. The imaging device according to claim 9.

11. During the storage period in which the signal charge is stored in the charge storage region, the voltage applied to the gate of the third transistor is a negative voltage. The imaging apparatus according to claim 10.

12. The concentration of the second conductivity type impurity in the channel region of the third transistor is higher than the concentration of the first conductivity type impurity in the channel region of the second transistor. The imaging apparatus according to claim 10.

13. The gate width of the first transistor is greater than the gate width of the third transistor. The imaging apparatus according to claim 10.

14. The gate length of the first transistor is greater than the gate length of the third transistor. The imaging apparatus according to claim 10.

15. The photoelectric conversion unit includes a first electrode connected to the charge storage region, a second electrode facing the first electrode, and a photoelectric conversion layer located between the first electrode and the second electrode. The second transistor is located within the well region of the first conductivity type, The voltage applied to the well region is the voltage between the voltage applied to the second electrode and the voltage applied to the other of the source and drain of the third transistor. The imaging apparatus according to claim 10.

16. First semiconductor substrate and The invention comprises a second semiconductor substrate laminated on the first semiconductor substrate, The first semiconductor substrate is located between the photoelectric conversion unit and the second semiconductor substrate. The first transistor is arranged on the first semiconductor substrate. The second transistor is located on the second semiconductor substrate. The imaging apparatus according to claim 7.

17. The imaging device comprises the imaging device described in any one of claims 1 to 16. Camera system.

Images