Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same. [Solution] The first semiconductor layer has a first region located between adjacent field plate electrodes in a first direction, a second region located between adjacent field plate electrodes in a second direction perpendicular to the first direction, and a third region located between adjacent field plate electrodes across the intersection of a gate electrode extending in the first direction and a gate electrode extending in the second direction. The concentration of first conductivity type impurities in the first region and the second region is higher than the concentration of first conductivity type impurities in the third region.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] There is known a power semiconductor device in which a plurality of field plate electrodes are arranged in a square lattice in a dot shape in a plan view.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

Means for Solving the Problems

[0005] According to the embodiment, the semiconductor device comprises a first electrode, a second electrode, a semiconductor portion provided between the first electrode and the second electrode, a plurality of field plate electrodes arranged in a first direction and a second direction orthogonal to the first direction within the semiconductor portion, and a gate electrode located between the plurality of field plate electrodes and extending in the first and second directions, wherein the semiconductor portion comprises a first semiconductor layer of a first conductivity type provided on the first electrode, a second semiconductor layer of a second conductivity type provided on the first semiconductor layer, and a gate electrode provided on the second semiconductor layer, in contact with the second electrode and extending further than the first semiconductor layer The semiconductor has a third semiconductor layer of a first conductivity type with a high concentration of first conductivity type impurities, the first semiconductor layer having a first region located between adjacent field plate electrodes in the first direction, a second region located between adjacent field plate electrodes in the second direction, and a third region located between adjacent field plate electrodes across the intersection of a gate electrode extending in the first direction and a gate electrode extending in the second direction, wherein the concentration of first conductivity type impurities in the first region and the second region is higher than the concentration of first conductivity type impurities in the third region. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic plan view of a semiconductor device according to an embodiment. [Figure 2] Cross-sectional view AA in Figure 1. [Figure 3] Cross-sectional view of BB in Figure 1. [Figure 4] Cross-sectional view of CC in Figure 1. [Figure 5] (a) and (b) are schematic plan views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] (a) and (b) are schematic plan views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. Note that the same components are denoted by the same reference numerals in each drawing.

[0008] Figure 1 is a schematic plan view showing the arrangement of the main components in the semiconductor device 1 according to this embodiment. Figure 2 is a cross-sectional view of AA in Figure 1. Figure 3 is a cross-sectional view of BB in Figure 1. Figure 4 is a cross-sectional view of CC in Figure 1.

[0009] In each drawing, the direction along the X-axis is designated as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The first direction X, the second direction Y, and the third direction Z are orthogonal to each other. For example, the direction of the arrow on the Z-axis is relatively upward.

[0010] As shown in Figures 2 to 4, the semiconductor device 1 according to this embodiment comprises a first electrode 21, a second electrode 22, and a semiconductor portion 10. The first electrode 21 and the second electrode 22 are located apart in the third direction Z.

[0011] The semiconductor portion 10 is located between the first electrode 21 and the second electrode 22 in the third direction Z. The semiconductor portion 10 has a first surface 10A and a second surface 10B. The first surface 10A faces the first electrode 21 in the third direction Z. The second surface 10B is located on the opposite side of the first surface 10A in the third direction Z.

[0012] For example, silicon can be used as the material for the semiconductor part 10. Alternatively, for example, silicon carbide, gallium nitride, etc., may be used as the material for the semiconductor part 10. In this embodiment, the semiconductor part 10 is described as having a first conductivity type of n type and a second conductivity type of p type, but the first conductivity type may be p type and the second conductivity type may be n type.

[0013] The semiconductor section 10 includes an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 provided on the first semiconductor layer 11, and an n-type third semiconductor layer 13 provided on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than that of the first semiconductor layer 11. The semiconductor section 10 also includes a fourth semiconductor layer 14 provided between the first electrode 21 and the first semiconductor layer 11.

[0014] The semiconductor device 1 according to the embodiment has, for example, a vertical MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. In the MOSFET, the first electrode 21 is the drain electrode, the second electrode 22 is the source electrode, the first semiconductor layer 11 is the drift layer, the second semiconductor layer 12 is the base layer, the third semiconductor layer 13 is the source layer, and the fourth semiconductor layer 14 functions as an n-type drain layer with a higher n-type impurity concentration than the first semiconductor layer 11.

[0015] Alternatively, the semiconductor device according to the embodiment may have a vertical IGBT (Insulated Gate Bipolar Transistor) structure. In the IGBT, the first electrode 21 functions as a collector electrode, the second electrode 22 as an emitter electrode, the first semiconductor layer 11 as a drift layer, the second semiconductor layer 12 as a base layer, the third semiconductor layer 13 as an emitter layer, and the fourth semiconductor layer 14 as a p-type collector layer. In the IGBT, an n-type buffer layer with a higher n-type impurity concentration than the first semiconductor layer 11 may be provided between the fourth semiconductor layer 14 (collector layer) and the first semiconductor layer 11 (drift layer).

[0016] The first electrode 21 is in contact with the first surface 10A of the semiconductor portion 10. In this embodiment, the first electrode 21 is in contact with the fourth semiconductor layer 14 and is electrically connected to the fourth semiconductor layer 14.

[0017] The second electrode 22 is provided on the second surface 10B of the semiconductor portion 10 via an insulating layer 53 to be described later. The second electrode 22 has a contact portion 22A that penetrates the insulating layer 53 and reaches the second semiconductor layer 12. The third semiconductor layer 13 is in contact with the side surface of the contact portion 22A and is electrically connected to the second electrode 22.

[0018] The semiconductor device 1 according to the embodiment further includes a gate electrode 30 and a gate insulating film 51. The gate electrode 30 extends downward from the second surface 10B of the semiconductor portion 10 and is located within the semiconductor portion 10. The lower end of the gate electrode 30 is located within the first semiconductor layer 11 below the pn junction between the second semiconductor layer 12 and the first semiconductor layer 11. As the material of the gate electrode 30, for example, polycrystalline silicon having conductivity can be used.

[0019] The gate insulating film 51 is provided between the gate electrode 30 and the semiconductor portion 10. The side surface of the gate electrode 30 faces the second semiconductor layer 12 via the gate insulating film 51.

[0020] The semiconductor device 1 according to the embodiment further includes a field plate electrode 40 and a field plate insulating film 52.

[0021] The field plate electrode 40 extends downward from the second surface 10B of the semiconductor portion 10 and is located within the semiconductor portion 10. In the semiconductor portion 10, a plurality of columnar field plate electrodes 40 are arranged in the first direction X and the second direction Y as shown in FIG. 1. In a plan view, the plurality of field plate electrodes 40 are arranged in a square lattice in the first direction X and the second direction Y. The shape of the field plate electrode 40 in a plan view is, for example, circular.

[0022] As shown in Figure 2, the field plate electrode 40 does not reach the fourth semiconductor layer 14. The lower end of the field plate electrode 40 is located within the first semiconductor layer 11. The shortest distance in the third direction Z between the lower end of the field plate electrode 40 and the first electrode 21 is shorter than the shortest distance in the third direction Z between the lower end of the gate electrode 30 and the first electrode 21. For example, conductive polycrystalline silicon can be used as the material for the field plate electrode 40.

[0023] The field plate insulating film 52 is provided between the field plate electrode 40 and the semiconductor portion 10, and between the field plate electrode 40 and the contact portion 22A of the second electrode 22.

[0024] As shown in Figure 1, in a plan view, the gate electrode 30 is located between a plurality of field plate electrodes 40 and extends in a first direction X and a second direction Y. Figure 4 is a cross-sectional view of the portion including the intersection 30A of the gate electrode 30 extending in the first direction X and the gate electrode 30 extending in the second direction Y, and is a CC cross-sectional view along the directions inclined in the first direction X and the second direction Y. The contact portion 22A of the second electrode 22 is located between the field plate electrode 40 and the gate electrode 30.

[0025] The semiconductor device 1 according to this embodiment further comprises an insulating layer 53. The insulating layer 53 is provided between the second surface 10B of the semiconductor portion 10 and the second electrode 22, between the upper surface of the gate electrode 30 and the second electrode 22, and between the field plate electrode 40 and the second electrode 22.

[0026] As shown in Figures 1 and 2, the first semiconductor layer 11 has a first region 11A located between adjacent field plate electrodes 40 in a first direction X. As shown in Figures 1 and 3, the first semiconductor layer 11 has a second region 11B located between adjacent field plate electrodes 40 in the second direction Y. As shown in Figures 1 and 4, the first semiconductor layer 11 has a third region 11C located between adjacent field plate electrodes 40 with the intersection 30A of the gate electrode 30 in between. In Figure 1, the outer edge of the third region 11C in a plan view is virtually shown by a dashed line.

[0027] As shown in Figure 2, the shortest distance between adjacent field plate electrodes 40 in the first direction X is defined as the first distance d1. As shown in Figure 3, the shortest distance between adjacent field plate electrodes 40 in the second direction Y is defined as the second distance d2. As shown in Figure 4, the shortest distance between adjacent field plate electrodes 40 across the intersection 30A of the gate electrode 30 is defined as the third distance d3. The third distance d3 is greater than the first distance d1 and greater than the second distance d2. The first distance d1 and the second distance d2 are approximately the same.

[0028] The n-type impurity concentrations in the first region 11A and the second region 11B are higher than the n-type impurity concentrations in the third region 11C. For example, the n-type impurity concentrations in the first region 11A and the second region 11B are between 1.2 and 1.4 times the n-type impurity concentration in the third region 11C.

[0029] When a first potential (e.g., a positive potential) is applied to the first electrode 21, a second potential lower than the first potential (e.g., a ground potential) is applied to the second electrode 22, and a gate voltage above a threshold is applied to the gate electrode 30, an n-type channel is formed in the region of the second semiconductor layer 12 facing the side surface of the gate electrode 30. Current flows between the first electrode 21 and the second electrode 22 through the fourth semiconductor layer 14, the first semiconductor layer 11, the channel, and the third semiconductor layer 13, and the semiconductor device 1 is turned on.

[0030] In the off state of the semiconductor device 1, when the application of a voltage above a threshold to the gate electrode 30 is stopped, a depletion layer expands from the pn junction between the second semiconductor layer 12 and the first semiconductor layer 11, and from the boundary between the field plate insulating film 52 and the first semiconductor layer 11, thereby maintaining the breakdown voltage of the semiconductor device 1.

[0031] The field plate electrode 40 is electrically connected, for example, to the second electrode 22. Alternatively, the field plate electrode 40 may be electrically connected to the gate electrode 30. Such a field plate electrode 40, in the off state, smooths the electric field distribution of the first semiconductor layer 11 (drift layer) and improves the breakdown voltage of the semiconductor device 1.

[0032] Here, as a comparative example, let's consider the case where the n-type impurity concentration in the first semiconductor layer 11 (drift layer) is the same in all regions. In this case, even if the n-type impurity concentration of the first semiconductor layer 11 is reduced, the third region 11C, where the third distance d3 between the field plate electrodes 40 is large, is not completely depleted, and the breakdown voltage is determined by the product of the n-type impurity concentration in the first region 11A and the first distance d1, and / or the product of the n-type impurity concentration in the second region 11B and the second distance d2.

[0033] According to this embodiment, the n-type impurity concentration in the first region 11A and the n-type impurity concentration in the second region 11B, which are regions where the distance between adjacent field plate electrodes 40 is shorter than that in the third region 11C, is made higher than the n-type impurity concentration in the third region 11C. The n-type impurity concentration in the third region 11C, which are regions where the distance between adjacent field plate electrodes 40 is greater than that in the first region 11A and the second region 11B, is made lower than the n-type impurity concentration in the first region 11A and the n-type impurity concentration in the second region 11B. By changing the n-type impurity concentration in the first semiconductor layer 11 according to the distance between adjacent field plate electrodes 40 in this way, the timing of complete depletion in the first region 11A, the second region 11B, and the third region 11C in the off state can be synchronized. This makes it possible to reduce the on-resistance while maintaining the breakdown voltage.

[0034] The first semiconductor layer 11 further has a fourth region 11D located between the lower end of the field plate electrode 40 and the first electrode 21. The fourth region 11D is located between the lower end of the field plate electrode 40 and the fourth semiconductor layer 14.

[0035] The n-type impurity concentration in the fourth region 11D is higher than that in the third region 11C. In this case, the on-resistance can be reduced.

[0036] Alternatively, the n-type impurity concentration in the fourth region 11D is lower than the n-type impurity concentrations in the first region 11A and the second region 11B. In this case, the electric field concentration at the lower end of the field plate electrode 40 can be mitigated, and the breakdown voltage can be increased.

[0037] Next, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to Figures 5(a) to 8(b).

[0038] The manufacturing method for the semiconductor device according to this embodiment includes the step of forming a first concentration region 101 and a second concentration region 102 in an n-type first semiconductor layer 11. The n-type impurity concentration in the second concentration region 102 is higher than the n-type impurity concentration in the first concentration region 101. In Figures 5(a) to 8(b), the second concentration region 102 is represented by dot hatching. The aforementioned first region 11A and second region 11B are located in the second concentration region 102. The aforementioned third region 11C is located in the first concentration region 101.

[0039] For example, after forming a first semiconductor layer 11 of a predetermined thickness in which the entire region is a first concentration region 101, n-type impurities can be implanted into the first semiconductor layer 11 by an ion implantation method using a resist mask to form a second concentration region 102.

[0040] Alternatively, a first semiconductor layer 11 of a predetermined thickness having a first concentration region 101 and a second concentration region 102 can be formed by repeatedly performing the following steps multiple times: forming a semiconductor layer in which the entire region is a first concentration region 101; implanting n-type impurities into the semiconductor layer by an ion implantation method using a resist mask to form a second concentration region 102; forming a new semiconductor layer on the semiconductor layer after ion implantation; and implanting n-type impurities into the newly formed semiconductor layer by an ion implantation method using a resist mask to form a second concentration region 102.

[0041] In the example shown in Figure 5(a), a second concentration region 102 is formed extending in the first direction X and the second direction Y. After forming the second concentration region 102, a hole h is formed at the intersection 102A of the second concentration region 102 extending in the first direction X and the second concentration region 102 extending in the second direction Y, as shown in Figure 5(b).

[0042] Figure 6(a) is a cross-sectional view of DD in Figure 5(b). Figure 6(b) is a cross-sectional view of EE in Figure 5(b). In regions where the distance between adjacent holes h is relatively short, a second concentration region 102 is formed as shown in Figure 6(a), and in regions where the distance between adjacent holes h is relatively large, a first concentration region 101 is formed as shown in Figure 6(b). When the ion implantation energy is not high, the impurity concentration below the bottom of the hole h may be lower than that of the second concentration region 102.

[0043] After forming the hole h, the field plate electrode 40 is embedded in the hole h via the field plate insulating film 52. In the first direction X, the region where the field plate electrode 40 is adjacent is the second concentration region 102, which is the first region 11A described above. In the second direction Y, the region where the field plate electrode 40 is adjacent is the second concentration region 102, which is the second region 11B described above. The region where the distance between the field plate electrodes 40 is greater than that between the first region 11A and the second region 11B is the first concentration region 101, which is the third region 11C described above.

[0044] Furthermore, in the examples shown in Figures 5(a) to 6(b), a second concentration region 102 is formed in the region below hole h. That is, the n-type impurity concentration in the aforementioned fourth region 11D below the field plate electrode 40 is higher than the n-type impurity concentration in the third region 11C (first concentration region 101).

[0045] In the example shown in Figure 7(a), the second concentration region 102 is not continuous in the first direction X and the second direction Y, but rather multiple second concentration regions 102 are arranged in the first direction X and the second direction Y. After forming the second concentration region 102, holes h are formed in the first concentration region 101 between adjacent second concentration regions 102 in the first direction X, and in the first concentration region 101 between adjacent second concentration regions 102 in the second direction Y, as shown in Figure 7(b).

[0046] Figure 8(a) is a cross-sectional view of FF in Figure 7(b). Figure 8(b) is a cross-sectional view of GG in Figure 7(b). In regions where the distance between adjacent holes h is relatively short, a second concentration region 102 is formed as shown in Figure 8(a), and in regions where the distance between adjacent holes h is relatively large, a first concentration region 101 is formed as shown in Figure 8(b).

[0047] Furthermore, in the examples shown in Figures 7(a) to 8(b), a first concentration region 101 is formed in the region below hole h. That is, the n-type impurity concentration in the aforementioned fourth region 11D below the field plate electrode 40 is higher than the n-type impurity concentration in the second concentration region 102.

[0048] In the method described above, after forming holes h in a first semiconductor layer 11 of a predetermined thickness in which the entire region is a first concentration region 101, a second concentration region 102 may be formed by ion implantation.

[0049] After forming the field plate electrode 40, the following steps are performed: forming a gate trench in the first semiconductor layer 11; embedding the gate electrode 30 in the gate trench via a gate insulating film 51; forming a second semiconductor layer 12 in the first semiconductor layer 11 by ion implantation; forming a third semiconductor layer 13 in the second semiconductor layer 12 by ion implantation; forming an insulating layer 53; forming a second electrode 22; and so on.

[0050] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0051] 1…Semiconductor device, 10…Semiconductor part, 11…First semiconductor layer, 11A…First region, 11B…Second region, 11C…Third region, 11D…Fourth region, 21…First electrode, 22…Second electrode, 22A…Contact part, 30…Gate electrode, 40…Field plate electrode, 51…Gate insulating film, 52…Field plate insulating film, 53…Insulating layer, 101…First concentration region, 102…Second concentration region, h…Hole

Claims

1. First electrode and The second electrode and A semiconductor portion provided between the first electrode and the second electrode, Within the semiconductor portion, a plurality of field plate electrodes are arranged in a first direction and a second direction perpendicular to the first direction, A gate electrode located between the plurality of field plate electrodes and extending in the first and second directions, Equipped with, The aforementioned semiconductor section is A first semiconductor layer of a first conductivity type provided on the first electrode, A second semiconductor layer of a second conductivity type is provided on the first semiconductor layer, A third semiconductor layer is provided on the second semiconductor layer, is in contact with the second electrode, and has a first conductivity type with a higher concentration of first conductivity type impurities than the first semiconductor layer, It has, The first semiconductor layer is A first region located between adjacent field plate electrodes in the first direction, A second region located between adjacent field plate electrodes in the second direction, A third region located between adjacent field plate electrodes, with the intersection of the gate electrode extending in the first direction and the gate electrode extending in the second direction in between, It has, A semiconductor device wherein the concentration of a first conductivity type impurity in the first region and the concentration of a first conductivity type impurity in the second region are higher than the concentration of a first conductivity type impurity in the third region.

2. The first semiconductor layer has a fourth region located between the field plate electrode and the first electrode, The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in the fourth region is higher than the concentration of the first conductivity type impurity in the third region.

3. The first semiconductor layer has a fourth region located between the field plate electrode and the first electrode, The semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in the fourth region is lower than the concentration of the first conductivity type impurity in the first region and the concentration of the first conductivity type impurity in the second region.

4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor portion further comprises a fourth semiconductor layer of a first conductivity type provided between the first electrode and the first semiconductor layer and in contact with the first electrode.

5. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor portion further comprises a fourth semiconductor layer of a second conductivity type provided between the first electrode and the first semiconductor layer and in contact with the first electrode.

6. A step of forming a first semiconductor layer of a first conductivity type with a first concentration region and a second concentration region having a higher concentration of first conductivity type impurities than the first concentration region and extending in a first direction and a second direction perpendicular to the first direction, A step of embedding a field plate electrode in a hole located at the intersection of the second concentration region extending in the first direction and the second concentration region extending in the second direction, via an insulating film, A method for manufacturing a semiconductor device, comprising:

7. A method for manufacturing a semiconductor device according to claim 6, wherein after forming the second concentration region, the hole is formed at the intersection.

8. A step of forming a first semiconductor layer of a first conductivity type with a first concentration region and a plurality of second concentration regions arranged in a first direction and a second direction perpendicular to the first direction, wherein the concentration of first conductivity type impurities is higher than that of the first concentration region. The steps include embedding a field plate electrode via an insulating film in a hole located in the first concentration region between adjacent second concentration regions in the first direction, and in a hole located in the first concentration region between adjacent second concentration regions in the second direction, A method for manufacturing a semiconductor device, comprising:

9. A method for manufacturing a semiconductor device according to claim 8, wherein, after forming the second concentration region, the hole is formed in the first concentration region.

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