Memory system

Abstract

This invention provides a memory system that improves the reliability of read, write, or erase operations in non-volatile memory. [Solution] The memory system includes a memory cell array containing multiple memory cells, a non-volatile memory 100 including a temperature sensor that acquires temperature data by temperature measurement and a buffer that holds the temperature data, and a memory controller. When the non-volatile memory performs a first operation based on a first instruction transmitted from the memory controller, the temperature sensor acquires temperature data that specifies the temperature of the non-volatile memory in the first operation, and the buffer holds the temperature data acquired by the temperature sensor as the latest data. Based on a second instruction transmitted from the memory controller, the non-volatile memory transmits the temperature data held in the buffer to the memory controller.

Description

Technical Field

[0001] Embodiments relate to a memory system.

Background Art

[0002] A memory system including a nonvolatile memory capable of storing data non-volatiley and a memory controller for controlling the nonvolatile memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To improve the reliability of the memory system.

Means for Solving the Problems

[0005] The memory system according to the embodiment includes a non-volatile memory including a plurality of memory cells, a temperature sensor that acquires temperature data by temperature measurement, and a buffer that holds the temperature data, and a memory controller. When the non-volatile memory performs a first operation based on a first instruction transmitted from the memory controller, the temperature sensor acquires temperature data that specifies the temperature of the non-volatile memory in the first operation, and the buffer holds the temperature data acquired by the temperature sensor as the latest data. The non-volatile memory is configured to transmit the temperature data held in the buffer to the memory controller based on a second instruction transmitted from the memory controller. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of a memory system including a memory system and host equipment according to the first embodiment. [Figure 2] A block diagram illustrating an example of the configuration of a non-volatile memory according to the first embodiment. [Figure 3] A circuit diagram showing an example of the circuit configuration of a memory cell array in a non-volatile memory according to the first embodiment. [Figure 4] A schematic diagram showing an example of the threshold voltage distribution of memory cell transistors in a memory system according to the first embodiment. [Figure 5] A schematic diagram showing an example of the temperature dependence of the threshold voltage distribution of a memory cell transistor in a memory system according to the first embodiment. [Figure 6] A schematic diagram showing an example of a command sequence for a read operation in the memory system according to the first embodiment. [Figure 7] A block diagram showing an example of the configuration of a memory system including a memory system and host equipment according to the second embodiment. [Figure 8] A flowchart illustrating an example of operation in the memory system according to the second embodiment. [Figure 9]A schematic diagram showing an example of a command sequence in an example of operation in the memory system according to the second embodiment. [Figure 10] A block diagram showing an example of the configuration of a memory system including a memory system and host equipment according to the third embodiment. [Figure 11] A flowchart illustrating an example of operation in the memory system according to the third embodiment. [Figure 12] A schematic diagram showing an example of a command sequence in operation in the memory system according to the third embodiment. [Figure 13] A flowchart illustrating an example of operation in the memory system according to the fourth embodiment. [Figure 14] A flowchart illustrating an example of operation in the memory system according to the fifth embodiment. [Figure 15] A flowchart illustrating an example of operation in the memory system according to the sixth embodiment. [Figure 16] A block diagram showing an example of the configuration of a memory system including a memory system and host equipment according to the seventh embodiment. [Figure 17] A flowchart illustrating an example of operation in the memory system according to the seventh embodiment. [Figure 18] A flowchart illustrating an example of operation in the memory system according to the eighth embodiment. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be denoted by the same reference numerals.

[0008] In the following explanation, components having substantially the same function and structure will be assigned the same reference numeral. When elements with similar structures need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0009] 1. First Embodiment 1.1 Configuration Hereinafter, a memory system including a non-volatile memory will be described.

[0010] 1.1.1 Memory System First, the configuration including the memory system will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the configuration of a memory system including the memory system according to the first embodiment and a host device.

[0011] The memory system 1 includes a non-volatile memory 100, a memory controller 200, and a volatile memory 300. The non-volatile memory 100, the memory controller 200, and the volatile memory 300 may constitute one semiconductor device, for example, by a combination thereof. The memory system 1 is, for example, an SSD (solid state drive) or an SD TM card. The memory system 1 is connected to an external host device 2. The memory system 1 stores data from the host device 2. Also, the memory system 1 reads out data to the host device 2.

[0012] The non-volatile memory 100 is, for example, a semiconductor memory that stores data non-volatily. The semiconductor memory is, for example, a NAND-type flash memory. The non-volatile memory 100 is configured to operate based on instructions from the memory controller 200.

[0013] The memory controller 200 is composed of an integrated circuit, such as a System-on-a-Chip (SoC). The memory controller 200 receives instructions from the host device 2. Based on the received instructions, the memory controller 200 controls the non-volatile memory 100. For example, based on a read instruction received from the host device 2, the memory controller 200 reads the data ordered to be read from the non-volatile memory 100. Then, the memory controller 200 transmits the data read from the non-volatile memory 100 to the host device 2. Also, for example, based on a write instruction received from the host device 2, the memory controller 200 writes the data ordered to be written to the non-volatile memory 100.

[0014] The volatile memory 300 is, for example, DRAM (Dynamic Random Access Memory). The volatile memory 300 stores firmware for managing the non-volatile memory 100, and various management information. The volatile memory 300 stores, for example, temperature information 310 and read voltage information 320. The temperature information 310 stores, for example, the latest temperature measured in the non-volatile memory 100. The read voltage information 320 is information for reading data from the non-volatile memory 100. The read voltage information 320 includes, for example, information about the read voltage used for read operations in the non-volatile memory 100. As will be described later, the optimal read voltage changes depending on the temperature of the non-volatile memory 100. The read voltage information 320 includes, for example, a specified read voltage, as well as the optimal read voltage at the latest temperature of the non-volatile memory 100. Alternatively, instead of including the optimal read voltage at the latest temperature, the read voltage information 320 may include, for example, a conversion formula or conversion table for calculating the optimal read voltage corresponding to the temperature.

[0015] 1.1.2 Memory Controller The memory controller 200 includes a processor (CPU) 210, a buffer memory 220, a host interface circuit (host I / F) 230, an ECC circuit 240, a NAND interface circuit (NAND I / F) 250, a read voltage conversion unit 260, and a DRAM interface circuit (DRAM I / F) 270. The functions of each part within the memory controller 200 can be realized by dedicated hardware, a processor executing a program (firmware), or a combination thereof.

[0016] The processor 210 uses a program stored in the ROM (Read Only Memory) within the memory controller 200 to execute the overall operation of the memory controller 200. For example, the processor 210 issues commands to instruct the execution of various processes, including writing, reading, and erasing data to the non-volatile memory 100.

[0017] The buffer memory 220 is, for example, SRAM (Static Random Access Memory). The buffer memory 220 temporarily stores data read by the memory controller 200 from the non-volatile memory 100, and data written from the host device 2.

[0018] The host interface circuit 230 is connected to the host device 2 via the host bus. The host interface circuit 230 is responsible for communication between the memory controller 200 and the host device 2. The host bus is, for example, SD TM The interface is a bus compliant with standards such as SAS (Serial attached SCSI (small computer system interface)), SATA (Serial ATA (advanced technology attachment)), or PCIe (Peripheral component integral express).

[0019] The ECC circuit 240 performs error detection and error correction processing for data stored in the non-volatile memory 100. More specifically, when data is written, the ECC circuit 240 generates an error correction code and adds the error correction code to the written data. The error correction code is, for example, a hard-decision decoded code such as a BCH (Bose-Chaudhuri-Hocquenghem) code or an RS (Reed-Solomon) code, or a soft-decision decoded code such as an LDPC (Low-Density Parity-Check) code. Furthermore, when data is read, the ECC circuit 240 decodes the error correction code and detects the presence or absence of error bits (fail bits). When an error bit is detected, the ECC circuit 240 identifies the location of the error bit and corrects the error.

[0020] The NAND interface circuit 250 is connected to the non-volatile memory 100 by a NAND bus. The NAND interface circuit 250 communicates based on the NAND interface standard. Various signals based on the NAND interface standard will be described later. The NAND interface circuit 250 is responsible for communication with the non-volatile memory 100. The NAND interface circuit 250 transmits data, commands, and addresses to the non-volatile memory 100 according to instructions from the processor 210. Commands are signals for controlling the entire non-volatile memory 100. Data includes read data and write data.

[0021] The read voltage conversion unit 260 calculates, for example, the optimal read voltage at the most recent temperature. The read voltage conversion unit 260 performs this calculation based, for example, the temperature information 310 stored in the volatile memory 300 and a conversion formula or conversion table. The conversion formula or conversion table may be stored in the memory controller 200 or in the volatile memory 300. The read voltage conversion unit 260 also updates the read voltage information 320 based on the result of the above calculation. Furthermore, if the read voltage information 320 includes a conversion formula or conversion table for calculating the optimal read voltage corresponding to the temperature, the read voltage conversion unit 260 may perform the above calculation when the memory controller 200 instructs a read operation. With this configuration, the optimal read voltage is applied during the read operation in the non-volatile memory 100.

[0022] The DRAM interface circuit 270 is connected to the volatile memory 300. The DRAM interface circuit 270 manages communication between the memory controller 200 and the volatile memory 300. The DRAM interface circuit 270 performs communication based on the DRAM interface standard.

[0023] 1.1.3 Non-volatile memory Next, the configuration of the non-volatile memory 100 will be explained using Figure 2. Figure 2 is a block diagram illustrating an example of the configuration of the non-volatile memory according to the first embodiment.

[0024] The non-volatile memory 100 includes, for example, an input / output circuit 10, a logic control circuit 11, a status register 12, an address register 13, a command register 14, a sequencer 15, a ready / busy circuit 16, a voltage generation circuit 17, a memory cell array 18, a driver module 19, a row decoder module 20, a sense amplifier module 21, a data register 22, a column decoder 23, a temperature sensor 24, and a buffer 25.

[0025] Communication between the non-volatile memory 100 and the memory controller 200 based on the NAND interface standard includes, for example, signals DQ[7:0], CEn, CLE, ALE, WEn, REn, and RBn.

[0026] Signal DQ[7:0] is, for example, an 8-bit wide signal. Signal DQ[7:0] includes data DAT, address ADD, and command CMD, etc. Data DAT includes data DATin input from memory controller 200 and data DATout output to memory controller 200.

[0027] Signal CEn is the Chip Enable signal. Signal CEn is a signal to enable the chip. Signal CLE is the Command Latch Enable signal. Signal CLE notifies non-volatile memory 100 that signal DQ, which is sent to non-volatile memory 100 while signal CLE is at the "H (High)" level, is a command. Signal ALE is the Address Latch Enable signal. Signal ALE notifies non-volatile memory 100 that signal DQ, which is sent to non-volatile memory 100 while signal ALE is at the "H (High)" level, is an address. Signal WEn is the Write Enable signal. Signal WEn instructs non-volatile memory 100 to capture signal DQ. Signal REn is the Read Enable signal. Signal REn instructs non-volatile memory 100 to output signal DQ. Signal RBn is the Ready Busy signal. The signal RBn indicates whether the non-volatile memory 100 is in a ready or busy state. The ready state means it is ready to receive external commands. The busy state means it is not ready to receive external commands.

[0028] The input / output circuit 10 controls the input and output of the signal DQ[7:0] between the non-volatile memory 100 and the memory controller 200. The input / output circuit 10 transmits the data DAT (write data) received from the memory controller 200 to the data register 22. The input / output circuit 10 transmits the address ADD received from the memory controller 200 to the address register 13. The input / output circuit 10 transmits the command CMD received from the memory controller 200 to the command register 14. The input / output circuit 10 transmits status information STS received from the status register 12, data DAT (read data) received from the data register 22, address ADD received from the address register 13, etc., to the memory controller 200.

[0029] The logic control circuit 11 receives signals from the memory controller 200, such as the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn. The logic control circuit 11 then controls the input / output circuit 10 and the sequencer 15 according to the signals received from the memory controller 200.

[0030] The status register 12 temporarily holds the status information STS received from the sequencer 15 during, for example, a write operation, a read operation, or an erase operation. The status information STS includes information that notifies the memory controller 200 whether, for example, a write operation, a read operation, an erase operation, etc., has been completed successfully.

[0031] The address register 13 temporarily holds the address ADD received from the input / output circuit 10. Address ADD may include, for example, a page address PA, a block address BA, a column address CA, etc. The address register 13 sends, for example, the page address PA to the driver module 19, the block address BA to the row decoder module 20, and the column address CA to the column decoder 23.

[0032] The command register 14 temporarily holds the command CMD received from the input / output circuit 10. The command CMD is associated with an operation that the non-volatile memory 100 can perform. The command CMD held by the command register 14 is referenced by the sequencer 15.

[0033] The sequencer 15 controls the operation of the entire non-volatile memory 100. For example, the sequencer 15 can control the status register 12, the ready / busy circuit 16, the voltage generation circuit 17, the driver module 19, the row decoder module 20, the sense amplifier module 21, the data register 22, the column decoder 23, and the temperature sensor 24. The sequencer 15 then performs write operations, read operations, erase operations, etc., according to the command CMD held by the command register 14.

[0034] The ready / busy circuit 16 generates a ready / busy signal RBn based on the operating state of the sequencer 15. The ready / busy circuit 16 then transmits the generated ready / busy signal RBn to the memory controller 200.

[0035] The voltage generation circuit 17 generates the voltages necessary for write operations, read operations, erase operations, etc., in accordance with the control of the sequencer 15. The voltage generation circuit 17 then supplies the generated voltages to the memory cell array 18, driver module 19, sense amplifier module 21, data register 22, column decoder 23, etc.

[0036] The memory cell array 18 includes a plurality of block BLKs (BLK0, BLK1, ..., BLK(m-1)), where m is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cell transistors, each storing data non-volatilely. A block BLK is used, for example, as a data erasure unit. That is, data held by multiple memory cell transistors contained in the same block BLK can be erased all at once. Each memory cell transistor is associated with one word line and one bit line.

[0037] The driver module 19 generates voltages used for read operations, write operations, erase operations, etc., and applies the generated voltages to the row decoder module 20. Specifically, the driver module 19 and the row decoder module 20 are connected by multiple signal lines. The driver module 19 then applies multiple types of voltages, set for read operations, write operations, erase operations, etc., to each of the multiple signal lines based on the page address PA.

[0038] The row decoder module 20 is connected between multiple signal lines connected to the driver module 19 and multiple wirings provided in each of the multiple block BLKs in the memory cell array 18. The row decoder module 20 selects one block BLK in the memory cell array 18 based on the block address BA. For example, the row decoder module 20 transfers the voltage applied to each of the multiple signal lines by the driver module 19 to the word lines, etc., in the selected block BLK.

[0039] During a read operation, the sense amplifier module 21 determines the data stored in the memory cell transistor based on the voltage of the bit lines. The sense amplifier module 21 then transfers the determination result as read data to the data register 22. During a write operation, the sense amplifier module 21 applies a voltage to each bit line according to the write data received from the data register 22.

[0040] The data register 22 includes multiple latch circuits. These latch circuits can hold write data, read data, etc. During a write operation, the data register 22 temporarily holds the write data (DATin) received from the input / output circuit 10 and transfers it to the sense amplifier module 21. During a read operation, the data register 22 temporarily holds the read data (DATout) received from the sense amplifier module 21 and transfers it to the input / output circuit 10. The data register 22 transmits the data DATout to the input / output circuit 10 via, for example, a buffer 25. Between the input / output circuit 10 and the data register 22, the data DATin and DATout are connected, for example, via eight data buses.

[0041] The column decoder 23 decodes the column address CA during, for example, a write operation, a read operation, and an erase operation. Then, the column decoder 23 selects a latch circuit in the data register 22 according to the decoding result.

[0042] The temperature sensor 24 performs temperature measurement of the non-volatile memory 100 under the control of the sequencer 15. The temperature sensor 24 transmits the measured temperature as identifiable data (temperature data) to the buffer 25. The temperature data includes the temperature.

[0043] Buffer 25 temporarily holds temperature data received from temperature sensor 24. When temperature measurement is performed by the control of sequencer 15, for example, buffer 25 transmits the held temperature data as data DATout to input / output circuit 10. Also, when buffer 25 receives read data (data DATout) from sense amplifier module 21, it transmits said data DATout to input / output circuit 10. Note that when buffer 25 holds temperature data, or when it receives read data from sense amplifier module 21, it may transmit the temperature data and read data as consecutive data DATout to input / output circuit 10.

[0044] 1.1.4 Memory cell array Next, the configuration of the memory cell array 18 of the non-volatile memory 100 according to the first embodiment will be described with reference to Figure 3. Figure 3 is a circuit diagram showing an example of the circuit configuration of the memory cell array of the non-volatile memory according to the first embodiment. In Figure 3, an example of the circuit diagram of one block BLK of the memory cell array 18 is shown.

[0045] Block BLK includes, for example, four string units SU0 to SU3. Since the configurations of string units SU2 and SU3 are the same as those of string units SU0 and SU1, their configurations are simplified in Figure 3. Furthermore, in the following description, when string units SU0 to SU3 are not distinguished, they will simply be referred to as string unit SU.

[0046] Each string unit SU contains multiple NAND strings NS.

[0047] Each NAND string NS comprises, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. The number of memory cell transistors MT included in a NAND string NS is not limited. Each memory cell transistor MT comprises a stacked gate including a control gate and a charge storage layer. In each NAND string NS, each memory cell transistor MT is connected in series between selection transistors ST1 and ST2.

[0048] Within each block BLK, the gates of the selection transistor ST1 of string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. In the following explanation, when selection gate lines SGD0 to SGD3 are not distinguished, they are simply referred to as selection gate line SGD. The gates of the selection transistor ST2 of all string units SU within each block BLK are commonly connected to selection gate line SGS. The control gates of memory cell transistors MT0 to MT7 within the same block BLK are connected to word lines WL0 to WL7, respectively. That is, word lines WL with the same address are commonly connected to all string units SU within the same block BLK, and selection gate line SGS is commonly connected to all string units SU within the same block BLK. On the other hand, selection gate line SGD is connected to only one string unit SU within the same block BLK.

[0049] Furthermore, among the NAND strings NS arranged in a matrix within the memory cell array 18, the other end of the selection transistor ST1 of a NAND string NS in the same row is connected to one of n bit lines BL (BL0 to BL(n-1)), where n is an integer of 2 or more. In addition, the bit lines BL are commonly connected to NAND strings NS in the same column across multiple blocks BLK.

[0050] Furthermore, the other end of the selection transistor ST2 is connected to the source line SL. The source line SL is commonly connected to multiple NAND strings NS across multiple blocks BLK.

[0051] As described above, data erasure is performed collectively, for example, on memory cell transistors MT within the same block BLK. In contrast, data read and write operations can be performed collectively on multiple memory cell transistors MT commonly connected to a word line WL in any string unit SU of any block BLK. Such a set of multiple memory cell transistors MT sharing a word line WL in a single string unit SU is called, for example, a cell unit CU. In other words, a cell unit CU is a set of multiple memory cell transistors MT on which write or read operations are performed collectively. For example, the storage capacity of a cell unit CU containing multiple memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". 1 page of data is used, for example, as a unit of data read. A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0052] 1.1.5 Threshold voltage distribution of memory cell transistors The threshold voltage distribution of memory cell transistors in the memory system 1 according to the first embodiment will be explained using Figure 4. Figure 4 is a schematic diagram showing an example of the threshold voltage distribution of memory cell transistors in the memory system according to the first embodiment. In the threshold voltage distribution shown in Figure 4, the vertical axis corresponds to the number of memory cell transistors MTs NMTs, and the horizontal axis corresponds to the threshold voltage Vth of the memory cell transistors MTs.

[0053] As shown in Figure 4, in the memory system 1 according to the first embodiment, the threshold voltage distribution includes eight states, for example, based on the threshold voltages of multiple memory cell transistors MT contained in one cell unit CU.

[0054] In the following, these eight states will be referred to as state "S0", state "S1", state "S2", state "S3", state "S4", state "S5", state "S6", and state "S7", in order from the lowest threshold voltage.

[0055] Seven read voltages R1, R2, R3, R4, R5, R6, and R7 are used to distinguish between the eight states "S0" to "S7". Additionally, the voltage VREAD is used to turn on all memory cell transistors MT regardless of the data being stored. The read voltages R1-R7 and the voltage VREAD are applied to the gate of the memory cell transistor MT. The relationship between the read voltages R1-R7 and the voltage VREAD is as follows: <R2<R3<R4<R5<R6<R7<VREADである。

[0056] The threshold voltage of the memory cell transistor MT in state "S0" is less than the read voltage R1. The threshold voltage of the memory cell transistor MT in state "S1" is greater than or equal to the read voltage R1 and less than the read voltage R2. The threshold voltage of the memory cell transistor MT in state "S2" is greater than or equal to the read voltage R2 and less than the read voltage R3. The threshold voltage of the memory cell transistor MT in state "S3" is greater than or equal to the read voltage R3 and less than the read voltage R4. The threshold voltage of the memory cell transistor MT in state "S4" is greater than or equal to the read voltage R4 and less than the read voltage R5. The threshold voltage of the memory cell transistor MT in state "S5" is greater than or equal to the read voltage R5 and less than the read voltage R6. The threshold voltage of the memory cell transistor MT in state "S6" is greater than or equal to the read voltage R6 and less than the read voltage R7. The threshold voltage of the memory cell transistor MT in state "S7" is greater than or equal to the read voltage R7 and less than the read voltage VREAD.

[0057] When a read voltage R1 is applied to the gate, the memory cell transistor MT belonging to state "S0" turns ON, and the memory cell transistors MT belonging to states "S1" to "S7" turn OFF. When a read voltage R2 is applied to the gate, the memory cell transistors MT belonging to states "S0" and "S1" turn ON, and the memory cell transistors MT belonging to states "S2" to "S7" turn OFF. When a read voltage R3 is applied to the gate, the memory cell transistors MT belonging to states "S0" to "S2" turn ON, and the memory cell transistors MT belonging to states "S3" to "S7" turn OFF. When a read voltage R4 is applied to the gate, the memory cell transistors MT belonging to states "S0" to "S3" turn ON, and the memory cell transistors MT belonging to states "S4" to "S7" turn OFF. When a read voltage R5 is applied to the gate, the memory cell transistors MT belonging to states "S0" to "S4" turn ON, and the memory cell transistors MT belonging to states "S5" to "S7" turn OFF. Furthermore, when the read voltage R6 is applied to the gate, the memory cell transistors MT belonging to states "S0" to "S5" turn ON, and the memory cell transistors MT belonging to states "S6" and "S7" turn OFF. Furthermore, when the read voltage R7 is applied to the gate, the memory cell transistors MT belonging to states "S0" to "S6" turn ON, and the memory cell transistors MT belonging to state "S7" turn OFF. Furthermore, when the read voltage VREAD is applied to the gate, all memory cell transistors MT belonging to states "S0" to "S7" turn ON.

[0058] For each of the eight states described above, a different 3-bit data is assigned. Below is an example of the "higher bit, middle bit, and lower bit" data assigned to each of the eight states.

[0059] State "S0": "1, 1, 1" data State "S1": "1, 1, 0" data State "S2": "1, 0, 0" data Status "S3": "0, 0, 0" data Status "S4": "0, 1, 0" data Status "S5": "0, 1, 1" data Status "S6": "0, 0, 1" data Status "S7": "1, 0, 1" data.

[0060] When data is allocated in this manner, the lower page data, consisting of the lower bits, is determined by read operations using read voltages R1 and R5. The middle page data, consisting of the middle bits, is determined by read operations using read voltages R2, R4, and R6. The upper page data, consisting of the upper bits, is determined by read operations using read voltages R3 and R7, respectively. In other words, the lower page data, middle page data, and upper page data are determined by read operations using two, three, and two types of read voltages, respectively. The read operations for determining the lower page data, middle page data, and upper page data are called lower page read, middle page read, and upper page read, respectively.

[0061] 1.1.6 Temperature Dependence of Threshold Voltage Distribution Next, the temperature dependence of the threshold voltage distribution of the memory cell transistor in the memory system 1 according to the first embodiment will be explained using Figure 5. Figure 5 is a schematic diagram showing an example of the temperature dependence of the threshold voltage distribution of the memory cell transistor in the memory system according to the first embodiment. In Figure 5, the threshold voltage distribution of the memory cell transistor is shown at the reference temperature, temperatures higher than the reference temperature (high temperature in Figure 5), and temperatures lower than the reference temperature (low temperature in Figure 5), with respect to the reference temperature.

[0062] The threshold voltage distribution of the memory cell transistors changes depending on the temperature of the non-volatile memory 100. Using the threshold voltage distribution of the memory cell transistors at the reference temperature as a baseline, the threshold voltage distribution at high temperatures changes to, for example, generally lower voltages. As a result, the read voltages R1~R7 and voltage VREAD at high temperatures become lower than, for example, the read voltages R1~R7 and voltage VREAD at the reference temperature. Conversely, using the threshold voltage distribution of the memory cell transistors at the reference temperature as a baseline, the threshold voltage distribution at low temperatures changes to, for example, generally higher voltages. As a result, the read voltages R1~R7 and voltage VREAD at low temperatures become higher than, for example, the read voltages R1~R7 and voltage VREAD at the reference temperature. Thus, the optimal read voltages R1~R7 change depending on the temperature.

[0063] In the first embodiment, the non-volatile memory 100 transmits the latest temperature (temperature data) measured by the temperature sensor 24 as data DATout to the memory controller 200. This allows the read voltage conversion unit 260 of the memory controller 200 to calculate the read voltages R1 to R7 at the latest temperature. Furthermore, the read voltages R1 to R7 thus calculated can be stored in the read voltage information 320 as the optimal read voltages at the latest temperature.

[0064] 1.2 Operation The operation of the memory system 1 according to the first embodiment will be described.

[0065] In the following section, an example of operation when a read operation is performed on the non-volatile memory 100 will be explained using Figure 6. Figure 6 is a schematic diagram showing an example of a command sequence for a read operation in the memory system according to the first embodiment. Figure 6 shows an example in which, during a read operation, the temperature data of the non-volatile memory 100 is transmitted to the memory controller 200 as data DATout via the signal DQ[7:0]. Note that the read operation in the operation of the memory system 1 according to the first embodiment may be a read operation executed by a command issued by the memory controller 200 based on an instruction from the host device 2, or it may be a read operation executed by a command issued by the memory controller 200 regardless of an instruction from the host device 2.

[0066] In the operation example according to the first embodiment, when performing a read operation, the memory controller 200 sends the commands "ZZh", "A2h", "00h", "ADD", and "30h" to the non-volatile memory 100 in this order. Command "ZZh" is a command that instructs, for example, to update the temperature information 310 using the latest temperature measured by the temperature sensor 24 during the read operation. Command "A2h" is a command that specifies the read operation. That is, command "A2h" specifies, for example, which read operation to perform from lower page read, middle page read, and upper page read. Command "00h" is a command that, for example, transmits that address ADD be entered after this command. Address ADD specified after command "00h" is sent to specify the memory cell transistor MT to be read. Address ADD includes, for example, the column address CA and the page address PA. Address "ADD" may be sent in multiple cycles. Command "30h" is a command that instructs, for example, to start the read operation. When the non-volatile memory 100 receives the command "30h", the sequencer 15 transitions the non-volatile memory 100 from the ready state to the busy state. The sequencer 15 also starts the read operation specified by the commands "A2h", "00h", and "ADD".

[0067] Furthermore, when the sequencer 15 starts a read operation, for example, the sequencer 15 activates the temperature sensor 24. As a result, the temperature sensor 24 measures the temperature of the non-volatile memory 100 from the start of the read operation until a period ts has elapsed. The period ts is the period from when the temperature measurement by the temperature sensor 24 starts until it is completed. When the period ts has elapsed, the temperature sensor 24 determines the temperature of the non-volatile memory 100 and completes the measurement. In the example in Figure 6, the temperature data Temp_info held in the buffer 25 is the temperature TpA before the read operation starts. After the read operation starts and the period ts has elapsed, the temperature data Temp_info becomes the latest temperature TpB measured by the temperature sensor 24 during the period ts.

[0068] Furthermore, when the sequencer 15 starts the read operation, the sequencer 15 instructs the voltage generation circuit 17 to prepare to generate the read voltage. As a result, the voltage generation circuit 17 transitions from a stopped state (stopped in Figure 6) to a state where it is preparing to generate the read voltage (prepared in Figure 6). When the preparation for generating the read voltage is complete, the voltage generation circuit 17 transitions to a state where it can generate voltage (voltage generated in Figure 6). As a result, the voltage generation circuit 17 starts generating the read voltage. Note that the generation of the read voltage by the voltage generation circuit 17 is performed, for example, after a period ts has elapsed. In this way, in generating the read voltage, the sequencer 15 can control the voltage generation circuit 17 to generate a read voltage corresponding to the latest temperature TpB measured by the temperature sensor 24. At this time, the sequencer 15 calculates the read voltage corresponding to the temperature TpB using, for example, a calculation means (not shown) in the non-volatile memory 100. In this way, as shown in Figure 6, the temperature measured by the temperature sensor 24 is reflected in the generation of the read voltage. Then, under the control of the sequencer 15, the generated read voltage is used to read data from the memory cell transistor MT corresponding to the specified address ADD. When the read operation is complete, the voltage generation circuit 17 performs recovery. As a result, the voltage of each wire in the non-volatile memory 100 is set to, for example, voltage VSS.

[0069] Once recovery is complete, the voltage generation circuit 17 transitions to a stopped state. The sequencer 15 then transfers the read result, as described above, to the data register 22. When the read result is transferred to the data register 22, the sequencer 15 transitions the non-volatile memory 100 from a busy state to a ready state. In this way, the read operation in the non-volatile memory 100 is completed.

[0070] When the read operation in the non-volatile memory 100 is completed, the memory controller 200 sends the commands "05h", "ADD", and "E0h" to the non-volatile memory 100 in that order. Command "05h" is a command that, for example, indicates that the next command should be entered to specify the address to be output from the data read by the read operation. The address ADD, which is specified after command "05h", is sent to specify the memory cell transistor MT that is the target of the output of the read data to the memory controller 200. Command "E0h" is a command that instructs the start of output of the read data Dout that is the target of the output.

[0071] After the command "E0h" is sent, the non-volatile memory 100 outputs the temperature data Temp_info (temperature TpB) to the memory controller 200 based on the command "ZZh" that precedes the command specifying the read operation. The non-volatile memory 100 also outputs the read data Dout, which was selected for output based on the commands "05h", "ADD", and "E0h", to the memory controller 200. The non-volatile memory 100 sends, for example, the temperature data Temp_info and the read data Dout in this order consecutively.

[0072] Subsequently, the memory controller 200 updates the temperature information 310 based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320.

[0073] Through the operations described above, the read voltage based on the most recent temperature obtained as described above can be applied to the next read operation in the non-volatile memory 100.

[0074] 1.3 Effects of the First Embodiment According to the memory system 1 of the first embodiment, the reliability of the memory system can be improved. The effects of the first embodiment will be described below.

[0075] The memory system 1 according to the first embodiment includes a non-volatile memory 100 and a memory controller 200. The non-volatile memory 100 includes a plurality of memory cell transistors MT, a temperature sensor 24 that acquires temperature data Temp_info by temperature measurement, and a buffer 25 that holds the temperature data Temp_info. When the non-volatile memory 100 performs a read operation based on a read operation instruction sent from the memory controller 200, the temperature sensor 24 is configured to acquire the temperature data Temp_info of the non-volatile memory 100 during the read operation. The buffer 25 is configured to hold the temperature data Temp_info acquired by the temperature sensor 24 as the latest data. The non-volatile memory 100 also transmits the temperature data Temp_info held in the buffer 25 to the memory controller 200 based on the command "ZZh" sent from the memory controller 200. With this configuration, information regarding the temperature of the non-volatile memory 100 can be acquired at a high frequency. Therefore, the reliability of the memory system 1 can be improved.

[0076] To elaborate, in the comparative example where the non-volatile memory does not include a buffer for holding temperature data, the non-volatile memory, for example, when instructed to send temperature data to the memory controller, transmits the temperature data from the temperature sensor to the input / output circuit under the control of the PLC. In this case, for example, the temperature data is output to the memory controller via the temperature sensor, PLC, and input / output circuit, which can cause a delay in data output. As a result, in the comparative example, a decrease in operating speed may occur due to the delay in the output of temperature data.

[0077] More specifically regarding the comparative example, when outputting temperature data during a read operation, after the read operation is completed, for example, a command is sent from the memory controller to the non-volatile memory to output the temperature data acquired by the temperature sensor. Based on this command, the temperature data is output to the memory controller. Subsequently, a command is sent from the memory controller to the non-volatile memory to output the data read by the read operation. As a result, the data read from the non-volatile memory is output to the memory controller. In this operation, in the comparative example, since the non-volatile memory does not contain a buffer to hold the temperature data, there is a waiting period between receiving the command to output the temperature data and actually outputting the temperature data to prepare for the output. Therefore, the operation may be delayed.

[0078] On the other hand, in this embodiment, during a read operation, the memory controller 200 sends a command "ZZh" to instruct the system to update the temperature information 310 immediately before a command such as "A2h" that specifies the read operation. For example, during the read operation, the temperature sensor 24 acquires temperature data Temp_info, and the temperature data Temp_info is held in the buffer 25. Then, when the read operation is completed and the non-volatile memory 100 receives a command such as "05h" to output the data read by the read operation, the temperature data Temp_info held in the buffer 25 is output along with the read data. As a result, according to this embodiment, there is no need to wait for a period of time to prepare for output, thus suppressing delays in operation. Therefore, temperature data can be acquired at a high frequency. Furthermore, when the next read operation is executed, the read voltage based on the latest temperature data acquired at a high frequency can be applied, thus suppressing an increase in the number of fail bits during read operations in the non-volatile memory 100.

[0079] 2. Second Embodiment In the first embodiment described above, an example was shown in which a command instructing the system to update the temperature information using the latest temperature measured by the temperature sensor is sent before the command specifying the read operation, but the system is not limited to this. The command instructing the system to update the temperature information using the latest temperature measured by the temperature sensor may be sent to the non-volatile memory 100 while the non-volatile memory 100 is performing a read operation.

[0080] The following describes the configuration and operation of the memory system 1 according to the second embodiment, highlighting the differences from the configuration and operation of the memory system according to the first embodiment.

[0081] The configuration of the memory system 1 according to the second embodiment will be explained with reference to Figure 7. Figure 7 is a block diagram showing an example of the configuration of a memory system including the memory system and host equipment according to the second embodiment.

[0082] The memory controller 200 according to the second embodiment further includes a temperature information determination unit 280. The temperature information determination unit 280 is configured to determine whether the temperature sensor 24 is operating based on the temperature data Temp_info received from the non-volatile memory 100. More specifically, the temperature sensor 24 of the non-volatile memory 100 according to the second embodiment, for example, when the temperature sensor 24 starts operating, sends data FFh, indicating that it cannot output an accurate temperature, as temperature data Temp_info to the buffer 25. As a result, while the temperature sensor 24 is operating (while the state of the temperature sensor 24 is "Disable"), the data FFh is held as temperature data Temp_info in the buffer 25. The non-volatile memory 100 is also configured to send temperature data Temp_info when it receives a temperature acquisition command from the memory controller 200. The temperature acquisition command is a command sent from the memory controller 200 to the non-volatile memory 100 to acquire the temperature of the non-volatile memory 100. With the above configuration, when the memory controller 200 receives the data FFh based on the above command, the temperature information determination unit 280 determines that the temperature sensor 24 is in a state where it cannot output an accurate temperature. In other words, the temperature information determination unit 280 determines that the temperature sensor 24 is operating. Furthermore, if the temperature data Temp_info received by the memory controller 200 based on the above command is not the data FFh (i.e., the state of the temperature sensor 24 is "Enable" and the temperature data Temp_info is a specific temperature), the unit determines that the temperature data Temp_info is the latest temperature.

[0083] The operation of the memory system 1 according to the second embodiment will now be described.

[0084] First, an example of operation in the memory system 1 according to the second embodiment will be explained using Figure 8. Figure 8 is a flowchart for explaining an example of operation in the memory system according to the second embodiment.

[0085] When a read operation in the non-volatile memory 100 begins, in S10 the memory controller 200 issues a temperature acquisition command to the non-volatile memory 100. Then the process proceeds to S11.

[0086] In S11, the memory controller 200 retrieves the temperature data Temp_info held in the buffer 25. Then, the process proceeds to S12.

[0087] In S12, the temperature information determination unit 280 of the memory controller 200 determines whether the acquired temperature data Temp_info is data FFh (Temp_info=FFh?). If it is determined that the temperature data Temp_info is data FFh (S12; YES), the process of S10 is executed again. If it is determined that the temperature data Temp_info is not data FFh (S12; NO), the process proceeds to S13.

[0088] As described above, while the temperature data Temp_info is data FFh (determined as YES in S12), the temperature acquisition command by the memory controller 200 is repeatedly issued until it is determined that the temperature data Temp_info is not data FFh.

[0089] If the temperature data Temp_info is determined not to be data FFh (S12; NO), in S13, the temperature information 310 of the volatile memory 300 is updated based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320.

[0090] As described above, the acquisition of temperature based on the temperature acquisition command is completed. Note that the acquisition of temperature based on the temperature acquisition command and the read operation are completed independently. The memory controller 200 acquires the temperature, for example, before the read operation is completed.

[0091] Next, an example of operation in the memory system 1 according to the second embodiment will be further explained with reference to Figure 9. Figure 9 is a schematic diagram showing an example of a command sequence in an example of operation in the memory system according to the second embodiment.

[0092] Figure 9 illustrates an example of the operation when a read operation is performed on the non-volatile memory 100. The following mainly describes the differences from the command sequence of the operation according to the first embodiment.

[0093] In the example of operation according to the second embodiment, when performing a read operation, the memory controller 200 sends the commands "A2h", "00h", "ADD", and "30h" to the non-volatile memory 100 in that order.

[0094] When the sequencer 15 starts a read operation, the memory controller 200 sends the command "7Ch" to the non-volatile memory 100. The command "7Ch" is a temperature acquisition command. During the period ts after the read operation starts, the temperature data Temp_info is FFh, which indicates that the temperature sensor 24 is unable to output an accurate temperature. As a result, the memory controller 200 sends the command "7Ch" to the non-volatile memory 100 again. In the example in Figure 9, when the second command "7Ch" is sent, the temperature sensor 24 has completed temperature measurement. Also, the buffer 25 holds the temperature TpB as temperature data Temp_info from the temperature sensor 24. Therefore, the non-volatile memory 100 sends the temperature data Temp_info (temperature TpB) to the memory controller 200 based on the command "7Ch". In this way, for example, while the read operation is being performed (while the non-volatile memory 100 is busy), the memory controller 200 acquires the latest temperature.

[0095] The transmission of read data to the memory controller 200 in response to the command "E0h" received from the memory controller 200 is the same as the command sequence in the operation according to the first embodiment, except that the temperature data Temp_info is not output to the memory controller 200.

[0096] Even with the operations described above, the read voltage based on the most recent temperature obtained as described above can be applied to the next read operation in the non-volatile memory 100.

[0097] The memory system 1 according to the second embodiment can also acquire information regarding the temperature of the non-volatile memory 100 at a high frequency, similar to the memory system according to the first embodiment. Therefore, the reliability of the memory system 1 can be improved.

[0098] 3. Third Embodiment In the second embodiment described above, an example was shown in which the memory controller 200 repeatedly issues temperature acquisition commands from the time the non-volatile memory 100 starts reading until it can obtain an accurate temperature, but it is not limited to this. The memory controller 200 may be configured to acquire temperature data after a period of time has elapsed until the temperature measurement by the temperature sensor 24 is completed.

[0099] The following describes the configuration and operation of the memory system 1 according to the third embodiment, highlighting the differences from the configuration and operation of the memory system according to the second embodiment.

[0100] The configuration of the memory system 1 according to the third embodiment will be explained with reference to Figure 10. Figure 10 is a block diagram showing an example of the configuration of a memory system including the memory system and host equipment according to the third embodiment.

[0101] The memory controller 200 according to the third embodiment further includes a prohibited period determination unit 290. The prohibited period determination unit 290 is configured to determine whether temperature measurement by the temperature sensor 24 has been completed when a read operation by the non-volatile memory 100 is performed. For example, the prohibited period determination unit 290 determines whether a period ts has elapsed from the start to the end of temperature measurement by the temperature sensor 24. While the prohibited period determination unit 290 determines that the period ts has not elapsed, the memory controller 200 does not issue a temperature acquisition command. When the prohibited period determination unit 290 determines that the period ts has elapsed, the memory controller 200 issues a temperature acquisition command. As a result, the memory controller 200 obtains the latest temperature from the non-volatile memory 100 using the temperature data Temp_info.

[0102] The operation of the memory system 1 according to the third embodiment will be described below.

[0103] First, an example of operation in the memory system 1 according to the third embodiment will be explained using Figure 11. Figure 11 is a flowchart for explaining an example of operation in the memory system according to the third embodiment.

[0104] When a read operation in the non-volatile memory 100 begins, for example, the prohibition period determination unit 290 starts determining whether the period ts has elapsed.

[0105] In S20, the prohibition period determination unit 290 determines that a period ts has elapsed since the start of the read operation. Then, the process proceeds to S21.

[0106] In S21, the memory controller 200 issues a temperature acquisition command to the non-volatile memory 100. Then, the process proceeds to S22.

[0107] In S22, the memory controller 200 retrieves the temperature data Temp_info held in buffer 25. Then, the process proceeds to S23.

[0108] In S23, the temperature information 310 of the volatile memory 300 is updated based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320.

[0109] As described above, the acquisition of temperature based on the temperature acquisition command is completed.

[0110] Next, an example of operation in the memory system 1 according to the third embodiment will be further explained with reference to Figure 12. Figure 12 is a schematic diagram showing an example of a command sequence in an example of operation in the memory system according to the third embodiment.

[0111] Figure 12 illustrates an example of the operation when a read operation is performed on the non-volatile memory 100. The following mainly describes the differences between the command sequence of the operation according to the second embodiment and the second embodiment.

[0112] In the example of operation according to the third embodiment, when the read operation is started, the prohibition period determination unit 290 starts determining whether the period ts has elapsed.

[0113] When the prohibition period determination unit 290 determines that the period ts has elapsed, the memory controller 200 sends the command "7Ch" to the non-volatile memory 100. In response, the non-volatile memory 100 sends temperature data Temp_info (temperature TpB) to the memory controller 200 based on the command "7Ch". In this way, the memory controller 200 obtains the latest temperature.

[0114] The memory system 1 according to the third embodiment can also acquire information regarding the temperature of the non-volatile memory 100 at a high frequency, similar to the memory system according to the first embodiment. Therefore, the reliability of the memory system 1 can be improved.

[0115] 4. Fourth Embodiment In the first to third embodiments described above, an example was shown in which the memory controller 200 is configured to acquire temperature data during operation of the non-volatile memory 100, but the invention is not limited to this. The memory controller 200 may be configured to acquire temperature data, for example, when the power supply to the non-volatile memory 100 is cut off, or when the non-volatile memory 100 is put into a standby state.

[0116] The configuration and operation of the memory system 1 according to the fourth embodiment will be described below.

[0117] First, the configuration of the memory system 1 according to the fourth embodiment will be described. Below, the differences between the configuration of the memory system 1 according to the fourth embodiment and the configuration of the memory system 1 according to the first embodiment will be explained.

[0118] In the fourth embodiment, the memory controller 200 is configured to send a temperature acquisition command to the non-volatile memory 100 when a predetermined process is executed. The predetermined process is, for example, a process to cut off the power to the non-volatile memory 100 (power cut-off process), or a process to put the non-volatile memory 100 into a standby state (standby process). Alternatively, the predetermined process may be, for example, a process to turn on power to the non-volatile memory 100, or a process to return the non-volatile memory 100 from the standby state.

[0119] The operation of the memory system 1 according to the fourth embodiment will be explained with reference to Figure 13. Figure 13 is a flowchart illustrating an example of operation in the memory system according to the fourth embodiment.

[0120] When the power cut-off process or standby process is initiated, the operation in the fourth embodiment begins.

[0121] In S31, the memory controller 200 sends, for example, a temperature acquisition command to the non-volatile memory 100. As a result, the temperature sensor 24 starts measuring the temperature.

[0122] When the temperature measurement by the temperature sensor 24 is completed, in S32, the non-volatile memory 100 sends the latest temperature as temperature data Temp_info to the memory controller 200.

[0123] In S33, the temperature information 310 of the volatile memory 300 is updated based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320.

[0124] As described above, temperature acquisition based on the temperature acquisition command is performed during power cut-off or standby processing.

[0125] With the above configuration, after power is restored or after returning from standby, for example, in the next read operation in the non-volatile memory 100, the read voltage based on the most recent temperature obtained as described above can be applied.

[0126] The fourth embodiment, like the memory system according to the first embodiment, allows for the acquisition of information regarding the temperature of the non-volatile memory 100 at a high frequency. Therefore, the reliability of the memory system 1 can be improved.

[0127] 5. Fifth Embodiment In the first to fourth embodiments described above, examples were shown in which the memory controller is configured to acquire the temperature of the non-volatile memory during operation or processing, but the invention is not limited to this. The memory controller 200 may be configured to acquire temperature data at predetermined intervals.

[0128] The configuration and operation of the memory system 1 according to the fifth embodiment will be described below.

[0129] First, the configuration of the memory system 1 according to the fifth embodiment will be described. Below, the differences between the configuration of the memory system according to the fifth embodiment and the configuration of the memory system according to the fourth embodiment will be explained.

[0130] In the fifth embodiment, for example, the memory controller 200 is configured to be able to count the period tp. As a result, the memory controller 200 is configured to send a temperature acquisition command to the non-volatile memory 100 each time a predetermined period Ttp (a threshold for period tp) has elapsed. More specifically, the memory controller 200 is configured to be able to determine whether period Ttp has elapsed, for example, in the operation to acquire temperature described later, after starting to count period tp from 0. For example, if the memory controller 200 determines that period tp has become greater than or equal to period Ttp, it sends a temperature acquisition command to the non-volatile memory 100. The memory controller 200 also resets period tp to 0. Furthermore, the memory controller 200 does not send a temperature acquisition command to the non-volatile memory 100 if period tp is less than period Ttp.

[0131] Next, the operation for obtaining the temperature in the memory system 1 according to the fifth embodiment will be explained using Figure 14. Figure 14 is a flowchart illustrating an example of operation in the memory system according to the fifth embodiment.

[0132] When the operation of the memory system 1 according to the fifth embodiment begins, in S40 the memory controller 200 sets the period tp to 0 (tp=0). Then the process proceeds to S41.

[0133] In S41, the memory controller 200 counts the period tp as time progresses. Then, the process proceeds to S42.

[0134] In S42, the memory controller 200 determines whether the period tp is less than a predetermined period Ttp. If the memory controller 200 determines that the period tp is less than the predetermined period Ttp (S42; YES), the process in S41 is executed again. If the memory controller 200 determines that the period tp is greater than or equal to the predetermined period Ttp (S42; NO), the process proceeds to S43.

[0135] In S43, the memory controller 200 sends, for example, a temperature acquisition command to the non-volatile memory 100. As a result, the temperature sensor 24 starts measuring the temperature.

[0136] When the temperature measurement by the temperature sensor 24 is completed, in S44, the non-volatile memory 100 sends the latest temperature as temperature data Temp_info to the memory controller 200. Then, the process proceeds to S45.

[0137] In S45, the temperature information 310 of the volatile memory 300 is updated based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320. Then the process proceeds to S46.

[0138] In S46, the memory controller 200 determines whether to terminate the update of the temperature information 310. If the memory controller 200 determines not to terminate the update of the temperature information 310 (S46; NO), the process in S40 is executed again. If the memory controller 200 determines to terminate the update of the temperature information 310 (S46; YES), the process terminates.

[0139] As described above, the temperature information 310 is updated each time the period Ttp elapses until it is determined that the update of the temperature information 310 has ended.

[0140] With the above configuration, when the next read operation is performed, the read voltage based on the most recent temperature can be applied.

[0141] In the fifth embodiment, by acquiring the latest temperature based on the period tp, information regarding the temperature of the non-volatile memory 100 can be acquired at a high frequency, similar to the memory system according to the first embodiment. Therefore, the reliability of the memory system 1 can be improved.

[0142] 6. Sixth Embodiment In the fifth embodiment described above, an example was shown in which the memory controller is configured to acquire the temperature of the non-volatile memory at predetermined intervals. However, the invention is not limited to this. The memory controller 200 may be configured to acquire temperature data based on the number of times a read operation has been performed by the non-volatile memory 100.

[0143] The configuration and operation of the memory system 1 according to the sixth embodiment will be described below.

[0144] First, the configuration of the memory system 1 according to the sixth embodiment will be described. Below, the differences between the configuration of the memory system according to the sixth embodiment and the configuration of the memory system according to the fifth embodiment will be explained.

[0145] In the sixth embodiment, for example, the memory controller 200 is configured to count the number of times nr a read operation has been performed (started) by the non-volatile memory 100. As a result, the memory controller 200 is configured to send a temperature acquisition command to the non-volatile memory 100 each time a predetermined number of read operations have been performed. More specifically, for example, in an operation to acquire temperature described later, the memory controller 200 is configured to determine whether a predetermined number of read operations Tnr (a threshold for the number of nr) have been performed after starting to count the number nr from 0. For example, if the memory controller 200 determines that the number nr has become greater than or equal to the number Tnr, it sends a temperature acquisition command to the non-volatile memory 100. The memory controller 200 also resets the number nr to 0. Furthermore, the memory controller 200 does not send a temperature acquisition command to the non-volatile memory 100 if the number nr is less than the number Tnr.

[0146] Next, the operation of the memory system 1 according to the sixth embodiment will be explained using Figure 15. Figure 15 is a flowchart illustrating an example of operation in the memory system according to the sixth embodiment.

[0147] When the operation of the memory system 1 according to the sixth embodiment begins, in S50 the memory controller 200 sets the count nr to 0 (nr=0). Then the process proceeds to S51.

[0148] In S51, the read operation of the non-volatile memory 100 is initiated by the instruction of the memory controller 200. Then, the process proceeds to S52.

[0149] In S52, the memory controller 200 increments the count nr (nr++). Then, the process proceeds to S53.

[0150] In S53, the memory controller 200 determines whether the count nr is less than the count Tnr. If the memory controller 200 determines that the count nr is less than the count Tnr (S53; YES), the process in S51 is executed again. If the memory controller 200 determines that the count nr is greater than or equal to the count Tnr (S53; NO), the process proceeds to S54.

[0151] In S54, the memory controller 200 sends, for example, a temperature acquisition command to the non-volatile memory 100. As a result, the temperature sensor 24 starts measuring the temperature.

[0152] When the temperature measurement by the temperature sensor 24 is completed, in S55, the non-volatile memory 100 sends the latest temperature as temperature data Temp_info to the memory controller 200. Then, the process proceeds to S56.

[0153] In S56, the temperature information 310 of the volatile memory 300 is updated based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320. Then the process proceeds to S57.

[0154] In S57, the memory controller 200 determines whether to terminate the update of the temperature information 310. If the memory controller 200 determines not to terminate the update of the temperature information 310 (S57; NO), the process in S50 is executed again. If the memory controller 200 determines to terminate the update of the temperature information 310 (S57; YES), the process terminates.

[0155] As described above, the temperature information 310 in the volatile memory is updated each time the read operation of the non-volatile memory 100 is performed a predetermined number of times (Tnr), until it is determined that the update of the temperature information 310 has been completed.

[0156] With the above configuration, when the next read operation is performed, the read voltage based on the most recent temperature can be applied.

[0157] In the sixth embodiment, information regarding the temperature of the non-volatile memory 100 can be obtained at a high frequency, similar to the memory system according to the first embodiment, by acquiring the latest temperature based on the number of times the operation has been performed. Therefore, the reliability of the memory system 1 can be improved.

[0158] 7. Seventh Embodiment In the first to sixth embodiments described above, examples were shown in which the memory controller is configured to acquire the temperature of the non-volatile memory based on the number of times and the duration of operations and processes performed. However, the memory controller 200 may also be configured to acquire the temperature of the non-volatile memory based on the temperature change of the memory controller 200 itself.

[0159] The configuration and operation of the memory system 1 according to the seventh embodiment will be described below.

[0160] First, the configuration of the memory system 1 according to the seventh embodiment will be explained using Figure 16. Figure 16 is a block diagram showing an example of the configuration of a memory system including the memory system and host equipment according to the seventh embodiment. Below, the differences between the configuration of the memory system according to the seventh embodiment and the configuration of the memory system according to the first embodiment will be explained.

[0161] In the seventh embodiment, the memory controller 200 further includes a temperature sensor 400. The temperature sensor 400 is configured to measure the temperature within the memory controller 200. The temperature measured by the temperature sensor 400 is temporarily stored, for example, in a buffer memory 220.

[0162] Furthermore, the memory controller 200 is configured to send a temperature acquisition command to the non-volatile memory 100 based on a temperature change calculated using the measurement results of the temperature sensor 400, for example, under the control of the processor 210. More specifically, the memory controller 200 is configured to measure the temperature of the memory controller 200 using the temperature sensor 400 at predetermined intervals. When the temperature of the memory controller 200 is measured by the temperature sensor 400, the memory controller 200 calculates the difference (absolute value) between the most recently measured temperature and the previous temperature measured by the temperature sensor 400. The memory controller 200 determines, for example, whether the difference is greater than a predetermined value. If the difference is greater than the predetermined value, the memory controller 200 determines that a temperature change has been detected and sends a temperature acquisition command to the non-volatile memory 100. If the difference is less than or equal to the predetermined value, the memory controller 200 determines that no temperature change was detected and does not send a temperature acquisition command.

[0163] Next, the operation of the memory system 1 according to the seventh embodiment will be explained using Figure 17. Figure 17 is a flowchart illustrating an example of operation in the memory system according to the seventh embodiment.

[0164] When the operation of the memory system 1 according to the seventh embodiment begins, in S60, the memory controller 200 sets the temperature Tprv to temperature Tdef (Tprv = Tdef). Then, the process proceeds to S61. Note that the temperature Tdef is, for example, a specified temperature, or the temperature of the memory controller 200 when the operation of the memory system 1 begins.

[0165] In S61, the temperature sensor 400 measures the temperature Tc of the memory controller 200. Then, the process proceeds to S62.

[0166] In S62, the memory controller 200 determines whether the difference between temperature Tc and temperature Tprv (|Tc-Tprv|) is greater than a predetermined value Ttc (threshold for the difference |Tc-Tprv|). If the difference is greater than the value Ttc (S62; YES), the process proceeds to S63. If the difference is less than or equal to the value Ttc (S62; NO), the process in S61 is executed again.

[0167] In S63, the memory controller 200 sets temperature Tprv to temperature Tc. Then, the process proceeds to S64.

[0168] In S64, the memory controller 200 sends, for example, a temperature acquisition command to the non-volatile memory 100. As a result, the temperature sensor 24 in the non-volatile memory 100 starts measuring the temperature.

[0169] When the temperature measurement by the temperature sensor 24 is completed, in S65, the non-volatile memory 100 sends the latest temperature as temperature data Temp_info to the memory controller 200. Then, the process proceeds to S66.

[0170] In S66, the temperature information 310 of the volatile memory 300 is updated based on the temperature data Temp_info. The memory controller 200 also calculates the read voltage based on the latest temperature, for example, based on the temperature data Temp_info, and updates the read voltage information 320. Then the process proceeds to S67.

[0171] In S67, the memory controller 200 determines whether to terminate the update of the temperature information 310. If the memory controller 200 determines not to terminate the update of the temperature information 310 (S67; NO), the process in S61 is executed again. If the memory controller 200 determines to terminate the update of the temperature information 310 (S67; YES), the process terminates.

[0172] As described above, when the difference (|Tc-Tprv|) between the temperature Tc in the memory controller 200 and the temperature Tprv in the memory controller 200 stored when the temperature information 310 was last updated becomes greater than the value Tc, the temperature information 310 for the non-volatile memory 100 is updated. In other words, when the memory controller 200 detects a temperature change in the memory controller 200, it estimates that there has also been a temperature change in the non-volatile memory 100 and updates the temperature information 310.

[0173] With the above configuration, when the next read operation is performed, the read voltage based on the most recent temperature can be applied.

[0174] In the seventh embodiment, by updating the temperature information 310 based on the temperature change of the memory controller 200, information regarding the temperature of the non-volatile memory 100 can be obtained at a high frequency, similar to the memory system according to the first embodiment. Therefore, the reliability of the memory system 1 can be improved.

[0175] 8. Eighth Embodiment In the eighth embodiment, an example is shown in which the memory controller is configured to obtain the temperature of the non-volatile memory based on the number of fail bits detected when a read operation is performed.

[0176] The configuration and operation of the memory system 1 according to the eighth embodiment will be described below.

[0177] First, the differences between the configuration of the memory system 1 according to the eighth embodiment and the configuration of the memory system according to the first embodiment will be explained.

[0178] In the eighth embodiment, the memory controller 200 is configured to count the number of fail bits fbc during a read operation performed in the non-volatile memory 100. The memory controller 200 is also configured to determine whether the number of fail bits fbc is greater than a predetermined value Tfbc. Furthermore, the memory controller 200 is configured to send a temperature acquisition command to the non-volatile memory 100 if the number of fail bits fbc in the non-volatile memory 100 is greater than the predetermined value Tfbc.

[0179] Next, the operation of the memory system 1 according to the eighth embodiment will be explained using Figure 18. Figure 18 is a flowchart illustrating an example of operation in the memory system according to the eighth embodiment.

[0180] In S70, the memory controller 200, for example, based on a request from the host device 2, sends a read command to the non-volatile memory 100 requesting a read operation. Then the process proceeds to S71.

[0181] In S71, a read operation is performed in the non-volatile memory 100. Then, the process proceeds to S72.

[0182] In S72, the memory controller 200 determines whether the number of fail bits fbc when the above read operation is performed is greater than a predetermined value Tfbc (fbc > Tfbc?). If the number of fail bits fbc is greater than the predetermined value Tfbc (S73; YES), the process proceeds to S74. If the number of fail bits fbc is less than or equal to the predetermined value Tfbc (S73; NO), the process proceeds to S75.

[0183] In S74, the memory controller 200 sends, for example, a temperature acquisition command to the non-volatile memory 100. As a result, the temperature sensor 24 in the non-volatile memory 100 starts measuring the temperature. Then the process proceeds to S75. The operation based on the temperature acquisition command is similar to, for example, the operations in S32 and S33 in the fourth embodiment. Furthermore, these operations can be performed independently of the operation example in the memory system according to the eighth embodiment.

[0184] In S75, the memory controller 200 transmits the data read in S71 to the host device 2. Then, the process ends.

[0185] As described above, when a read request is received from the host device 2, the memory controller 200 updates the temperature information 310 of the non-volatile memory 100 based on the number of fail bits.

[0186] With the above configuration, when the next read operation is performed, the read voltage based on the most recent temperature can be applied.

[0187] In the eighth embodiment, by updating the temperature information 310 based on the number of fail bits fbc in the read operation, information regarding the temperature of the non-volatile memory 100 can be obtained at a high frequency, similar to the memory system according to the first embodiment. Therefore, the reliability of the memory system 1 can be improved.

[0188] 9 Others In the first embodiment described above, an example was shown in which the memory controller 200 sends the commands "A2h", "00h", and "30h" to cause the non-volatile memory 100 to perform a read operation, and the command "ZZh" to instruct the non-volatile memory 100 to update the temperature information 310 before address ADD, but the embodiment is not limited to this. For example, the memory controller 200 may be configured to send a command to instruct the non-volatile memory 100 to update the temperature information 310 immediately before sending a command to cause the non-volatile memory 100 to perform a write operation or erase operation, similar to the first embodiment. In this case, for example, similar to the first embodiment, when the various operations in the non-volatile memory 100 are completed and the non-volatile memory 100 changes from a busy state to a ready state, the temperature data is sent from the non-volatile memory 100 to the memory controller 200.

[0189] Furthermore, while the second and third embodiments described above show examples in which a read operation is performed in the non-volatile memory 100 and the temperature acquisition command "7Ch" is sent while the non-volatile memory 100 is busy, the embodiment is not limited to this. The memory controller 200 may, for example, send the temperature acquisition command "7Ch" while a write operation or erase operation is performed in the non-volatile memory 100 and the non-volatile memory 100 is busy.

[0190] Furthermore, while the sixth embodiment described above shows an example in which the temperature acquisition command "7Ch" is transmitted based on the number of times a read operation is performed, the memory controller 200 may transmit the temperature acquisition command "7Ch" based on the number of times a predetermined operation is performed. The predetermined operation is, for example, a write operation, an erase operation, or a predetermined operation other than a read operation, a write operation, and an erase operation. Also, the number of times the predetermined operation is performed may be, for example, the number of times any one of the operations such as a read operation, a write operation, and an erase operation is performed.

[0191] Furthermore, although not shown in the figures, the non-volatile memory 100 may comprise multiple chips. In this case, each chip has a configuration substantially equivalent to that of the non-volatile memory in the first embodiment, for example. The NAND interface circuit 250 is configured to communicate independently with each chip of the non-volatile memory 100. As a result, when the non-volatile memory 100 comprises multiple chips, each chip performs operations similar to those of the non-volatile memory in the first to eighth embodiments described above.

[0192] Although several embodiments have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0193] 1...Memory system, 2...Host device, 100...Non-volatile memory, 10...Input / output circuit, 11...Logic control circuit, 12...Status register, 13...Address register, 14...Command register, 15...Programmable logic controller, 16...Ready / busy circuit, 17...Voltage generation circuit, 18...Memory cell array, 19...Driver module, 20...Row decoder module, 21...Sense amplifier module, 22...Data register, 23...Column decoder, 24...Temperature sensor, 25...Buffer, 200...Memory controller, 210...Processor, 220...Buffer memory, 230...Host interface circuit, 240...ECC circuit, 250...NAND interface circuit, 260...Read voltage conversion unit, 270...DRAM interface circuit, 280...Temperature information determination unit, 290...Prohibition period determination unit, 300...Volatile memory, 310...Temperature information, 320...Read voltage information.

Claims

1. A non-volatile memory including multiple memory cells, a temperature sensor that acquires temperature data by temperature measurement, and a buffer that holds the temperature data, The memory controller, Equipped with, When the non-volatile memory performs a first operation based on a first instruction transmitted from the memory controller, The temperature sensor acquires the temperature data that identifies the temperature of the non-volatile memory during the first operation. The buffer holds the temperature data acquired by the temperature sensor as the latest data. It is configured in such a way, The non-volatile memory transmits the temperature data held in the buffer to the memory controller based on a second instruction transmitted from the memory controller. A memory system configured in such a way.

2. The first operation is a read operation, a write operation, or an erase operation in the non-volatile memory. The memory system according to claim 1.

3. The aforementioned temperature sensor is After the first operation is started, the temperature of the non-volatile memory is measured during the first period. It is configured in such a way. The memory system according to claim 1.

4. The memory controller is configured to send the second instruction to the non-volatile memory before sending the first instruction. The memory system according to claim 3.

5. The first operation is a read operation, The aforementioned non-volatile memory is After the non-volatile memory has performed the first operation based on the first instruction, it transmits the temperature data stored in the buffer to the memory controller, in conjunction with the read data from the first operation. It is configured in such a way. The memory system according to claim 4.

6. The aforementioned memory controller The non-volatile memory is configured to transmit the second instruction after it has started executing the first operation based on the first instruction. The memory system according to claim 3.

7. The memory controller includes a temperature information determination unit, The temperature sensor is configured to store first data in the buffer indicating that it cannot output an accurate temperature when measuring the temperature of the non-volatile memory during the first period, and to store the temperature data in the buffer after the first period has elapsed. If the non-volatile memory receives the second instruction from the memory controller within the first period, it transmits the first data to the memory controller. The temperature information determination unit is configured to determine whether the data from the non-volatile memory corresponding to the second instruction is the first data. The aforementioned memory controller When the temperature information determination unit determines that it has received the first data from the non-volatile memory, it transmits the second instruction to the non-volatile memory again. It is configured in such a way. The memory system according to claim 6.

8. The aforementioned memory controller After the first operation is started, a period determination unit is provided to determine whether the first period has elapsed. Including, The aforementioned memory controller When the period determination unit determines that the first period has elapsed, the second instruction is transmitted to the non-volatile memory. It is configured in such a way. The memory system according to claim 3.

9. The system further comprises a volatile memory that stores temperature information relating to the temperature of the non-volatile memory, The aforementioned memory controller The temperature information is updated using the temperature data received from the non-volatile memory. When instructing the non-volatile memory to perform a read operation, the instruction is given to execute the read operation using a read voltage calculated based on the temperature information. The memory system according to claim 1.

10. The non-volatile memory is configured such that data read from the non-volatile memory can be transmitted to the memory controller via the buffer. The memory system according to claim 1.

11. A non-volatile memory including multiple memory cells and a first temperature sensor that acquires temperature data by temperature measurement, The memory controller, Equipped with, If the first condition is met, The memory controller transmits a first instruction to the non-volatile memory to acquire the temperature data. The first temperature sensor acquires the temperature data relating to the temperature of the non-volatile memory based on the first instruction. The non-volatile memory transmits the acquired temperature data to the memory controller. It is configured in such a way. Memory system.

12. The first condition is that the following processes have been executed: a power-off process for the non-volatile memory, a standby process for the non-volatile memory, a power-on process for the non-volatile memory whose power has been cut off, or a recovery process for the non-volatile memory in standby mode. The memory system according to claim 11.

13. The memory controller is configured to determine whether the first period elapsed since the start of time counting is less than a predetermined second period. The first condition is that the memory controller determines that the first period is equal to or greater than the second period. When the memory controller determines that the first period is equal to or greater than the second period, it resets the first period and starts counting time again. The memory system according to claim 11.

14. The memory controller is configured to determine whether the first number of times the first operation has been performed is less than a predetermined second number of times. The first condition is that the memory controller determines that the first number of times is equal to or greater than the second number of times. When the memory controller determines that the first count is equal to or greater than the second count, it resets the first count and starts counting the first count again. The memory system according to claim 11.

15. The first operation is a read operation, a write operation, or an erase operation in the non-volatile memory, or any one of these operations. The memory system according to claim 14.

16. The memory controller includes a second temperature sensor that acquires temperature data by temperature measurement, and is configured to detect temperature changes based on the temperature measurement of the second temperature sensor. The first condition is that the memory controller detects the temperature change. The memory system according to claim 11.

17. The memory controller is configured to count the number of fail bits in the read operation of data stored in the non-volatile memory, The first condition is that the counted number of fail bits is greater than a predetermined value. The memory system according to claim 11.

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