Semiconductor equipment

Abstract

To provide semiconductor devices that can reduce leakage current. [Solution] The semiconductor device comprises a substrate, a nitride semiconductor layer having a first layer and a second layer provided on the first layer having a wider band gap than the first layer, a source electrode, a drain electrode, a gate electrode located between the source electrode and the drain electrode in a first direction, and an insulating film provided between the gate electrode and the nitride semiconductor layer. The nitride semiconductor layer has a p-type semiconductor layer. The p-type semiconductor layer has a connection portion connected to the source electrode and an extended portion extending from the connection portion in a first direction within the nitride semiconductor layer. The extended portion is located between the first interface between the first layer and the second layer and the second interface between the substrate and the nitride semiconductor layer, and is not in contact with the first interface or the second interface. The end of the extended portion away from the connection portion in the first direction is located between the position of the gate electrode and the position of the drain electrode in the first direction.

Description

Technical Field

[0001] The embodiment relates to a semiconductor device.

Background Art

[0002] As a power device, a HEMT (High Electron Mobility Transistor) using a gallium nitride-based material is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The embodiment provides a semiconductor device capable of reducing leakage current.

Means for Solving the Problems

[0005] According to the embodiment, the semiconductor device includes a substrate, a nitride semiconductor layer provided on the substrate, the nitride semiconductor layer having a first layer and a second layer provided on the first layer and having a wider band gap than the first layer, a source electrode provided on the nitride semiconductor layer and in contact with the nitride semiconductor layer, a drain electrode located away from the source electrode in a first direction and provided on the nitride semiconductor layer and in contact with the nitride semiconductor layer, a gate electrode located between the source electrode and the drain electrode in a first direction, and an insulating film provided between the gate electrode and the nitride semiconductor layer. The nitride semiconductor layer comprises a p-type semiconductor layer, the p-type semiconductor layer having a connection portion connected to the source electrode, and an extended portion extending in the first direction from the connection portion within the nitride semiconductor layer, the extended portion being located between a first interface between the first layer and the second layer and a second interface between the substrate and the nitride semiconductor layer, and not in contact with the first interface and the second interface, and the end of the extended portion away from the connection portion in the first direction being located between the position of the end of the gate electrode on the drain electrode side and the position of the end of the drain electrode on the gate electrode side in the first direction. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic cross-sectional view of a semiconductor device according to the first embodiment. [Figure 2] This is a schematic cross-sectional view of a semiconductor device according to the second embodiment. [Figure 3] This is a schematic cross-sectional view of a semiconductor device according to the third embodiment. [Figure 4] This is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 5] This is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment. [Figure 6] This is a schematic plan view showing the arrangement of the main components in the semiconductor device according to the fifth embodiment. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings. Note that the same components are denoted by the same reference numerals in each drawing.

[0008] [First Embodiment] As shown in Figure 1, the semiconductor device 1 according to the first embodiment comprises a substrate 100 and a nitride semiconductor layer 10 provided on the substrate 100.

[0009] For example, a p-type silicon substrate can be used as the substrate 100. A potential of 0V may be applied to the substrate 100.

[0010] Two directions intersecting each other in a plane parallel to the surface of the substrate 100 are defined as the first direction X and the second direction Y. In this example, the first direction X and the second direction Y are orthogonal to each other. The direction orthogonal to the first direction X and the second direction Y is defined as the third direction Z. In the third direction Z, the direction from the substrate 100 toward the nitride semiconductor layer 10 is defined as upward. The direction from the nitride semiconductor layer 10 toward the substrate 100 is defined as downward.

[0011] The nitride semiconductor layer 10 has a first layer 11 and a second layer 12 provided on the first layer 11. In the third direction Z, the first layer 11 is located between the substrate 100 and the second layer 12. The band gap of the second layer 12 is wider than the band gap of the first layer 11. For example, the first layer 11 is an n-type gallium nitride (GaN) layer, and the second layer 12 is an undoped aluminum gallium nitride (AlGaN) layer. Due to the piezoelectric polarization effect, a two-dimensional electron gas 200 is distributed near the interface (first interface) S1 between the first layer 11 and the second layer 12. The thickness of the second layer 12 is thinner than the thickness of the first layer 11. The first layer 11 may also be an undoped GaN layer. The composition ratio of Al to Ga in the AlGaN layer of the second layer 12 is arbitrary.

[0012] The nitride semiconductor layer 10 may further have a buffer layer 13. The buffer layer 13 is located between the substrate 100 and the first layer 11 in the third direction Z. The buffer layer 13 mitigates lattice mismatch between the substrate 100 and the first layer 11. The buffer layer 13 can be, for example, a carbon or iron-doped GaN layer, a superlattice structure of a GaN layer and an AlGaN layer, or a combination thereof.

[0013] The semiconductor device 1 further comprises a source electrode 31, a drain electrode 32, and a gate electrode 33, all provided on a nitride semiconductor layer 10. The source electrode 31, gate electrode 33, and drain electrode 32 extend in a third direction Y.

[0014] The source electrode 31 and the drain electrode 32 are in contact with the nitride semiconductor layer 10. The source electrode 31 and the drain electrode 32 are in ohmic contact with the nitride semiconductor layer 10. In the example shown in Figure 1, the source electrode 31 and the drain electrode 32 are in contact with the second layer 12.

[0015] The source electrode 31 and the drain electrode 32 are located apart in a first direction X. The gate electrode 33 is located between the source electrode 31 and the drain electrode 32 in a first direction X. The distance in a first direction X between the end 32A of the drain electrode 32 on the gate electrode 33 side and the end 33B of the gate electrode 33 on the drain electrode 32 side is longer than the distance in a first direction X between the end 31A of the source electrode 31 on the gate electrode 33 side and the end 33A of the gate electrode 33 on the source electrode 31 side.

[0016] The semiconductor device 1 further includes an insulating film 41 provided on the nitride semiconductor layer 10 between the source electrode 31 and the drain electrode 32. The insulating film 41 is provided between the gate electrode 33 and the nitride semiconductor layer 10, and the gate electrode 33 is not in contact with the nitride semiconductor layer 10. For example, a silicon nitride film can be used as the insulating film 41.

[0017] The semiconductor device 1 further includes a protective film 42. The protective film 42 is provided on the insulating film 41 and covers a part of the source electrode 31 and a part of the drain electrode 32. Also, the protective film 42 covers the gate electrode 33. As the protective film 42, for example, a silicon oxide film or a silicon nitride film can be used.

[0018] The semiconductor device 1 further includes a gate field plate electrode 36 and a source field plate electrode 35. The gate field plate electrode 36 is connected to a part of the upper surface of the gate electrode 33 and extends in the protective film 42 toward the drain electrode 32 side. The source field plate electrode 35 is connected to the upper surface of the source electrode 31 and extends on the protective film 42 toward the drain electrode 32 side. The gate field plate electrode 36 and the source field plate electrode 35 suppress the current collapse phenomenon.

[0019] In the first direction X, the position of the end 36A of the gate field plate electrode 36 on the drain electrode 32 side is located between the position of the end 33B of the gate electrode 33 on the drain electrode 32 side and the end 32A of the drain electrode 32 on the gate electrode 33 side. In the first direction X, the position of the end 35A of the source field plate electrode 35 on the drain electrode 32 side is located between the position of the end 36A of the gate field plate electrode 36 on the drain electrode 32 side and the end 32A of the drain electrode 32 on the gate electrode 33 side.

[0020] The nitride semiconductor layer 10 has a p-type semiconductor layer 20 containing, for example, magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 20 has a connection portion 21 connected to the source electrode 31 and an extension portion 22 extending in the nitride semiconductor layer 10 in the first direction X from the connection portion 21.

[0021] The connection portion 21 contacts the lower surface of the source electrode 31 and extends downward from the lower surface of the source electrode 31 into the nitride semiconductor layer 10.

[0022] The stretched portion 22 is located between the first interface S1 between the first layer 11 and the second layer 12 and the second interface S2 between the substrate 100 and the nitride semiconductor layer 10. In the example shown in Figure 1, the stretched portion 22 is located within the first layer 11. The stretched portion 22 does not come into contact with the first interface S1 or the two-dimensional electron gas 200 distributed within the first layer 11. Furthermore, the stretched portion 22 does not come into contact with the second interface S2 between the substrate 100 and the nitride semiconductor layer 10.

[0023] The extended portion 22 extends from the connection portion 21 toward the drain electrode 32 in a first direction X, beyond the position of the gate electrode 33. The end 23 of the extended portion 22 away from the connection portion 21 in the first direction X is located between the position of the drain electrode 32-side end 33B of the gate electrode 33 and the position of the gate electrode 33-side end 32A of the drain electrode 32. The position of the end 23 of the extended portion 22 in the first direction X is between the position of the drain electrode 32-side end 33B of the gate electrode 33 and the position of the gate electrode 33-side end 32A of the drain electrode 32. In the first direction X, the end 23 of the extended portion 22 is located in the nitride semiconductor layer 10 below the region between the gate electrode 33 and the drain electrode 32.

[0024] When a first potential (for example, several hundred volts) is applied to the drain electrode 32, a second potential (for example, 0 volts) lower than the first potential is applied to the source electrode 31, and a gate voltage above a threshold is applied to the gate electrode 33, a current flows between the drain electrode 32 and the source electrode 31 through the two-dimensional electron gas 200, and the semiconductor device 1 turns on.

[0025] When a potential lower than the threshold (for example, around -10V) is applied to the gate electrode 33, the two-dimensional electron gas 200 below the gate electrode 33 is blocked, and the semiconductor device 1 is turned off.

[0026] In the off state described above, a large number of holes are likely to be generated in the nitride semiconductor layer 10 due to impact ionization near the end 32A of the drain electrode 32 where the electric field is strong. These holes flow through the nitride semiconductor layer 10 toward the source electrode 31 and the gate electrode 33. In particular, since the potential of the gate electrode 33 in the off state (for example, around -10V) is lower than the potential of the source electrode 31 (for example, 0V), holes tend to accumulate below the gate electrode 33. This reduces the influence of the potential provided by the gate electrode 33 to block the two-dimensional electron gas 200, causing electrons to flow from the source electrode 31 toward the drain electrode 32 and generating positive feedback that promotes impact ionization near the drain electrode 32. As a result, the leakage current increases. Furthermore, the above feedback generates a large amount of hot carriers, reducing reliability.

[0027] According to this embodiment, by providing a p-type semiconductor layer 20 connected to the source electrode 31 within the nitride semiconductor layer 10, holes generated by impact ionization can be easily discharged to the source electrode 31 via the p-type semiconductor layer 20. This suppresses the accumulation of holes generated by impact ionization below the gate electrode 33, thereby reducing leakage current and improving reliability.

[0028] In this embodiment, the stretched portion 22 of the p-type semiconductor layer 20 is located within the first layer 11 and is not in contact with the first interface S1 between the first layer 11 and the second layer 12. Furthermore, the stretched portion 22 is not in contact with the two-dimensional electron gas 200 distributed within the first layer 11. As a result, the p-type semiconductor layer 20 does not affect the on-resistance.

[0029] Furthermore, the stretched portion 22 of the p-type semiconductor layer 20 is not provided on the substrate 100, but is located within the nitride semiconductor layer 10. This makes it easier to discharge holes generated by impact ionization near the edge 32A of the drain electrode 32 to the source electrode 31 via the p-type semiconductor layer 20, compared to when the p-type semiconductor layer 20 is located on the substrate 100.

[0030] If the end 23 of the extended portion 22 extends to a position that overlaps below the drain electrode 32, it will lead to a decrease in breakdown voltage. Also, if the end 23 of the extended portion 22 does not extend further toward the drain electrode 32 than the end 33B of the gate electrode 33 on the drain electrode 32 side, holes generated by impact ionization tend to flow toward the gate electrode 33 and tend to accumulate below the gate electrode 33. According to this embodiment, the end 23 of the extended portion 22 is located between the position of the end 33B of the gate electrode 33 on the drain electrode 32 side and the position of the end 32A of the drain electrode 32 on the gate electrode 33 side in the first direction X. This makes it possible to suppress a decrease in breakdown voltage while facilitating the discharge of holes generated by impact ionization to the source electrode 31 via the p-type semiconductor layer 20.

[0031] To promote the removal of holes generated by impact ionization, the p-type impurity concentration in the p-type semiconductor layer 20 is set to 1 × 10⁻⁶ 15 cm -3 The above is preferable.

[0032] Other embodiments will be described below. The other embodiments will primarily be described in terms of their configurations that differ from the first embodiment described above.

[0033] [Second Embodiment] As shown in Figure 2, the semiconductor device 2 according to the second embodiment, the stretched portion 22 of the p-type semiconductor layer 20 may be located within the buffer layer 13. The buffer layer 13 is located further from the end 32A of the drain electrode 32 in the third direction Z than the first layer 11. Therefore, it is preferable that the end 23 of the stretched portion 22 located within the buffer layer 13 is located closer to the drain electrode 32 in the first direction X than the end 23 of the stretched portion 22 located within the first layer 11. This makes it easier to discharge holes generated by impact ionization near the end 32A of the drain electrode 32 to the source electrode 31 via the p-type semiconductor layer 20.

[0034] [Third Embodiment] As shown in Figure 3, the semiconductor device 3 according to the third embodiment, the extended portion of the p-type semiconductor layer 20 may have a first extended portion 22A located in the first layer 11 and a second extended portion 22B located in the buffer layer 13. The first extended portion 22A extends from the connection portion 21 through the first layer 11 in a first direction X, and the second extended portion 22B extends from the connection portion 21 through the buffer layer 13 in a first direction X.

[0035] The end 23B of the second extension portion 22B, away from the connection portion 21 in the first direction X, is located closer to the drain electrode 32 in the first direction X than the end 23A of the first extension portion 22A, away from the connection portion 21 in the first direction X. This makes it easier to discharge holes generated by impact ionization near the end 32A of the drain electrode 32 to the source electrode 31 via the first extension portion 22A and the second extension portion 22B.

[0036] [Fourth Embodiment] As shown in Figure 4, the semiconductor device 4 according to the fourth embodiment, the stretched portion 22 of the p-type semiconductor layer 20 may be located within the second layer 12. The stretched portion 22 extends from the connection portion 21 through the second layer 12 in a first direction X. The stretched portion 22 does not contact the first interface S1 between the first layer 11 and the second layer 12. Furthermore, the stretched portion 22 does not contact the two-dimensional electron gas 200. As a result, the p-type semiconductor layer 20 does not affect the on-resistance.

[0037] Furthermore, the end 23 of the extended portion 22, away from the connection portion 21 in the first direction X, is located between the position of the end 31A of the source electrode 31 on the gate electrode 33 side and the position of the end 33A of the gate electrode 33 on the source electrode 31 side in the first direction X. The position of the end 23 of the extended portion 22 in the first direction X is between the position of the end 31A of the source electrode 31 on the gate electrode 33 side and the position of the end 33A of the gate electrode 33 on the source electrode 31 side in the first direction X. In the first direction X, the end 23 of the extended portion 22 is located in the nitride semiconductor layer 10 below the region between the source electrode 31 and the gate electrode 33.

[0038] The second layer 12 is the uppermost layer of the nitride semiconductor layer 10 and is closer to the gate electrode 33 in the third direction Z than the other layers. By positioning the end 23 of the stretched portion 22 as described above, the stretched portion 22 located in the second layer 12 can be prevented from reducing the influence of the potential provided by the gate electrode 33 for blocking the two-dimensional electron gas 200. As a result, the semiconductor device 4 can be turned off by controlling the gate electrode 33.

[0039] [Fifth Embodiment] The semiconductor device 5 according to the fifth embodiment shown in Figure 5 further comprises a negative electrode 34 provided on the nitride semiconductor layer 10. The negative electrode 34 is provided, for example, on the second layer 12. The negative electrode 34 is supplied with a negative potential that is different from the potential of the source electrode 31.

[0040] The connection portion 21 of the p-type semiconductor layer 20 is connected to the negative electrode 34, not the source electrode 31. A potential lower than the potential applied to the gate electrode 33 in the off state (e.g., -20V) can be applied to the negative electrode 34. This can further promote the discharge of holes generated by impact ionization to the negative electrode 34 via the p-type semiconductor layer 20.

[0041] As shown in Figure 6, for example, the negative electrode 34 is located in the terminal region 302 outside the cell region 301 where the source electrode 31, gate electrode 33, and drain electrode 32 are arranged. This ensures that the negative electrode 34 does not affect the layout of the source electrode 31, gate electrode 33, and drain electrode 32 in the cell region 301. For example, the negative electrode 34 is located in each of the two terminal regions 302 that are situated on either side of the cell region 301 in the third direction Y. The connection portion 21 of the p-type semiconductor layer 20 is connected to the lower surfaces of the two negative electrodes 34 in the terminal region 302 and extends in the third direction Y. The extension portion 22 of the p-type semiconductor layer 20 extends from the connection portion 21 in the first direction X and is located in the cell region 301.

[0042] The negative electrode 34 may be placed on the nitride semiconductor layer 10 of the cell region 301.

[0043] The embodiments described above can be combined in any way, within the limits of what is not technically contradictory.

[0044] For example, any of the p-type semiconductor layers 20 from the first to fourth embodiments can be used as the p-type semiconductor layer 20 connected to the negative electrode 34 in the fifth embodiment.

[0045] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0046] 1-5... Semiconductor device, 10... Nitride semiconductor layer, 11... First layer, 12... Second layer, 13... Buffer layer, 20... p-type semiconductor layer, 21... Connection part, 22... Stretched part, 22A... First stretched part, 22B... Second stretched part, 31... Source electrode, 32... Drain electrode, 33... Gate electrode, 34... Negative electrode, 35... Source field plate electrode, 36... Gate field plate electrode, 41... Insulating film, 42... Protective film, 100... Substrate, 200... Two-dimensional electron gas, 301... Cell region, 302... Termination region, S1... First interface, S2... Second interface

Claims

1. circuit board and A nitride semiconductor layer provided on the substrate, comprising a first layer and a second layer provided on the first layer and having a wider band gap than the first layer, A source electrode provided on the nitride semiconductor layer and in contact with the nitride semiconductor layer, A drain electrode is located away from the source electrode in the first direction, provided on the nitride semiconductor layer, and in contact with the nitride semiconductor layer. In the first direction, a gate electrode located between the source electrode and the drain electrode, An insulating film is provided between the gate electrode and the nitride semiconductor layer, Equipped with, The nitride semiconductor layer has a p-type semiconductor layer, The p-type semiconductor layer has a connection portion connected to the source electrode and an extended portion extending from the connection portion in the nitride semiconductor layer in the first direction. The stretched portion is located between the first interface between the first layer and the second layer and the second interface between the substrate and the nitride semiconductor layer, and is not in contact with the first interface and the second interface. A semiconductor device wherein the end of the extended portion away from the connection portion in the first direction is located between the position of the end of the gate electrode on the drain electrode side and the position of the end of the drain electrode on the gate electrode side in the first direction.

2. The extended portion is located in the first layer, as described in claim 1.

3. The nitride semiconductor layer further comprises a buffer layer provided between the substrate and the first layer. The semiconductor device according to claim 1, wherein the extended portion is located in the buffer layer.

4. The nitride semiconductor layer further comprises a buffer layer provided between the substrate and the first layer. The stretched portion comprises a first stretched portion located in the first layer and a second stretched portion located in the buffer layer. The semiconductor device according to claim 1, wherein the end of the second extension portion away from the connection portion in the first direction is located closer to the drain electrode in the first direction than the end of the first extension portion away from the connection portion in the first direction.

5. circuit board and A nitride semiconductor layer provided on the substrate, comprising a first layer and a second layer provided on the first layer and having a wider band gap than the first layer, A source electrode provided on the nitride semiconductor layer and in contact with the nitride semiconductor layer, A drain electrode is located away from the source electrode in the first direction, provided on the nitride semiconductor layer, and in contact with the nitride semiconductor layer. In the first direction, a gate electrode located between the source electrode and the drain electrode, An insulating film is provided between the gate electrode and the nitride semiconductor layer, Equipped with, The nitride semiconductor layer has a p-type semiconductor layer, The p-type semiconductor layer has a connection portion connected to the source electrode and an extended portion extending from the connection portion in the nitride semiconductor layer in the first direction. The extended portion is located in the second layer, A semiconductor device wherein the end of the extended portion away from the connection portion in the first direction is located between the position of the gate electrode side end of the source electrode and the position of the source electrode side end of the gate electrode in the first direction.

6. circuit board and A nitride semiconductor layer provided on the substrate, comprising a first layer and a second layer provided on the first layer and having a wider band gap than the first layer, A source electrode provided on the nitride semiconductor layer and in contact with the nitride semiconductor layer, A drain electrode is located away from the source electrode in the first direction, provided on the nitride semiconductor layer, and in contact with the nitride semiconductor layer. In the first direction, a gate electrode located between the source electrode and the drain electrode, An insulating film is provided between the gate electrode and the nitride semiconductor layer, A negative electrode provided on the nitride semiconductor layer to which a negative potential is applied, Equipped with, The nitride semiconductor layer has a p-type semiconductor layer connected to the negative electrode.

7. The p-type semiconductor layer has a connection portion connected to the negative electrode and an extended portion extending from the connection portion in the nitride semiconductor layer in the first direction. The stretched portion is located between the first interface between the first layer and the second layer and the second interface between the substrate and the nitride semiconductor layer, and is not in contact with the first interface and the second interface. The semiconductor device according to claim 6, wherein the end of the extension portion away from the connection portion in the first direction is located in the region between the position of the end of the gate electrode on the drain electrode side and the position of the end of the drain electrode on the gate electrode side in the first direction.

8. The semiconductor device according to claim 6, wherein the negative electrode is located in a terminal region outside the cell region in which the source electrode, the gate electrode, and the drain electrode are arranged.

9. The semiconductor device according to any one of claims 1 to 8, wherein the extended portion does not come into contact with the two-dimensional electron gas distributed in the first layer.

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