Dresser and method for manufacturing the same

Abstract

The present invention provides a dresser capable of creating a suitable protrusion for dressing, and a method for manufacturing the same. [Solution] According to one embodiment, the dresser comprises a substrate. The dresser further comprises a first layer provided on the substrate. The dresser further comprises one or more protrusions provided on the substrate or the first layer, having an upper end higher than the upper surface of the first layer and having a different composition from the first layer. The dresser further comprises a second layer provided on the one or more protrusions.

Description

Technical Field

[0001] Embodiments of the present invention relate to a dresser and a method for manufacturing the same.

Background Art

[0002] In a polishing apparatus such as a CMP (Chemical Mechanical Polishing) apparatus, the surface of a polishing pad may be dressed using a dresser having a plurality of convex portions (protrusions) on a substrate. In this case, a problem is how to form these convex portions.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a dresser and a method for manufacturing the same that can realize suitable convex portions for dressing.

Means for Solving the Problems

[0005] According to one embodiment, a dresser includes a substrate. The dresser further includes a first layer provided on the substrate. The dresser further includes one or more convex portions provided on the substrate or the first layer, having an upper end higher than the upper surface of the first layer and having a composition different from that of the first layer. The dresser further includes a second layer provided on the one or more convex portions.

Brief Description of the Drawings

[0006] [Figure 1]This is a perspective view showing the configuration of the polishing apparatus according to the first embodiment. [Figure 2] This is a perspective view showing the structure of the dresser according to the first embodiment. [Figure 3] This is a cross-sectional view showing the structure of the chip according to the first embodiment. [Figure 4] This is a plan view showing the structure of the chip according to the first embodiment. [Figure 5] This is a plan view showing the structure of a chip of a modified example of the first embodiment. [Figure 6] This is a cross-sectional view (1 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 7] This is a cross-sectional view (2 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 8] This is a cross-sectional view (3 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 9] This is a cross-sectional view (4 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 10] This is a cross-sectional view (5 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 11] This is a cross-sectional view (6 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 12] This is a cross-sectional view (7 / 7) showing the manufacturing method of the chip according to the first embodiment. [Figure 13] These are a plan view and a perspective view showing the manufacturing method of the dresser according to the first embodiment. [Figure 14] This is a plan view showing the manufacturing method of the chip according to the first embodiment. [Figure 15] This is a plan view showing a modified example of the chip manufacturing method of the first embodiment. [Figure 16] This is a cross-sectional view showing the structure of a comparative example chip of the first embodiment. [Figure 17] This is a cross-sectional view (1 / 4) showing the manufacturing method of a comparative example chip of the first embodiment. [Figure 18] This is a cross-sectional view (2 / 4) showing the manufacturing method of a comparative example chip of the first embodiment. [Figure 19]Cross-sectional view (3 / 4) showing the manufacturing method of the chip of the comparative example of the first embodiment. [Figure 20] Cross-sectional view (4 / 4) showing the manufacturing method of the chip of the comparative example of the first embodiment. [Figure 21] Cross-sectional view showing the structure of the chip of the second embodiment. [Figure 22] Plan view showing the structure of the chip of the second embodiment. [Figure 23] Cross-sectional view showing the manufacturing method of the chip of the second embodiment. [Figure 24] Plan view showing the manufacturing method of the chip of the second embodiment. [Figure 25] Plan view showing various examples of the manufacturing method of the chip of the third embodiment. [Figure 26] Plan view showing the manufacturing method of the chip of the fourth embodiment. [Figure 27] Plan view showing the manufacturing method of the chip of the modified example of the fourth embodiment. [Figure 28] Cross-sectional view (1 / 3) showing the manufacturing method of the chip of the fourth embodiment. [Figure 29] Cross-sectional view (2 / 3) showing the manufacturing method of the chip of the fourth embodiment. [Figure 30] Cross-sectional view (3 / 3) showing the manufacturing method of the chip of the fourth embodiment. [Figure 31] Cross-sectional view (1 / 3) showing the manufacturing method of the chip of the modified example of the first embodiment. [Figure 32] Cross-sectional view (2 / 3) showing the manufacturing method of the chip of the modified example of the first embodiment. [Figure 33] Cross-sectional view (3 / 3) showing the manufacturing method of the chip of the modified example of the first embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 33, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) Figure 1 is a perspective view showing the configuration of the polishing apparatus 10 of the first embodiment. The polishing apparatus 10 is, for example, a CMP apparatus.

[0009] The polishing apparatus 10 comprises a polishing table 11, a dressing mechanism 12, a polishing head 13, a slurry supply unit 14, and a control unit 15.

[0010] Figure 1 shows the X, Y, and Z directions perpendicular to each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0011] The polishing table 11 holds and rotates the polishing pad 1. In Figure 1, the polishing table 11 holds the polishing pad 1 so that its surface faces the +Z direction, and rotates the polishing pad 1 in the XY plane.

[0012] The dressing mechanism 12 dresses (sharpens) the polishing pad 1 with the dresser 2. In Figure 1, the dressing mechanism 12 holds the dresser 2 so that its surface faces the -Z direction, and brings the surface of the dresser 2 into contact with the surface of the polishing pad 1. As a result, the surface of the polishing pad 1 is dressed by the dresser 2.

[0013] The polishing head 13 holds the wafer 3 to be polished by the polishing pad 1. In Figure 1, the polishing head 13 holds the wafer 3 so that its surface faces the -Z direction, and brings the surface of the wafer 3 into contact with the surface of the polishing pad 1. As a result, the surface of the wafer 3 is polished by the polishing pad 1. The wafer 3 is used, for example, to manufacture multiple semiconductor devices (semiconductor chips).

[0014] The slurry supply unit 14 supplies slurry 4 to the polishing pad 1. In the polishing apparatus 10, the slurry supply unit 14 supplies slurry 4 to the surface of the polishing pad 1, the polishing table 11 rotates the polishing pad 1, and the polishing head 13 brings the surface of the wafer 3 into contact with the surface of the polishing pad 1. As a result, the surface of the wafer 3 is polished by the polishing pad 1 to which the slurry 4 has been supplied.

[0015] The control unit 15 controls the operation of the polishing apparatus 10. For example, the control unit 15 controls the rotation of the polishing pad 1 by the polishing table 11, the movement of the dresser 2 by the dressing mechanism 12, the movement of the wafer 3 by the polishing head 13, and the supply of slurry 4 from the slurry supply unit 14.

[0016] Figure 2 is a perspective view showing the structure of the dresser 2 of the first embodiment.

[0017] The dresser 2 comprises a base plate 21 and one or more chips 22. The base plate 21 is an example of a chip holding member. Each chip 22 is an example of a first chip.

[0018] In Figure 2, the base plate 21 has an annular shape, and one or more tips 22 are arranged in an annular pattern on the working surface of the base plate 21. The working surface of the base plate 21 is the surface that faces the polishing pad 1 in Figure 1. In Figure 2, the dresser 2 is positioned so that the working surface of the base plate 21 is the upper surface of the base plate 21, but in Figure 1, it is held so that the working surface of the base plate 21 is the lower surface of the base plate 21. In this embodiment, the surface of the polishing pad 1 is dressed by each tip 22.

[0019] The base metal 21 is made of, for example, stainless steel (SUS) or iron. Each chip 22 is manufactured, for example, from a wafer 22' (see Figure 13(a)) described later. In Figure 2, there are 12 chips 22 on the base metal 21, but other numbers are also acceptable. However, in order to uniformly dress the polishing pad 1, it is desirable that there be two or more chips 22 on the base metal 21, and that the arrangement of the chips 22 on the base metal 21 be symmetrical.

[0020] Figure 3 is a cross-sectional view showing the structure of the chip 22 of the first embodiment.

[0021] Figure 3 shows one of the one or more chips 22 shown in Figure 2. Each chip 22 in this embodiment has the structure shown in Figure 3. The chip 22 shown in Figure 3 comprises a substrate 31, a stopper layer 32, one or more protrusions (projections) 33, and a thin film 34. The stopper layer 32 is an example of a first layer. Each protrusion 33 is an example of a first protrusion. The thin film 34 is an example of a second layer.

[0022] Further details of the chip 22 of this embodiment will be described below with reference to Figure 3. Figures 4 and 5 will also be referenced as appropriate in this description. Figure 4 is a plan view showing the structure of the chip 22 of the first embodiment. Figure 5 is a plan view showing the structure of a modified example of the chip 22 of the first embodiment. Figure 3 shows a longitudinal section (XZ section) along the line X-X' shown in Figures 4 and 5.

[0023] [Circuit board 31] The substrate 31 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Figure 3 shows the front surface S1 and back surface S2 of the substrate 31. In Figure 3, the front surface S1 and back surface S2 of the substrate 31 are parallel to the X and Y directions and perpendicular to the Z direction. The chip 22 shown in Figure 3 is placed on the base metal 21 such that the back surface S2 of the substrate 31 faces the working surface of the base metal 21. The substrate 31 is, for example, a Si substrate with a (111) plane.

[0024] [Stopper layer 32] The stopper layer 32 is formed on the substrate 31. The stopper layer 32 is an insulating film such as an SiO2 film (silicon oxide film) or a SiN film (silicon nitride film). However, the stopper layer 32 may be an insulating film other than an SiO2 film or a SiN film, or it may be a material other than an insulating film. The thickness of the stopper layer 32 is, for example, 20 to 30 μm. The stopper layer 32 in this embodiment is used as an etching stopper during etching, which will be described later.

[0025] The stopper layer 32 has one or more recesses (openings) 32a. These recesses 32a are arranged in a square grid shape, for example (Figure 4). However, these recesses 32a may be arranged in other grid shapes, for example, a triangular grid shape (Figure 5). Figures 4 and 5 show the pitch P between these recesses 32a. The pitch P is, for example, 200 to 400 μm. Each recess 32a is formed to penetrate the stopper layer 32, as shown in Figure 3.

[0026] [Protrusion 33] Each protrusion 33 is formed on the substrate 31 and the stopper layer 32, and has an upper end higher than the upper surface of the stopper layer 32. Therefore, each protrusion 33 protrudes in the +Z direction relative to the upper surface of the stopper layer 32. Each protrusion 33 is, for example, a semiconductor layer such as a silicon layer. In this embodiment, each protrusion 33 is formed by epitaxial growth from the substrate 31, as will be described later. Therefore, the substrate 31 and each protrusion 33 in this embodiment are formed from the same semiconductor material (for example, silicon). This silicon is, for example, single-crystal silicon.

[0027] In this embodiment, each protrusion 33 has a different composition from the stopper layer 32. In this embodiment, each protrusion 33 is, for example, a silicon layer, and the stopper layer 32 is, for example, an SiO2 film or a SiN film. This makes it possible to use the stopper layer 32 as an etching stopper when forming each protrusion 33 from the growth layer 33' described later.

[0028] Each protrusion 33 includes a lower portion 33a and an upper portion 33b. The lower portion 33a is an example of a first portion. The upper portion 33b is an example of a second portion.

[0029] In each protrusion 33, the lower portion 33a is formed on the substrate 31 within a single recess 32a. Therefore, the lower portion 33a is in contact with the surface S1 of the substrate 31. The lower portion 33a in this embodiment has a cylindrical shape, and therefore has a circular shape in plan view and a rectangular (e.g., rectangular) vertical cross-sectional shape. Figure 4 shows the diameter D1 of the lower portion 33a.

[0030] In each protrusion 33, the upper portion 33b is formed on the lower portion 33a and the stopper layer 32. Therefore, the upper portion 33b has an upper end that is higher than the upper surface of the stopper layer 32. In this embodiment, the upper portion 33b has a conical shape, and therefore has a circular shape in plan view and a triangular (e.g., isosceles triangle) vertical cross-sectional shape. In this case, the upper end of each protrusion 33 (the upper end of the upper portion 33b) is the vertex of the cone. Figure 4 shows the diameter D2 of the upper portion 33b. In this embodiment, the diameter D2 is larger than the diameter D1. As a result, in each protrusion 33, the area of ​​the upper portion 33b in plan view is (π × D2 2 ) is the area of ​​the lower part 33a in plan view (π × D1 2 It is larger than ). Also, in each convex portion 33 shown in Figure 3, the width of the upper portion 33b in the X direction is longer than the width of the lower portion 33a in the X direction. The diameter D2 is, for example, 200 to 400 μm.

[0031] Figure 3 shows the thickness T1 of each protrusion 33, the thickness T2 of the lower portion 33a of each protrusion 33, and the thickness T3 of the upper portion 33b of each protrusion 33 (T1 = T2 + T3). The thickness T2 is, for example, 20 to 30 μm. The thickness T3 is, for example, 100 to 150 μm. In Figure 3, the thickness T3 is greater than the thickness T2, but it may also be less than the thickness T2.

[0032] The chip 22 shown in Figure 3 comprises one or more recesses 32a and one or more protrusions 33 that correspond one-to-one. In Figure 4, since the recesses 32a are arranged in a square grid shape, the protrusions 33 are also arranged in a square grid shape. In Figure 4, the pitch between the protrusions 33 is equal to the pitch P between the recesses 32a.

[0033] [Thin film 34] The thin film 34 is formed on each of the protrusions 33. In this embodiment, the thin film 34 is formed continuously on the stopper layer 32 and one or more protrusions 33. The thin film 34 is, for example, a carbon (C) layer such as a diamond layer. In this embodiment, the thickness of the thin film 34 is smaller than the thicknesses T2 and T3.

[0034] As described above, the dresser 2 of this embodiment includes one or more protrusions 33 provided on the substrate 31 via a stopper layer 32, and these protrusions 33 are covered with a thin film 34. The dresser 2 of this embodiment dresses the polishing pad 1 with these protrusions 33 (and thin film 34).

[0035] Figures 6 to 12 are cross-sectional views showing the manufacturing method of the chip 22 according to the first embodiment.

[0036] First, a stopper layer 32 is formed on the substrate 31 (Figure 6). The stopper layer 32 is formed, for example, by CVD (Chemical Vapor Deposition). Note that the substrate 31 shown in Figure 6 is not the substrate 31 in the state of the chip 22, but the substrate 31 in the state of the wafer 22' (see Figure 13(a)). This is also the case in Figures 7 to 12, which will be described later.

[0037] Next, one or more recesses 32a are formed within the stopper layer 32 by lithography and RIE (Reactive Ion Etching) (Figure 7). As a result, the surface S1 of the substrate 31 is exposed within each recess 32a.

[0038] Next, a growth layer 33' is formed on the substrate 31 and the stopper layer 32, and the surface of the growth layer 33' is planarized by CMP (Figure 8). The growth layer 33' is formed, for example, by epitaxial growth from the substrate 31. The growth layer 33' is formed to include one or more lower portions 33a' and an upper portion 33b'. Each lower portion 33a' is formed on the substrate 31 within a single recess 32a. The upper portion 33b' is formed on one or more lower portions 33a' and the stopper layer 32. The growth layer 33' is, for example, a semiconductor layer such as a silicon layer. The growth layer 33' is an example of a third layer.

[0039] Next, a mask layer 35 is formed on the growth layer 33' (Figure 9). In Figure 9, the mask layer 35 includes a lower mask layer 41 formed on the growth layer 33' and an upper mask layer 42 formed on the lower mask layer 41. The lower mask layer 41 is, for example, a TEOS (tetraethyl orthosilicate) layer formed by CVD. The lower mask layer 41 may also be an SiO2 layer or a carbon layer formed by plasma CVD. The upper mask layer 42 is, for example, a resist layer. Mask layer 35 is an example of a fourth layer.

[0040] Next, the mask layer 35 is processed by lithography and RIE (Figure 10). In Figure 10, one or more mask portions 35a are formed from the mask layer 35 by forming an opening 35b within the mask layer 35. As a result, the surface of the growth layer 33' is exposed within the opening 35b of the mask layer 35. Each mask portion 35a includes a mask portion 41a formed from the lower mask layer 41 and a mask portion 42a formed from the upper mask layer 42. The opening 35b includes an opening 41b formed within the lower mask layer 41 and an opening 42b formed within the upper mask layer 42.

[0041] Each mask portion 35a in this embodiment is machined into a cylindrical shape, similar to the lower portion 33a of each protrusion 33 shown in Figure 3. Therefore, each mask portion 35a in this embodiment has a circular shape in plan view and a rectangular (e.g., rectangular) vertical cross-sectional shape. Further details of each mask portion 35a will be described later with reference to Figures 14 and 15.

[0042] Next, the growth layer 33' is processed by dry etching using the mask layer 35 (Figure 11). As a result, an opening H1 is formed in the growth layer 33' below the opening 35b, and one or more protrusions 33 are formed from the growth layer 33'. Each protrusion 33 is formed to include a lower portion 33a formed from the lower portion 33a' and an upper portion 33b formed from the upper portion 33b'. Since each protrusion 33 includes the upper portion 33b, it has an upper end higher than the upper surface of the stopper layer 32. The dry etching in Figure 11 is carried out until the upper surface of the stopper layer 32 is exposed.

[0043] In the dry etching shown in Figure 11, the stopper layer 32 is used as an etching stopper. Therefore, it is desirable that the stopper layer 32 be a layer with a high etching selectivity ratio between the stopper layer 32 and the growth layer 33'. The dry etching shown in Figure 11 is performed using a mixed gas containing, for example, SF6 gas, C4F8 gas, and O2 gas (S represents sulfur, F represents fluorine, C represents carbon, and O represents oxygen). If the lower mask layer 41 is a carbon layer, the dry etching shown in Figure 11 may be performed using a mixed gas containing, for example, HBr gas, Cl2 gas, and NF3 gas, along with O2 gas (H represents hydrogen, Br represents bromine, Cl represents chlorine, and N represents nitrogen). Each protrusion 33 in this embodiment is processed to include a lower portion 33a having a cylindrical shape and an upper portion 33b having a conical shape.

[0044] The mask layer 35 is removed after this dry etching is performed. Each mask portion 35a may fall between the protrusions 33 during or after this dry etching. In this case, the mask layer 35 is removed, including the fallen mask portions 35a. In this embodiment, the mask layer 35 is removed by chemical treatment. This chemical treatment may be performed, for example, using an aqueous hydrofluoric acid solution, or using a mixture of sulfuric acid and hydrogen peroxide. In this chemical treatment, the upper surface of the stopper layer 32 may be partially etched.

[0045] Next, a thin film 34 is formed on one or more protrusions 33 formed from the growth layer 33' (Figure 12). In this embodiment, the thin film 34 is formed continuously on the stopper layer 32 and one or more protrusions 33. The thin film 34 is, for example, a diamond layer formed under high-temperature conditions by plasma CVD.

[0046] In addition, dry etching as shown in Figure 11 may etch a portion of the stopper layer 32. As a result, in Figure 12, the upper surface of the area of ​​the stopper layer 32 not covered by the protrusions 33 may be lower than the upper surface of the area of ​​the stopper layer 32 covered by the protrusions 33.

[0047] Figure 13 is a plan view and a perspective view showing the manufacturing method of the dresser 2 according to the first embodiment.

[0048] Figure 13(a) shows the wafer 22' after the process shown in Figure 12. In this embodiment, the wafer 22' is divided into a plurality of chips 22 by dicing. Each chip 22 has the structure shown in Figures 3 and 12.

[0049] Next, one or more chips 22 are mounted onto the base plate 21 (Figure 13(b)). These chips 22 mounted on the base plate 21 may be manufactured from the same wafer 22' or from different wafers 22'. In this way, the dresser 2 shown in Figure 2 is manufactured.

[0050] Note that the process shown in Figure 12 may be performed between the process shown in Figure 13(a) and the process shown in Figure 13(b), instead of before the process shown in Figure 13(a). In other words, the thin film 34 may be formed on top of the substrate 31 included in the wafer 22' before dicing, or on top of the substrate 31 included in each chip 22 after dicing. In the former case, the manufacturer of the dresser 2 may, for example, prepare (e.g., manufacture or purchase) a wafer 22' with the thin film 34 on it, and then perform the processes shown in Figures 13(a) and 13(b) in order on the prepared wafer 22'. In the latter case, the manufacturer of the dresser 2 may, for example, prepare (e.g., manufacture or purchase) a wafer 22' without the thin film 34 on it, and then perform the processes shown in Figures 13(a), 12, and 13(b) in order on the prepared wafer 22'. An example of such processing will be explained with reference to Figures 31 to 33.

[0051] Figures 31 to 33 are cross-sectional views showing a modified version of the chip 22 according to the first embodiment. In Figures 31 to 33, the substrate 31 in the wafer 22' state and the substrate 31 in the chip 22 state will be described separately.

[0052] Figure 31 shows the substrate 31, etc., after the process shown in Figure 11 and before the process shown in Figure 12. The substrate 31 shown in Figure 31 is in the wafer 22' state.

[0053] Next, the process shown in Figure 13(a) is performed to divide the wafer 22' into multiple chips 22. Figure 32 shows one of these chips 22. Figure 32 shows the front surface S1, back surface S2, and side surface S3 of the substrate 31 in the state of the chip 22.

[0054] Next, the process shown in Figure 12 is performed to form a thin film 34 on one or more protrusions 33. Figure 33 shows the thin film 34 formed in this manner. In this modified example, the thin film 34 is also formed on the side surface S3 of the substrate 31 and on the side surface of the stopper layer 32. In this modified example, the thin film 34 may also be formed on the back surface S2 of the substrate 31. As shown in Figure 33, in this modified example, the thin film 34 is formed continuously on the surface of the protrusions 33, the upper surface of the stopper layer 32, and the side surface of the stopper layer 32. In this modified example, the thin film 34 may also be formed continuously on the surface of the protrusions 33, the upper surface of the stopper layer 32, the side surface of the stopper layer 32, the side surface S3 of the substrate 31, and the back surface S2 of the substrate 31.

[0055] Figure 33 shows the corner (edge) K of the thin film 34. The corner K of the thin film 34 is located between the top surface and the side surface of the thin film 34. In this modified example, since the thin film 34 is formed after dividing the wafer 22' into multiple chips 22, the corner K of the thin film 34 becomes rounded. Furthermore, the thin film 34 is formed to continuously cover the top surface and side surface of the stopper layer 32. This makes it possible to suppress cracking of the thin film 34 from the corner K.

[0056] In this modified example, the process shown in Figure 13(b) is then carried out. In this way, the dresser 2 shown in Figure 2 is manufactured.

[0057] Figure 14 is a plan view showing a method for manufacturing the chip 22 according to the first embodiment. Figure 15 is a plan view showing a modified method for manufacturing the chip 22 according to the first embodiment.

[0058] Figure 14 shows one or more mask portions 35a and openings 35b within the mask layer 35 shown in Figure 10. For comparison, Figure 14 further shows one or more protrusions 33 formed in the process shown in Figure 11 with dashed lines. Similar to Figure 4, Figure 14 shows the diameter D1 of the lower portion 33a of each protrusion and the diameter D2 of the upper portion 33b of each protrusion. Figure 14 further shows the diameter D3 of each mask portion 35a shown in Figure 10. In this embodiment, diameter D3 is set to be larger than diameter D2.

[0059] One or more mask portions 35a within the mask layer 35 may be formed in the shape of a square grid as shown in Figure 14, or in the shape of a triangular grid as shown in Figure 15. Furthermore, these mask portions 35a may be formed in other grid shapes.

[0060] Next, with reference to Figures 16 to 20, a comparative example chip 22 of this embodiment will be described.

[0061] Figure 16 is a cross-sectional view showing the structure of a comparative example chip 22 of the first embodiment.

[0062] The chip 22 of the first embodiment (Figure 3) comprises a substrate 31, a stopper layer 32, one or more protrusions 33, and a thin film 34. On the other hand, the chip 22 of this comparative example (Figure 16) comprises a substrate 31 and a thin film 34.

[0063] The substrate 31 of this comparative example includes a lower portion 31a and one or more upper portions 31b formed on the lower portion 31a, and the thin film 34 of this comparative example is formed continuously on these upper portions 31b. Each upper portion 31b has a conical shape, similar to the upper portion 33b of each protrusion 33 in the first embodiment. Figure 16 shows the thickness T1' of each upper portion 31b. The thickness T1' is, for example, 100 to 150 μm.

[0064] The dresser 2 of this comparative example has the same structure as the dresser 2 of the first embodiment, as shown in Figure 2. However, the dresser 2 of this comparative example includes one or more upper portions 31b as part of the substrate 31, and these upper portions 31b are covered with a thin film 34. The dresser 2 of this comparative example dresses the polishing pad 1 with these upper portions 31b (and the thin film 34).

[0065] Figures 17 to 20 are cross-sectional views showing a method for manufacturing a comparative example chip 22 of the first embodiment.

[0066] First, a mask layer 35 is formed on the substrate 31 (Figure 17). In Figure 17, the mask layer 35 includes a lower mask layer 41 and an upper mask layer 42.

[0067] Next, the mask layer 35 is processed by lithography and RIE (Figure 18). In Figure 18, one or more mask portions 35a are formed from the mask layer 35 by forming an opening 35b within the mask layer 35. As a result, the surface S1 of the substrate 31 is exposed within the opening 35b of the mask layer 35. Each mask portion 35a includes a mask portion 41a in the lower mask layer 41 and a mask portion 42a in the upper mask layer 42. The opening 35b includes an opening 41b in the lower mask layer 41 and an opening 42b in the upper mask layer 42.

[0068] Next, the substrate 31 is processed by dry etching using the mask layer 35 (Figure 19). As a result, a recess H2 is formed in the substrate 31 below the opening 35b, and a lower portion 31a and one or more upper portions 31b are formed in the substrate 31. The mask layer 35 is removed after this dry etching.

[0069] Next, thin films 34 are continuously formed on one or more upper portions 31b formed within the substrate 31 (Figure 20). The thin films 34 in this comparative example are, as in the first embodiment, for example, diamond layers.

[0070] Next, we will compare the chip 22 of the first embodiment with the chip 22 of the comparative example of the first embodiment.

[0071] In the comparative example, one or more upper portions 31b are formed within the substrate 31 for dressing the polishing pad 1. In the comparative example, the thickness T1' of each upper portion 31b is determined by the pitch P between the upper portions 31b. For example, as the pitch P increases, the thickness T1' also increases. On the other hand, in order to set the density of the upper portions 31b on the surface of the dresser 2 to a predetermined value, the pitch P is often set to a predetermined value, and this determines the thickness T1'. Therefore, in the comparative example, the thickness T1' cannot often be freely set.

[0072] If the thickness T1' is too large, the pad cut rate of the polishing pad 1 during dressing becomes large, which is problematic. The pad cut rate is the amount of thickness reduction of the polishing pad 1 per unit time. If the thickness T1' is too large, the polishing pad 1 will wear out in a short period of time, increasing the cost of the polishing pad 1.

[0073] Furthermore, if the thickness T1' is too small, the surface roughness of the polishing pad 1 will not be sufficiently large during dressing, which is a problem. If the roughness of the polishing pad 1 is too small, the polishing performance of the polishing pad 1 will be reduced. Conversely, if the thickness T1' is too large, the surface roughness of the polishing pad 1 will be too large during dressing, which is a problem. If the roughness of the polishing pad 1 is too large, dirt will get trapped in the spaces between the protrusions and depressions on the surface of the polishing pad 1 along with the particles of the slurry 4.

[0074] On the other hand, in this embodiment, one or more protrusions 33 are formed on the substrate 31 via a stopper layer 32 for dressing the polishing pad 1. In the comparative example, each upper portion 31b contributes to dressing, whereas in this embodiment, the upper portion 33b of each protrusion 33 contributes to dressing. According to this embodiment, the thickness T3 of the upper portion 33b of each protrusion 33 can be determined independently of the pitch P between the protrusions 33. This is because the thickness T3 of the upper portion 33b of each protrusion 33 can be adjusted by adjusting the thickness of the stopper layer 32, i.e., the thickness T2 of the lower portion 33a of each protrusion 33. Therefore, according to this embodiment, by setting the thickness T3 to an appropriate value, it is possible to reduce the pad cut rate of the polishing pad 1 during dressing and to adjust the surface roughness of the polishing pad 1 to an appropriate value during dressing.

[0075] As described above, the dresser 2 of this embodiment includes one or more protrusions 33 provided on the substrate 31 via a stopper layer 32, and these protrusions 33 are covered with a thin film 34. Therefore, according to this embodiment, it is possible to realize suitable protrusions 33 for dressing. For example, the thickness T3 of the upper portion 33b of each protrusion 33 can be determined independently of the pitch P between the protrusions 33.

[0076] In this embodiment, the dresser 2 includes, for example, an SiO2 film or a SiN film as a stopper layer 32. Since this SiO2 film or SiN film is a stopper layer 32 formed for use as an etching stopper, in this embodiment, this SiO2 film or SiN film is used as an etching stopper. On the other hand, this SiO2 film or SiN film does not have to be used as an etching stopper and may be formed for other purposes. Such an SiO2 film or SiN film is also an example of a first layer.

[0077] Furthermore, the dresser 2 of this embodiment may also include a thin film 34 other than the diamond layer. The thin film 34 other than the diamond layer is also an example of a second layer.

[0078] (Second Embodiment) Figure 21 is a cross-sectional view showing the structure of the chip 22 of the second embodiment.

[0079] The chip 22 of this embodiment (Figure 21) comprises a substrate 31, a stopper layer 32, one or more protrusions 33, and a thin film 34, similar to the chip 22 of the first embodiment (Figure 3). However, in the chip 22 of this embodiment, the number of recesses 32a in the stopper layer 32 is less than the number of protrusions 33.

[0080] Therefore, the chip 22 of this embodiment includes a protrusion 33 that includes a lower portion 33a and an upper portion 33b, and a protrusion 33 that includes only the upper portion 33b. The former protrusion 33 is formed on the substrate 31 and the stopper layer 32 and is in contact with the substrate 31, while the latter protrusion 33 is formed on the stopper layer 32 and is not in contact with the substrate 31. The former protrusion 33 is an example of a first protrusion, and the latter protrusion 33 is an example of a second protrusion.

[0081] Figure 22 is a plan view showing the structure of the chip 22 of the second embodiment.

[0082] Figure 22 shows recesses 32a and protrusions 33 arranged in a square grid shape, similar to Figure 4. However, the chip 22 shown in Figure 22 includes protrusions 33 that overlap with the recesses 32a in a plan view, and protrusions 33 that do not overlap with the recesses 32a in a plan view.

[0083] Figure 23 is a cross-sectional view showing the manufacturing method of the chip 22 according to the second embodiment.

[0084] Figure 23 shows a cross-section corresponding to Figure 10. The chip 22 of this embodiment can be manufactured by the process shown in Figures 6 to 12, similar to the chip 22 of the first embodiment. However, the growth layer 33' and mask layer 35 of this embodiment are formed such that the number of recesses 32a is less than the number of mask portions 35a. The growth layer 33' of this embodiment is formed by epitaxial growth from the substrate 31, for example, similar to the growth layer 33' of the first embodiment. According to this embodiment, both the protrusions 33 that overlap with the recesses 32a in a plan view and the protrusions 33 that do not overlap with the recesses 32a in a plan view can be formed by epitaxial growth from the substrate 31 exposed within the recesses 32a.

[0085] Figure 24 is a plan view showing the manufacturing method of the chip 22 according to the second embodiment.

[0086] Figure 24 shows one or more mask portions 35a and openings 35b within the mask layer 35 shown in Figure 23. For comparison, Figure 24 further shows one or more protrusions 33 formed after the process shown in Figure 23, indicated by dashed lines.

[0087] The shapes of the mask portion 35a and the opening 35b shown in Figure 24 are the same as the shapes of the mask portion 35a and the opening 35b shown in Figure 14. However, the mask layer 35 shown in Figure 24 includes a mask portion 35a that is arranged to overlap with the recess 32a in a plan view, and a mask portion 35a that is arranged not to overlap with the recess 32a in a plan view.

[0088] Furthermore, it is desirable that each recess 32a be positioned so as to overlap with one of the protrusions 33 in a plan view. The reason is that if a recess 32a is positioned so as not to overlap with any of the protrusions 33 in a plan view, when the growth layer 33' is processed, the growth layer 33' formed in that recess 32a will be removed, and the substrate 31 will be exposed in that recess 32a.

[0089] According to this embodiment, it is possible to realize a suitable protrusion 33 for dressing using fewer recesses 32a than protrusions 33.

[0090] In this embodiment, the chip 22 includes both a protrusion 33 that is in contact with the substrate 31 and a protrusion 33 that is not in contact with the substrate 31. However, it may also include only the protrusion 33 that is not in contact with the substrate 31. Examples of such a chip 22 will be described in the third and fourth embodiments below.

[0091] (Third embodiment) Figure 25 is a plan view showing various examples of the manufacturing method of the chip 22 according to the third embodiment.

[0092] Figure 25(a) shows a first example of the method for manufacturing the chip 22 of this embodiment. More specifically, Figure 25(a) shows a wafer 22' before being diced into a plurality of chips 22, a stopper layer 32 contained in the wafer 22', and a plurality of recesses 32a formed within the stopper layer 32. In Figure 25(a), the stopper layer 32 is shown with dot hatching, and the recesses 32a are shown in white. Similarly, Figures 25(b), 25(c), and 25(d) show second, third, and fourth examples of the method for manufacturing the chip 22 of this embodiment.

[0093] In the first example, the plurality of recesses 32a are arranged on two straight lines passing through the center of the wafer 22'. In the second example, the plurality of recesses 32a are arranged on a single circumference surrounding the center of the wafer 22'. In the third example, the plurality of recesses 32a are arranged on four straight lines passing through the center of the wafer 22'. In the fourth example, the plurality of recesses 32a are arranged on two circumferences surrounding the center of the wafer 22'.

[0094] In each of the first to fourth examples, the wafer 22' may include a chip 22 with a recess 32a and a chip 22 without a recess 32a.

[0095] According to this embodiment, similar to the second embodiment, it is possible to realize suitable protrusions 33 for dressing using fewer recesses 32a than protrusions 33.

[0096] (Fourth Embodiment) Figure 26 is a plan view showing the manufacturing method of the chip 22 according to the fourth embodiment.

[0097] Figure 26 shows a wafer 22' before being diced into multiple chips 22, multiple chip regions R1 within the wafer 22', and a scribe region (dicing region) R2 within the wafer 22'. Each chip region R1 has a rectangular shape (e.g., square or rectangle) in plan view. The scribe region R2 has a mesh-like shape formed by combining multiple straight sections extending in the X direction and multiple straight sections extending in the Y direction in plan view. In this embodiment, each chip region R1 becomes a single chip 22 by cutting the wafer 22' along the scribe region R2.

[0098] Figure 26 further shows the stopper layer 32 contained in the wafer 22' and the recesses 32a formed within the stopper layer 32. In Figure 26, the stopper layer 32 is shown with dot hatching, and the recesses 32a are shown in white. The recesses 32a in this embodiment have a mesh-like shape in plan view and have the same planar shape as the scribe region R2. Therefore, the stopper layer 32 in this embodiment is divided into the same number of parts as the number of chip regions R1. Each part of the stopper layer 32 in this embodiment has a rectangular shape in plan view and has the same planar shape as one chip region R1. Thus, each chip 22 in this embodiment is manufactured so as not to contain recesses 32a within the stopper layer 32. This is because the recesses 32a are formed only within the scribe region R2.

[0099] Figure 27 is a plan view showing a modified example of the fourth embodiment for manufacturing the chip 22.

[0100] Figure 27 also shows the wafer 22' before it is diced into multiple chips 22, multiple chip regions R1 within the wafer 22', and scribe regions R2 within the wafer 22'. Figure 27 further shows a stopper layer 32 included in the wafer 22' and multiple recesses 32a formed within the stopper layer 32. In this modified example, each recess 32a is formed within the scribe region R2. Therefore, each chip 22 in this modified example is also manufactured so that it does not contain any recesses 32a within the stopper layer 32.

[0101] Figures 28 to 30 are cross-sectional views showing the manufacturing method of the chip 22 according to the fourth embodiment.

[0102] Figure 28 shows a cross-section corresponding to Figure 10. However, Figure 28 shows multiple chip regions R1 and scribe regions R2 within the wafer 22'. The recess 32a shown in Figure 28 has a mesh-like shape in plan view and has the same planar shape as the scribe region R2.

[0103] Next, the growth layer 33' is processed by dry etching using the mask layer 35 (Figure 29). As a result, an opening H1 is formed in the growth layer 33' below the opening 35b, and one or more protrusions 33 are formed from the growth layer 33'. Each protrusion 33 is formed to include the upper portion 33b formed from the upper portion 33b', but not the lower portion 33a formed from the lower portion 33a'. Since each protrusion 33 includes the upper portion 33b, it has an upper end higher than the upper surface of the stopper layer 32. The mask layer 35 is removed after this dry etching is performed.

[0104] In the process shown in Figure 29, the growth layer 33' formed in the recess 32a is removed, and the substrate 31 is exposed in the recess 32a. Therefore, in Figure 29, the surface S1 of the substrate 31 below the recess 32a is recessed by the dry etching described above.

[0105] Next, a thin film 34 is formed on one or more protrusions 33 formed from the growth layer 33' (Figure 30). In this embodiment, the thin film 34 is formed continuously on the stopper layer 32 and one or more protrusions 33. In this embodiment, the thin film 34 is also formed on the side surfaces of the stopper layer 32 within the recess 32a, and on the surface S1 and side surfaces of the substrate 31 below the recess 32a.

[0106] Subsequently, the wafer 22' is processed in the steps shown in Figures 13(a) and 13(b). In this way, the dresser 2 of this embodiment is manufactured.

[0107] According to this embodiment, it is possible to realize a suitable protrusion 33 for dressing using one or more recesses 32a within the scribe region R2.

[0108] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel dresser and method described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the dresser and method described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of Symbols]

[0109] 1: Polishing pad, 2: Dresser, 3: Wafer, 4: Slurry, 10: Polishing device, 11: Polishing table, 12: Dressing mechanism, 13: Polishing head, 14: Slurry supply unit, 15: Control unit, 21: Base metal, 22: Chip, 22': Wafer 31: Substrate, 31a: Lower part, 31b: Upper part, 32: Stopper layer, 32a: Recess, 33: convex part, 33a: lower part, 33b: upper part, 33': growth layer, 33a': lower part, 33b': upper part, 34: Thin film, 35: Mask layer, 35a: Mask portion, 35b: Opening, 41: Lower mask layer, 41a: Mask portion, 41b: Opening, 42: Upper mask layer, 42a: Mask portion, 42b: Opening

Claims

1. circuit board and A first layer provided on the substrate, One or more protrusions provided on the substrate or the first layer, having an upper end higher than the upper surface of the first layer and having a different composition from the first layer, A second layer provided on one or more of the aforementioned protrusions, A dresser equipped with a dresser.

2. The one or more of the aforementioned protrusions are A first protrusion is provided on the substrate so as to be in contact with the substrate, A second protrusion is provided on the first layer so as not to be in contact with the substrate, A dresser according to claim 1, comprising at least one of the following:

3. The first of the one or more protrusions is A first portion provided on the substrate within the first layer, A second portion is provided on the first portion and has an upper end that is higher than the upper surface of the first layer, A dresser according to claim 1, including the following:

4. The dresser according to claim 3, wherein the area of ​​the second portion in plan view is greater than the area of ​​the first portion in plan view.

5. The dresser according to claim 3, wherein the second part is provided on the first part and the first layer.

6. The dresser according to claim 3, wherein the shape of the longitudinal section of the second part is triangular.

7. The aforementioned substrate is a semiconductor substrate, The one or more protrusions are formed of a semiconductor material. The dresser according to claim 1.

8. The dresser according to claim 1, wherein the substrate and the one or more protrusions are formed of the same semiconductor material.

9. The first layer is an insulating film, The previous second layer is a diamond layer. The dresser according to claim 1.

10. The dresser according to claim 1, wherein the second layer is provided on the one or more protrusions and the first layer, or is provided on the one or more protrusions and the first layer and on the substrate and the side surface of the first layer.

11. Chip holding member and One or more chips are provided on the chip holding member, Furthermore, The dresser according to claim 1, wherein the first chip among the one or more chips includes the substrate, the first layer, the one or more protrusions, and the second layer.

12. A first layer is formed on the substrate. A third layer having a different composition from the first layer is formed on the substrate or the first layer. The third layer is processed until the first layer is exposed, and one or more protrusions are formed from the third layer. A second layer is formed on one or more of the aforementioned protrusions. A method for manufacturing a dresser, including the following.

13. The first of the one or more protrusions is The first portion of the first protrusion is formed on the substrate within the first layer, The second portion of the first protrusion is formed on the first portion such that it has an upper end higher than the upper surface of the first layer. A method for manufacturing a dresser according to claim 12, wherein the dresser is formed by the following:

14. The method for manufacturing a dresser according to claim 12, wherein the third layer is formed by epitaxial growth from the substrate.

15. The process further includes forming one or more recesses within the first layer before forming the third layer, The third layer is formed in one or more recesses and on the first layer. A method for manufacturing a dresser according to claim 12.

16. Before processing the third layer, a fourth layer is formed on the third layer. The third layer is processed by etching using the fourth layer to form one or more protrusions from the third layer. After processing the third layer, the fourth layer is removed. A method for manufacturing a dresser according to claim 12, further comprising the following:

17. Manufacture one or more chips, The one or more chips are placed on the chip holding member. This further includes, The method for manufacturing a dresser according to claim 12, wherein the first chip among the one or more chips is manufactured to include the substrate, the first layer, the one or more protrusions, and the second layer.

18. A wafer is prepared, comprising a substrate, a first layer provided on the substrate, and one or more protrusions provided on the substrate or the first layer, having a different composition from the first layer. One or more chips are manufactured from the aforementioned wafer. The one or more chips are placed on the chip holding member. A method for manufacturing a dresser, including the following.

19. After preparing the wafer, a second layer is formed on one or more protrusions. After the formation of the second layer, a first chip including the substrate, the first layer, the one or more protrusions, and the second layer is manufactured from the wafer. A method for manufacturing a dresser according to claim 18, further comprising the following:

20. After preparing the wafer, a first chip including the substrate, the first layer, and one or more protrusions is manufactured from the wafer. After the manufacturing of the first chip, a second layer is formed on the one or more protrusions. A method for manufacturing a dresser according to claim 18, further comprising the following:

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