Memory system

Abstract

To improve the reliability of data writing and reading. [Solution] The memory controller 20 of the embodiment generates first write data by performing error suppression coding on data to be written to multiple memory cells of multiple word lines based on a first coding parameter, determines the error rate for each word line from the first read data of the first write data, and selects a first word line from multiple word lines based on the error rate for each word line. Furthermore, it generates second write data by performing error suppression coding on data to be written to the first memory cell of the first word line by changing the first coding parameter, sets a second coding parameter based on the error rate of the second read data for the second write data, and performs error suppression coding on data to be written to the first memory cell of the first word line based on the second coding parameter.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a memory system. [Background technology]

[0002] For example, a memory system is composed of semiconductor memory, including NAND flash memory, and a memory controller that controls the semiconductor memory. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6960877 specification [Overview of the project] [Problems that the invention aims to solve]

[0004] This provides a memory system that can improve the reliability of data writing and reading. [Means for solving the problem]

[0005] The memory system of the embodiment comprises a semiconductor memory including a plurality of word lines to which a plurality of memory cells are connected, and a memory controller that performs error suppression coding on data written to the semiconductor memory. The memory controller generates first write data by performing error suppression coding on data written to the plurality of memory cells connected to the plurality of word lines based on a first coding parameter, reads the first write data written to the plurality of memory cells as first read data, determines the error rate for each word line in the plurality of word lines from the first read data, selects a first word line from the plurality of word lines based on the error rate for each word line, generates second write data by performing error suppression coding on data written to a first memory cell connected to the first word line by changing the first coding parameter, sets a second coding parameter based on the error rate of the second read data for the second write data, and performs error suppression coding on data written to the first memory cell connected to the first word line based on the second coding parameter. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing the configuration of the memory system according to the first embodiment. [Figure 2] This is a block diagram showing the circuit configuration of a semiconductor memory according to the first embodiment. [Figure 3] This is a circuit diagram of a block in a memory cell array according to the first embodiment. [Figure 4] This figure shows the relationship between the possible threshold voltage distribution and data for the memory cell transistor according to the first embodiment. [Figure 5] This diagram shows the data flow during write and read operations in the memory system according to the first embodiment. [Figure 6] This is a flowchart showing the write operation in the memory system according to the first embodiment. [Figure 7]It is a diagram showing data formats to which various coding rates according to the first embodiment are applied. [Figure 8] It is a diagram showing an example when coding rates are respectively set for a plurality of pages according to the first embodiment. [Figure 9] It is a flowchart showing an optimization process of coding parameters in error suppression coding of a memory system according to the first embodiment. [Figure 10] It is a diagram showing information stored in the RAM of a memory controller according to the first embodiment. [Figure 11] It is a flowchart showing an optimization process of state control variables according to the first embodiment. [Figure 12] It is a diagram showing a change in error rate due to an optimization process in error suppression coding of a memory system according to the first embodiment. [Figure 13] It is a diagram showing the error rate for each word line when error suppression coding is performed on data written to memory cells of word lines in a target block according to the first embodiment. [Figure 14] It is a flowchart showing an optimization process of coding parameters in error suppression coding of a memory system according to the second embodiment. [Figure 15] It is a flowchart showing an optimization process of state control variables according to the second embodiment. [Figure 16] It is a diagram showing a change in error rate due to an optimization process in error suppression coding of a memory system according to the second embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference numerals. Also, the embodiments shown below are examples of devices and methods for embodying the technical idea of this embodiment, and do not specify the materials, shapes, structures, arrangements, etc. of the components as follows.

[0008] Functional blocks can be implemented as hardware, computer software, or a combination of both. It is not necessary for functional blocks to be distinguished as shown in the following example. For example, some functions may be performed by functional blocks other than those shown in the example. Furthermore, the example functional block may be further divided into smaller functional subblocks.

[0009] 1. First Embodiment For example, when writing and reading data in a memory system, one technique to improve the reliability of data during writing and reading is error suppression coding and decoding. Error suppression coding and decoding reduce the data error rate and suppress memory cell fatigue by encoding (e.g., data transformation) the data being written to the memory device and decoding the data being read from the memory device. Examples of error suppression coding and decoding include those using asymmetric coding (AC) and those using page symmetric coding (PSC).

[0010] The following will first describe the configuration of the memory system, and then explain error suppression coding and decoding in the operation of the memory system.

[0011] 1.1 Memory System Configuration First, the configuration of the memory system 1 of the first embodiment will be described. Figure 1 is a block diagram showing the configuration of the memory system of the first embodiment. The memory system 1 is connected to an external host device 2 and can perform various operations in response to commands from the host device 2. The memory system 1 includes a semiconductor memory 10 and a memory controller 20.

[0012] The semiconductor memory 10 includes, for example, a NAND flash memory in which memory cells (also referred to as memory cell transistors) are arranged in two or three dimensions, and stores data non-volatilely. Details of the semiconductor memory 10 will be described later.

[0013] The memory controller 20 is connected to the semiconductor memory 10 via a NAND bus. The memory controller 20 controls the semiconductor memory 10. The NAND bus transmits and receives signals according to the NAND interface. The memory controller 20 is also connected to the host device 2 via a host bus. The memory controller 20 accesses the semiconductor memory 10 in response to commands received from the host device 2.

[0014] The semiconductor memory 10 and memory controller 20 described above may, for example, be combined to form a single semiconductor device. Such a semiconductor device could be, for example, an SD TM Examples include memory cards containing cards, and SSDs (solid state drives). The memory controller 20 may also be, for example, a SoC (system-on-a-chip).

[0015] Host device 2 is, for example, a personal computer, a mobile device such as a smartphone, or a digital camera. The host bus is, for example, an SD card. TM It is a bus that follows an interface.

[0016] 1.1.1 Memory Controller Referring to Figure 1, the configuration of the memory controller 20 will be described. The memory controller 20 includes a processor 21, RAM (random access memory) 22, ROM (read-only memory) 23, a randomizer 24, an error suppression coding / decoding circuit 25, an ECC (error checking and correction) circuit 26, a NAND interface circuit (NAND I / F) 27, and a host interface circuit (host I / F) 28.

[0017] The processor 21 controls the overall operation of the memory controller 20. For example, when the processor 21 receives a write command from the host device 2, it issues a write command to the NAND interface circuit 27 in response. Similarly, when the processor 21 receives a read command or an erase command, it issues a read command and an erase command to the NAND interface circuit 27 in response.

[0018] The processor 21 also performs various processes for managing the semiconductor memory 10, such as wear leveling. The operation of the memory controller 20, as described below, may be implemented by the processor 21 executing software or firmware, or by hardware. The processor 21 includes, for example, a CPU (central processing unit).

[0019] RAM22 is used as a workspace for the processor 21. RAM22 temporarily stores firmware for managing the semiconductor memory 10, various management tables such as logical / physical address translation tables, and data.

[0020] RAM22 stores, for example, user data received from host device 2, data processed by randomizer 24, error suppression coding / decoding circuit 25, and ECC circuit 26, and write data to be written to semiconductor memory 10. RAM22 also stores read data received from semiconductor memory 10 and data to be transmitted to host device 2. RAM22 stores, for example, coding parameters used in error suppression coding and decoding by error suppression coding / decoding circuit 25. The coding parameters will be described later.

[0021] RAM22 is a volatile type of memory. RAM22 is a type of semiconductor memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0022] ROM23 stores, for example, software or firmware executed by processor 21, and various parameters necessary for the execution of processor 21. ROM23 is a non-volatile memory. ROM23 is, for example, an EEPROM. TM (Electrically erasable, programmable, read-only memory)

[0023] The randomizer 24 randomizes user data in order to distribute memory cells evenly across the possible states of the memory cells in the semiconductor memory 10. The randomizer 24 includes, for example, a linear feedback shift register. The linear feedback shift register generates a pseudorandom number that is uniquely determined for the input value. The processor 21 performs an exclusive OR operation between the pseudorandom number and the user data to generate randomized data (hereinafter referred to as randomized data). The randomizer 24 also derandomizes the randomized data read from the semiconductor memory 10 to restore the randomized data to the user data before randomization. The possible states of the memory cells will be described later.

[0024] The error suppression coding / decoding circuit 25 performs error suppression coding on data written to the semiconductor memory 10 to reduce the error rate. The error suppression coding / decoding circuit 25 also performs error suppression decoding on data read from the semiconductor memory 10. For example, during a write operation, the error suppression coding / decoding circuit 25 performs error suppression coding on user data or randomized data received from the host device 2 using coding parameters. During a read operation, the error suppression coding / decoding circuit 25 performs error suppression decoding on read data or data that has undergone error correction decoding received from the semiconductor memory 10 using coding parameters. Details of the error suppression coding / decoding circuit 25 will be described later.

[0025] The ECC circuit 26 performs error correction processing for data. The ECC circuit 26 performs error detection and correction processing for data written to the semiconductor memory 10 and data read from the semiconductor memory 10. Specifically, during a write operation, the ECC circuit 26 generates parity based on the data to be written to the semiconductor memory 10 and assigns the generated parity to the data to be written. During a read operation, the ECC circuit 26 generates a syndrome based on the data read from the semiconductor memory 10 and detects and corrects errors in the read data based on the generated syndrome.

[0026] The NAND interface circuit 27 is connected to the semiconductor memory 10 via a NAND bus and is responsible for communication with the semiconductor memory 10. Based on instructions received from the processor 21, the NAND interface circuit 27 transmits various signals, commands, and data to the semiconductor memory 10. The NAND interface circuit 27 also receives various signals and data from the semiconductor memory 10.

[0027] The host interface circuit 28 is connected to the host device 2 via the host bus and is responsible for communication with the host device 2. The host interface circuit 28 transfers commands and data received from the host device 2 to the processor 21 and RAM 22, respectively. In addition, the host interface circuit 28 transmits data in RAM 22 to the host device 2 in response to commands from the processor 21.

[0028] 1.1.2 Semiconductor memory The semiconductor memory 10 of the first embodiment will be described.

[0029] 1.1.2.1 Circuit configuration of semiconductor memory First, the circuit configuration of the semiconductor memory 10 of the first embodiment will be described. Figure 2 is a block diagram showing the circuit configuration of the semiconductor memory of the first embodiment.

[0030] The semiconductor memory 10 includes a memory cell array 11, an input / output circuit 12, a logic control circuit 13, a ready / busy circuit 14, a group of registers 15, a sequencer (or control circuit) 16, a voltage generation circuit 17, a row decoder 18, a column decoder 19A, a data register 19B, and a sense amplifier 19C. The group of registers 15 includes a status register 15A, an address register 15B, and a command register 15C.

[0031] The memory cell array 11 comprises one or more blocks BLK0, BLK1, BLK2, ..., BLKn (where n is a non-negative integer). Each of the multiple blocks BLK0 to BLKn includes multiple memory cell transistors (hereinafter also referred to as memory cells) associated with rows and columns. The memory cell transistors are electrically erasable and programmable non-volatile memory cells. The memory cell array 11 includes multiple word lines, multiple bit lines, and source lines for applying voltage to the memory cell transistors. The specific configuration of block BLKn will be described later.

[0032] The input / output circuit 12 and the logic control circuit 13 are connected to the memory controller 20 via input / output terminals (or a NAND bus). The input / output circuit 12 sends and receives I / O signals DQ (e.g., DQ0, DQ1, DQ2, ..., DQ7) to and from the memory controller 20 via the input / output terminals. The I / O signals DQ communicate commands, addresses, data, etc.

[0033] The logic control circuit 13 receives external control signals from the memory controller 20 via input / output terminals (or the NAND bus). These external control signals include, for example, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the write protect signal WPn. The "n" appended to the signal name indicates that the signal is active-low.

[0034] The chip enable signal CEn allows selection of a semiconductor memory 10 when multiple semiconductor memories 10 are installed, and is asserted when a particular semiconductor memory 10 is selected. The command latch enable signal CLE allows a command transmitted as signal DQ to be latched in the command register 15C. The address latch enable signal ALE allows an address transmitted as signal DQ to be latched in the address register 15B. The write enable signal WEn allows data transmitted as signal DQ to be stored in the input / output circuit 12. The read enable signal REn allows data read from the memory cell array 11 to be output as signal DQ. The write protect signal WPn is asserted when write and erase operations on the semiconductor memory 10 are prohibited.

[0035] The ready / busy circuit 14 generates a ready / busy signal R / Bn in response to control from the sequencer 16. The ready / busy signal R / Bn indicates whether the semiconductor memory 10 is in a ready state or a busy state. The ready state indicates that the semiconductor memory 10 is in a state where it can accept instructions from the memory controller 20. The busy state indicates that the semiconductor memory 10 is in a state where it cannot accept instructions from the memory controller 20. The memory controller 20 can know whether the semiconductor memory 10 is in a ready state or a busy state by receiving the ready / busy signal R / Bn from the semiconductor memory 10.

[0036] The status register 15A stores the status information STS necessary for the operation of the semiconductor memory 10. The status register 15A transfers the status information STS to the input / output circuit 12 according to the instructions of the sequencer 16.

[0037] The address register 15B stores the address ADD transferred from the input / output circuit 12. The address ADD includes a row address and a column address. The row address includes, for example, a block address that specifies the block BLKn to be operated on, and a page address that specifies the word line WL to be operated on within the specified block.

[0038] Command register 15C stores the command CMD transferred from the input / output circuit 12. The command CMD includes, for example, a write command that instructs the sequencer 16 to perform a write operation, a read command that instructs it to perform a read operation, and an erase command that instructs it to perform an erase operation.

[0039] For example, static random access memory (SRAM) can be used for the status register 15A, address register 15B, and command register 15C.

[0040] The sequencer 16 receives a command from the command register 15C and comprehensively controls the semiconductor memory 10 according to the sequence based on this command.

[0041] The sequencer 16 controls the voltage generation circuit 17, row decoder 18, column decoder 19A, data register 19B, and sense amplifier 19C to perform write, read, and erase operations. Specifically, based on a write command received from the command register 15C, the sequencer 16 controls the voltage generation circuit 17, row decoder 18, data register 19B, and sense amplifier 19C to write data to the multiple memory cell transistors specified by address ADD. The sequencer 16 also controls the voltage generation circuit 17, row decoder 18, column decoder 19A, data register 19B, and sense amplifier 19C to read data from the multiple memory cell transistors specified by address ADD based on a read command received from the command register 15C. The sequencer 16 also controls the voltage generation circuit 17, row decoder 18, column decoder 19A, data register 19B, and sense amplifier 19C to erase the data stored in the block specified by address ADD based on an erase command received from the command register 15C. The circuit including the column decoder 19A and data register 19B, etc., is referred to as the column control circuit.

[0042] The voltage generation circuit 17 receives the power supply voltage VDD and the ground voltage VSS from outside the semiconductor memory 10 via the power supply terminal. The power supply voltage VDD is an external voltage supplied from outside the semiconductor memory 10. The ground voltage VSS is an external voltage supplied from outside the semiconductor memory 10, and is, for example, 0V.

[0043] The voltage generation circuit 17 uses the power supply voltage VDD to generate multiple voltages necessary for write, read, and erase operations. The voltage generation circuit 17 supplies the generated voltages to the memory cell array 11, the row decoder 18, and the sense amplifier 19C, etc.

[0044] The row decoder 18 receives a row address from the address register 15B and decodes this row address. Based on the decoding result of the row address, the row decoder 18 selects one of several blocks and then selects a word line WL within the selected block BLKn. Furthermore, the row decoder 18 transfers multiple voltages supplied from the voltage generation circuit 17 to the selected block BLKn.

[0045] The column decoder 19A receives the column address from the address register 15B and decodes this column address. Based on the decoding result of the column address, the column decoder 19A selects a latch circuit in the data register 19B.

[0046] The data register 19B includes multiple latch circuits. The latch circuits temporarily store the data to be written or read.

[0047] During data read operations, the sense amplifier 19C senses and amplifies the data read from the memory cell transistor to the bit line. Furthermore, the sense amplifier 19C temporarily stores the read data DAT read from the memory cell transistor and transfers the stored read data DAT to the data register 19B. During data write operations, the sense amplifier 19C temporarily stores the write data DAT transferred from the input / output circuit 12 via the data register 19B. Furthermore, the sense amplifier 19C transfers the write data DAT to the bit line.

[0048] Next, the circuit configuration of the memory cell array 11 in the semiconductor memory 10 of the first embodiment will be described. As mentioned above, the memory cell array 11 has a plurality of blocks BLK0 to BLKn. The circuit configuration of block BLKn will be described below.

[0049] Figure 3 is a circuit diagram of block BLKn in the memory cell array 11. Block BLKn comprises, for example, multiple string units SU0, SU1, SU2, and SU3. Hereafter, when a string unit SU is referred to, it refers to each of the string units SU0 to SU3. A string unit SU comprises multiple NAND strings (or memory strings) NS.

[0050] Here, for the sake of simplicity, we will show an example where the NAND string NS comprises, for example, eight memory cell transistors MT0, MT1, MT2, ..., MT7, and two selection transistors ST1 and ST2. Hereafter, when we refer to a memory cell transistor MT, we are referring to each of the memory cell transistors MT0 to MT7.

[0051] The memory cell transistor MT comprises a control gate and a charge storage layer, and stores data nonvolatilously. Memory cell transistors MT0 to MT7 are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The memory cell transistor MT can store 1 bit of data or 2 or more bits of data.

[0052] The gates of multiple selection transistors ST1 included in string unit SU0 are connected to selection gate line SGD0. Similarly, the gates of each selection transistor ST1 in string units SU1 to SU3 are connected to selection gate lines SGD1 to SGD3, respectively. Each of the selection gate lines SGD0 to SGD3 is independently controlled by the row decoder 18.

[0053] The gates of the multiple selection transistors ST2 included in string unit SU0 are connected to the selection gate line SGS. Similarly, the gates of each selection transistor ST2 in string units SU1 to SU3 are connected to the selection gate line SGS. In some cases, the gates of the selection transistors ST2 in string units SU0 to SU3 may also be connected to individual selection gate lines SGS. Selection transistors ST1 and ST2 are used to select string unit SU in various operations.

[0054] The control gates of the memory cell transistors MT0 to MT7 in block BLKn are connected to word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is independently controlled by the row decoder 18.

[0055] Each bit line BL0, BL1, BL2, ..., BLm (where m is a non-negative integer) is connected to multiple blocks BLK0 to BLKn, and to a single NAND string NS within a string unit SU contained in block BLKn. That is, each bit line BL0 to BLm is connected to the drain of a selection transistor ST1 of multiple NAND strings NS located in the same column within a matrix-like arrangement of NAND strings NS in block BLKn. In addition, the source line SL is connected to multiple blocks BLK0 to BLKn. That is, the source line SL is connected to the source of multiple selection transistors ST2 contained in block BLKn.

[0056] In short, a string unit SU includes multiple NAND strings NS connected to different bit lines BL and the same selected gate line SGD. A block BLKn also includes multiple string units SU that share a common word line WL. Furthermore, the memory cell array 11 includes multiple blocks BLK0 to BLKn that share a common bit line BL.

[0057] A block BLKn is, for example, a data erasure unit. That is, data stored in the memory cell transistor MT contained within a block BLKn is erased all at once. Note that the data may be erased in units of string units SU, or in units smaller than string units SU.

[0058] Multiple memory cell transistors MT that share a word line WL within a single string unit SU are called a cell unit CU. A collection of 1-bit data stored by each of the multiple memory cell transistors MT contained within a cell unit CU is called a page. The storage capacity of a cell unit CU changes depending on the number of bits of data stored by the memory cell transistors MT. For example, a cell unit CU stores 1 page of data when each memory cell transistor MT stores 1 bit of data, 2 pages of data when it stores 2 bits of data, and 3 pages of data when it stores 3 bits of data.

[0059] Write and read operations on the cell unit CU are performed on a page-by-page basis. In other words, read and write operations are performed simultaneously on multiple memory cell transistors MT connected to a single word line WL located on a single string unit SU.

[0060] Furthermore, the number of string units in block BLKn is not limited to SU0 to SU3, but can be set arbitrarily. Also, the number of NAND strings NS included in string unit SU, and the number of memory cell transistors and selection transistors in NAND strings NS can also be set arbitrarily. In addition, the memory cell transistor MT may be a MONOS (metal-oxide-nitride-oxide-silicon) type using an insulating film as the charge storage layer, or an FG (floating gate) type using a conductive layer as the charge storage layer.

[0061] Next, we will explain the relationship between the possible threshold voltage distribution of the memory cell transistor MT and the data. Figure 4 is a diagram showing the relationship between the possible threshold voltage distribution of the memory cell transistor MT and the data.

[0062] Here, we show an example where the TLC (Triple-Level Cell) method, which allows one memory cell transistor MT to store 3 bits of data, is applied as the storage method for the memory cell transistor MT. This embodiment can also be applied to other storage methods, such as the SLC (Single-Level Cell) method, which allows one memory cell transistor MT to store 1 bit of data; the MLC (Multi-Level Cell) method, which allows one memory cell transistor MT to store 2 bits of data; and the QLC (Quad-Level Cell) method, which allows one memory cell transistor MT to store 4 bits of data.

[0063] The 3 bits of data that a memory cell transistor (MT) can store are defined by a lower bit, a middle bit, and an upper bit. When a memory cell transistor (MT) stores 3 bits, it can be in one of eight states corresponding to multiple threshold voltages. These eight states, in descending order from lowest to highest, are called "Er", "A", "B", "C", "D", "E", "F", and "G". Multiple memory cell transistors (MT) belonging to each of the states "Er", "A", "B", "C", "D", "E", "F", and "G" form a threshold voltage distribution as shown in Figure 4.

[0064] The states "Er", "A", "B", "C", "D", "E", "F", and "G" are assigned, for example, the data "111", "110", "100", "000", "010", "011", "001", and "101", respectively. The bit order is "ZYX", where the lower bit is "X", the middle bit is "Y", and the upper bit is "Z". The assignment of threshold voltage distribution to data can be set arbitrarily.

[0065] To read data stored in the memory cell transistor MT, the state to which the threshold voltage of the memory cell transistor MT belongs is determined. The read voltages AR, BR, CR, DR, ER, FR, and GR are used to determine the state.

[0066] Voltage VREAD is the voltage applied to the word line WL connected to the memory cell transistor MT of the cell unit CU that is not being read. Voltage VREAD is higher than the threshold voltage of the memory cell transistor MT in any state. Therefore, when voltage VREAD is applied to the control gate of a memory cell transistor MT, it turns ON regardless of the data it holds.

[0067] As described above, each memory cell transistor MT can be set to one of eight states and store 3 bits of data. Writing and reading are performed in page units within a single cell unit CU. When a memory cell transistor MT stores 3 bits of data, the lower bit, middle bit, and upper bit are allocated to the three pages within a single cell unit CU. The pages written to in a single write operation, or read out in a single read operation, that is, the sets of lower bits, middle bits, and upper bits held by the cell unit CU, are called the lower page, middle page, and upper page, respectively.

[0068] When the above data allocation is applied, lower pages are determined by read operations using read voltages AR and ER. Middle pages are determined by read operations using read voltages BR, DR, and FR. Upper pages are determined by read operations using read voltages CR and GR.

[0069] 1.2 Memory System Operation An overview of the write and read operations in the memory system 1 of the first embodiment will be described. Figure 5 is a diagram showing the data flow of the write and read operations in the memory system of the first embodiment. Figure 6 is a flowchart showing the write operation in the memory system.

[0070] In the read operation in memory system 1, as shown in Figure 5, the memory controller 20 sequentially performs randomization, error suppression coding, and error correction coding on the user data input from the host device 2, and outputs it to the semiconductor memory 10 as write data. The semiconductor memory 10 writes the write data to the memory cell array 11.

[0071] The writing operation will be explained below with reference to Figure 6.

[0072] User data is transmitted from the host device 2 to the memory controller 20. The user data transmitted to the memory controller 20 is randomized by the randomizer 24 to generate randomized data (S1). The randomized data is error-suppressed encoding by the error-suppression encoding / decoding circuit 25 to generate error-suppression encoded data (hereinafter referred to as encoded data) (S2). The encoded data is error-corrected encoding by the ECC circuit 26 to generate write data (S3). The write data is transmitted from the memory controller 20 to the semiconductor memory 10. The write data transmitted to the semiconductor memory 10 is written, for example, to block BLKn in the memory cell array 11 of the semiconductor memory 10 (S4).

[0073] On the other hand, in the read operation in memory system 1, the reverse process of the write operation is performed. As shown in Figure 5, the memory controller 20 sequentially performs error correction decoding, error suppression decoding, and derandomization on the read data read from the semiconductor memory 10, and outputs it to the host device 2 as user data.

[0074] In this embodiment, we will focus on the error suppression coding process performed by the error suppression coding / decoding circuit 25 during the write operation and describe its detailed method. In the following operation description, the processing performed by the randomizer 24 and ECC circuit 26 at the input and output stages of the error suppression coding / decoding circuit 25 will be omitted.

[0075] Error suppression coding and decoding, as described above, aim to reduce the data error rate by performing data conversion on the data written to the semiconductor memory 10. The data error rate can be expressed, for example, by the bit error rate (BER) or the frame error rate (FER). BER is the ratio of the number of error bits to the total number of bits of the data being transferred. For example, when data is read after it has been written to the semiconductor memory 10, errors occur in the read data. BER is the ratio of error bits to the total number of bits of the data being written.

[0076] The error suppression coding performed by the error suppression coding / decoding circuit 25 uses coding parameters. The coding parameters include two parameters: one is the state control variable CO, and the other is the coding rate CR. In this specification, at least one of the state control variable CO and the coding rate CR is referred to as the coding parameter (or coding condition).

[0077] The state control variable CO is a variable that controls the probability of occurrence of the state to which a memory cell belongs. The state control variable CO sets the ratio of memory cells for each state in the memory cells that a page has. For example, when TLC is applied to memory cells, the state control variable CO sets the ratio of memory cells for each of the eight states from state Er to G.

[0078] The code-to-code ratio (CR) divides user data into fixed-size data chunks and sets whether or not bit inversion is applied to each chunk. The CR code-to-code ratio can be set for each page of data.

[0079] Figure 7 shows data formats with various encoding rates applied. For example, user data is divided into 32-bit, 64-bit, or 128-bit segments, and bit inversion is applied or not applied to each segment.

[0080] When the coding rate is set to 32, the user data is divided into 32-bit segments, as shown in Figure 7(a). Furthermore, a flag FG indicating whether bit inversion is applied or not is added to the user data.

[0081] Similarly, when the coding rate is set to 64, the user data is divided into 64-bit segments, as shown in Figure 7(b). Furthermore, a flag FG indicating whether bit inversion is applied or not is added to the user data.

[0082] When the coding rate is set to 128, as shown in Figure 7(c), the user data is divided into 128-bit segments, and a flag FG indicating whether or not bit inversion is applied is added to the user data. Flag FG is referenced when error suppression decoding is performed on the read data read from the semiconductor memory 10.

[0083] The encoding parameters for the state control variable CO and the coding rate CR are stored, for example, in the RAM 22 within the memory controller 20. When the error suppression coding is performed by the error suppression coding / decoding circuit 25, the memory controller 20 reads the encoding parameters stored in the RAM 22 and performs error suppression coding on the user data received from the host device 2 based on the encoding parameters.

[0084] The write data transmitted from the memory controller 20 to the semiconductor memory 10 includes user data and flag FG, as well as management data MD and ECC data ED. The management data MD includes various data used by the memory controller 20 in write and read operations. The ECC data ED includes data generated by error correction coding of the ECC circuit 26 (e.g., parity bits).

[0085] Furthermore, the coding rate (CR) can be set to a different value for each page. For example, when TLC is applied to a memory cell, the coding rate can be set for the lower, middle, and upper pages, respectively.

[0086] Figure 8 shows an example of setting different coding rates for multiple pages. For example, a coding rate of 32 is set for the lower page, a coding rate of 64 for the middle page, and a coding rate of 128 for the upper page. Note that in some cases, a coding rate of 0 is used, and bit inversion is not applied to the page.

[0087] Next, the write operation, read operation, and error suppression coding operation in the first embodiment of the memory system 1 will be described.

[0088] In the write operation in memory system 1, first, user data is transmitted from the host device 2 to the memory controller 20. The memory controller 20 determines the block in the memory cell array 11 of the semiconductor memory 10 to which the user data should be written, i.e., the target block (hereinafter referred to as the target block) BLKn. The memory controller 20 reads the encoding parameters corresponding to the target block BLKn from the RAM 22. Using the read encoding parameters, the memory controller 20 performs error suppression encoding on the user data and generates the write data. The memory controller 20 transmits the write data to the semiconductor memory 10. The semiconductor memory 10 writes the write data received from the memory controller 20 to multiple memory cells connected to word lines in the target block BLKn of the memory cell array 11.

[0089] The read operation in memory system 1 is as follows: Data written to memory cells connected to multiple word lines within the target block BLKn is read by the semiconductor memory 10 and transmitted to the memory controller 20 as read data. The memory controller 20 reads the encoding parameters corresponding to the target block BLKn from the RAM 22. The memory controller 20 uses the read encoding parameters and the flag FG included in the read data to perform error suppression decoding on the read data and restore the user data. The restored user data is transmitted from the memory controller 20 to the host device 2.

[0090] Next, we will describe the error suppression coding in the write operation of the memory system 1 of the first embodiment.

[0091] During the write operation, error suppression coding is performed by the error suppression coding / decoding circuit 25 on the write data to be written to memory cells connected to multiple word lines within the target block BLKn. Subsequently, a word line (hereinafter referred to as the target word line) WL is selected from among the multiple word lines within the target block BLKn in which the error rate BER of the read data does not improve below the expected value. Then, optimization of the coding parameters used in error suppression coding is performed on the write data to be written to the memory cell connected to the target word line WL. Note that the selected target word line WL may be a single word line or multiple word lines.

[0092] In the optimization of coding parameters, N (where N is an integer greater than or equal to 1) coding rates are set for the write data written to the memory cell of the target word line WL, and the state control variable CO is optimized for the write data of each coding rate. Then, the coding rate that shows the smallest error rate among the error rates obtained by the error suppression coding with optimized state control variable CO is selected.

[0093] For example, the N coding rates are set as follows: If the target word line WL has three pages (lower page, middle page, and upper page), and each page can take on four coding rates of 0, 32, 64, and 128, then 64 coding rates are set for the target word line WL.

[0094] The process of optimizing coding parameters in error suppression coding of the memory system of the first embodiment will be described below with reference to Figures 9, 10, and 11.

[0095] Figure 9 is a flowchart showing the process of optimizing coding parameters in error suppression coding of the memory system of the first embodiment. This optimization process of coding parameters is controlled by the memory controller 20 (or processor 21).

[0096] Figure 10 shows the information stored in RAM22, which is used in the optimization process of coding parameters. RAM22 stores coding parameters including the state control variable CO and the coding rate CR, as well as the error rate CER. In the explanation using Figures 9 to 11, the initial state control variable is denoted as COa, and the updated state control variable is denoted as COu. When a state control variable CO is written, it is assumed to include at least one of the state control variables COa and COu.

[0097] Before being used by a user, an initial operational test is performed on the semiconductor memory 10, and the coding parameters and error rate CER are set or calculated using the test data obtained from the operational test. The coding parameters to be set include an initial state control variable COa that is applied to multiple word lines within the target block BLKn. The calculated error rate CER is the cell error rate (CER), and for example, when TLC is applied to a memory cell, the error rate CER is calculated for each of the eight states Er to G.

[0098] The average error rate CER of each state is determined, and the state control variable COa is calculated based on this average error rate CER. In other words, the state control variable COa is calculated such that memory cells belonging to states with an error rate CER higher than the average decrease, and memory cells belonging to states with an error rate CER lower than the average increase.

[0099] Within the memory cell array 11 of the semiconductor memory 10, there is usually a memory area where the setting information necessary for operation is stored. For example, in this case, this memory area is referred to as a ROM block. The state control variables COa (and COu) and the error rate CER are stored in the ROM block provided within the memory cell array 11.

[0100] When power is supplied to the memory system 1, the memory controller 20 reads the state control variables COa (and COu) and the error rate CER from the ROM block and stores them in the RAM 22. The memory controller 20 reads the state control variables COa and the error rate CER from the RAM 22 as needed and uses them for the optimization of encoding parameters.

[0101] The process of optimizing coding parameters is described below with reference to Figure 9.

[0102] First, the memory controller 20 calculates the probability PR for each state from the state control variable COa read from the RAM 22 (S11).

[0103] Next, the memory controller 20 calculates the error rate E for each word line from the occurrence probability PR for each state and the error rate CER read from the RAM 22 (S12).

[0104] Next, the memory controller 20 compares the calculated error rates E for each word line and, for example, selects the word line with the highest error rate as the word line WL to be optimized for encoding parameters (S13).

[0105] Next, the memory controller 20 applies N coding rates to the write data to be written to the memory cell of the target word line WL selected from within the target block BLKn. Furthermore, the memory controller 20 optimizes the state control variable COa for each write data to which the N coding rates have been applied (S14). Details of this optimization of the state control variable COa will be described later.

[0106] Next, the memory controller 20 selects an encoding rate that minimizes the error rate E of the read data for the write data to be written to the memory cell of the target word line WL (S15).

[0107] With the above steps, the optimization of the coding parameters (i.e., the state control variable COa and the coding rate CR) used in error suppression coding for the target word line WL is complete.

[0108] Furthermore, during subsequent write operations, error suppression coding is performed on the data written to the target word line WL within the target block BLKn, based on optimized coding parameters. For data written to other word lines within the target block BLKn, error suppression coding is performed based on the initial coding parameters.

[0109] Next, we will describe in detail the optimization of the state control variable COa as described in step S14. Figure 11 is a flowchart showing the process of optimizing the state control variable COa.

[0110] First, the memory controller 20 assigns 1 to variables i and k (S141 and S142). Variable i indicates which of the N possible coding rates it is. Variable i is an integer between 1 and N, where N is the number of coding rates and is an integer greater than or equal to 1. Variable k is the number of loops for the process to minimize the error rate, i.e., the process to optimize the state control variable COa. Variable k is an integer greater than or equal to 1.

[0111] Next, the memory controller 20 calculates the probability of occurrence PR for each state from the state control variable CO when the i-th coding rate is applied to the write data written to the memory cell of the target word line WL (S143). The state control variable COa is used to calculate the probability of occurrence PR for the first time, and the state control variable COu is used to calculate the probability of occurrence PR for the second time and beyond.

[0112] Next, the memory controller 20 calculates the error rate E of the read data read from the memory cell of the target word line WL based on the occurrence probability PR for each state and the error rate CER for each state in the target word line WL. k Calculate (S144).

[0113] Next, the memory controller 20 calculates the decrease value (or change amount) of the error rate E obtained this time k subtracted from the error rate E obtained in the previous time k-1 to obtain the decrease value of the error rate E k . Then, it is determined whether the decrease value of the error rate E k is less than or equal to a predetermined threshold value E t (S145).

[0114] When the decrease value of the error rate E k is greater than the threshold value E t (No), the memory controller 20 increments k (S146). Further, the memory controller 20 calculates the change amount ΔCO of the state control variable CO such that the error rate E k decreases. In the calculation of the change amount ΔCO, a local optimization method such as the gradient descent method or the Nelder Mead method is used. Note that the first calculation of the change amount ΔCO targets the state control variable COa, and the second and subsequent calculations of the change amount ΔCO target the state control variable COu.

[0115] Next, the memory controller 20 updates the state control variable CO with the value obtained by adding the change amount ΔCO as the new state control variable CO (S148). Note that in the first update of the state control variable, the change amount ΔCO is added to the state control variable COa, and in the second and subsequent updates of the state control variable, the change amount ΔCO is added to the state control variable COu. After that, the memory controller 20 transfers the process to step S143 and executes the processes after step S143. That is, the memory controller 20 changes the state control variable CO by the change amount ΔCO until the decrease value of the error rate E k becomes less than or equal to the threshold value E t and updates the state control variable CO.

[0116] On the other hand, in step S145, when the decrease value of the error rate E k is less than or equal to the threshold value E tIf the following is true (Yes), the memory controller 20 determines whether the variable i is equal to N (S149). If the variable i is not equal to N (No), the memory controller 20 increments the variable i (S150), proceeds to step S142, and executes the processes from step S142 onward. That is, the memory controller 20 repeats the processes from step S142 onward until the variable i becomes equal to N, or in other words, until the calculation of the case when the Nth coding rate is applied to the write data written to the memory cell of the target word line WL is completed.

[0117] On the other hand, in step S149, if variable i is equal to N (Yes), the memory controller 20 finishes the optimization process for the state control variable COa and proceeds to step S15.

[0118] Figure 12 shows the change in error rate E due to optimization processing in error suppression coding of the memory system of the first embodiment. In Figure 12, BER is represented as the error rate E for different coding rates CRa, CRb, and CRc. For example, CRa has a coding rate of 32, CRb has a coding rate of 64, and CRc has a coding rate of 128.

[0119] As shown in Figure 12, the BER can be reduced for any data to which any coding rate is applied by repeatedly updating the state control variable CO in steps S143 to S148. In the coding rates shown here, the coding rate CRa that shows the smallest error rate E is selected in step S15.

[0120] 1.3 Effects of the First Embodiment According to the first embodiment, a memory system can be provided that can improve the reliability of data writing and reading.

[0121] For example, when error suppression coding is performed on data written to memory cells connected to all word lines within a block to be written, there may be word lines (target word lines) where the error rate of the read data does not improve below the expected value. In the first embodiment, error suppression coding optimization is performed on the data written to the memory cells connected to these target word lines. For each of the N coding rates among the coding parameters in error suppression coding, the state control variable CO is first optimized, and the coding rate with the lowest error rate is selected. Then, error suppression coding is performed on the data written to the memory cells connected to the target word lines based on the selected coding parameters.

[0122] Figure 13 shows the BER (or FER) for each word line when error suppression coding is applied to all word lines within the target block and the write data written to the memory cells connected to the target word lines. In Figure 13, there are 162 word lines within the target block, and these word lines are indicated as WL0-WL161. The horizontal axis represents the BER of the read data read from the word lines within the target block, and the vertical axis represents the position of the word lines within the target block.

[0123] Figure 13 shows the BER (Block Error Rate) when error suppression coding is performed using the same coding parameter PSCa for data written to memory cells connected to all word lines within the target block (A), and the BER when error suppression coding is not performed (X). Furthermore, the BER when error suppression coding is performed based on the optimized coding parameter PSCb for data written to memory cells connected to the target word lines (B) is shown.

[0124] As shown in Figure 13, when error suppression coding is performed on all word lines within the target block using the same coding parameter PSCa, the BER decreases for all word lines, but there is still a word line WL80 whose BER does not decrease to the expected value.

[0125] In the first embodiment, a word line WL80 is selected in which the BER does not decrease to the expected value, i.e., a word line WL80 in which the BER does not improve. Then, optimization of the coding parameters in error suppression coding is performed on the selected word line (hereinafter referred to as the target word line) WL80. The coding parameter PSCb used in error suppression coding is optimized for the data written to the target word line WL80 so that the BER of the data read from the target word line WL80 decreases. As a result, as shown by B in Figure 13, the BER of the data read from the target word line WL80 can be reduced.

[0126] As described above, the memory system of the first embodiment can improve the reliability of data writing and reading.

[0127] 2. Second Embodiment The memory system of the second embodiment will now be described. In the second embodiment, the coding rate is first optimized for the data written to the memory cell connected to the target word line WL within the target block BLKn, and then the state control variable CO is optimized for the data to which the optimized coding rate has been applied. The second embodiment will mainly be described in terms of differences from the first embodiment. Other configurations not described in the second embodiment are the same as in the first embodiment.

[0128] 2.1 Memory System Operation Referring to Figures 14 and 15, the process of optimizing coding parameters in error suppression coding of the memory system of the second embodiment will be described.

[0129] Figure 14 is a flowchart showing the optimization process of coding parameters in error suppression coding of a memory system in the second embodiment. This optimization process of coding parameters is controlled by the memory controller 20 (or processor 21). In the explanation using Figures 14 and 15, the initial state control variable is denoted as COa, and the updated state control variable is denoted as COu. When a state control variable is denoted as CO, it is assumed to include at least one of the state control variables COa and COu.

[0130] As described above, an initial operational test is performed on the semiconductor memory 10, and the state control variable COa and the error rate CER are set or calculated using the test data obtained from the operational test. The state control variable COa (and COu) and the error rate CER are stored in the RAM 22. The memory controller 20 reads the state control variable COa and the error rate CER from the RAM 22 and uses them for the optimization of the encoding parameters.

[0131] The process of optimizing the coding parameters is described below with reference to Figure 14.

[0132] First, the memory controller 20 calculates the probability PR for each state from the state control variable COa read from the RAM 22 (S11).

[0133] Next, the memory controller 20 calculates the error rate E for each word line from the occurrence probability PR for each state and the error rate CER read from the RAM 22 (S12).

[0134] Next, the memory controller 20 compares the calculated error rates E for each word line and, for example, selects the word line with the highest error rate as the word line WL to be optimized for encoding parameters (S13).

[0135] Next, the memory controller 20 applies N coding rates to the write data written to the target word line WL within the target block BLKn. Furthermore, the memory controller 20 calculates the error rate E(N) of the read data obtained for each write data to which the N coding rates have been applied (S21).

[0136] Next, the memory controller 20 selects the coding rate CRm corresponding to the minimum value among the calculated error rates E(N) (S22).

[0137] Next, the memory controller 20 optimizes the state control variable COa for the write data to which the coding rate CRm has been applied (S23). That is, the memory controller 20 optimizes the state control variable COa for the write data to which the coding rate CRm has been applied to the memory cell of the target word line WL. Details of this optimization of the state control variable COa will be described later.

[0138] With the above steps, the optimization of the coding parameters (i.e., coding rate CR and state control variable COa) used in error suppression coding for the target word line WL is complete.

[0139] Furthermore, during subsequent write operations, error suppression coding is performed on the data written to the target word line WL within the target block BLKn, based on optimized coding parameters. For data written to other word lines within the target block BLKn, error suppression coding is performed based on the initial coding parameters.

[0140] Next, we will describe in detail the optimization of the state control variable COa as described in step S23. Figure 15 is a flowchart showing the process of optimizing the state control variable COa.

[0141] First, the memory controller 20 assigns 1 to the variable k (S231). The variable k is the number of loops for the process to optimize the state control variable COa. The variable k is an integer greater than or equal to 1.

[0142] Next, the memory controller 20 calculates the probability of occurrence PR for each state from the state control variable CO when the coding rate CRm is applied to the write data written to the memory cell of the target word line WL (S232). The state control variable COa is used to calculate the probability of occurrence PR for the first time, and the state control variable COu is used to calculate the probability of occurrence PR for the second time and beyond.

[0143] Next, the memory controller 20 calculates the error rate E of the read data read from the memory cell of the target word line WL based on the occurrence probability PR for each state and the error rate CER for each state in the target word line WL. k Calculate (S233).

[0144] Next, the memory controller 20 uses the error rate E that was determined this time. k The error rate E calculated last time k-1 Subtract the error rate E k We calculate the decrease in the error rate E. k The decrease value is a predetermined threshold E t Determine whether the following applies (S234).

[0145] The memory controller 20 has an error rate E k The decrease value is the threshold E. t When it is greater than (No), k is incremented (S235). Furthermore, the memory controller 20 has an error rate E k The change in the state control variable CO, ΔCO, that reduces the value is calculated (S236). Local optimization methods such as gradient descent or the Nelder-Mead method are used to calculate the change in ΔCO. Note that the first calculation of the change in ΔCO targets the state control variable COa, while subsequent calculations target the state control variable COu.

[0146] Next, the memory controller 20 updates the state control variable CO with a value obtained by adding the change amount ΔCO to the current state control variable CO (S237). Note that for the first update of the state control variable, the change amount ΔCO is added to the state control variable COa, and for subsequent updates, the change amount ΔCO is added to the state control variable COu. After that, the memory controller 20 proceeds to step S232 and executes the processes from step S232 onward.

[0147] On the other hand, in step S234, the error rate E k The decrease value is the threshold E. t When the following is true (Yes), the memory controller 20 terminates the optimization process of the state control variable COa and also terminates the error suppression coding process.

[0148] In other words, the memory controller 20 has an error rate E k The decrease value is the threshold E. t The state control variable CO is changed by an amount ΔCO until the following condition is met, and the state control variable CO is updated. Then, the error rate E k The decrease value is the threshold E. t The error suppression coding process will terminate when the following conditions are met.

[0149] Figure 16 shows the change in the error rate E due to the optimization process in the error suppression coding of the memory system of the second embodiment. In Figure 16, the BER for the coding rate CRm of the target word line and the BER for the coding rate CR of all word lines in the target block are shown.

[0150] As shown in Figure 16, in error suppression coding, by optimizing the coding rate, i.e., selecting the coding rate CRm, and further optimizing the state control variable CO, the BER for the write data written to the memory cell of the target word line can be reduced.

[0151] 2.3 Effects of the Second Embodiment According to the second embodiment, a memory system can be provided that can improve the reliability of data writing and reading.

[0152] In the second embodiment, the coding rate is first optimized for the data written to the memory cell connected to the target word line, and then the state control variable CO is optimized for the data to which the optimized coding rate has been applied. Then, error suppression coding is performed on the data written to the memory cell connected to the target word line based on the optimized coding parameters, i.e., the optimized coding rate and state control variable.

[0153] As described above, the memory system of the second embodiment can improve the reliability of data writing and reading.

[0154] Furthermore, although the above embodiment used NAND flash memory as an example of semiconductor memory, it is not limited to NAND flash memory but can be applied to all other semiconductor memories, and even to various storage devices other than semiconductor memory. Also, the flowchart described in the above embodiment can be rearranged as much as possible in terms of the order of processing.

[0155] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0156] 1...Memory system, 2...Host device, 10...Semiconductor memory, 11...Memory cell array, 12...Input / output circuit, 13...Logic control circuit, 14...Ready / busy circuit, 15A...Status register, 15B...Address register, 15C...Command register, 16...Programmable logic controller, 17...Voltage generation circuit, 18...Raw decoder, 19A...Column decoder, 19B...Data register, 19C...Sense amplifier, 20...Memory controller, 21...Processor, 22...RAM, 23...ROM, 24...Randomizer, 25...Error suppression coding / decoding circuit, 26...ECC circuit, 27...NAND interface circuit, 28...Host interface circuit.

Claims

1. A semiconductor memory including multiple word lines connected to multiple memory cells, A memory controller that performs error suppression coding on the data written to the semiconductor memory, It is equipped with, The aforementioned memory controller For the data to be written to the plurality of memory cells connected to the plurality of word lines, the error suppression coding is performed based on the first coding parameter to generate first write data. The first written data written to the plurality of memory cells is read out as the first read data. The error rate for each of the multiple word lines is determined from the first read data, and a first word line is selected from the multiple word lines based on the error rate for each word line. For data to be written to the first memory cell connected to the first word line, the first coding parameter is changed and the error suppression coding is performed to generate second write data. Based on the error rate of the second read data relative to the second written data, the second encoding parameter is set. Error suppression coding is performed on the data written to the first memory cell connected to the first word line, based on the second coding parameter. Memory system.

2. Each of the plurality of memory cells connected to the plurality of word lines has a threshold voltage, The threshold voltage of each of the aforementioned plurality of memory cells belongs to one of a plurality of states to which a plurality of voltage distributions are assigned. Each of the first coding parameter and the second coding parameter includes a control variable that indicates the ratio of the number of memory cells belonging to each of the plurality of states, The memory system according to claim 1.

3. The memory controller calculates the control variable included in the second encoding parameter from the value at which the error rate of the second read data takes its minimum value, while changing the control variable included in the first encoding parameter. The memory system according to claim 2.

4. The first coding parameter includes a first coding rate for setting the first data amount when dividing the data written to the plurality of memory cells connected to the plurality of word lines into first data amounts, The second coding parameter includes a second coding rate for setting the second data amount when dividing the data written to the first memory cell connected to the first word line into second data amounts, The aforementioned memory controller In the error suppression coding based on the first coding parameter, whether or not to perform data inversion is set for each segment of data divided by the first coding rate. In the error suppression coding based on the second coding parameter, the second coding rate and whether or not to perform data inversion are set for each partitioned data partitioned by the second coding rate. The memory system according to claim 1.

5. The first coding parameter includes a first coding rate for setting the first data amount when dividing the data written to the plurality of memory cells connected to the plurality of word lines into first data amounts, The second coding parameter includes a second coding rate for setting the second data amount when dividing the data written to the first memory cell connected to the first word line into second data amounts, The aforementioned memory controller In the error suppression coding based on the first coding parameter, whether or not to perform data inversion is set for each segment of data divided by the first coding rate. In the error suppression coding based on the second coding parameter, the second coding rate and whether or not to perform data inversion are set for each partitioned data partitioned by the second coding rate. In setting the second coding parameter, the memory controller For the data to be written to the first memory cell, error suppression coding is performed using each of the multiple second coding rates and the control variable, while changing the control variable, to generate a plurality of second write data. Using the value that minimizes the error rate of the second read data for each of the plurality of second write data, the second coding rate included in the second coding parameter is selected from the plurality of second coding rates. The memory system according to claim 2.

6. The first coding parameter includes a first coding rate for setting the first data amount when dividing the data written to the plurality of memory cells connected to the plurality of word lines into first data amounts, The second coding parameter includes a second coding rate for setting the second data amount when dividing the data written to the first memory cell connected to the first word line into second data amounts, The aforementioned memory controller In the error suppression coding based on the first coding parameter, whether or not to perform data inversion is set for each segment of data divided by the first coding rate. In the error suppression coding based on the second coding parameter, the second coding rate and whether or not to perform data inversion are set for each partitioned data partitioned by the second coding rate. In setting the second coding parameter, the memory controller For the data to be written to the first memory cell, error suppression coding is performed using each of the multiple second coding rates and the control variable to generate a plurality of second write data. Using the value that minimizes the error rate of the second read data for each of the plurality of second write data, the second coding rate included in the second coding parameter is selected from the plurality of second coding rates. For the data to be written to the first memory cell, the error suppression coding is performed using the selected second coding rate and the control variable, while changing the control variable, to generate a plurality of the second write data. The control variable included in the second coding parameter is calculated from the value at which the error rate of the second read data is minimized for each of the plurality of second write data. The memory system according to claim 2.

7. The error rate for each word line is determined for each word line and is the ratio of the number of error bits to the total number of bits of data written to the plurality of memory cells connected to each word line. The error rate of the second read data is the ratio of the number of error bits in the second read data to the total number of bits in the second written data. The memory system according to claim 1.

8. The first word line includes one or more word lines, The memory system according to claim 1.

9. The aforementioned memory controller Multiple second write data are generated by performing the error suppression coding while changing the first coding parameter, When the change in the error rate of the plurality of second read data relative to the plurality of second write data falls below a threshold, the first coding parameter is changed, and the first coding parameter at the end is set as the second coding parameter. The memory system according to claim 1.

10. The data written to the first memory cell connected to the first word line includes a plurality of pages, The memory controller performs the error suppression coding and sets the second coding parameter for each page in the plurality of pages. The memory system according to claim 1.

11. The memory controller is The error rate is calculated for each state from the first read data, The average error rate of the state is calculated, and the control variable is generated from the average error rate. Based on the control variables, the probability of occurrence for each state corresponding to the data written to the first memory cell connected to the first word line is calculated. The error rate of the second readout data is calculated from the occurrence probability for each state and the error rate for each state for the first word line. The memory system according to claim 2.

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