Semiconductor memory

Abstract

To provide a semiconductor memory device that can suppress power consumption. [Solution] The semiconductor memory device 2 comprises an input / output pad group 32, a memory cell array 21 including a plurality of memory cells, and an input / output circuit 22 provided between the input / output pad group 32 and the memory cell array 21. The input / output circuit 22 comprises a plurality of transistors QH1, QL1, and substrate bias voltage supply circuits 40, 41 that can switch between supplying a first voltage with the same value as the power supply voltage of the input / output circuit and a second voltage with a different value from the first voltage as the substrate bias voltage of the plurality of transistors QH1, QL1.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] Semiconductor memory devices applicable to non-volatile memories are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the embodiments of the present invention is to provide a semiconductor memory device capable of suppressing power consumption.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes an input / output pad, a memory cell array including a plurality of memory cells, and an input / output circuit provided between the input / output pad and the memory cell array. The input / output circuit includes a plurality of transistors and a substrate bias voltage supply circuit capable of switching and supplying a first voltage having the same value as the power supply voltage of the input / output circuit and a second voltage having a value different from the first voltage as the substrate bias voltage of the plurality of transistors.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a block diagram showing the configuration of a memory system including a semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 is a block diagram showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 3A]Figure 3A shows an example of a command sequence that instructs a write operation to non-volatile memory. [Figure 3B] Figure 3B shows an example of a command sequence for writing to non-volatile memory. [Figure 4A] Figure 4A shows an example of a command sequence that instructs a read operation on non-volatile memory. [Figure 4B] Figure 4B shows an example of a command sequence for reading operations from non-volatile memory. [Figure 5] Figure 5 is a block diagram showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 6] Figure 6 is a circuit diagram showing an example of a data transmission path applied to the input / output circuit of a semiconductor memory device according to the first embodiment. [Figure 7] Figure 7 is a diagram illustrating the first operation in the first implementation system. [Figure 8] Figure 8 is a diagram illustrating the second operation in the first implementation system. [Figure 9] Figure 9 is a circuit diagram showing an example of a data transmission path applied to the input / output circuit of a semiconductor memory device according to the second embodiment. [Figure 10] Figure 10 is a diagram illustrating the first operation in the second implementation system. [Figure 11] Figure 11 is a diagram illustrating the second operation in the second implementation system. [Modes for carrying out the invention]

[0007] The embodiments will be described with reference to the drawings. In the drawings described below, identical or similar parts are denoted by the same or similar reference numerals. The drawings are schematic. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical idea and do not specify the material, shape, structure, arrangement, etc. of the parts. Various modifications can be made to the embodiments.

[0008] (First Embodiment) The semiconductor memory device according to the first embodiment is applicable, for example, to the non-volatile memory 2 included in the memory system 3 shown in Figure 1. The non-volatile memory 2 is a semiconductor memory that stores data non-volatilely. The non-volatile memory 2 includes, for example, NAND flash memory. The memory controller 1 controls the operation of the non-volatile memory 2. The host is, for example, an electronic device such as a personal computer or a mobile terminal.

[0009] First, let's explain the memory system 3 shown in Figure 1. In the following explanation, signal DQ<7:0> refers to signal DQ, where each is a 1-bit signal. <0> DQ <1> ...DQ <7> This represents a set of values. Signal DQ<7:0> is an 8-bit signal.

[0010] Memory controller 1 receives instructions from the host and controls non-volatile memory 2 based on the received instructions. Specifically, memory controller 1 writes data to non-volatile memory 2 when instructed to do so by the host, and reads data from non-volatile memory 2 when instructed to do so by the host and sends it to the host. The non-volatile memory cells to be written to in non-volatile memory 2 are specified by memory controller 1. In the following, non-volatile memory cells in non-volatile memory 2 will also be referred to as "memory cells".

[0011] The memory controller 1 and the non-volatile memory 2 transmit and receive signals via separate signal lines, in accordance with the interface standards of the memory controller 1 and the non-volatile memory 2. The signals transmitted and received between the memory controller 1 and the non-volatile memory 2 include signals / CE, / RB, CLE, ALE, / WE, / RE, RE, / WP, DQ<7:0>, DQS, and / DQS.

[0012] Signal / CE is a chip enable signal for enabling non-volatile memory 2. Signal / RB is a ready-busy signal indicating whether non-volatile memory 2 is ready (ready to receive external commands) or busy (not ready to receive external commands). Signal CLE is a command latch enable signal that notifies non-volatile memory 2 that signal DQ<7:0> sent to non-volatile memory 2 while signal CLE is at a high level is a command. Signal ALE is an address latch enable signal that notifies non-volatile memory 2 that signal DQ<7:0> sent to non-volatile memory 2 is an address while signal ALE is at a high level. Signal / WE is a write enable signal that instructs non-volatile memory 2 to capture signal DQ<7:0> sent to non-volatile memory 2. In Single Data Rate (SDR) mode, the rising edge of signal / WE instructs non-volatile memory 2 to capture signal DQ<7:0> as a command, address, or data sent to non-volatile memory 2. Furthermore, in Double Data Rate (DDR) mode, the rising edge of signal / WE instructs the non-volatile memory 2 to capture signal DQ<7:0> as a command or address. Signal / WE is asserted by the memory controller 1 each time the non-volatile memory 2 receives a command, address, or data.

[0013] The signal / RE is a read enable signal that instructs the memory controller 1 to read the signal DQ<7:0> from the non-volatile memory 2. The signal RE is the complementary signal of the signal / RE. For example, the signals / RE and RE are used to control the timing at which the non-volatile memory 2 outputs the signal DQ<7:0>. More specifically, in the single data rate mode, it instructs the non-volatile memory 2 to output the signal DQ<7:0> as data at the falling edge of the signal / RE. Also, in the double data rate mode, it instructs the non-volatile memory 2 to output the signal DQ<7:0> as data at the falling edge and rising edge of the signal / RE. The signal / WP is a write protect signal that instructs the non-volatile memory 2 to prohibit writing data.

[0014] The signal DQ<7:0> is the entity of the data transmitted and received between the non-volatile memory 2 and the memory controller 1. The signal DQ<7:0> includes the command CMD, the address ADD, and the data DAT. The data DAT includes the data to be written to the non-volatile memory (hereinafter also referred to as "write data") and the data read from the non-volatile memory (hereinafter also referred to as "read data"). The signal DQS is a data strobe signal used to control the operation timing of the non-volatile memory 2 related to the signal DQ<7:0>. The signal / DQS is the complementary signal of the signal DQS. The signals DQS and / DQS are generated based on, for example, the signals RE and / RE. More specifically, in the double data rate mode, it instructs the non-volatile memory 2 to capture the signal DQ<7:0> as data at the falling edge and rising edge of the signal DQS. Also, in the double data rate mode, the signal DQS is generated based on the falling edge and rising edge of the signal / RE and is output together with the signal DQ<7:0> as data from the non-volatile memory 2.

[0015] The memory controller 1 includes a RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. The RAM 11, the processor 12, the host interface 13, the ECC circuit 14, and the memory interface 15 are connected to each other by a bus 16.

[0016] The RAM 11 temporarily stores the data received from the host until it is stored in the non-volatile memory 2, or temporarily stores the data read from the non-volatile memory 2 until it is transmitted to the host. The RAM 11 is a general-purpose semiconductor memory such as, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0017] The processor 12 controls the operation of the entire memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit), a MPU (Micro Processing Unit), or the like. The processor 12 issues a read instruction to the non-volatile memory 2 in response to a read instruction for the data received from the host, for example. This operation is the same in the case of writing data. The processor 12 determines the storage area (memory area) of the non-volatile memory 2 for the data stored in the RAM 11. In addition, the processor 12 has a function of performing various operations on the read data from the non-volatile memory 2.

[0018] The host interface 13 is connected to the host and executes processing according to the interface standard between the host and itself. The host interface 13 transfers, for example, the instructions and data received from the host to the processor 12. In addition, the host interface 13 transmits the data read from the non-volatile memory 2, the response from the processor 12, etc. to the host.

[0019] The ECC circuit 14 encodes the data stored in the RAM 11 to generate a codeword. The ECC circuit 14 also decodes the codeword read from the non-volatile memory 2.

[0020] The memory interface 15 is connected to the non-volatile memory 2 via a bus and performs communication with the non-volatile memory 2. The memory interface 15 sends the command CMD, address ADD, and write data to the non-volatile memory 2 according to instructions from the processor 12. The memory interface 15 also receives read data from the non-volatile memory 2.

[0021] Figure 1 shows an example configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be integrated into the memory interface 15. Alternatively, the ECC circuit 14 may be integrated into the non-volatile memory 2.

[0022] When a write command is received from the host, the memory system 3 operates as follows: The processor 12 temporarily stores the data to be written in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0023] When a read command is received from the host, the memory system 3 operates as follows: The memory interface 15 inputs the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0024] Figure 2 is a block diagram showing an example configuration of the non-volatile memory 2. The non-volatile memory 2 comprises a memory cell array 21, an input / output circuit 22, a logic control circuit 24, a register 26, a sequencer 27, a voltage generation circuit 28, a row decoder 30, a sense amplifier 31, and a control signal transmission circuit 50. Furthermore, the non-volatile memory 2 comprises a group of input / output pads 32, a group of logic control pads 34, and a group of power input terminals 35.

[0025] The memory cell array 21 includes a plurality of memory cells (not shown) associated with word lines and bit lines. The memory cell array 21 has, for example, a NAND string.

[0026] The input / output circuit 22 transmits and receives signals DQ<7:0>, DQS, and / DQS to and from the memory controller 1. The input / output circuit 22 transfers the command CMD and address ADD within signal DQ<7:0> to register 26. The input / output circuit 22 also transmits and receives write data and read data to and from the sense amplifier 31.

[0027] The logic control circuit 24 receives signals / CE, CLE, ALE, / WE, / RE, RE, / WP, and / RB from the memory controller 1. The logic control circuit 24 also forwards signal / RB to the memory controller 1 to notify the outside of the state of the non-volatile memory 2.

[0028] Register 26 holds the command CMD and address ADD. Register 26 transfers address ADD to the row decoder 30 and sense amplifier 31, and also transfers command CMD to the sequencer 27.

[0029] The sequencer 27 receives a command CMD and controls the entire non-volatile memory 2 according to a sequence based on the received command CMD. The sequencer 27 supplies control signals to the row decoder 30 and sense amplifier 31, for example, via control signal wiring 50M. For example, multiple control signal wirings 50M may be provided. In this case, multiple types of control signals are supplied from the sequencer 27 to the row decoder 30 and / or sense amplifier 31, respectively, via multiple control signal wirings 50M.

[0030] The voltage generation circuit 28 generates the voltages necessary for operations such as writing data, reading data, and erasing data, based on instructions from the sequencer 27. Based on the address from the register 26, the voltage generation circuit 28 supplies various voltages to the row decoder 30, sense amplifier 31, and memory cell array 21.

[0031] The row decoder 30 receives the block address and row address in address ADD from register 26. The row decoder 30 selects a block based on the block address and a word line based on the row address.

[0032] The sense amplifier 31 is connected to the memory cell array 21. When reading data, the sense amplifier 31 senses the read data read from the memory cell onto the bit line and transfers the sensed read data to the input / output circuit 22. When writing data, the sense amplifier 31 transfers the write data to the memory cell via the bit line.

[0033] Data transfer between the input / output circuit 22 and the sense amplifier 31 is performed via the data bus YIO. The data bus YIO includes multiple data wires connected between the input / output circuit 22 and the sense amplifier 31. Data written to and read from the non-volatile memory 2 propagates along the data bus YIO.

[0034] The control signal transmission circuit 50 generates a clock signal used for the operation of the non-volatile memory 2 based on the signals / RE and RE supplied from the memory controller 1. In Figure 2, the control signal transmission circuit 50 is shown as part of the sequencer 27. However, the control signal transmission circuit 50 may be configured, for example, as part of the input / output circuit 22 and / or the logic control circuit 24. Alternatively, the control signal transmission circuit 50 may be configured as a circuit separate from the sequencer 27, the input / output circuit 22, and the logic control circuit 24.

[0035] The input / output pad group 32 is equipped with multiple terminals (pads) corresponding to signals DQ<7:0> and DQS, / DQS, for transmitting and receiving various signals including data between the non-volatile memory 2 and the memory controller 1.

[0036] The logic control pad group 34 is equipped with multiple terminals (pads) corresponding to signals / CE, CLE, ALE, / WE, / RE, RE, / WP, and / RB in order to transmit and receive signals between the non-volatile memory 2 and the memory controller 1.

[0037] The power input terminal group 35 includes multiple terminals to which a first power supply voltage Vcc, a second power supply voltage VccQ, and a ground voltage Vss as a third power supply voltage are input, in order to supply various operating power to the non-volatile memory 2 from an external source. The first power supply voltage Vcc is a circuit power supply voltage that is generally supplied externally as an operating power supply. The first power supply voltage Vcc is the power supply voltage supplied to the core portion of the semiconductor chip (hereinafter simply referred to as "chip") on which the non-volatile memory 2 is formed, and is, for example, 2.5V. The second power supply voltage VccQ is used when sending and receiving signals between the memory controller 1 and the non-volatile memory 2, and is, for example, 1.2V.

[0038] Figure 3A shows an example of a command sequence that instructs a write operation to non-volatile memory 2 (hereinafter also referred to as a "data-in operation"). Figure 3B shows an example of a command sequence related to a data-in operation.

[0039] As shown in Figure 3A, during a data-in operation, the memory controller 1 issues a set of commands to the non-volatile memory 2 to instruct the data-in operation while toggling the signal / WE. The set of commands to instruct the data-in operation includes, for example, the read command "80h", an address ADD over 5 cycles, and the command "10h". The read command "80h" is a command that instructs the writing of data to the user data area in the memory cell array 21. The command "10h" is a command that instructs the start of the data-in operation.

[0040] After the command "10h", the memory controller 1 transfers the data to be written to the memory cell array 21 as the signal DQ<7:0> to the non-volatile memory 2, as shown in Figure 3B. When transferring the data to be written to the non-volatile memory 2, the memory controller 1 toggles the signals DQS and / DQS in synchronization with the signal DQ<7:0> and transfers the data to the non-volatile memory 2.

[0041] When the non-volatile memory 2 receives data to be written, it starts writing to the user data area in the memory cell array 21 and sets the signal / RB to L level to inform the memory controller 1 that the non-volatile memory 2 is busy. After the writing operation is complete, the non-volatile memory 2 sets the signal / RB to H level to inform the memory controller 1 that the non-volatile memory 2 is ready.

[0042] Figure 4A shows an example of a command sequence that instructs a read operation of non-volatile memory 2 (hereinafter also referred to as a "data-out operation"). Figure 4B shows an example of a command sequence related to a data-out operation.

[0043] As shown in Figure 4A, during a data-out operation, the memory controller 1 issues a set of commands to the non-volatile memory 2 to instruct the data-out operation while toggling the signal / WE. The set of commands to instruct the data-out operation includes, for example, the read command "00h", an address ADD over 5 cycles, and the command "30h". The read command "00h" is a command that instructs the non-volatile memory 2 to read data from the memory cell array 21. The command "30h" is a command that instructs the start of the data-out operation. When the non-volatile memory 2 receives the command "30h", it starts reading data from the memory cell array 21 and sets the signal / RB to L level to inform the memory controller 1 that the non-volatile memory 2 is busy. After the reading operation is complete, the non-volatile memory 2 sets the signal / RB to H level to inform the memory controller 1 that the non-volatile memory 2 is ready.

[0044] After confirming that the non-volatile memory 2 is ready, the memory controller 1 toggles signals / RE and RE as shown in Figure 4B. The non-volatile memory 2 transfers the read data to the memory controller 1 as signal DQ<7:0> in synchronization with signals / RE and RE. The non-volatile memory 2 also toggles signals DQS and / DQS in synchronization with signal DQ<7:0> and transfers them to the memory controller 1.

[0045] Furthermore, after confirming that the non-volatile memory 2 is ready, the memory controller 1 may issue a command set to the non-volatile memory 2 to instruct a data-out operation while toggling the signal / WE. The command set to instruct a data-out operation includes, for example, the data-out command "05h", address ADD over 5 cycles, and the command "E0h". In this case, after sending the command "E0h" to the non-volatile memory 2, the memory controller 1 toggles the signals / RE and RE after a predetermined period of time has elapsed. The non-volatile memory 2 transfers the read data to the memory controller 1 as the signal DQ<7:0> in synchronization with the signals / RE and RE. The non-volatile memory 2 also toggles the signals DQS and / DQS in synchronization with the signal DQ<7:0> and transfers the data to the memory controller 1.

[0046] Figure 5 is a block diagram showing a part of the configuration of the non-volatile memory 2. The following explanation will describe the transmission and reception of data between the input / output circuit 22 and the sense amplifier 31 in the non-volatile memory 2, with reference to Figure 5.

[0047] The input / output circuit 22 transmits and receives write and read data to and from the sense amplifier 31 via the data bus YIO. The data bus YIO is configured in which multiple data wires connected between the input / output circuit 22 and the sense amplifier 31 are arranged adjacently without shielding. The data bus YIO includes, for example, 200 data wires. By not shielding the data wires, the increase in the area of ​​the chip on which the non-volatile memory 2 is formed can be suppressed.

[0048] The sense amplifier 31 includes a sense amplifier unit 31A connected to the bit lines BL0-BLm, a data register 31B connected to the sense amplifier unit 31A, and a data multiplexer 31C connected to the data register 31B. The number of bit lines is, for example, approximately 130,000. The sense amplifier unit 31A senses the read data read onto the bit lines and transfers the write data to the memory cell via the bit lines. The data register 31B holds the read and write data. The data multiplexer 31C selects the data to propagate along the signal lines constituting the data bus YIO from the data propagating along the bit lines BL0-BLm.

[0049] The input / output circuit 22 may include a conversion circuit 221 for converting the bus width. The conversion circuit 221 converts the bus width of a data bus YIO containing, for example, 128 bit lines to a bus containing 8 signal lines, each carrying a signal DQ<7:0>. The conversion circuit 221 may also be, for example, a FIFO (First In First Out) circuit. For example, the connection between the sense amplifier 31 and the input / output circuit 22, and between the input / output circuit 22 and the memory controller 1, operates at a second power supply voltage VccQ (e.g., 1.2V).

[0050] The control signal transmission circuit 50 is, for example, part of the sequencer 27 shown in Figure 2. The control signal transmission circuit 50 generates a clock signal CLK based on the signals / RE and RE supplied from the memory controller 1 during data-out operation.

[0051] Figure 6 is a circuit diagram showing an example of a data transmission path SL1 and a board bias voltage supply circuit 40 applied to the input / output circuit 22 in the first embodiment. The data transmission path SL1 is for transmitting data SIG from the data input terminal In to the data output terminal Out. Data SIG is a binary digital signal, for example, of the levels of the second power supply voltage VccQ and the ground voltage Vss.

[0052] The input / output circuit 22 includes a plurality of data transmission paths SL1, which are composed of a plurality of arms A1 to A3, provided between the data input terminal In and the data output terminal Out, and a board bias voltage supply circuit 40. The data input terminal In is connected, for example, to one of the signal lines that constitute the data bus YIO. The data output terminal Out is connected, for example, to the corresponding terminal (pad) of the input / output pad group 32 via the conversion circuit 221.

[0053] In Figure 6, three arms A1 to A3 are shown for simplification, but any number of arms can be arranged according to the length of the data transmission path SL1. Furthermore, any number of data transmission paths SL1 corresponding to the number of signal lines constituting the data bus YIO can be provided inside the input / output circuit 22.

[0054] In the data transmission path SL1, each arm A1 to A3 has the same configuration; therefore, the configuration will be explained using the first arm A1, and the explanations of the second arm A2 and third arm A3 will be omitted. The first arm A1 comprises a high-side transistor QH1 and a low-side transistor QL1. The high-side transistor QH1 is composed of a P-channel MOSFET. The low-side transistor QL1 is composed of an N-channel MOSFET.

[0055] The first electrode (drain) of the high-side transistor QH1 is connected to the second power supply voltage VccQ. The second electrode (source) of the high-side transistor QH1 is connected to the first electrode (drain) of the low-side transistor QL1. The second electrode (source) of the low-side transistor QL1 is connected to the ground voltage Vss. In other words, the high-side transistor QH1 and the low-side transistor QL1 constitute a CMOS circuit. The control electrode (gate) of the high-side transistor QH1 and the control electrode (gate) of the low-side transistor QL1 are connected to the data input terminal In. The connection point of the high-side transistor QH1 and the low-side transistor QL1 is connected to the control electrode (gate) of the high-side transistor QH2 and the control electrode (gate) of the low-side transistor QL2 of the second arm A2, which is adjacent to the downstream side of the first arm A1. The connection point of the high-side transistor QH3 and the low-side transistor QL3 of the third arm A3, which is located at the furthest downstream, is connected to the data output terminal Out.

[0056] The back gate (substrate electrode) of the high-side transistor QH1 is connected to the first switch SW1 via the first bias wiring B1. The first switch SW1 is configured to switch between the second power supply voltage VccQ (e.g., 1.2V) and the adjustment voltage Vreg (e.g., in the range of 1.2 to 2.5V) and connect to the first bias wiring B1.

[0057] The adjustment voltage Vreg may be set to a variable value in the range of 1.2 to 2.5V, for example, or it may be a fixed value in the range of 1.2 to 2.5V that is greater than the second power supply voltage VccQ. The adjustment voltage Vreg may be, for example, the power supply voltage used in parts of the chip other than the input / output circuit 22 on which the non-volatile memory 2 is formed, or it may be the power supply voltage supplied to the input / output circuit 22. The adjustment voltage Vreg may also be a voltage adjusted from the first power supply voltage Vcc. Alternatively, the adjustment voltage Vreg may be supplied with a dedicated power supply voltage from outside the chip on which the non-volatile memory 2 is formed. The first switch SW1 may be configured to switch between multiple adjustment voltages Vreg and connect to the first bias wiring B1. This makes the value of the first substrate bias voltage Vbp supplied to the back gate (substrate electrode) of the high-side transistor QH1 variable.

[0058] The back gate (substrate electrode) of the low-side transistor QL1 is connected to the second switch SW2 via the second bias wiring B2. The second switch SW2 is configured to switch between a ground voltage Vss (e.g., 0V) and a negative power supply voltage Vne (e.g., in the range of -1.0 to 0V) and connect to the second bias wiring B2.

[0059] The negative power supply voltage Vne may be the same or adjusted negative power supply voltage used in parts of the chip other than the input / output circuit 22 on which the non-volatile memory 2 is formed, or a dedicated power supply voltage may be supplied from outside the chip on which the non-volatile memory 2 is formed. The second switch SW2 may be configured to switch between multiple negative power supply voltages Vne and connect to the second bias wiring B2. This makes the value of the second substrate bias voltage Vbn supplied to the back gate (substrate electrode) of the low-side transistor QL1 variable.

[0060] The first bias wiring B1, the first switch SW1, the second bias wiring B2, and the second switch SW2 constitute the board bias voltage supply circuit 40. Multiple data transmission paths SL1 are provided inside the input / output circuit 22. The board bias voltage supply circuit 40 is configured to share one circuit with multiple data transmission paths SL1 provided inside the input / output circuit 22. Alternatively, the multiple data transmission paths SL1 may be classified into multiple data transmission path groups, and one circuit bias voltage supply circuit 40 may be shared with each data transmission path group.

[0061] During the first operation, which is normal operation that does not require power consumption reduction, the second power supply voltage VccQ is supplied as the first substrate bias voltage Vbp, and the ground voltage Vss is supplied as the second substrate bias voltage Vbn. During the first operation, the operating thresholds of the control electrodes of the high-side transistor QH1 and the low-side transistor QL1 are set to target values, so that the data transmission path SL1 and the non-volatile memory 2 can be operated at a relatively high speed (e.g., 4.8 Gbps applications).

[0062] In contrast, during the second operation, which requires reduced power consumption, an adjustment voltage Vreg is supplied as the first substrate bias voltage Vbp, and a negative power supply voltage Vne is supplied as the second substrate bias voltage Vbn. During the second operation, the operating thresholds of the control electrodes of the high-side transistor QH1 and the low-side transistor QL1 are set to a value higher than the target value due to the substrate bias effect, thereby reducing current consumption. As a result, in the second operation, the data transmission path SL1 and the non-volatile memory 2 are operated at a relatively lower speed (e.g., 1.4 Gbps applications), but power consumption can be reduced compared to the first operation. Users can switch between the first and second operations depending on the application.

[0063] According to the inventors' research, circuit simulations confirmed the following: For example, by switching the first substrate bias voltage Vbp of the high-side transistor QH1, which is composed of a P-channel MOSFET, from 1.2V (first operation) to 1.65V (second operation), the operating threshold of the control electrode could be shifted to a 53mV higher potential. This is expected to reduce the current consumption of one high-side transistor QH1 by about 16mA. When considering the input / output circuit 22 as a whole, this means that a considerable amount of power consumption can be suppressed.

[0064] By further improving the isolation of the high-side transistor QH1 to the first substrate bias voltage Vbp, and enabling the application of a larger first substrate bias voltage Vbp, power consumption can be further reduced.

[0065] If the data bus YIO is driven by the second power supply voltage VccQ, the data transmission path SL1 and the board bias voltage supply circuit 40 can also be applied to the data bus YIO portion. This allows for even greater power consumption reduction when considering the input / output circuit 22 as a whole. Furthermore, although the data transmission path SL1 was described as an example above, it goes without saying that the operating threshold of transistors in other circuits included in the input / output circuit 22 can also be adjusted using the board bias voltage supply circuit 40.

[0066] Thus, according to the first embodiment, it is possible to provide a semiconductor memory device that can suppress power consumption.

[0067] Next, Figure 7 will be used to explain the first operation, which is the normal operation. When the non-volatile memory 2 is powered on by instruction from the host or memory controller 1, the first power supply voltage Vcc turns on, followed by the second power supply voltage VccQ. Then, the second power supply voltage VccQ is applied as the first substrate bias voltage Vbp, and the ground voltage Vss is applied as the second substrate bias voltage Vbn.

[0068] Next, in response to a Power-On-Read (POR) startup command from the host by the user, the non-volatile memory 2 reads and sets operating parameters from the memory controller 1, and after the non-volatile memory 2 enters the startup state, it enters a standby state. Subsequently, in response to a user command from the host, the non-volatile memory 2 can repeatedly write and read data at high speed (e.g., for 4.8 Gbps applications) and enter the standby state.

[0069] Next, using Figure 8, we will explain the second operation that requires power consumption reduction. When the non-volatile memory 2 is powered on by instruction from the host or memory controller 1, the first power supply voltage Vcc turns on, followed by the second power supply voltage VccQ. Then, the second power supply voltage VccQ is applied as the first substrate bias voltage Vbp, and the ground voltage Vss is applied as the second substrate bias voltage Vbn.

[0070] Next, in response to a Power-On-Read (POR) startup command from the host issued by the user, non-volatile memory 2 reads and sets operating parameters from memory controller 1, and non-volatile memory 2 enters the powered-up state. Then, in response to a Set Feature command from the host issued by the user, the first switch SW1 and the second switch SW2 are switched, the adjustment voltage Vreg is applied as the first board bias voltage Vbp, and the negative power supply voltage Vne is applied as the second board bias voltage Vbn. At this time, it is possible to configure the system to switch both the first switch SW1 and the second switch SW2, or to switch either the first switch SW1 or the second switch SW2.

[0071] Next, non-volatile memory 2 enters a standby state. Then, in response to instructions from the host by the user, non-volatile memory 2 can repeatedly write and read data and enter a standby state at a low speed (e.g., for 1.4 Gbps applications) and with low power consumption.

[0072] (Second Embodiment) Figure 9 will be used to illustrate the data transmission path SL2 and the substrate bias voltage supply circuit 41 according to the second embodiment. The second embodiment differs from the first embodiment in the following respects. In the first arm A1 of the data transmission path SL2, the back gate (substrate electrode) of the high-side transistor QH1 is connected to the first switch SW1 via the first bias wiring B1. The first switch SW1 is configured to switch between a second power supply voltage VccQ (e.g., 1.2V), a fourth power supply voltage VDD (e.g., 1.5V), and a fifth power supply voltage VDDA (e.g., 2.2V) and connect to the first bias wiring B1. In the second embodiment, the first bias wiring B1 and the first switch SW1 constitute the substrate bias voltage supply circuit 41. The number of power supply voltages that the first switch SW1 can switch is not limited to 3, and it can be configured to switch between any number of power supply voltages.

[0073] Here, the fourth power supply voltage VDD and the fifth power supply voltage VDDA are power supply voltages supplied to a part of the chip on which the non-volatile memory 2 is formed that is different from the input / output circuit 22. As a result, the value of the first substrate bias voltage Vbp supplied to the back gate (substrate electrode) of the high-side transistor QH1 is configured to be variable with respect to the values ​​of the multiple power supply voltages supplied to the non-volatile memory 2.

[0074] Furthermore, the back gate (substrate electrode) of the low-side transistor QL1 is connected to the ground voltage Vss. The second arm A2 and the third arm A3 are configured in the same way as the first arm A1, so their description is omitted. The other configurations of the second embodiment are the same as those of the first embodiment, so their description is omitted.

[0075] In the second embodiment, the first substrate bias voltage Vbp of the high-side transistor QH1, which is composed of a P-channel MOSFET requiring a positive substrate bias voltage, is made variable, while the second substrate bias voltage Vbn is fixed. The second substrate bias voltage Vbn of the low-side transistor QL1, which is composed of an N-channel MOSFET requiring a negative substrate bias voltage, is fixed to the ground voltage Vss. Furthermore, the value of the first substrate bias voltage Vbp is made variable by the values ​​of multiple power supply voltages supplied to the non-volatile memory 2 from an external source. Therefore, the second embodiment allows for a simpler circuit configuration compared to the first embodiment.

[0076] In the second embodiment, as in the first embodiment, a semiconductor memory device capable of suppressing power consumption can be provided.

[0077] Next, Figure 10 will be used to explain the first operation, which is the normal operation. When the non-volatile memory 2 is powered on by instruction from the host or memory controller 1, the first power supply voltage Vcc turns on, and then the second power supply voltage VccQ turns on. Then, the second power supply voltage VccQ is applied as the first substrate bias voltage Vbp.

[0078] Next, in response to a Power-On-Read (POR) startup command from the host by the user, the non-volatile memory 2 reads and sets operating parameters from the memory controller 1, and after the non-volatile memory 2 enters the startup state, it enters a standby state. Subsequently, in response to a user command from the host, the non-volatile memory 2 can repeatedly write and read data at high speed (e.g., for 4.8 Gbps applications) and enter the standby state.

[0079] Next, using Figure 11, we will explain the second operation that requires power consumption reduction. When the non-volatile memory 2 is powered on by instruction from the host or memory controller 1, the first power supply voltage Vcc turns on, followed by the second power supply voltage VccQ. Then, the second power supply voltage VccQ is applied as the first substrate bias voltage Vbp.

[0080] Next, in response to a Power-On-Read (POR) startup command from the host issued by the user, the non-volatile memory 2 reads and sets its operating parameters from the memory controller 1, and the non-volatile memory 2 enters the power-on state. Then, in response to a "Set Feature" command from the host issued by the user, the first switch SW1 is switched, and the fourth power supply voltage VDD or the fifth power supply voltage VDDA is applied as the first board bias voltage Vbp, as selected by the user. Next, the non-volatile memory 2 enters a standby state. Then, in response to a user instruction from the host, the non-volatile memory 2 can repeatedly write and read data and enter the standby state at low speed (e.g., for 1.4 Gbps applications) and low power consumption.

[0081] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be carried out in various other forms, and various omissions, rewrites, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0082] 1…Memory controller 2…Non-volatile memory (semiconductor memory device) 3…Memory System 21…Memory cell array 22…Input / Output Circuits 32… Input / Output Pads 40, 41… PCB bias voltage supply circuit A1, A2, A3... Arm B1...First bias wiring B2...Second bias wiring QH1, QH2, QH3... High-side transistors (P-channel MOSFETs) QL1, QL2, QL3... Low-side transistors (N-channel MOSFETs) SL1, SL2…Data transmission paths SW1...First switch SW2...Second Switch Vcc…First power supply voltage VccQ…Second power supply voltage VDD…Fourth power supply voltage VDDA…5th power supply voltage Vne…Negative power supply voltage Vreg... Adjustable voltage Vss...Ground voltage (third power supply voltage) YIO...Databus

Claims

1. Input / output pads, A memory cell array containing multiple memory cells, An input / output circuit is provided between the input / output pad and the memory cell array, Equipped with, The aforementioned input / output circuit is Multiple transistors, A substrate bias voltage supply circuit capable of switching between supplying a first voltage with the same value as the power supply voltage of the input / output circuit and a second voltage with a different value from the first voltage as the substrate bias voltage of the plurality of transistors, Equipped with, Semiconductor memory device.

2. The plurality of transistors include P-channel type MOSFETs, The first voltage supplied as the substrate bias voltage for the P-channel type MOSFET is a positive voltage. The second voltage supplied as the substrate bias voltage of the P-channel type MOSFET is a positive voltage that is greater than the first voltage. The semiconductor memory device according to claim 1.

3. The semiconductor memory device according to claim 2, wherein the second voltage is the same value as the power supply voltage of a portion of the semiconductor memory device that is different from the input / output circuit.

4. The plurality of transistors include N-channel type MOSFETs, The first voltage supplied as the substrate bias voltage of the N-channel MOSFET is the ground voltage. The second voltage supplied as the substrate bias voltage for the N-channel MOSFET is a negative voltage. A semiconductor memory device according to any one of claims 1 to 3.

5. The plurality of transistors include P-channel MOSFETs and N-channel MOSFETs. The first voltage supplied as the substrate bias voltage for the P-channel type MOSFET is a positive voltage. The second voltage supplied as the substrate bias voltage of the P-channel type MOSFET is a positive voltage that is greater than the first voltage. The semiconductor memory device according to claim 1.

6. The semiconductor memory device according to claim 5, wherein the P-channel MOSFET and the N-channel MOSFET constitute a CMOS circuit in which the source of the P-channel MOSFET is connected to the drain of the N-channel MOSFET.

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