Chip stacking device and method for manufacturing a chip stacking device

Abstract

To provide a chip stacked device with an appropriate structure according to the function of the joint, and a method for manufacturing a chip stacked device. [Solution] The chip stacking device comprises a first junction electrically connected to a signal line, a second junction electrically connected to a ground line, and a first chip and a second chip joined to each other via the first and second junctions. The first chip has a first substrate having a first surface, a first conductive film provided in an island shape on the first surface and electrically connected to a signal line, and a second conductive film provided on the first surface, away from the first conductive film and connected to a ground line. The first junction covers the first conductive film, and the second junction is located on the second conductive film, away from the first conductive film and the first junction.

Description

Technical Field

[0004] ,

[0001] Embodiments of the present invention relate to a chip stacked device and a method for manufacturing a chip stacked device.

Background Art

[0002] Devices in which two chips are stacked by bonding metals are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention aim to provide a chip stacked device having an appropriate structure according to the function of a joint and a method for manufacturing a chip stacked device.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a chip stacked device includes a first joint electrically connected to a signal line, a second joint electrically connected to a ground line, and a first chip and a second chip joined to each other via the first joint and the second joint. The first chip has a first substrate having a first surface, a first conductive film provided in an island shape on the first surface and electrically connected to the signal line, and a second conductive film provided on the first surface apart from the first conductive film and connected to the ground line. The first joint covers the first conductive film, and the second joint is located on the second conductive film apart from the first conductive film and the first joint.

[0006] According to an embodiment of the present invention, a chip stacked device comprises a first junction electrically connected to a signal line, a second junction electrically connected to a ground line, and a first chip and a second chip joined to each other via the first and second junctions. The second chip includes a second substrate having a second surface, a third conductive film provided in an island-like manner on the second surface and electrically connected to the signal line, and a fourth conductive film provided on the second surface, separated from the third conductive film and connected to the ground line. The first junction covers the third conductive film, and the second junction is located on the fourth conductive film, separated from the third conductive film and the first junction.

[0007] According to an embodiment of the present invention, a method for manufacturing a chip stacked device comprises the steps of: preparing a first structure on a first surface of a first substrate, wherein a plurality of first metal parts electrically connected to signal lines and a plurality of third metal parts electrically connected to a ground line are provided on the first surface of a first substrate; preparing a second structure on a second surface of a second substrate, wherein a plurality of second metal parts and a plurality of fourth metal parts are provided on the second surface of a second substrate; and placing the first surface and the second surface opposite each other in a first direction, applying a load in the first direction to the first structure and the second structure to join the first metal parts and the third metal parts and the fourth metal parts, wherein a convex portion is provided on the first joining surface to which at least one of the first metal parts and the second metal parts is joined to the other metal part, and the step difference on the second joining surface to which at least one of the third metal parts and the fourth metal part is joined to the other metal part is smaller than the step difference on the first joining surface. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view of a chip stacking device according to the first embodiment. [Figure 2] This is a schematic plan view of the first surface side of the first substrate in a chip stacking device according to the first embodiment. [Figure 3] This is a schematic plan view of the first surface side of the first substrate in a chip stacking device according to the first embodiment. [Figure 4] This is a schematic cross-sectional view showing a method for manufacturing a chip stacked device according to the first embodiment. [Figure 5] This is a schematic cross-sectional view of a chip stacking device according to the second embodiment. [Figure 6] This is a schematic cross-sectional view of a chip stacking device according to the third embodiment. [Figure 7] This is a schematic cross-sectional view of a chip stacking device according to the fourth embodiment. [Modes for carrying out the invention]

[0009] Each embodiment will be described below with reference to the drawings. Drawings are schematic or conceptual, and the relationships between the thickness and width of each part, as well as the ratios of the sizes of different parts, are not necessarily identical to those of reality. Even when representing the same part, the dimensions and ratios may be depicted differently in different drawings. Furthermore, identical or similar elements are assigned the same symbol.

[0010] [First Embodiment] As shown in Figure 1, the chip stacking device 1 according to the first embodiment comprises a first chip 101 and a second chip 102. The first chip 101 and the second chip 102 are stacked in the first direction Z. Two mutually orthogonal directions in a plane perpendicular to the first direction Z are denoted as the second direction X and the third direction Y.

[0011] The first chip 101 includes a first substrate 10 having a first surface 10A, a first conductive film 11 provided on the first surface 10A, and a second conductive film 12 provided on the first surface 10A. The first substrate 10 is, for example, a silicon substrate. The first chip 101 also includes a first insulating film 31 provided on the first surface 10A. The first insulating film 31 is, for example, a silicon oxide film. The first conductive film 11 and the second conductive film 12 are provided on the first insulating film 31. If the first substrate 10 is insulating, the first insulating film 31 may be omitted, and the first conductive film 11 and the second conductive film 12 may be provided directly on the first surface 10A. The first conductive film 11 and the second conductive film 12 are, for example, titanium nitride films.

[0012] Figure 2 is a schematic plan view of the first substrate 10, looking at the first surface 10A side. Figure 2 shows an example of the arrangement of the first conductive film 11, the second conductive film 12, the first metal part 41 of the first joint 40 (described later), and the third metal part 51 of the second joint 50 (described later).

[0013] Multiple first conductive films 11 are arranged apart from each other in the second direction X and the third direction Y. For example, the second conductive film 12 extends over a larger area on the first surface 10A than the combined area of ​​the multiple first conductive films 11. The first conductive films 11 are provided in an island-like manner within the first openings 12A formed in the second conductive film 12, and are separated from the second conductive film 12.

[0014] The second chip 102 includes a second substrate 20 having a second surface 20A, a third conductive film 21 provided on the second surface 20A, and a fourth conductive film 22 provided on the second surface 20A. The second surface 20A of the second substrate 20 faces the first surface 10A of the first substrate 10 in the first direction Z. The second substrate 20 is, for example, a silicon substrate. The second chip 102 also includes a second insulating film 32 provided on the second surface 20A. The second insulating film 32 is, for example, a silicon oxide film. The third conductive film 21 and the fourth conductive film 22 are provided on the second insulating film 32 and are separated from each other. If the second substrate 20 is insulating, the second insulating film 32 may be omitted, and the third conductive film 21 and the fourth conductive film 22 may be provided directly on the second surface 20A. The third conductive film 21 and the fourth conductive film 22 are, for example, titanium nitride films.

[0015] As shown in Figure 1, the chip stacking device 1 further comprises a plurality of first bonding portions 40 and a plurality of second bonding portions 50 provided between the first chip 101 and the second chip 102 in the first direction Z. The first chip 101 and the second chip 102 are bonded to each other via the plurality of first bonding portions 40 and the plurality of second bonding portions 50.

[0016] The first joint 40 has a first metal part 41 provided on the first tip 101 side and a second metal part 42 located between the first metal part 41 and the second tip 102 in the first direction Z and joined to the first metal part 41. The second joint 50 has a third metal part 51 provided on the first tip 101 side and a fourth metal part 52 located between the third metal part 51 and the second tip 102 in the first direction Z and joined to the third metal part 51. The first metal part 41 and the second metal part 42 include, for example, gold, and the first joint 40 is a joint of gold. The third metal part 51 and the fourth metal part 52 include, for example, gold, and the second joint 50 is a joint of gold.

[0017] The plurality of fourth metal portions 52 on the side of the second chip 102 are connected to a common fourth conductive film 22 provided on the second surface 20A of the second substrate 20. Corresponding to the number of the plurality of first joining portions 40, the plurality of third conductive films 21 are provided apart from each other on the second surface 20A.

[0018] The second conductive film 12 of the first chip 101 is provided on the entire surface of the surface of the second joining portion 50 that faces the first surface 10A of the first substrate 10 (the lower surface of the third metal portion 51 in FIG. 1), and is electrically connected to the second joining portion 50. As shown in FIG. 2, a plurality of third metal portions 51 are connected to the common second conductive film 12 that spreads on the first surface 10A. The second joining portion 50 is located on the second conductive film 12, apart from the first conductive film 11 and the first joining portion 40.

[0019] The first conductive film 11 is provided on a part of the surface of the first joining portion 40 that faces the first surface 10A of the first substrate 10 (the lower surface of the first metal portion 41 in FIG. 1), and is electrically connected to the first joining portion 40. As shown in FIG. 2, in a plan view, the first metal portion 41 is located on the first conductive film 11 within the first opening 12A formed in the second conductive film 12. In a plan view, the outer edge (indicated by a broken line) of the first conductive film 11 is located inside the outer edge (indicated by a solid line) of the first metal portion 41 of the first joining portion 40. The first joining portion 40 covers the surface 11A (the upper surface in FIG. 1) of the first conductive film 11 that faces the second chip 102 and the side surface 11B of the first conductive film 11 within the first opening 12A.

[0020] As shown in FIG. 1, the first conductive film 11 is not provided on other portions of the surface of the first joint portion 40 that faces the first surface 10A except for the above-mentioned part. A part of the first joint portion 40 is in contact with the first insulating film 31. The first joint portion 40 covers a step portion between the surface 31A of the first insulating film 31 (the surface facing the second chip 102) and the surface 11A of the first conductive film 11. The first metal portion 41 of the first joint portion 40 covers the first conductive film 11 so as to cover a step portion between the surface 11A of the first conductive film 11 provided between the first joint portion 40 and the first surface 10A and the surface 31A of the first insulating film 31. Due to the presence of the above-mentioned step portion, a step portion is also formed on the joint surface of the first metal portion 41 that is joined to the second metal portion 42, and a first convex portion 41A is formed on the joint surface of the first metal portion 41 that is joined to the second metal portion 42. The width of the first convex portion 41A in the second direction X is larger than the width of the first conductive film 11 in the second direction X.

[0021] The first metal portion 41 is joined to the second metal portion 42 at least at the first convex portion 41A. The joint surface of the third metal portion 51 of the second joint portion 50 that is joined to the fourth metal portion 52 has higher flatness (fewer steps) than the joint surface of the first metal portion 41 where the first convex portion 41A is formed. The joining of the first metal portion 41 and the second metal portion 42 is a joining via the first convex portion 41A, and the joining of the third metal portion 51 and the fourth metal portion 52 is a joining between surfaces with higher flatness than the first joint portion 40. For example, the joint area between the first metal portion 41 and the second metal portion 42 is smaller than the joint area between the third metal portion 51 and the fourth metal portion 52.

[0022] Each of the plurality of first conductive films 11 is electrically connected to the signal line SL, and each of the plurality of first joint portions is electrically connected to the signal line SL via the first conductive film 11. The third conductive film 21 of the second chip 102 is electrically connected to the signal line SL via the first joint portion 40 and the first conductive film 11. The signal line SL, the first conductive film 11, the first joint portion 40, and the third conductive film 21 are electrically connected to form a signal system. For example, the plurality of first joint portions are connected to different signal lines SL, and the potentials of the plurality of signal systems can be controlled independently of each other.

[0023] The second conductive film 12 is electrically connected to the ground line GL. Multiple second junctions 50 are electrically connected to the ground line GL via a common second conductive film 12. The fourth conductive film 22 of the second chip 102 is electrically connected to the ground line GL via the second junctions 50 and the second conductive film 12. A ground potential can be applied to the fourth conductive film 22 via the ground line GL, the second conductive film 12, and the second junctions 50.

[0024] Next, with reference to Figure 4, a method for manufacturing the chip stacked device 1 according to the first embodiment will be described.

[0025] A method for manufacturing a chip stacked device 1 according to the first embodiment comprises the steps of preparing a first structure 110 and preparing a second structure 120.

[0026] The first structure 110 has a configuration in which the first metal part 41 is connected to the first conductive film 11 in the first chip 101 described above, and the third metal part 51 is connected to the second conductive film 12. The second structure 120 has a configuration in which the second metal part 42 is connected to the third conductive film 21 in the second chip 102 described above, and the fourth metal part 52 is connected to the fourth conductive film 22.

[0027] The manufacturing method of the chip stacked device 1 according to the first embodiment includes the steps of: facing the first surface 10A of the first substrate 10 and the second surface 20A of the second substrate 20 in the first direction Z, applying a load in the first direction Z to the first structure 110 and the second structure 120 to join the first metal part 41 and the second metal part 42, and joining the third metal part 51 and the fourth metal part 52.

[0028] By bringing the first metal part 41 and the second metal part 42 into contact, applying a load in the first direction Z to the first metal part 41 and the second metal part 42, and heating them, the first metal part 41 and the second metal part 42 are directly joined, forming the first joint 40 shown in Figure 1. By bringing the third metal part 51 and the fourth metal part 52 into contact, applying a load in the first direction Z to the third metal part 51 and the fourth metal part 52, and heating them, the third metal part 51 and the fourth metal part 52 are directly joined, forming the second joint 50 shown in Figure 1.

[0029] A protrusion is provided on the first joining surface of at least one of the first metal part 41 and the second metal part 42, which is joined to the other metal part. Furthermore, the step difference on the second joining surface of at least one of the third metal part 51 and the fourth metal part 52, which is joined to the other metal part, is smaller than the step difference on the first joining surface where the protrusion is provided.

[0030] According to this embodiment, a first protrusion 41A is provided on the first joining surface 41B of the first metal part 41 that is joined to the second metal part 42. By providing the first protrusion 41A, the contact area between the first metal part 41 and the second metal part 42 during joining when a load is applied in the first direction Z can be reduced compared to when the first protrusion 41A is not provided on the first joining surface 41B of the first metal part 41, and the pressure applied to the joining surface between the first metal part 41 and the second metal part 42 can be increased. As a result, the first metal part 41 and the second metal part 42 can be reliably joined, and the signal of the signal line SL can be reliably supplied from the first chip 101 side to the second chip 102 side.

[0031] Furthermore, the step at the second joining surface 51B of the third metal part 51, which is joined to the fourth metal part 52, is smaller than the step at the first joining surface 41B of the first metal part 41. As a result, the joining area between the third metal part 51 and the fourth metal part 52 per second joining part 50 can be made larger than the joining area between the first metal part 41 and the second metal part 42 per first joining part 40, thereby increasing the joining strength between the first tip 101 and the second tip 102.

[0032] The pressure applied to the joint surface between the third metal part 51, which has no protrusions, and the fourth metal part 52 is lower than the pressure applied to the joint surface between the first metal part 41 and the second metal part 42, and the bonding performance at the second joint 50 tends to be lower than that at the first joint 40. However, since the multiple second joints 50 are commonly connected to the second conductive film 12 of the first chip 101 and also commonly connected to the fourth conductive film 22 of the second chip 102, if any of the multiple second joints 50 are reliably bonded, a ground potential can be applied from the first chip 101 to the fourth conductive film 22 of the second chip 102.

[0033] According to this embodiment, it is possible to achieve both good bonding between the first metal part 41 and the second metal part 42 used in the signal system, and increased bonding strength due to an increased bonding area between the first chip 101 and the second chip 102.

[0034] As shown in Figure 2, in a plan view, the number of third metal parts 51 of a second joint 50 arranged around a first metal part 41 of a first joint 40 is the same as the number of first metal parts 41 of a first joint 40 arranged around a third metal part 51 of a second joint 50. For example, four third metal parts 51 are arranged around one first metal part 41, and four first metal parts 41 are arranged around one third metal part 51. This ensures that the bonding area between the first tip 101 and the second tip 102 is not uneven, and that the first tip 101 and the second tip 102 maintain uniform bonding strength in a plane parallel to the XY plane.

[0035] Furthermore, as shown in Figure 3, the number of third metal parts 51 in the ground system can be reduced. This allows the overall bonding area between the first tip 101 and the second tip 102 to be adjusted, and the bonding pressure to be adjusted.

[0036] [Second Embodiment] Figure 5 is a schematic cross-sectional view of the chip stacked device 2 according to the second embodiment.

[0037] The third conductive film 21 of the second chip 102 of the chip stacked device 2 is provided on a portion of the surface of the first junction 40 that faces the second surface 20A of the second substrate 20, and is electrically connected to the first junction 40. The third conductive film 21 is not provided on any other portion of the surface of the first junction 40 that faces the second surface 20A. The first junction 40 covers the surface 21A (bottom surface in Figure 5) of the third conductive film 21 that faces the first chip 101, and the side surface 21B of the third conductive film 21. A portion of the first junction 40 is in contact with the second insulating film 32. The first junction 40 covers the step between the surface 32A (the surface facing the first chip 101) of the second insulating film 32 and the surface 21A of the third conductive film 21. The second metal portion 42 of the first joint portion 40 covers the third conductive film 21 so as to cover the step between the surface 21A of the third conductive film 21, which is provided between the first joint portion 40 and the second surface 20A, and the surface 32A of the second insulating film 32. Due to the presence of the step, a step is also formed on the joint surface of the second metal portion 42 that is joined to the first metal portion 41, and a second protrusion 42A is formed on the joint surface of the second metal portion 42 that is joined to the first metal portion 41. The width of the second protrusion 42A in the second direction X is greater than the width of the third conductive film 21 in the second direction X.

[0038] The second metal part 42 is joined to the first metal part 41 at least at the second protrusion 42A. The first metal part 41 and the second metal part 42 are joined via the second protrusion 42A. By providing the second protrusion 42A on the second metal part 42, the pressure applied to the joint surface between the first metal part 41 and the second metal part 42 when a load is applied in the first direction Z can be increased compared to when the second protrusion 42A is not provided. As a result, the first metal part 41 and the second metal part 42 can be reliably joined, and the signal of the signal line SL can be reliably supplied from the first chip 101 side to the second chip 102 side.

[0039] The joining surface of the fourth metal part 52 of the second joint 50, which is electrically connected to the ground line GL, that joins with the third metal part 51, is flatter (has less of a step) than the joining surface of the second metal part 42 on which the second protrusion 42A is formed. The third metal part 51 and the fourth metal part 52 are joined by surfaces that are flatter than the first joint 40. As a result, the joining area between the third metal part 51 and the fourth metal part 52 per second joint 50 can be made larger than the joining area between the first metal part 41 and the second metal part 42 per first joint 40, and the joining strength between the first tip 101 and the second tip 102 can be increased.

[0040] [Third Embodiment] Figure 6 is a schematic cross-sectional view of the chip stacked device 3 according to the third embodiment.

[0041] The chip stacking device 3 according to the third embodiment has a configuration that combines the chip stacking device 1 according to the first embodiment and the chip stacking device 2 according to the second embodiment.

[0042] In other words, the first metal part 41 and the second metal part 42 are joined via the first protrusion 41A and the second protrusion 42A. At least the first protrusion 41A and the second protrusion 42A are joined to each other. This makes it possible to increase the pressure applied to the joint surface between the first metal part 41 and the second metal part 42 when a load is applied in the first direction Z, and ensures that the first metal part 41 and the second metal part 42 are reliably joined.

[0043] Furthermore, the third metal part 51 and the fourth metal part 52 are joined by surfaces that are flatter than the first joint 40. This makes the joining area between the third metal part 51 and the fourth metal part 52 per second joint 50 larger than the joining area between the first metal part 41 and the second metal part 42 per first joint 40, thereby increasing the joining strength between the first tip 101 and the second tip 102.

[0044] [Fourth Embodiment] Figure 7 is a schematic cross-sectional view of the chip stacked device 4 according to the fourth embodiment.

[0045] The first chip 101 in the chip stacking device 4 includes a wiring section 60 provided on the first surface 10A of the first substrate 10. The wiring section 60 includes an insulating layer 65 provided on the first surface 10A of the first substrate 10, a first wiring layer 61 provided within the insulating layer 65, and a second wiring layer 62 provided within the insulating layer 65, separated from the first wiring layer 61.

[0046] The wiring section 60 is a multilayer wiring structure having at least two first wiring layers 61 and at least two second wiring layers 62. Different layers of the first wiring layers 61 are electrically connected to each other by first conductive vias 63. Different layers of the second wiring layers 62 are electrically connected to each other by second conductive vias 64.

[0047] The first conductive film 11 is provided on the surface of the insulating layer 65 and in the first connection hole 65A that extends from the surface of the insulating layer 65 to the first wiring layer 61, and is connected to the first wiring layer 61. The first wiring layer 61 is, for example, a signal line.

[0048] The first joint 40 is connected to the first conductive film 11 on the surface of the insulating layer 65 and also connected to the first conductive film 11 within the first connection hole 65A. The first joint 40 is electrically connected to the first wiring layer 61 via the first conductive film 11.

[0049] The second conductive film 12 is provided on the surface of the insulating layer 65 and in the second connection hole 65B that extends from the surface of the insulating layer 65 to the second wiring layer 62, and is connected to the second wiring layer 62. The second wiring layer 62 is, for example, a ground line.

[0050] The second joint 50 is connected to the second conductive film 12 on the surface of the insulating layer 65 and also connected to the second conductive film 12 within the second connection hole 65B. The second joint 50 is electrically connected to the second wiring layer 62 via the second conductive film 12.

[0051] The first conductive film 11 is provided on a portion of the surface of the first joint 40 that faces the first surface 10A. The first conductive film 11 is not provided on any other portion of the surface of the first joint 40 that faces the first surface 10A. The first metal portion 41 of the first joint 40 covers the first conductive film 11 so as to cover the step between the first conductive film 11 and the insulating layer 65. Due to the presence of this step, a step is also formed on the joint surface of the first metal portion 41 that is joined to the second metal portion 42, and a first protrusion 41A is formed on the joint surface of the first metal portion 41 that is joined to the second metal portion 42.

[0052] The first metal part 41 is joined to the second metal part 42 at least at the first protrusion 41A. This increases the pressure applied to the joint surface between the first metal part 41 and the second metal part 42 when a load is applied in the first direction Z, thereby ensuring a secure joint between the first metal part 41 and the second metal part 42.

[0053] The joining surface of the third metal part 51 of the second joint 50 that is joined to the fourth metal part 52 has higher flatness (less step) compared to the joining surface of the first metal part 41 on which the first protrusion 41A is formed. The third metal part 51 and the fourth metal part 52 are joined by surfaces that are flatter than the first joint 40. As a result, the joining area between the third metal part 51 and the fourth metal part 52 per second joint 50 can be made larger than the joining area between the first metal part 41 and the second metal part 42 per first joint 40, and the joining strength between the first tip 101 and the second tip 102 can be increased.

[0054] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0055] 1-4…Chip stacked device, 10…First substrate, 10A…First surface, 11…First conductive film, 12…Second conductive film, 12A…First opening, 20…Second substrate, 20A…Second surface, 21…Third conductive film, 22…Fourth conductive film, 31…First insulating film, 32…Second insulating film, 40…First junction, 41…First metal part, 41A…First protrusion, 41B…First junction surface, 42…Second metal part, 42A...Second protrusion, 50...Second joint, 51...Third metal part, 51B...Second joint surface, 52...Fourth metal part, 60...Wiring part, 61...First wiring layer, 62...Second wiring layer, 63...First conductive via, 64...Second conductive via, 65...Insulating layer, 65A...First connection hole, 65B...Second connection hole, 101...First tip, 102...Second tip, 110...First structure, 120...Second structure

Claims

1. A chip stacking device comprising: a first junction electrically connected to a signal line; a second junction electrically connected to a ground line; and a first chip and a second chip joined to each other via the first junction and the second junction, The first chip is A first substrate having a first surface, A first conductive film is provided in an island-like manner on the first surface and is electrically connected to the signal line, A second conductive film is provided on the first surface, separated from the first conductive film, and connected to the ground line, It has, The first joint covers the first conductive film, The chip stacked device is characterized in that the second junction is located on the second conductive film, separate from the first conductive film and the first junction.

2. The first chip further comprises a first insulating film provided on the first surface of the first substrate, The first conductive film and the second conductive film are provided on the first insulating film. A portion of the first joint is in contact with the first insulating film, The chip stacking device according to claim 1, wherein the first bonding portion covers the step between the surface of the first insulating film and the surface of the first conductive film.

3. The second chip is A second substrate having a second surface facing the first surface of the first substrate, A third conductive film is provided in an island-like manner on the second surface, A fourth conductive film provided on the second surface, separated from the third conductive film, It has, The first joint covers the third conductive film, The chip stacked device according to claim 1, wherein the second joint is located on the fourth conductive film, separate from the third conductive film and the first joint.

4. A chip stacking device comprising: a first junction electrically connected to a signal line; a second junction electrically connected to a ground line; and a first chip and a second chip joined to each other via the first junction and the second junction, The second chip is A second substrate having a second surface, A third conductive film is provided in an island-like manner on the second surface and is electrically connected to the signal line, A fourth conductive film is provided on the second surface, separated from the third conductive film, and connected to the ground line, It has, The first joint covers the third conductive film, A chip stacked device wherein the second junction is located on the fourth conductive film, separate from the third conductive film and the first junction.

5. The second chip further comprises a second insulating film provided on the second surface of the second substrate, The third conductive film and the fourth conductive film are provided on the second insulating film, A portion of the first joint is in contact with the second insulating film, The chip stacked device according to claim 4, wherein the first bonding portion covers the step between the surface of the second insulating film and the surface of the third conductive film.

6. The first joint portion comprises a first metal portion and a second metal portion located between the first metal portion and the second tip and joined to the first metal portion. The second joint portion has a third metal portion and a fourth metal portion located between the third metal portion and the second tip and joined to the third metal portion. The chip stacking device according to any one of claims 1 to 5, wherein the bonding area between the first metal part and the second metal part is smaller than the bonding area between the third metal part and the fourth metal part.

7. The first chip comprises an insulating layer provided on the first surface of the first substrate, a first wiring layer provided within the insulating layer, and a second wiring layer provided within the insulating layer. The first conductive film is provided on the surface of the insulating layer and in the first connection hole that extends from the surface of the insulating layer to the first wiring layer, and is connected to the first wiring layer. The first joint connects to the first conductive film on the surface of the insulating layer and also connects to the first conductive film within the first connection hole. The second conductive film is provided on the surface of the insulating layer and in the second connection hole that extends from the surface of the insulating layer to the second wiring layer, and is connected to the second wiring layer. The chip stacking device according to any one of claims 1 to 5, wherein the second joint is connected to the second conductive film on the surface of the insulating layer and is also connected to the second conductive film within the second connection hole.

8. A step of preparing a first structure on the first surface of a first substrate, wherein a plurality of first metal parts electrically connected to signal lines and a plurality of third metal parts electrically connected to a ground line are provided. A step of preparing a second structure having a plurality of second metal parts and a plurality of fourth metal parts provided on the second surface of a second substrate, A step of joining the first metal part and the second metal part, and joining the third metal part and the fourth metal part, by facing the first surface and the second surface in a first direction and applying a load in the first direction to the first structure and the second structure, Equipped with, A protrusion is provided on the first joining surface of at least one of the first metal part and the second metal part, which is joined to the other metal part. A method for manufacturing a chip stacked device, wherein the step difference at the second bonding surface, where at least one of the third metal part and the fourth metal part is joined to the other metal part, is smaller than the step difference at the first bonding surface.

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