Semiconductor circuits, memory devices, and memory systems

Abstract

To improve the characteristics of semiconductor circuits. [Solution] The semiconductor circuit of the embodiment includes a detection unit that detects a first signal waveform of a first input signal on a first communication path and a second signal waveform of a second input signal on a second communication path different from the first communication path; a signal generation unit that generates a control signal based on the detected first and second signal waveforms; and a first driver unit that outputs an output signal corresponding to the first input signal based on the driver strength based on the control signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor circuit, a memory device, and a memory system.

Background Art

[0002] An interface circuit for performing high-speed parallel communication is applied to an information processing system.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the characteristics of the semiconductor circuit.

Means for Solving the Problems

[0005] The semiconductor circuit of the embodiment includes a detection unit that detects a first signal waveform of a first input signal on a first communication path and a second signal waveform of a second input signal on a second communication path different from the first communication path, a signal generation unit that generates a control signal based on the detected first and second signal waveforms, and a first driver unit that outputs an output signal corresponding to the first input signal with a driver strength based on the control signal.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing a configuration example of an information communication system including the semiconductor circuit of the embodiment. [Figure 2] A block diagram illustrating the overview of the semiconductor circuit of the first embodiment. [Figure 3] A diagram illustrating the control of a semiconductor circuit in the first embodiment. [Figure 4] A circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the first embodiment. [Figure 5] A timing chart showing an example of the operation of a semiconductor circuit according to the first embodiment. [Figure 6] A schematic diagram illustrating the characteristics of the semiconductor circuit of the first embodiment. [Figure 7] A circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the second embodiment. [Figure 8] A block diagram illustrating the overview of the semiconductor circuit of the third embodiment. [Figure 9] A diagram illustrating the control of a semiconductor circuit in a third embodiment. [Figure 10] A circuit diagram showing an example of the circuit configuration of a semiconductor circuit according to the fourth embodiment. [Figure 11] A circuit diagram showing an example of the circuitry within the semiconductor circuit of the fourth embodiment. [Figure 12] A circuit diagram showing an example of the circuitry within the semiconductor circuit of the fourth embodiment. [Figure 13] A circuit diagram showing an example of the circuitry within the semiconductor circuit of the fourth embodiment. [Figure 14] A circuit diagram showing an example of the circuitry within the semiconductor circuit of the fourth embodiment. [Figure 15] A diagram illustrating the control of a semiconductor circuit in the fourth embodiment. [Figure 16] A schematic diagram illustrating the characteristics of the semiconductor circuit of the first embodiment. [Figure 17] A block diagram showing an example of the application of the semiconductor circuit of the embodiment. [Modes for carrying out the invention]

[0007] Referring to FIGS. 1 to 17, a semiconductor circuit, a memory device, and a memory system according to an embodiment will be described. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Further, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) with reference numerals accompanied by numbers / letters at the end for differentiation do not need to be distinguished from each other, descriptions (reference numerals) in which the numbers / letters at the end are omitted are used.

[0008] (Embodiment) (1) First Embodiment Referring to FIGS. 1 to 6, a semiconductor circuit according to the first embodiment will be described.

[0009] (a) Configuration Example (a-1) Overall Configuration FIG. 1 is a block diagram showing a configuration example of an information processing system including the semiconductor circuit of the present embodiment.

[0010] The information processing system 9 includes a first device 1 and a second device 2. The first device 1 is a device on the transmission side of information. The second device 2 is a device on the reception side of information.

[0011] The first device 1 communicates with the second device 2 via a plurality of communication paths TP (TPn-2, TPn-1, TPn, TPn-1, TPn-2) that form wireless or wired parallel communication.

[0012] The first device 1 includes a processing circuit 10 and the semiconductor circuit 11 of the present embodiment.

[0013] The processing circuit 10 executes various information processes. The processing circuit 10 includes a processor, a controller, and the like. The processing circuit 10 generates a plurality of signals (data) based on the result of the information process. The processing circuit 10 sends the generated signals to the semiconductor circuit 11.

[0014] In this embodiment, the semiconductor circuit 11 is a transmitting circuit 11 within the interface circuit of the device 1. The transmitting circuit 11 receives a signal from the processing circuit 10. The transmitting circuit 11 performs various processes on the signal from the processing circuit 10 for the purpose of transmitting the signal.

[0015] The transmission circuit 11 includes multiple transmitters TX (TXn-2, TXn-1, TXn, TXn-1, TXn-2). Each transmitter TX processes the signals IN (INn-2, INn-1, INn, INn-1, INn-2) from the processing circuit 10. The transmission circuit 11 sends the information, including the signals processed by each transmitter TX, to the second device 2 via the communication path TP.

[0016] The internal configuration of the transmitter TX will be described later.

[0017] The second device 2 receives information from the first device 1. The second device 2 includes a receiving circuit 20 and a processing circuit 21.

[0018] The receiving circuit 20 receives multiple signals from the transmitting circuit 11 of the first device 1 via the communication path TP. The receiving circuit 20 performs various processing on the signals from the transmitting circuit 11 for signal reception. The receiving circuit 20 includes multiple receivers RX (RXn-2, RXn-1, RXn, RXn-1, RXn-2). Each of the receivers RX processes the signal from the corresponding transmitter TX of the transmitting circuit 11. The receiving circuit 20 sends the multiple signals processed by each of the receivers RX to the processing circuit 21.

[0019] The processing circuit 21 performs various processes, such as calculating and storing information according to the signals, for multiple signals from the receiving circuit 20.

[0020] When transmitting information containing multiple signals, crosstalk (XTK) occurs between multiple communication channels (TP).

[0021] In this embodiment, the transmission circuit 11 reduces the jitter caused by crosstalk XTK between wiring during parallel communication using a Feed Forward Equalizer (FFE) circuit.

[0022] (a-2) Transmitter circuit Figure 2 is a block diagram showing an overview of the transmitting circuit 11 as a semiconductor circuit in this embodiment. In Figure 2, one transmitter TXn of the transmitting circuit 11 in this embodiment is shown.

[0023] The transmitter TXn in Figure 2 includes a driver consisting of FFEs at the transmitting end of the high-speed interface. As shown in Figure 2, the transmitter TXn includes two driver circuits 110, 120 and an adder (calculator) 150.

[0024] In this embodiment, the transmitter Txn obtains the output signal OUTn using the two-bit signals INn and INn-1 on the adjacent communication channel TP. The transmitter TXn receives the input signal INn of the data to be transmitted (to be processed) and the input signal INn-1 of the adjacent communication channel TP. The transmitter TXn sends the output signal OUTn, obtained by processing the two input signals INn and INn-1, to the receiving circuit 20 via the communication channel TP.

[0025] In the following, regarding the relationship between signals affected by crosstalk in the communication channel, signal INn is the victim's signal, and signal INn-1 is the aggressor's signal.

[0026] The driver circuit 110 includes two driver sections (also called buffers) 111a and 111b and a delay element (conversion filter) 119.

[0027] The input node of the driver unit 111a is connected to node ND1. The input node of the driver unit 111a receives the input signal INn from the preceding circuit (not shown). The output node of the driver unit 111a is connected to the adder 150. The driver unit 111a sends the input signal INn to the adder 150. The driver unit 111a performs various processes on the input signal INn, such as amplification, attenuation, or inversion.

[0028] The input node of the delay element 119 is connected to node ND1. The input node of the delay element 119 receives the input signal INn from the preceding circuit. The output node of the delay element 119 is connected to the input node of the driver unit 111b. The delay element 119 delays the input signal INn. The delay element 119 sends the delayed input signal zINn to the driver unit 111b. The delay element 119 forms an isolated path for the signal path of the input signal INn.

[0029] The driver unit 111b is located on the isolation path between the delay element 119 and the adder 150. The input node of the driver unit 111b is connected to the delay element 119. The input node of the driver unit 111b receives a delayed input signal (hereinafter also called the delayed signal) zINn from the delay element 119. The output node of the driver unit 111b is connected to the adder 150. The driver unit 111b sends the delayed input signal zINn to the adder 150. The driver unit 111b performs various processes on the input signal zINn, such as amplification, attenuation, or inversion.

[0030] The driver circuit 120 includes two driver units 121a and 121b and a delay element (conversion filter) 129.

[0031] The input node of the driver unit 121a is connected to node ND2. The input node of the driver unit 121a receives the input signal INn-1 from the preceding circuit. The output node of the driver unit 121a is connected to the adder 150. The driver unit 121a sends the input signal INn-1 to the adder 150. The driver unit 121a performs various processes on the input signal INn-1, such as amplification, attenuation, or inversion.

[0032] The input node of the delay element 129 is connected to node ND2. The input node of the delay element 129 receives the input signal INn-1 from the preceding circuit. The output node of the delay element 119 is connected to the input node of the driver unit 121b. The delay element 129 delays the input signal INn-1. The delay element 129 sends the delayed input signal zINn-1 to the driver unit 121b. The delay element 129 forms an isolated path for the signal path of the input signal INn-1.

[0033] The driver unit 121b is located on the isolation path between the delay element 129 and the adder 150. The input node of the driver unit 121b is connected to the delay element 129. The input node of the driver unit 121b receives the delayed input signal zINn-1 from the delay element 129. The output node of the driver unit 121b is connected to the adder 150. The driver unit 121b sends the delayed input signal (delayed signal) zINn-1 to the adder 150. The driver unit 121b performs various processes on the input signal zINn-1, such as amplification, attenuation, or inversion.

[0034] The adder 150 receives the input signal INn from the driver unit 111a, the delayed input signal zINn from the driver unit 111b, the input signal INn-1 from the driver unit 121a, and the delayed input signal zINn-1 from the driver unit 121b. The adder 150 performs the addition of the four received signals INn, zINn, INn-1, and zINn-1. The adder 150 sends the result of the addition of the multiple signals INn, zINn, INn-1, and zINn-1 as the output signal OUTn corresponding to the input signal INn to the subsequent communication channel TP.

[0035] As a result, the FFE transmitter TXn outputs an output signal OUTn, which has an analog signal waveform, with respect to the input signal INn, depending on the signal state of another input signal INn-1.

[0036] The driver circuits 110 and 120 (driver sections 111a, 111b, 121a, and 121b) are controlled by the RISE / FALL control signal. The RISE / FALL control signal is a signal used to control the driver strength (also called drive capability or drive strength) of the driver circuits 110 and 120 (driver sections 111a, 111b, 121a, and 121b).

[0037] Driver strength is an indicator (degree) of the magnitude of the current that a driver circuit (driver section) can supply, or the ability of a driver circuit to supply current.

[0038] In this embodiment, the transmitter TXn controls the driver strength setting in response to changes in the signal states of the input 2-bit signals (for example, 2-bit signals with adjacent communication channels) INn and INn-1 (operations on the victim side and aggressor side).

[0039] Figure 3 shows an example of setting the driver strength of the transmitter (FFE driver) TX in the transmission circuit 11 of this embodiment.

[0040] Figure 3(a) shows an example of setting the pull-up driver strength for the transmitter TXn driver. Figure 3(b) shows an example of setting the pull-down driver strength for the transmitter TXn driver. In Figures 3(a) and (b), "R" indicates that the detected signal waveform is in a rising state (rising edge), and "F" indicates that the detected signal waveform is in a falling state (falling edge). Also, "-" indicates that the detected signal waveform is fixed at an "L" level or an "H" level (unchanged state).

[0041] Depending on the actions of the victim and the aggressor, the output signal of the transmitter TXn is affected by crosstalk XTK. In this embodiment, in order to suppress the effect of crosstalk XTK, the transmitter TXn controls the magnitude of the driver intensity.

[0042] As shown in Figures 3(a) and 3(b), depending on the operation of the victim and the operation of the aggressor, if both the signal waveform of the victim's input signal INn and the signal waveform of the aggressor's input signal INn-1 are in a rising (R) state or a falling (F) state, the transmitter TXn is set to a strong driver strength (e.g., strength of +1).

[0043] Depending on the operation of the victim and aggressor, if the signal waveform of the victim's input signal INn differs from the signal waveform of the aggressor's input signal INn-1, the transmitter TXn is set to a weaker driver strength (e.g., strength -1) compared to when the signal waveforms of the victim and aggressor are the same.

[0044] If there is no activity on the aggressor side and the signal waveform of the aggressor side signal INn-1 does not change (Case 3), the transmitter TXn assumes there is no crosstalk XTK effect and sets the driver strength to its initial value (e.g., strength 0) without changing the driver strength.

[0045] Thus, in the transmission circuit 11 of this embodiment, the transmitter TXn, which includes the FFE driver, controls the driver strength based on the changes in the signal waveforms of the input signals INn and INn-1 corresponding to the operation of the victim and the operation of the aggressor. As a result, the transmission circuit 11 of this embodiment can reduce the jitter caused by the mutual inductance between the communication channels TP in crosstalk XTK.

[0046] Figure 3 shows an example where the driver strength is increased or decreased depending on the operation of the victim and aggressor. However, depending on the circuit configuration or specifications, it may be difficult to decrease (or increase) the driver strength. In such cases, the operating characteristics of the transmitter TXn may be controlled solely by increasing the driver strength. Even in this case, the transmitter TXn can suppress the effects of crosstalk XTK.

[0047] As described above, the transmitting circuit 11 of this embodiment generates a single output signal OUTn using two potentially interfering signals INn and INn-1. This allows the transmitting circuit 11 of this embodiment to mitigate the adverse effects of crosstalk XTK, such as jitter.

[0048] (b) Example of operation An example of the operation of the transmission circuit 11 of this embodiment will be described with reference to Figure 4.

[0049] Figure 4 is a timing chart showing an example of the operation of the transmitter TXn in the transmission circuit 11 of this embodiment, to which two-bit input signals INn and INn-1 are supplied. In Figure 4, the signal levels of the two input signals INn and INn-1, and the signal levels of the control signals RISE+ and RISE- are shown. In Figure 4, the solid line shows the signal waveform of the input signal IN when there is no crosstalk effect, and the dashed line shows the signal waveform of the input signal IN when crosstalk effect occurs.

[0050] The control signals RISE+, RISE-, FALL+, and FALL- in Figure 4 are signals for controlling the driver strength of the transmitter TXn. The control signal RISE+ is a signal that increases the driver strength of the victim's driver circuit when the signal level of the victim's input signal INn rises from "L (low)" to "H (high)" and the signal level of the aggressor's input signal INn-1 rises from "L" to "H". The control signal RISE- is a signal that decreases the driver strength of the victim's driver circuit when the signal level of the victim's input signal INn rises from "L" to "H" and the aggressor's input signal INn-1 falls from "H" to "L". The FALL+ control signal is used to increase the driver strength of the victim's driver circuit when the signal level of the victim's input signal INn falls from a high level to a low level, and the input signal INn-1 on the aggressor side falls from a high level to a low level. The FALL- control signal is used to decrease the driver strength of the victim's driver circuit when the signal level of the victim's input signal INn falls from a high level to a low level, and the input signal INn-1 on the aggressor side rises from a low level to a high level.

[0051] Figure 4 shows the control of the driver strength of the driver in Figure 3.

[0052] As shown in Figure 4, input signals INn and INn-1 are supplied to the transmitter TXn in the transmission circuit 11 of this embodiment.

[0053] At time t10, the signal level of input signal INn rises from "L" level to "H" level. At time t11, the signal level of input signal INn falls from "H" level to "L" level.

[0054] During the period from time t10 to time t11, the signal level of input signal INn-1 remains unchanged and is maintained at the "L" level.

[0055] During the period from time t10 to time t11, there is no change in the aggressor's input signal INn-1, so no crosstalk effect occurs on the victim's input signal INn. Therefore, during the period from time t10 to time t11, control of the driver strength by the control signals RISE+ and RISE- is not performed. The signal levels of the control signals RISE+ and RISE- are maintained at the "L" level. As a result, the driver strength of the transmitter TXn is maintained at the initial state (0).

[0056] At time t20, the signal level of input signal INn rises from "L" to "H". Simultaneously at time t20, the signal level of input signal INn-1 rises from "L" to "H". When both input signals INn and INn-1 rise simultaneously, the waveform of input signal INn is distorted due to crosstalk between the two input signals INn and INn-1. To suppress the effects of crosstalk, at time t20, transmitter TXn changes the signal level of control signal RISE+ from "L" to "H" according to the detection results of the signal waveforms of input signals INn and INn-1. In accordance with the transition of the signal level of control signal RISE+, transmitter TXn controls the driver strength of driver circuits 110 and 120. As a result, the driver strengths of driver circuits 110 and 120 in transmitter TXn are added together.

[0057] For example, the operating speed of the signal level transition of the control signal RISE+ is less than half the response speed of the input signal INn.

[0058] Furthermore, both input signals INn and INn-1 have signal levels that rise from "L" level to "H" level. Therefore, at time t20, the signal levels of the control signals FALL+ and FALL- are maintained at "L" level.

[0059] As a result, at time t20, the crosstalk effect of the input signal INn (and input signal INn-1) is suppressed. Therefore, the phase delay of the output signal OUTn is reduced.

[0060] At time t21, the signal level of input signal INn falls from a high level to a low level. At this time, the signal level of input signal INn-1 is maintained at a high level. For example, the signal level of control signal RISE+ is maintained at a high level, and the signal level of control signal RISE- is maintained at a low level.

[0061] Furthermore, at time t21, the signal level of input signal INn changes from "H" level to "L" level, but the signal level of input signal INn-1 remains at "H" level, so the signal levels of control signals FALL+ and FALL- remain at "L" level.

[0062] At time t30, the signal level of input signal INn rises from "L" to "H". At time t30, the signal level of input signal INn-1 falls from "H" to "L".

[0063] At this time, since the signal level of the input signal INn changes from "L" level to "H" level, the signal levels of the control signals FALL+ and FALL- are maintained at "L" level.

[0064] If the direction of the signal level transition of input signal INn-1 is opposite to the direction of the signal level transition of input signal INn, the waveform of input signal INn will be distorted due to the crosstalk effect between the two input signals INn and INn-1. To suppress the effect of crosstalk, at time t30, transmitter TXn changes the signal level of the control signal RISE- from "L" level to "H" level in response to the rising edge of input signal INn (and the falling edge of input signal INn-1), according to the detection result of the signal waveforms of input signals INn and INn-1. At this time (time t30), transmitter TXn also changes the signal level of the control signal RISE+ from "H" level to "L" level. In accordance with the transition of the signal level of the control signal RISE-, transmitter TXn controls the driver strength of driver circuits 110 and 120. As a result, the driver strength of driver circuits 110 and 120 in transmitter TXn is reduced.

[0065] As a result, at time t30, the effect of crosstalk between the input signal INn (and input signal INn-1) is suppressed. Therefore, the phase lead of the output signal OUTn is reduced.

[0066] For example, the operating speed of the signal level transitions of the control signals RISE+ and RISE- is less than half the response speed of the input signal INn.

[0067] At time t31, the signal level of input signal INn falls from "H" level to "L" level. At time t31, the signal level of input signal INn-1 is maintained at "L" level. At this time, for example, the signal level of control signal RISE- is maintained at "H" level. The signal level of control signal RISE+ is maintained at "L" level.

[0068] At time t31, the signal level of input signal INn changes from "H" level to "L" level, but the signal level of input signal INn-1 remains at "L" level. Therefore, the signal levels of control signals FALL+ and FALL- remain at "L" level.

[0069] As described above, in this embodiment, the transmitter TXn of the transmission circuit 11 controls the signal levels of the control signals RISE+, RISE-, FALL+, FALL- for controlling the driver strength in accordance with the signal transitions of two adjacent input signals INn and INn-1.

[0070] In this embodiment, the transmitter TXn controls the driver intensity of the driver circuits 110 and 120.

[0071] As a result, in the transmission circuit 11 of this embodiment, the effect of crosstalk between transmitters TXn is suppressed.

[0072] Furthermore, in this embodiment, the control signals RISE+ and RISE- are activated when the signal level transition state (signal edge) of the victim's input signal INn is a rising edge, and the driver strength of the victim's transmitter TXn changes in accordance with the signal level transition of the aggressor's input signal INn-1. By activating the control signals RISE+ and RISE-, the signal levels of the control signals RISE+ and RISE- are controlled. The control signals FALL+ and FALL- are activated when the signal level transition state of the victim's input signal INn is a falling edge, and the driver strength of the victim's transmitter TXn changes in accordance with the signal level transition of the aggressor's input signal INn-1. By activating the control signals FALL+ and FALL-, the signal levels of the control signals FALL+ and FALL- are controlled.

[0073] Thus, multiple control signals RISE+, RISE-, FALL+, and FALL- for controlling the driver strength of the driver are provided for each transition state of the signal levels of the input signals INn and INn-1 in adjacent communication channels.

[0074] This allows the operating speed of the signal level transitions for the control signals RISE+, RISE-, FALL+, and FALL- to be less than half the rate of change in the signal level of the reference victim's input signal INn (the response speed of the input signal INn).

[0075] As a result, in the transmission circuit 11 of this embodiment, the transmitter TXn can relax the constraints on the timing of the control signals RISE+, RISE-, FALL+, and FALL-.

[0076] Furthermore, in this embodiment, the period for the transition of the signal levels of the control signals RISE+, RISE-, FALL+, FALL- can be shortened, and the activation of the control signals RISE+, RISE-, FALL+, FALL- is controlled according to the transition state of the signal levels of the input signals INn, INn-1. Therefore, in the transmission circuit 11 of this embodiment, the transmitter TXn can reduce the current generated by the operation for controlling the control signals RISE+, RISE-, FALL+, FALL-.

[0077] Furthermore, with regard to the falling edge of the input signal INn, the driver strength on the pull-down side of the driver circuits 110 and 120 can be controlled by a control signal in accordance with the signal level transition of the adjacent input signal INn-1, as shown in the control shown in Figure 3(b), by a process substantially similar to the control of the driver strength with respect to the rising edge of the input signal INn shown in Figure 4.

[0078] (c)Specific examples Figure 5 is a circuit diagram showing an example of a specific circuit configuration of the transmitter TXn in this embodiment.

[0079] The transmitter TXn in Figure 5 receives the input signal INn and sends the inverted signal of the input signal INn as the output signal OUTn to the receiving circuit 20 via the communication path TP. Note that the example of the transmitter TXn in Figure 5 includes components for increasing the driver strength but does not include components for decreasing the driver strength.

[0080] The transmitter TXn includes flip-flops 200, 201, 202, 203, 204, an edge detection unit 210, a signal generation unit 220, logic gates 230, 231, and driver units 240, 250, 260, 290.

[0081] In the transmitter TXn shown in Figure 5, flip-flop 200 receives the input signal INn(t) at the input terminal of transmitter TXn, and flip-flop 201 receives the input signal INn-1(t) at the input terminal of transmitter TXn. Flip-flops 200 and 201 hold the received input signals IN(t) and INn-1(t). Depending on how long they hold the input signals IN(t) and INn-1(t) at a certain time t, flip-flops 200 and 201 output the signals from the previous cycle (one clock cycle prior) (hereinafter also called past signals or held signals) INn(t-1) and INn-1(t-1). For example, past signals INn(t-1) and INn-1(t-1), respectively, are supplied from flip-flops 200 and 201 to the edge detection unit 210. Flip-flops 200 and 201 are, for example, D-type flip-flops. A D-type flip-flop is also known as a DFF.

[0082] <Edge detection unit 210> The edge detection unit 210 detects the change state (signal edge) of the signal waveform of the input signals INn and INn-1. The edge detection unit 210 detects the change state of the signal level of the input signal IN from a "L" level to a "H" level (rising edge) and the change state of the signal level of the input signal IN from a "H" level to a "L" level (falling edge).

[0083] In the edge detection unit 210, logic gates 211 and 212 are provided on the pull-up side of the driver units 240, 250, and 260.

[0084] The logic gate 211 is an AND gate 211. The AND gate 211 has a positive logic input node and a negative logic input node. The AND gate 211 has an output node connected to the signal generation unit 220. The AND gate 211 receives the input signal INn-1(t) at the positive logic input node. The AND gate 211 receives the signal INn-1(t-1) at the negative logic input gate. The AND gate 211 performs a logical AND operation between the input signal INn-1(t) and the inverted signal of the signal INn-1(t-1). The AND gate 211 outputs the result of the operation to the signal generation unit 220.

[0085] If the signal level of input signal INn-1(t) is "L" and the signal level of signal INn-1(t-1) is "H", then the AND gate 211 outputs a "L" level signal.

[0086] If the signal level of input signal INn-1(t) is "L" level and the signal level of signal INn-1(t-1) is "L" level, the AND gate 211 outputs a "L" level signal.

[0087] If the signal level of input signal INn-1(t) is "H" level and the signal level of signal INn-1(t-1) is "H" level, then the AND gate 211 outputs a "L" level signal.

[0088] If the signal level of input signal INn-1(t) is "H" level and the signal level of signal INn-1(t-1) is "L" level, the AND gate 211 outputs a "H" level signal.

[0089] Thus, the AND gate 211 on the pull-up side outputs an "H" level signal as a result of the calculation when the signal level of the input signal INn-1 changes from a "L" level to a "H" level.

[0090] The logic gate 212 is an AND gate 212. The AND gate 212 has a positive logic input node and a negative logic input node. The AND gate 212 has an output node connected to the signal generation unit 220. The AND gate 212 receives the input signal INn(t) at the positive logic input node. The AND gate 212 receives the signal INn(t-1) at the negative logic input gate. The AND gate 212 performs an AND operation between the input signal INn(t) and the inverted signal of signal INn(t-1). The AND gate 212 outputs the result of the operation to the signal generation unit 220.

[0091] If the signal level of input signal INn(t) is "L" and the signal level of signal INn(t-1) is "H", then the AND gate 212 outputs a "L" level signal.

[0092] If the signal level of input signal INn(t) is "L" and the signal level of signal INn(t-1) is "L", then the AND gate 212 outputs a "L" level signal.

[0093] If the signal level of input signal INn(t) is "H" level and the signal level of signal INn(t-1) is "H" level, then AND gate 212 outputs a "L" level signal.

[0094] If the signal level of input signal INn(t) is "H" level and the signal level of signal INn(t-1) is "L" level, the AND gate 212 outputs a "H" level signal.

[0095] Thus, the AND gate 212 on the pull-up side outputs an "H" level signal as a result of the calculation when the signal level of the input signal INn changes from a "L" level to a "H" level.

[0096] In the edge detection unit 210, logic gates 213 and 214 are provided on the pull-down side of the driver units 240, 250, and 260.

[0097] The logic gate 213 is an AND gate 213. The AND gate 213 has a positive logic input node and a negative logic input node. The AND gate 213 has an output node connected to the signal generation unit 220. The AND gate 213 receives the signal INn-1(t-1) at the positive logic input node. The AND gate 213 receives the input signal INn-1(t) at the negative logic input gate. The AND gate 213 performs a logical AND operation between the signal INn-1(t-1) and the inverted signal of the input signal INn-1(t). The AND gate 213 outputs the result of the operation to the signal generation unit 220.

[0098] If the signal level of input signal INn-1(t) is "H" level and the signal level of signal INn-1(t-1) is "L" level, the AND gate 213 outputs a "L" level signal.

[0099] If the signal level of input signal INn-1(t) is "H" level and the signal level of signal INn-1(t-1) is "H" level, then AND gate 213 outputs a "L" level signal.

[0100] If the signal level of input signal INn-1(t) is "L" and the signal level of signal INn-1(t-1) is "L", then the AND gate 213 outputs a "L" level signal.

[0101] If the signal level of input signal INn-1(t) is "L" and the signal level of signal INn-1(t-1) is "H", then the AND gate 213 outputs a "H" level signal.

[0102] Thus, the AND gate 213 on the pull-down side outputs an "H" level signal as a result of the calculation when the signal level of the input signal INn-1 changes from an "H" level to an "L" level.

[0103] The logic gate 214 is an AND gate 214. The AND gate 214 has a positive logic input node and a negative logic input node. The AND gate 214 has an output node connected to the signal generation unit 220. The AND gate 214 receives the signal INn(t-1) at the positive logic input node. The AND gate 214 receives the input signal INn(t) at the negative logic input gate. The AND gate 214 performs an AND operation between the signal INn(t-1) and the inverted signal of the input signal INn(t). The AND gate 214 outputs the result of the operation to the signal generation unit 220.

[0104] If the signal level of input signal INn(t) is "H" level and the signal level of signal INn(t-1) is "L" level, the AND gate 214 outputs a "L" level signal.

[0105] If the signal level of input signal INn(t) is "H" level and the signal level of signal INn(t-1) is "H" level, the AND gate 214 outputs a "L" level signal.

[0106] If the signal level of input signal INn(t) is "L" and the signal level of signal INn(t-1) is "L", then the AND gate 214 outputs a "L" level signal.

[0107] If the signal level of input signal INn(t) is "L" and the signal level of signal INn(t-1) is "H", then the AND gate 214 outputs a "H" level signal.

[0108] Thus, the AND gate 214 on the pull-down side outputs an "H" level signal as a result of the calculation when the signal level of the input signal INn changes from an "H" level to an "L" level.

[0109] <Signal generation unit 220> The signal generation unit 220 receives the detection results of the signal level transitions (signal edges) of the input signals INn and INn-1 by the edge detection unit 210. Based on the signal edge detection results, the signal generation unit 220 generates control signals RISE+ and FALL+ for FFE.

[0110] The signal generation unit 220 includes two logic gates 221 and 222. The logic gates 221 and 222 are AND gates 221 and 222.

[0111] The AND gate 221 has two positive logic input nodes. The AND gate 221 has an output node connected to the flip-flop 203. The AND gate 221 receives the result of the AND gate 211's operation on the detection result of the signal edge of the input signal INn-1 at one input node. The AND gate 221 receives the result of the AND gate 212's operation on the detection result of the signal edge of the input signal INn at the other input node. The AND gate 221 performs an AND operation with the signal from AND gate 211 and the signal from AND gate 212. The AND gate 221 sends a control signal RISE+ corresponding to the result of the AND operation to the flip-flop 203.

[0112] AND gate 221 outputs a low-level signal RISE+ if at least one of the results of the operation of the two AND gates 211 and 212 is at a low level. AND gate 221 outputs a high-level signal RISE+ if both of the results of the operation of the two AND gates 211 and 212 are at a high level. In other words, AND gate 221 outputs a high-level signal RISE+ if the signal levels of both input signals INn and INn-1 transition from a low level to a high level (i.e., both signal edges of input signals INn and INn-1 are rising edges).

[0113] The AND gate 222 has two positive logic input nodes. The AND gate 222 has an output node connected to the flip-flop 204. The AND gate 222 receives the result of the AND gate 213's operation on the detection result of the signal edge of the input signal INn-1 at one input node. The AND gate 222 receives the result of the AND gate 214's operation on the detection result of the signal edge of the input signal INn at the other input gate. The AND gate 222 performs an AND operation with the signal from AND gate 213 and the signal from AND gate 214. The AND gate 222 sends a control signal FALL+ corresponding to the result of the AND operation to the flip-flop 204.

[0114] AND gate 222 outputs a low-level signal FALL+ if at least one of the results of the operation of the two AND gates 213 and 214 is at a low level. AND gate 222 outputs a high-level signal FALL+ if both of the results of the operation of the two AND gates 213 and 214 are at a high level. In other words, AND gate 222 outputs a high-level signal FALL+ if the signal levels of both input signals INn and INn-1 transition from a high level to a low level (when both signal edges of input signals INn and INn-1 are falling edges).

[0115] In this way, the signal generation unit 220 can generate signals RISE+ and FALL+ for controlling the FFE according to the state of the signal edges of the two input signals INn and INn-1, which may cause crosstalk.

[0116] <Flip-flops 202, 203, 204> Flip-flops 202, 203, and 204 are provided for the high-speed operation of the transmitter TXn. Flip-flops 202, 203, and 204 are, for example, D-type flip-flops.

[0117] Flip-flop 202 receives the input signal INn(t). Flip-flop 202 temporarily holds the received input signal INn(t). Flip-flop 202 outputs the held input signal INn(t) at a certain timing according to the clock.

[0118] The flip-flop 203 receives the signal RISE+ from the AND gate 221 of the signal generation unit 220. The flip-flop 203 temporarily holds the received signal RISE+. At a certain timing corresponding to the clock, the flip-flop 203 outputs the held signal RISE+.

[0119] The flip-flop 204 receives the FALL+ signal from the AND gate 222 of the signal generation unit 220. The flip-flop 204 temporarily holds the received FALL+ signal. At a certain timing according to the clock, the flip-flop 204 outputs the held FALL+ signal.

[0120] Furthermore, flip-flops 202, 203, and 204 do not need to be provided if there are no problems with the input / output timing of the signals in the transmitter TXn.

[0121] <Logic gates 230, 231> Logic gate 230 receives signals from flip-flops 202 and 203. Logic gate 230 is a NAND gate. The NAND gate 230 has two positive logic input nodes. The NAND gate 230 has an output node connected to the driver unit 250. The NAND gate 230 receives the input signal INn(t) from flip-flop 202 at one input node. The NAND gate 230 receives the signal RISE+ from flip-flop 203 at the other input gate. The NAND gate 230 performs a negative logical AND operation (NAND operation) between the signal INn(t) from flip-flop 202 and the signal RISE+ from flip-flop 203. The NAND gate 230 sends a control signal corresponding to the result of the NAND operation to the driver unit 250.

[0122] The NAND gate 230 outputs an "H" level control signal if at least one of the signals from the two flip-flops 202 and 203 is at an "L" level. The NAND gate 230 outputs an "L" level control signal if both of the signals from the two flip-flops 202 and 203 are at an "H" level.

[0123] As described above, the signal RISE+ held in the flip-flop 203 is a signal corresponding to the detection result of the rising edge of the input signals INn and INn-1. Therefore, the signal corresponding to the result of the NAND operation by the NAND gate 230 shows a value in which the detection result of the rising edge of signals INn and INn-1 is reflected in the input signal INn.

[0124] Furthermore, the NAND gate 230 may be treated as part of the signal generation unit 220 or as part of the driver unit 250.

[0125] Logic gate 231 receives signals from flip-flops 202 and 204. Logic gate 231 is an AND gate. The AND gate 231 has a positive logic input node and a negative logic input node. The AND gate 231 has an output node connected to the driver unit 260. The AND gate 231 receives the input signal INn(t) from flip-flop 202 at the negative logic input node. The AND gate 231 receives the signal FALL+ from flip-flop 204 at the positive logic input gate. The AND gate 231 performs an AND operation between the inverted signal INn(t) from flip-flop 202 and the signal FALL+ from flip-flop 204. The AND gate 231 sends a control signal indicating the result of the operation to the driver unit 260.

[0126] The AND gate 231 outputs a control signal at an "H" level if the signal INn(t) from the flip-flop 202 is at an "L" level and the signal FALL+ from the flip-flop 204 is at an "H" level.

[0127] The AND gate 231 outputs a low-level control signal if the signal INn(t) from flip-flop 202 is low and the signal FALL+ from flip-flop 204 is low.

[0128] The AND gate 231 outputs a low-level control signal if the signal INn(t) from flip-flop 202 is at a high level and the signal FALL+ from flip-flop 204 is at a high level.

[0129] The AND gate 231 outputs a low-level control signal if the signal INn(t) from flip-flop 202 is at a high level and the signal FALL+ from flip-flop 204 is at a low level.

[0130] As described above, the signal FALL+ held in the flip-flop 204 is a signal corresponding to the detection result of the falling edge of the input signals INn and INn-1. Therefore, the signal corresponding to the result of the AND operation by the AND gate 231 shows a value in which the detection result of the falling edge of signals INn and INn-1 is reflected in the input signal INn.

[0131] Furthermore, the AND gate 231 may be treated as part of the signal generation unit 220 or as part of the driver unit 260.

[0132] <Driver section 240, 250, 260, 290> The driver unit 290 is a pre-driver for the driver unit 240. Hereafter, the driver unit 290 will also be referred to as the pre-driver 290.

[0133] The pre-driver 290 is connected between the flip-flop 202 and the input node of the driver unit 240. The input node of the pre-driver 290 is connected to the output node of the flip-flop 202. The output node of the pre-driver 290 is connected to the input node of the driver unit 240.

[0134] The pre-driver 290 outputs the inverted signal INn(t) from the flip-flop 202 to the driver unit 240.

[0135] The driver unit 240 is the main driver for the transmitter TXn. The input node of the driver unit 240 is connected via the pre-driver 290 to the output node of the flip-flop 202 that holds the input signal INn(t). The output node of the driver unit 240 is connected to the output terminal 190 of the transmitter TXn.

[0136] The driver unit 240 includes a P-type field-effect transistor (e.g., a P-channel MOS transistor) 241, an N-type field-effect transistor (e.g., an N-channel MOS transistor) 242, and resistors 243 and 244. Hereafter, the field-effect transistor will simply be referred to as a transistor.

[0137] One end of the current path of transistor 241 is connected to a voltage node (hereinafter referred to as the power supply node) to which the voltage VDD is supplied. The other end of the current path of transistor 241 is connected to one end of resistor 243. The other end of resistor 243 is connected to the output node of driver unit 240. The gate of transistor 241 is connected to the output node of pre-driver 290 as an input node of driver unit 240.

[0138] One end of the current path of transistor 242 is connected to a voltage node (hereinafter referred to as the ground node) to which the voltage VSS is supplied. The other end of the current path of transistor 242 is connected to one end of resistor 244. The other end of resistor 244 is connected to the output node of driver unit 240. The gate of transistor 242 is connected to the output node of pre-driver 290 as an input node of driver unit 240.

[0139] The gates of transistors 241 and 242 receive an inverted signal of the input signal INn from the pre-driver 290.

[0140] The driver unit 240 operates according to the signal level of the input signal INn. When the signal level of the input signal INn is "L" level, the N-type transistor 242 of the driver unit 240 is driven by the inverted signal of the input signal INn from the pre-driver 290. In this case, the P-type transistor 241 of the driver unit 240 functions as a load. As a result, the driver unit 240 outputs an "L" level signal, which is the common-mode signal of the input signal INn. When the signal level of the input signal INn is "H" level, the P-type transistor 241 of the driver unit 240 is driven by the inverted signal of the input signal INn from the pre-driver 290. In this case, the N-type transistor 242 functions as a load. As a result, the driver unit 240 outputs an "H" level signal, which is the common-mode signal of the input signal INn.

[0141] The driver unit 250 is a pull-up driver (sub-driver) for the main driver 240. The input node of the driver unit 250 is connected to the output node of the NAND gate 230. The output node of the driver unit 250 is connected to the output terminal 190 of the transmitter TX.

[0142] The driver unit 250 includes a P-type transistor 251 and a resistor 253.

[0143] One end of the current path of transistor 251 is connected to the power supply node. The other end of the current path of transistor 251 is connected to one end of resistor 253. The other end of resistor 253 is connected to the output node of driver unit 250. The gate of transistor 251 is connected to the output node of NAND gate 230.

[0144] The driver unit 250 operates in response to the signal from the NAND gate 230. When the signal level from the NAND gate 230 is at the "L" level, the P-type transistor 251 of the driver unit 250 is driven. As a result, the driver unit 250 outputs a "H" level signal. When the signal level from the NAND gate 230 is at the "H" level, the P-type transistor 251 is turned off. As a result, the driver unit 250 is in a non-driven state and is electrically isolated from the output terminal 190.

[0145] Thus, when both the signal level of the input signal INn and the signal level of the signal from the flip-flop 203 are at the "H" level, the driver unit 250 outputs an "H" level signal. On the other hand, when the signal level of the input signal INn is at the "L" level, the driver unit 250 turns off, regardless of the signal level of the signal from the flip-flop 203.

[0146] Therefore, when the signal level of the input signal INn(t) is at the "H" level and both input signals INn and INn-1 are on the rising edge, the output of the pull-up driver unit 250 enhances the output of the driver unit 240. In this way, the driven driver units 240 and 250 increase the driver strength of the driver units 240 and 250 of the transmitter TX. As a result, the transmitter TX can supply a large current to the output terminal 190.

[0147] The driver unit 260 is a pull-down driver (sub-driver) relative to the main driver 240. The input node of the driver unit 260 is connected to the output node of the AND gate 231. The output node of the driver unit 260 is connected to the output terminal 190 of the transmitter TXn.

[0148] The driver unit 260 includes an N-type transistor 26 and a resistor 263.

[0149] One end of the current path of transistor 261 is connected to the ground node. The other end of the current path of transistor 261 is connected to one end of resistor 263. The other end of resistor 263 is connected to the output node of driver unit 260. The gate of transistor 261 is connected to the output node of AND gate 231.

[0150] The driver unit 260 operates in response to the signal from the AND gate 231. When the signal level from the AND gate 231 is at the "L" level, the N-type transistor 261 of the driver unit 260 is turned off. As a result, the driver unit 260 is in a non-driven state and is electrically isolated from the output terminal 190. On the other hand, when the signal level from the AND gate 231 is at the "H" level, the N-type transistor 261 is driven. As a result, the driver unit 260 outputs a "L" level signal.

[0151] If the signal level of the input signal INn is "L" and the signal level of the signal from the flip-flop 204 is "H", the driver unit 260 outputs a "L" level signal. If the signal level of the input signal INn is "H", or if the signal level of the signal from the flip-flop 204 is "L", the driver unit 260 turns off.

[0152] Therefore, when the signal level of the input signal INn(t) is at the "L" level and both input signals INn and INn-1 are on the falling edge, the output of the pull-down driver unit 250 enhances the output of the driver unit 240. In this way, the driven driver units 240 and 260 increase the driver strength of the driver units 240 and 260 of the transmitter TX. As a result, the transmitter TX can supply a large current to the output terminal 190.

[0153] <Example of operation> In the transmission circuit 11 of this embodiment, the transmitter TXn in Figure 5 operates as follows.

[0154] The transmitter TXn in Figure 5 receives input signals INn and INn-1.

[0155] Within the transmitter TXn, the edge detection unit 210 detects the change state (rising edge or falling edge) of the signal waveform of the input signal INn. The signal generation unit 220 generates control signals RISE+ and FALL+ based on the signal edge detection result of the edge detection unit 210.

[0156] In the transmitter TXn having the circuit configuration shown in Figure 5, when the signal level of the input signal INn is at the "H" level, the control signal RISE+ is at the "H" level, and the control signal FALL+ is at the "L" level (when both signal edges of the 2-bit input signals INn and INn-1 are rising edges), the driver unit (main driver) 240 outputs a "H" level signal, and the driver unit (pull-up sub-driver) 250 outputs a "H" level signal. At this time, the driver unit (pull-down sub-driver) 260 is turned off. As a result, the output signal OUTn from the transmitter TXn is output with the signal delay caused by jitter suppressed.

[0157] In the transmitter TXn having the circuit configuration shown in Figure 5, when the signal level of the input signal INn is "L", the control signal RISE+ is "L", and the control signal FALL+ is "H" (when both signal edges of the 2-bit input signals INn and INn-1 are falling edges), the driver unit (main driver) 240 outputs a "L" level signal, and the driver unit (pull-down sub-driver) 260 outputs a "L" level signal. At this time, the driver unit (pull-up sub-driver) 250 is turned off. As a result, the output signal OUTn from the transmitter TXn is output with the signal delay caused by jitter suppressed.

[0158] (d) Summary In interface circuits that perform parallel communication, crosstalk occurs between parallel communication paths. Due to the effects of crosstalk, such as jitter, the transmitted signal may be degraded.

[0159] In this embodiment, the transmission circuit 11 controls the driver strength of the transmitter TXn's driver unit according to the state of multiple signals transferred from each of the multiple adjacent communication paths. This controls the output timing (response speed) of the transmission circuit 11's output signal OUTn. As a result, the transmission circuit 11 in this embodiment can suppress the effects of crosstalk.

[0160] Figure 6 is a diagram illustrating the characteristics of the transmission circuit 11 in this embodiment.

[0161] Figure 6(a) shows the waveform of a signal output from a typical transmitting circuit. Figure 6(b) shows the waveform of a signal output from the transmitting circuit 11 of this embodiment.

[0162] As shown in Figure 6(a), in a typical transmitting circuit, the difference between the phase of a signal delayed due to jitter and the phase of a signal that has led is indicated by "J1".

[0163] As shown in Figure 6(b), in the transmission circuit 11 of this embodiment, the difference between the phase of a signal that is delayed due to jitter and the phase of a signal that is leading is indicated by "J2". The difference J2 is smaller than the difference J1.

[0164] Thus, the transmission circuit 11 of this embodiment can reduce the effects of jitter by controlling the driver strength of the driver unit according to the state of multiple adjacent signals INn and INn-1 in the communication path.

[0165] As described above, the transmission circuit as a semiconductor circuit in this embodiment can have improved characteristics.

[0166] (2) Second embodiment Referring to Figure 7, the semiconductor circuit of the second embodiment will be described.

[0167] Figure 7 is a circuit diagram showing an example configuration of a transmitting circuit as a semiconductor circuit in this embodiment.

[0168] As shown in Figure 7, in the transmission circuit 11 of this embodiment, the driver sections 240A, 250A, and 260A of the transmitter TXn are composed of N-type transistors without using P-type transistors.

[0169] The driver unit 240A includes two N-type transistors 242 and 245, resistors 243 and 244, an inverter 248, and a buffer 249. Transistor 245 is, for example, an N-type field-effect transistor (e.g., an N-channel MOS transistor).

[0170] One end of the current path of transistor 245 is connected to the power supply node. The other end of the current path of transistor 245 is connected to one end of resistor 243.

[0171] The input node of inverter 248 is connected to the output node of pre-driver 290. The output node of inverter 248 is connected to the gate of transistor 245.

[0172] The input node of buffer 249 is connected to the output node of pre-driver 290. The output node of buffer 249 is connected to the gate of transistor 242.

[0173] The signal from the pre-driver 290 (the inverted signal of the input signal INn) is supplied to the input node of the inverter 248 and the input node of the buffer 249. The inverter 248 supplies the signal from the flip-flop 202 and the in-phase signal to the gate of the transistor 245. The buffer 249 supplies the inverted signal from the flip-flop 202 to the gate of the transistor 242 at a timing corresponding to the output timing of the signal from the inverter 248.

[0174] As a result, the driver unit 240A, which consists of two N-type transistors 242 and 245, outputs the input signal INn.

[0175] The driver unit 250A includes a transistor 252, a resistor 254, and an inverter 258. The transistor 252 is, for example, an N-type field-effect transistor (e.g., an N-channel MOS transistor).

[0176] One end of the current path of transistor 252 is connected to the power supply node. The other end of the current path of transistor 252 is connected to one end of resistor 254. The other end of resistor 254 is connected to the output node of driver unit 250A.

[0177] The input node of inverter 258 is connected to the output node of NAND gate 230. The output node of inverter 258 is connected to the gate of transistor 252.

[0178] The signal from the NAND gate 230 is supplied to the input node of the inverter 258. The inverter 258 supplies the inverted signal from the NAND gate 230 to the gate of transistor 252.

[0179] As a result, the driver unit 250A, which is composed of N-type transistors 252, operates in response to the inverted signal from the NAND gate 230.

[0180] The driver unit 260A includes an N-type transistor 261, a resistor 263, and a buffer 268.

[0181] The input node of buffer 268 is connected to the output node of AND gate 231. The output node of buffer 268 is connected to the gate of transistor 261.

[0182] The signal from AND gate 231 is supplied to the input node of buffer 268. Buffer 268 supplies the signal from AND gate 231 to the gate of transistor 261.

[0183] As a result, the driver unit 260A, which is composed of N-type transistors 261, operates in response to the signal from the AND gate 231.

[0184] As in this embodiment, even if the driver sections 240A, 250A, and 260A of the transmitter TXn are composed only of N-type transistors, the transmitter TXn of the transmission circuit 11 can control the driver strength of the driver according to the signal state of the two supplied input signals INn and INn-1.

[0185] Therefore, the transmitting circuit 11 as a semiconductor circuit in the second embodiment can obtain substantially the same effects as in the first embodiment.

[0186] (3) Third Embodiment Referring to Figures 8 and 9, a semiconductor circuit of the third embodiment will be described.

[0187] Figure 8 shows an overview of the transmitting circuit 11 as a semiconductor circuit in this embodiment.

[0188] As shown in Figure 8, the transmission circuit 11 may also be a transmitter including an FFE using 3-bit input signals INn, INn-1, and INn+1. The communication channel corresponding to input signal INn is provided between the communication channel corresponding to input signal INn-1 and the communication channel corresponding to input signal INn+1.

[0189] The transmitter TXn in Figure 8 includes a driver consisting of FFEs at the transmitting end of the high-speed interface. As shown in Figure 2, the transmitter TXn includes three driver circuits 110, 120, 130 and an adder 150.

[0190] The transmitter TXn obtains the output signal OUTn using the 3-bit signals INn, INn-1, and INn+1. The transmitter TXn receives the input signal INn of the device to be transmitted (to be processed) and the input signals INn-1 and INn+1 from the two communication channels TP on both sides. The transmitter TXn sends the output signal OUTn, obtained by processing the signal states (e.g., signal edges) of the three input signals INn, INn-1, and INn+1, to the receiving circuit 20 via the communication channel TP.

[0191] Figure 9 shows an example of setting the driver strength of the transmitter TXn in the transmission circuit 11 of this embodiment.

[0192] Figure 9(a) shows an example of setting the pull-up driver strength of the transmitter TXn driver section. Figure 9(b) shows an example of setting the pull-down driver strength of the transmitter TXn driver section. In Figures 9(a) and (b), "R" indicates that the signal waveform is in a rising state, and "F" indicates that the signal waveform is in a falling state.

[0193] As described above, if the signal waveform of the victim's signal INn and the signal waveforms of the aggressor's signals INn-1 and INn+1 are the same, the output signal OUTn will have a delayed output timing due to crosstalk. The transmitter TXn increases the driver's on-resistance (driver strength) to suppress the timing delay. This speeds up the output timing of the output signal OUTn.

[0194] As shown in Figures 9(a) and (b), if the signal waveform of the victim's signal INn and one or more of the two aggressor's signals INn-1 and INn+1 are identical without containing signal edges of different waveform states, the transmitter TXn increases the driver's on-resistance in proportion to the number of identical waveform states.

[0195] Furthermore, if the mutual inductance of the aggressor is large, the effect of crosstalk (e.g., jitter) is reduced by setting a strong on-resistance.

[0196] If the signal waveform of the victim's signal INn is different from that of the aggressor's signals INn-1 and INn+1, without containing any signal edges that are identical to those of the aggressor's signals INn-1 and INn+1, the output timing of the output signal OUTn will be advanced due to the effects of crosstalk. In this case, the on-resistance of the transmitter TXn is reduced. This causes the output timing of the output signal OUTn to be delayed toward a predetermined timing.

[0197] If the signal waveforms of the two signals INn-1 and INn+1 on the aggressor side do not change, the transmitter TXn is set to a driver strength of "0" without changing the on-resistance, assuming there is no crosstalk effect between signals INn, INn-1, and INn+1.

[0198] If the signal waveform of one aggressor's signal INn-1 differs from the signal waveform of the other aggressor's signal INn+1, the transmitter sets the driver strength according to the number of states of the aggressor's signals INn-1 and INn+1 relative to the state of the victim's signal INn, as shown in equation (f1) below. Here, the number of aggressors with signal edges in the same state as the victim's signal edges is denoted as "N1", and the number of aggressors with signal edges in a different state than the victim's signal edges is denoted as "N2".

[0199] Driver strength = N1 - N2 ... (f1)

[0200] For example, if there is a difference in the magnitude of multiple mutual inductances between the victim's communication channel and the communication channels of each aggressor, the driver strength is determined using a coefficient set for each aggressor, as shown in equation (f2) below. Here, of the two aggressor signals INn-1 and INn+1 adjacent to the victim, the coefficient set for one aggressor's signal INn-1 is denoted as "a", and the coefficient set for the other aggressor's signal INn+1 is denoted as "b". The number of aggressor signals INn-1 that have the same signal waveform as the victim's signal INn is denoted as N1p, and the number of aggressor signals INn+1 that have the same signal waveform as the victim's signal INn is denoted as N1q. The number of signals INn-1 on one aggressor side that have a different signal waveform from the victim's signal INn is denoted as N2p, and the number of signals INn+1 on the other aggressor side that have a different signal waveform from the victim's signal INn is denoted as N2q.

[0201] Driver strength = a × N1p + b × N1q - a × N2p - b × N2q ... (f2)

[0202] If the number of aggressors relative to the victim is two or more, the magnitude of the coefficient corresponding to the mutual inductance may be set to a different magnitude for each aggressor.

[0203] In this embodiment, an example is shown in which the driver strength of the victim's transmitter is increased and decreased according to the signal waveform on the aggressor side. However, if it is difficult to implement a configuration for decreasing the driver strength depending on the circuit configuration of the transmitting circuit, the transmitting circuit may control the driver strength using only a configuration for increasing the driver strength. Even in this case, the transmitting circuit of this embodiment can mitigate the effects of crosstalk such as jitter.

[0204] Furthermore, in the transmission circuit 11 of this embodiment, the number of input signals IN supplied to the transmitter TXn may be 4 or more.

[0205] As described above, the transmitting circuit as a semiconductor circuit of the third embodiment can obtain substantially the same effects as the embodiments described above.

[0206] (4) Fourth Embodiment A semiconductor circuit of the fourth embodiment will be described with reference to Figures 10 to 15.

[0207] (a) Circuit example Figure 10 is a circuit diagram showing the circuit configuration of the transmitting circuit 11 as a semiconductor circuit in this embodiment. The transmitting circuit 11 in this embodiment reduces the effects of crosstalk by using a time adjustment unit 320 that can control the time for signal transfer.

[0208] As shown in Figure 10, in the transmission circuit 11 of this embodiment, the transmitter TXn includes a flip-flop 300, a time adjustment unit 320, and driver units 240 and 290. The time adjustment unit 320 is composed of, for example, an edge detection unit 330, a timing control signal generation unit 340, and a timing control unit 350.

[0209] The flip-flop 300 holds the input signal INn supplied to the transmitter TXn for a certain period (for example, a period of one clock cycle). The flip-flop 300 then outputs the held signal as the past signal INn(t-1).

[0210] The edge detection unit 330 detects the signal edges of the input signal INn(t). The edge detection unit 330 outputs an edge detection signal EGn(t) according to the detection result. For example, the edge detection unit 330 uses the input signal INn(t) and the past signal INn(t-1) to detect whether the signal waveform of the input signal INn(t) is a rising edge or a falling edge. Note that for input signals IN that are not affected by jitter due to crosstalk, signal edges do not need to be detected.

[0211] The timing control signal generation unit 340 generates a control signal TC to control the transmission timing (e.g., delay time) of the input signal. For example, the timing control signal generation unit 340 receives edge detection signals EGn(t) for the corresponding input signal INn(t) and edge detection signals EGn-1(t) and EGn+1(t) for other input signals of several bits (e.g., 2-bit input signals) INn-1 and INn+1 at a certain time t. The timing control signal generation unit 340 generates a control signal TC using the multiple edge detection signals EGn(t), EGn-1(t), and EGn+1(t). The magnitude of the delay time indicated by the control signal TC is set according to the relationship between the state of the signal waveform of the input signal INn and the state of the signal waveforms of adjacent input signals INn-1 and INn+1, and the number of rising and falling edges of the signal waveforms of adjacent input signals INn-1 and INn+1, as shown in Figures 3 and 9.

[0212] The timing control unit 350 adjusts the transmission timing (delay time of signal INn(t)) of the input signal INn(t) based on the control signal TC. The timing control unit 350 outputs the input signal INn(t)a to the driver unit 240 at a timing corresponding to the delay time indicated by the control signal TC. For example, the timing control unit 350 includes a time adjustment buffer.

[0213] The driver unit 290 is connected between the timing control unit 350 and the driver unit 240. The driver unit 290 is a pre-driver 290 for the driver unit 240. The input node of the pre-driver 290 is connected to the output node of the timing control unit 350. The output node of the pre-driver 290 is connected to the input node of the driver unit 240. The pre-driver 290 outputs an inverted signal of the input signal INn(t)a, to the driver unit 240, to which a certain delay amount has been added by the timing control unit 350.

[0214] The driver unit (main driver) 240 is connected between the pre-driver 290 and the output terminal 190 of the transmitter TXn. The input node of the driver unit 240 is connected to the output node of the pre-driver 290. The output node of the driver unit 240 is connected to the output terminal 190 of the transmitter TXn. The driver unit 240 outputs a signal in phase with the input signal INn(t)a, to which a certain delay amount has been added by the timing control unit 350, as the output signal OUTn of the transmitter TXn to the output terminal 190.

[0215] <Edge detection unit 330> Figure 11 is a circuit diagram showing an example configuration of the edge detection unit 330 of the transmitter TXn in the transmission circuit 11 of this embodiment.

[0216] The edge detection unit 330 detects the signal edge of the input signal INn(t) by performing a logical operation between the current input signal INn(t) and a past input signal (for example, the input signal from one clock cycle ago) INn(t-1).

[0217] The edge detection unit 330 includes two logic gates 331 and 332.

[0218] The edge detection unit 330 detects the rising edge of the input signal INn using a logic gate 331. The logic gate 331 is an AND gate 331. The AND gate 331 includes a positive logic input node and a negative logic input node.

[0219] The AND gate 331 receives the current input signal INn(t) at its positive logic input node. The AND gate 331 also receives the input signal INn(t-1) from the flip-flop 300 one clock cycle ago at its negative logic input node.

[0220] If the signal level of the current input signal INn(t) is "H" level and the signal level of the signal (past signal) INn(t-1) is "L" level, the AND gate 331 outputs a signal EG-p at "H" level.

[0221] If the current input signal INn(t) has a high signal level and the signal INn(t-1) has a high signal level, the AND gate 331 outputs a low signal EG-p.

[0222] If the current input signal INn(t) has a low level and the signal INn(t-1) has a low level, the AND gate 331 outputs a low-level signal EG-p.

[0223] If the current input signal INn(t) has a low level and the signal INn(t-1) has a high level, the AND gate 331 outputs a low-level signal EG-p.

[0224] The situation where the signal level of the past input signal INn(t-1) was "L" and the signal level of the current input signal INn(t) is "H" indicates that the signal waveform (signal state) of the input signal INn(t) is a rising edge. Therefore, the "H" level signal EG-p output from the AND gate 331 indicates that the rising edge of the input signal INn(t) has been detected.

[0225] The edge detection unit 330 detects the falling edge of the input signal INn using a logic gate 332. The logic gate 332 is an AND gate 332. The AND gate 332 includes a negative logic input node and a positive logic input node.

[0226] The AND gate 332 receives the current input signal INn(t) at its negative logic input node. The AND gate 332 also receives the input signal INn(t-1) from the flip-flop 300, which was one clock cycle prior, at its positive logic input node.

[0227] If the current input signal INn(t) has a high signal level and the signal INn(t-1) has a low signal level, the AND gate 332 outputs a low signal EG-n. If the current input signal INn(t) has a high signal level and the signal INn(t-1) has a high signal level, the AND gate 332 outputs a low signal EG-n.

[0228] If the current input signal INn(t) has a low level and the signal INn(t-1) has a low level, the AND gate 332 outputs a low-level signal EG-n.

[0229] If the current input signal INn(t) has a low level and the signal INn(t-1) has a high level, the AND gate 332 outputs a high-level signal EG-n.

[0230] The situation where the signal level of the past input signal INn(t-1) was at the "H" level and the signal level of the current input signal INn(t) is at the "L" level indicates that the signal waveform of the input signal INn(t) is at a falling edge. Therefore, the "H" level signal output from the AND gate 332 indicates that the rising edge of the input signal INn(t) has been detected.

[0231] Thus, the edge detection unit 330 in Figure 11 can detect the rising edge and falling edge of the input signal INn(t).

[0232] Figure 12 is a schematic diagram showing the relationship between the edge detection unit 330 (330n, 330n-1, 330n+1, 330n+2) and the timing control signal generation unit 340 (340n, 340n-1, 340n+1, 340n+2) with respect to four communication channels (four input signals INn, INn-1, INn+1, INn+2).

[0233] <Timing control signal generation unit 340> The timing control signal generation unit 340 receives an edge detection signal EGn from the corresponding edge detection unit 330, and a plurality of edge detection signals EGn-1, EGn+1, EGn+2 relating to other input signals INn-1(t), INn+1(t), INn+2(t). The plurality of edge detection signals EGn-1, EGn+1, EGn+2 are supplied from other transmitters TXn-1, TXn+1, TXn+2. Based on the plurality of edge detection signals EGn, EGn-1, EGn+1, EGn+2, the timing control signal generation unit 340 generates a control signal TC indicating a time adjustment amount (e.g., delay amount) to be added to the corresponding input signal INn(t).

[0234] The timing control signal generation unit 340 supplies the generated control signal TC to the timing control unit (time adjustment buffer) 350. The control signal TC is a signal represented by a value of several bits. For example, the control signal TC includes codes (bit values) ENP and ENN for controlling the driving force of the timing control unit 350.

[0235] Code ENN is a signal that is activated when the signal level transition of the input signal INn is a falling edge and the magnitude of the delay amount (driver strength) of the timing control unit 350 is changed. Code ENP is a signal that is activated when the signal level transition of the input signal INn is a falling edge and the magnitude of the delay amount of the timing control unit 350 is changed.

[0236] In this way, since code ENP is controlled to correspond to the rising edge of the input signal INn and code ENN is controlled to correspond to the falling edge of the input signal INn, the operating speed for controlling codes ENP and ENN is less than half the response speed of the input signal INn.

[0237] Furthermore, since the operations for controlling codes ENP and ENN are executed only when codes ENP and ENN change, the current generated by the operation of the timing control signal generation unit 340 can be reduced.

[0238] <Edge detection unit 330> As shown in Figure 12, in the time adjustment units 320n, 320n-1, 320n+1, 320n+2 of the multiple transmitters TXn, TXn-1, TXn+1, TXn+2, each of the multiple edge detection units 330n, 330n-1, 330n+1, 330n+2 independently detects the rising edge or falling edge of the received input signals INn, INn-1, INn+1, INn+2.

[0239] Each edge detection unit 330 outputs an edge detection signal EG(EGn, EGn-1, EGn+1, EGn+2) corresponding to the signal edge detected from the input signal IN(t) and the past signal IN(t-1).

[0240] Each edge detection unit 330 sends an edge detection signal EG to the corresponding and other multiple timing control signal generation units 340.

[0241] For example, the edge detection unit 330n sends the edge detection signal EGn related to the signal edge detected in the input signal INn to the corresponding timing control signal generation unit 340n and other timing control signal generation units 340n-1, 340n+1, and 340n+2.

[0242] The edge detection unit 330n-1 sends the edge detection signal EGn-1 related to the signal edge detected in the input signal INn-1 to the corresponding timing control signal generation unit 340n-1 and other timing control signal generation units 340n, 340n+1, and 340n+2.

[0243] The edge detection unit 330n+1 sends the edge detection signal EGn+1 related to the signal edge detected in the input signal INn+1 to the corresponding timing control signal generation unit 340n+1 and other timing control signal generation units 340n, 340n-1, and 340n+2.

[0244] The edge detection unit 330n+2 sends the edge detection signal EGn+2 related to the signal edge detected in the input signal INn+2 to the corresponding timing control signal generation unit 340n+2 and other timing control signal generation units 340n, 340n-1, and 340n+1.

[0245] The timing control signal generation unit 340n sets the codes ENPn and ENNn of the control signal TCn based on the edge detection signals EGn, EGn-1, EGn+1, and EGn+2. The timing control signal generation unit 340n sends the control signal TCn, including the codes ENPn and ENNn, to the corresponding timing control unit 350n.

[0246] The timing control signal generation unit 340n-1 sets the codes ENPn-1 and ENNn-1 of the control signal TCn-1 based on the edge detection signals EGn, EGn-1, EGn+1, and EGn+2. The timing control signal generation unit 340n-1 sends the control signal TCn-1, including the codes ENPn-1 and ENNn-1, to the corresponding timing control unit 350n-1.

[0247] The timing control signal generation unit 340n+1 sets the codes ENPn+1 and ENNn+1 of the control signal TCn+1 based on the edge detection signals EGn, EGn-1, EGn+1, and EGn+2. The timing control signal generation unit 340n+1 sends the control signal TCn+1, which includes the codes ENPn+1 and ENNn+1, to the corresponding timing control unit 350n+1.

[0248] The timing control signal generation unit 340n+2 sets the codes ENPn+2 and ENNn+2 of the control signal TCn+2 based on the edge detection signals EGn, EGn-1, EGn+1, and EGn+2. The timing control signal generation unit 340n+2 sends the control signal TCn+2, which includes the codes ENPn+2 and ENNn+2, to the corresponding timing control unit 350n+2.

[0249] In this way, the edge detection unit 330 and the timing control signal generation unit 340 can set a delay amount for the corresponding input signal IN based on the signal state (signal edge) of the corresponding communication channel TP and multiple communication channels TP in its vicinity.

[0250] <Timing control unit 350> The timing control unit 350 receives the input signal INn(t) and the control signal TC. The timing control unit 350 adds a delay amount corresponding to the control signal TC to the input signal INn(t). As a result, the timing control unit 350 outputs the delayed input signal INn(t)a at a timing corresponding to the delay amount of the control signal TC.

[0251] Figure 13 is a circuit diagram showing an example configuration of the timing control unit 350 of the transmitter TXn in the transmission circuit 11 of this embodiment.

[0252] As shown in Figure 13, the timing control unit 350 includes an inverter 351 and P-type transistors 352, 354 and N-type transistors 353, 355.

[0253] The input node of inverter 351 receives the input signal INn(t). The output node of inverter 351 is connected to the gate of P-type transistor 352 and the gate of N-type transistor 353.

[0254] Transistors 352, 353, 354, and 355 are cascode inverter CIs.

[0255] One end of the current path of transistor 352 is connected to the output node NDa of the timing control unit 350. The other end of the current path of transistor 352 is connected to one end of the current path of P-type transistor 354. The other end of the current path of transistor 354 is connected to a power supply node to which the voltage VDD is applied.

[0256] One end of the current path of transistor 353 is connected to the output node NDa of the timing control unit 350. The other end of the current path of transistor 353 is connected to one end of the current path of N-type transistor 354. The other end of the current path of transistor 354 is connected to a ground node to which the voltage GND is applied.

[0257] The gate of transistor 354 receives the code ENP included in the control signal TC. Transistor 354 operates with a driving force corresponding to the value of the received code ENP. Transistor 354 functions as a load (variable resistor) in the cascode inverter CI.

[0258] The gate of transistor 355 receives the code ENN contained in the control signal TC. Transistor 355 operates with a driving force corresponding to the value of the received code ENN. Transistor 355 functions as a load in a cascode inverter.

[0259] The timing control unit 350 outputs a signal that is in phase with (at the same signal level as) the input signal INn, with a delay amount corresponding to the codes ENP and ENN of the control signal TC.

[0260] Figure 14 is a circuit diagram showing another configuration example of the timing control unit 350.

[0261] As shown in Figure 14, the timing control unit 350 further includes a P-type transistor 356 and an N-type transistor 357. Transistors 356 and 357 function as the main buffer (main driver) MB of the timing control unit 350. One end of the current path of transistor 356 is connected to the output node NDa of the timing control unit 350. The other end of the current path of transistor 356 is connected to the power supply node. One end of the current path of transistor 357 is connected to the output node NDa of the timing control unit 350. The other end of the current path of transistor 357 is connected to the ground node. The gates of transistor 356 and transistor 357 are connected to the output node of inverter 351.

[0262] The main buffer MB is connected in parallel to the cascode-structured inverter CI between the power node and the ground node. The main buffer MB is an always-on type buffer.

[0263] The timing control unit 350 in Figure 14 outputs a signal that is in phase with (at the same signal level as) the input signal INn, with a delay amount corresponding to the codes ENP and ENN of the control signal TC.

[0264] <Example of setting control signal TC> Figure 15 shows an example of setting the driver strength by the timing control signal generation unit 340 for the transmitter TXn in the transmission circuit 11 of this embodiment. In Figure 15, an example of setting the driver strength of the timing control unit 350 according to the detection results of three edge detection signals EGn, EGn-1, and EGn+1 is shown. In Figures 15(a) and (b), "R" indicates that the detected signal waveform is in a rising state (rising edge), and "F" indicates that the detected signal waveform is in a falling state (falling edge). Also, "-" indicates that the detected signal waveform is fixed at an "L" level or an "H" level (unchanged state).

[0265] Figure 15(a) shows an example of setting the driver strength on the pull-up side of the transmitter TXn. Figure 15(b) shows an example of setting the driver strength on the pull-down side of the transmitter TXn.

[0266] Here, the edge detection signal EGn corresponds to the victim's communication channel (input signal INn), and the edge detection signals EGn-1 and EGn+1 correspond to the aggressor's communication channels (input signals INn-1 and INn+1).

[0267] As shown in Figures 15(a) and (b), when the detection results of the victim's edge detection signal GNN and the aggressor's edge detection signals EGn-1 and EGn+1 are the same, the input signals INn, INn-1, and INn+1 are operating on the same signal edge. Therefore, the output signal OUTn will experience a delay in output timing due to crosstalk. To suppress this timing delay, the transmitter TXn sets the driver strength, indicated by the values ​​of codes ENP and ENN, to a large value such as +2. This increases the driver strength (on-resistance) of the timing control unit 350. As a result, the output timing of the output signal OUTn becomes earlier.

[0268] If the detection result of the victim's edge detection signal EGn is the same as one or more detection results of the two aggressor's edge detection signals EGn-1 and EGn+1, the transmitter TXn increases the driver strength of the timing control unit 350 according to the number of identical detection results.

[0269] Furthermore, if the mutual inductance of the aggressor is large, the effect of crosstalk (e.g., jitter) is reduced by setting a strong on-resistance.

[0270] If the detection result of the victim's edge detection signal EGn differs from the detection results of all the aggressor's signals EGn-1 and EGn+1, the input signals INn, INn-1, and INn+1 are operating on signal edges in different states. As a result, the output timing of the output signal OUTn becomes earlier due to the effect of crosstalk. In this case, the transmitter TXn sets the driver strength to a small value such as -1 to suppress the timing advance. This weakens the driver strength of the timing control unit 350. Consequently, the output timing of the output signal OUTn is delayed.

[0271] When the detection results of the edge detection signals EGn-1 and EGn+1 on the aggressor side do not change, the transmitter TXn sets the value of the driver strength to 0 (zero), assuming that there is no influence of crosstalk among the input signals INn, INn-1, and INn+1, and does not change the driver strength of the timing control unit 350.

[0272] When the detection result of the edge detection signal EGn-1 on a certain aggressor side is different from the detection result of the edge detection signal EGn+1 on another aggressor side, the transmitter TXn can set the driver strength according to the detection results of the edge detection signals EGn-1 and EGn+1 on the aggressor side with respect to the detection result of the edge detection signal EGn on the victim side, similar to the above formula (f1).

[0273] Also, when there is a difference in the magnitudes of the plurality of mutual inductances between the communication path of the victim and the communication paths of each aggressor, the driver strength of the timing control unit 350 may be determined using the coefficients set for each aggressor, similar to the above formula (f2).

[0274] (b) Operating example Hereinafter, an operating example of the transmitter TXn including the time adjustment unit 320 in the transmission circuit 11 of the present embodiment will be described.

[0275] In the transmitter TXn of FIG. 10, at time t, the input signal INn(t) is supplied to the transmitter TXn. The transmitter TXn receives the input signal INn(t).

[0276] The edge detection unit 330 receives the input signal INn(t) and the past input signal INn(t-1) from the flip-flop 300. The edge detection unit 330 detects the state of the signal edge of the input signal INn(t) based on the input signal INn(t) and the input signal INn(t-1). The edge detection unit 330 sends an edge detection signal EGn corresponding to the input signal INn to the timing control signal generation unit 340.

[0277] The timing control signal generation unit 340 receives edge detection signals EGn and edge detection signals EG(EGn-1, EGn+1, ...) from other transmitters TX. Based on the multiple edge detection signals EG, the timing control signal generation unit 340 generates a timing control signal TC including codes ENP and ENN. The timing control signal generation unit 340 sends the generated timing control signal TC to the timing control unit 350.

[0278] The timing control unit 350 receives the input signal INn and the timing control signal TC. The timing control unit 350 operates according to the driving force (operating speed) corresponding to the codes ENP and ENN of the timing control signal TC.

[0279] As a result, the input signal INn is sent to the driver unit 240 with a delay amount corresponding to the driving force of the timing control unit 350. However, depending on the state of the multiple edge detection signals EG, the delay amount may not be added to the input signal INn.

[0280] The driver unit 240 receives an input signal INn from the timing control unit 350, which operates according to the timing control signal TC. The driver unit 240 outputs a signal corresponding to the input signal INn (for example, an inverted signal of the input signal INn) as an output signal OUTn.

[0281] As described above, in the transmission circuit 11 of this embodiment, the transmitter TX outputs an output signal OUT that corresponds to the input signal IN.

[0282] (c) Summary In this embodiment, the transmitting circuit 11 adds a delay amount to the corresponding input signal INn, depending on the signal states of neighboring input signals INn-1 and INn+1. This adjusts the output timing of the output signal OUTn in accordance with the signal INn. As a result, the transmitting circuit 11 in this embodiment can suppress the effects of crosstalk.

[0283] Figure 16 is a diagram illustrating the effects of the transmission circuit 11 in this embodiment.

[0284] Figure 16(a) shows the waveform of a signal output from a typical transmitting circuit. Figure 16(b) shows the waveform of a signal output from the transmitting circuit 11 of this embodiment.

[0285] As shown in Figure 16(a), in a typical transmitting circuit, the difference between the phase of a signal delayed due to jitter and the phase of a signal that leads is represented by "Ja". As shown in Figure 16(b), in the transmitting circuit 11 of this embodiment, the difference between the phase of a signal delayed due to jitter and the phase of a signal that leads is represented by "Jb". The difference Jb is smaller than the difference Ja.

[0286] Thus, the transmission circuit 11 of this embodiment can reduce the effects of crosstalk such as jitter by adjusting the output timing of the output signal OUTn corresponding to the input signal INn, according to the state of multiple adjacent signals INn and INn-1 in the communication path.

[0287] As described above, the transmission circuit as a semiconductor circuit in this embodiment can have improved characteristics.

[0288] (5) Examples of application An example of the application of the semiconductor circuit of the embodiment will be described with reference to Figure 17.

[0289] The transmitting circuit 11, as a semiconductor circuit in this embodiment, can be applied, for example, to an interface circuit in a memory system.

[0290] As shown in Figure 17, a certain information and communication system includes a host 4 and a memory system 5. The memory system 5 performs data writing, data reading, and data erasure within the memory system 5 based on requests from the host 4. The internal configuration of the memory system 5 will be described later.

[0291] Host 4 can generate commands (hereinafter referred to as host commands) for requesting various processes and operations for the memory system 5. Host 4 can generate data corresponding to the host commands. The generated data includes information (such as addresses), parameters, and data to be written to the memory system 5 that are used for the processes and operations of the memory system 5.

[0292] Host 4 includes a processor 40, a RAM 41, an interface circuit 42, etc. Host 4 may further include a storage device (not shown) such as an HDD (Hard Disc Drive).

[0293] For example, Host 4 is a personal computer, a smartphone, a feature phone, a mobile terminal (e.g., a tablet terminal), a game device, an in-vehicle terminal, a router, a base station, etc.

[0294] The memory system 5 includes a memory controller 50 and a NAND flash memory (memory device) 60. For example, the memory system 500 is an SSD (Solid State Drive), a UFS (Universal Flash Storage) device, a memory card, or a USB (Universal Serial Bus) memory, etc. Instead of the NAND flash memory 60, other non-volatile or volatile memory devices may be used for the memory system 5.

[0295] Based on the requests from Host 4, the memory controller 50 commands the NAND flash memory 60 to perform various processes and operations such as data writing, data reading, and data erasing.

[0296] The memory controller 50 includes a processor 51, a RAM 52, a buffer memory 53, and interface circuits 54, 55.

[0297] The processor 51 can issue commands for various processes or operations on the NAND flash memory 60. For example, the processor 51 can generate commands (hereinafter also called controller commands) for the NAND flash memory 60.

[0298] RAM 52 functions as a workspace within the memory controller 50 for various processes and operations of the processor 51. RAM 52 temporarily stores programs and data used in various processes by the processor 51 (calculation results, data and parameters during calculations). RAM 52 may also be a memory area provided within the processor 51.

[0299] The buffer memory 53 temporarily stores data transferred between the memory controller 50 and the host 4, and data transferred between the memory controller 50 and the NAND flash memory 60.

[0300] The interface circuit (also called the host interface (host I / F) circuit) 54 performs communication (data transfer) between the host 4 and the memory controller 50 based on a certain interface standard. The interface standard (and communication protocol) of the interface circuit 54 is the same standard (or a standard compliant with) as the interface standard of the host 4's interface circuit.

[0301] The interface circuit (also called a memory interface (memory I / F) circuit) 55 communicates between the memory controller 50 and the NAND flash memory 60 based on the NAND interface standard. The interface circuit 55 communicates with the NAND flash memory 60, for example, using parallel transmission (parallel communication). The interface circuit 55 includes a transmit circuit 11 and a receive circuit 20 within the physical layer (PHY layer).

[0302] When the memory controller 50 commands the NAND flash memory 60 to perform an operation, the memory controller 50 sends a data set containing the command and address (hereinafter also referred to as a memory command set) to the NAND flash memory 60. Furthermore, when the memory controller 50 commands the NAND flash memory 60 to write data, the memory command set also includes the data to be written.

[0303] In addition to the above configuration, the memory controller 50 may include other configurations such as an ECC circuit (not shown) for detecting and correcting errors in the data.

[0304] NAND flash memory 60 is a non-volatile semiconductor memory device. NAND flash memory 60 can store data in a substantially non-volatile manner. Hereafter, NAND flash memory 60 will also be simply referred to as flash memory 60.

[0305] The flash memory 60 includes multiple memory chips 600 and a bridge chip 650.

[0306] Each memory chip 600 includes a memory cell array 601 and a CMOS circuit 602. The memory cell array 601 is a data storage area. The CMOS circuit 602 is a group of circuits for controlling various operations of the memory cell array 601. Data sent from the memory controller 50 is written to the memory cell array 601. Data requested from the memory controller 50 is read from the memory cell array 601. Multiple chip groups GR, each containing a predetermined number of memory chips 600, communicate with the bridge chip 650 via a corresponding channel Ch. Multiple memory chips 600 are accessed on a channel Ch basis.

[0307] The bridge chip 650 includes a device responsible for communication between the memory controller 50 and each flash memory 60. For example, the bridge chip 650 is a semiconductor chip independent of the memory controller 50 and the memory chips 600. The bridge chip 650 and the multiple memory chips 600 may be configured as a single package device. However, the bridge chip 650 may be provided as a separate package device from the memory chips 600.

[0308] The flash memory 60 communicates with the memory controller 50 via the bridge chip 650. Communication between the flash memory 60 and the memory controller 50 is supported by a NAND interface standard such as the toggle DDR standard or the ONFi standard. For example, the command latch enable signal CLE, address latch enable signal ALE, write enable signal WEN, read enable signal REn, ready busy signal RBn, and input / output signal DQ are used for communication between the flash memory 60 and the memory controller 50.

[0309] The command latch enable signal CLE indicates that the input / output signal DQ received by the flash memory 60 is a command. The address latch enable signal ALE indicates that the signal DQ received by the flash memory 60 is an address. The chip enable signal CEn sets the memory chip 600 to be accessed into an enabled state. The write enable signal WEn commands the flash memory 60 to accept input from the input / output signal DQ. The read enable signal REn commands the flash memory 60 to accept output from the input / output signal DQ. The ready busy signal RBn notifies the memory controller 50 from the flash memory 60 whether the flash memory 60 is ready to accept commands from the memory controller 50 or busy not to accept commands. The input / output signal DQ is, for example, an 8-bit wide signal set. The input / output signal DQ may include commands, addresses, data, etc.

[0310] The bridge chip 650 includes interface circuits 651 and 654, a control circuit 652, a buffer memory 653, and the like.

[0311] The interface circuit (bridge interface (bridge I / F) circuit) 651 communicates with the memory controller 50 via parallel transmission. The bridge interface circuit 651 transmits or receives signals CLE, ALE, CEn, WEn, REn, RBn, DQ, and DQS.

[0312] The control circuit 652 controls various operations within the bridge chip 650. For example, the control circuit 652 performs command queuing, command analysis and generation, command execution status verification, and control signal generation. For instance, the control circuit 652 generates a data strobe signal DQS in response to the read enable signal REn.

[0313] Buffer memory 653 temporarily stores data that is written to or read from memory chip 600.

[0314] The interface circuit (channel interface (channel I / F) circuit) 654 communicates with the corresponding chip group GR via channel Ch by parallel transmission. The channel interface circuit 654 sends commands, addresses, and data to the chip group GR. The channel interface circuit 654 receives data from the chip group GR. The channel interface circuit 654 sends various signals CLE, ALE, CEn, WEn, REn, RBn, and DQS to the chip group GR. The channel interface circuit 654 sends or receives input / output signals DQ to the chip group GR.

[0315] Furthermore, the bridge chip 650 may include a device configured to convert signals sent serially from the memory controller 50 into parallel transmissions within the flash memory 60.

[0316] The transmitting circuit 11 and transmitter TX, which are semiconductor circuits in this embodiment, are provided within the interface circuits 54 and 55 of the memory controller 50, and within the interface circuits 651 and 654 of the bridge chip 650.

[0317] In the interface circuits 54 and 55 of the memory controller 50, the transmitting circuit 11 includes the transmitter TX of this embodiment within the physical layer (PHY layer). In the interface circuits 651 and 654 of the bridge chip 650, the transmitting circuit 11 includes the transmitter TX of this embodiment within the physical layer. In the interface circuits 54, 55, 651, and 654, the receiving circuit 20 includes the receiver RX within the PHY layer.

[0318] For example, between the memory controller 50 and the flash memory 60, the transmitter TX and receiver RX are used for relatively high-speed data transfer of 3 Gbps or more.

[0319] The transmission circuit 11 and transmitter TX of this embodiment may also be applied to the interface circuit 42 of the host 4.

[0320] In the memory system 5 and NAND flash memory 60 of this application example, the transmission circuit 11 and transmitter TX of this embodiment can suppress the effects of crosstalk such as jitter. As a result, the transmission circuit 11 of this embodiment can improve the reliability of data transfer in the memory system 5.

[0321] The transmission circuit 11 and transmitter TX of this embodiment may be applied to systems (devices) other than memory systems. For example, the transmission circuit 11 and transmitter TX of this embodiment may be applied to wireless communication systems or computing systems including multiple processors.

[0322] (6) Others While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0323] 11: Transmitting circuit, TX, TXn: Transmitter, 210: Edge detection unit, 220: Signal generation unit, 240: Driver unit, 320: Time adjustment unit, 330: Edge detection unit, 340: Timing control signal generation unit, 350: Timing control unit, 5: Memory system, 60: NAND flash memory.

Claims

1. A detection unit that detects the first signal waveform of a first input signal on a first communication path, and the second signal waveform of a second input signal on a second communication path different from the first communication path, A signal generation unit generates a control signal based on the detected first and second signal waveforms, A first driver unit that outputs an output signal corresponding to the first input signal based on the driver strength based on the control signal, A semiconductor circuit comprising the following features.

2. When the first signal waveform is in a first changing state and the second signal waveform is in a constant state, the signal generation unit sets the driver strength of the control signal to the first driver strength. If the first signal waveform is in the first change state and the second signal waveform is in the first change state, the signal generation unit sets the driver strength of the control signal to a second driver strength that is higher than the first driver strength. If the first signal waveform is in the first change state and the second signal waveform is in a second change state different from the first change state, the signal generation unit sets the driver strength of the control signal to a third driver strength that is lower than the first driver strength. The semiconductor circuit according to claim 1.

3. The detection unit is A first logic gate that detects the first signal waveform in a first changing state based on the signal level of the first input signal at a first time and the signal level of the first input signal at a second time prior to the first time, A second logic gate that detects the second signal waveform of the first changed state based on the signal level of the second input signal at the first time and the signal level of the second input signal at the second time, A third logic gate detects the first signal waveform in a second change state that is different from the first change state, based on the signal level of the first input signal at the first time and the signal level of the first input signal at the second time. A fourth logic gate that detects the second signal waveform of the second changing state based on the signal level of the second input signal at the first time and the signal level of the second input signal at the second time, including, The semiconductor circuit according to claim 1.

4. The signal generation unit, A fifth logic gate that sets a first value of the control signal based on the first change state of the first signal waveform and the first change state of the second signal waveform, A sixth logic gate sets a second value of the control signal based on a second change state of the first signal waveform that is different from the first change state of the first signal waveform and the second change state of the second signal waveform, including, The semiconductor circuit according to claim 1.

5. A seventh logic gate that generates a first signal of the control signal based on the signal from the fifth logic gate and the first input signal, An eighth logic gate that generates a second signal of the control signal based on the signal from the sixth logic gate and the first input signal, The semiconductor circuit according to claim 4, further comprising the above.

6. A second driver unit controls the pull-up side of the first driver unit based on the first signal from the seventh logic gate, A third driver unit controls the pull-down side of the first driver unit based on the second signal from the eighth logic gate, The semiconductor circuit according to claim 5, further comprising:

7. The first driver unit described above is A first transistor of a first conductivity type, including a first gate that receives an inverted signal of the first input signal, a first end connected to a first voltage node, and a first other end connected to a first node that sends the output signal, A second transistor having a second conductivity type different from the first, including a second gate that receives the inverted signal of the first input signal, a second end connected to the first node, and a second other end connected to the second voltage node, including The semiconductor circuit according to claim 1.

8. The first driver unit described above is An inverter that receives an inverted signal of the first input signal, A buffer that receives the inverted signal of the first input signal, A first transistor of a first conductivity type, including a first gate connected to the output node of the inverter, a first end connected to a first voltage node, and a first other end connected to a first node that sends the output signal. A second transistor of the first conductivity type, comprising a second gate connected to the output node of the buffer, a second end connected to the first node, and a second other end connected to the second voltage node, including, The semiconductor circuit according to claim 1.

9. A memory cell array that stores data, An interface circuit including the semiconductor circuit of claim 1, A memory device equipped with the following features.

10. A memory device including a memory cell array for storing data, A memory controller comprising an interface circuit including the semiconductor circuit of claim 1, configured to control the operation of the memory device, A memory system that includes this.

11. A first detection unit that acquires a first detection signal indicating the detection result of the signal waveform of a first input signal on a first communication path, A signal generation unit generates a first control signal based on the first detection signal and a second detection signal indicating the detection result of the signal waveform of the second input signal on the second communication path, An adjustment unit adjusts the output timing of the first input signal based on the first control signal, A driver unit that outputs an output signal based on the first input signal from the adjustment unit, A semiconductor circuit comprising the following features.

12. The first detection unit is, A first logic gate that detects a first change state of the first input signal based on the signal level of the first input signal at a first time and the signal level of the first input signal at a second time prior to the first time, A second logic gate that detects a second change state of the first input signal that is different from the first change state of the first input signal, based on the signal level of the first input signal at the first time and the signal level of the first input signal at the second time, including, The semiconductor circuit according to claim 11.

13. The first logic gate includes a first AND gate having a first positive logic input node that receives the first input signal at a first time, and a second negative logic input node that receives the first input signal at a second time. The second logic gate includes a second AND gate having a third negative logic input node that receives the first input signal at the first time, and a fourth positive logic input node that receives the first input signal at the second time. The semiconductor circuit according to claim 12.

14. The adjustment unit is, An inverter that receives the first input signal, A first transistor comprising a first gate that receives a first code of the first control signal and a first end connected to a first voltage node, A second transistor comprising a second gate connected to the output node of the inverter, a second end connected to the other end of the first transistor, and the other end connected to the first node, A third transistor comprising a third gate connected to the output node of the inverter and a third end connected to the first node, A fourth transistor comprising a fourth gate that receives a second code of the first control signal, a fourth end connected to the third other end of the third transistor, and a fourth other end connected to a second voltage node, including, The semiconductor circuit according to claim 11.

15. The adjustment unit is, A fifth transistor comprising a fifth gate connected to the output node of the inverter, a fifth end connected to the first voltage node, and a fifth other end connected to the first node, A fifth transistor comprising a sixth gate connected to the output node of the inverter, a sixth end connected to the first node, and a sixth other end connected to the second voltage node, Further including, The semiconductor circuit according to claim 14.

16. A memory cell array that stores data, An interface circuit including the semiconductor circuit of claim 11, A memory device equipped with the following features.

17. A memory device including a memory cell array for storing data, A memory controller comprising an interface circuit including the semiconductor circuit of claim 11, configured to control the operation of the memory device, A memory system that includes this.

18. A first driver unit that receives a first input signal on a first communication path, A second driver unit that receives the first input signal via a first conversion unit, A third driver unit that receives a second input signal on a second communication path, A fourth driver unit that receives the second input signal via a second conversion unit, A calculation unit that calculates an output signal corresponding to the first input signal based on the signal from the first driver unit, the signal from the second driver unit, the signal from the third driver unit, and the signal from the fourth driver unit, A semiconductor circuit comprising the following features.

19. A fifth driver unit that receives a third input signal on a third communication path, A sixth driver unit that receives the third input signal via a fourth conversion unit, Furthermore, it is equipped with, The calculation unit, Based on the signals from the first driver unit, the second driver unit, the third driver unit, the fourth driver unit, the fifth driver unit, and the sixth driver unit, an output signal corresponding to the first input signal is calculated. The semiconductor circuit according to claim 18.

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