Manufacturing method of printed circuit boards

Abstract

The present invention provides a method for manufacturing printed circuit boards that can produce printed circuit boards equipped with conductor circuits having wiring widths that conform to the design specifications at a low cost. [Solution] The method includes forming a positive-type photoresist layer on an opening where a seed layer is formed and on a second resin insulating layer, placing a photomask between an exposure source and a positive-type photoresist, irradiating the positive-type photoresist with a second exposure light I1 and a second exposure light I2 generated from a first exposure light I0 generated from an exposure source, respectively to perform an exposure process, developing the material to form recesses for conductor layer formation, forming a second conductor circuit in the recesses for second conductor circuit formation, and forming a via conductor in the recesses for via hole formation, wherein the transmittance X, which is the ratio of the second exposure light I1 to the first exposure light I0, and the transmittance Y, which is the ratio of the second exposure light I2 for forming the recesses for second conductor circuit formation to the first exposure light I0, satisfy the following relation (1). TIFF2026056227000005.tif13150

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a printed wiring board. More specifically, by forming a plating resist using a positive photoresist and making the exposure amount of the via hole forming portion larger than the exposure amount of the conductor circuit forming portion, it relates to a method for manufacturing a printed wiring board capable of forming a conductor circuit having a wiring width as designed.

Background Art

[0002] A method for manufacturing a multilayer wiring board has been proposed in which a photosensitive organic polymer material is used for an interlayer insulating film and wiring is formed by a semi-additive method using a positive photoresist. In this method for manufacturing a multilayer wiring board, as the interlayer insulating layer made of a photosensitive organic polymer material becomes thicker, it becomes more difficult to form vertical vias. Therefore, in the method for manufacturing a multilayer wiring board, if multiple exposures are performed following the exposure of the wiring pattern, portions of the positive photoresist layer that are not irradiated with light will occur, and the photoresist layer will remain in these portions after development. As a result, electrolytic plating will not be deposited in the portions of the positive photoresist layer that were not irradiated with light, and the conductor layers between the layers cannot be connected.

[0003] From such a technical perspective, a method for manufacturing a multilayer wiring board has been proposed (Patent Document 1) that uses an organic polymer material capable of preventing the photoresist from remaining inside the via hole and improving the yield of interlayer connection as the interlayer insulating film. FIG. 3 is a cross-sectional view showing an embodiment of such a method for manufacturing a multilayer wiring board. This method for manufacturing a multilayer wiring board includes a step of exposing a wiring pattern using a photomask on a positive photoresist layer, and a step of exposing the via hole portion using a photomask having an exposure diameter larger than the designed diameter of the via hole.

[0004] Specifically, as shown in Figure 3(a), an insulating film 2 is formed on a substrate 1, and then a base conductive film 3a is formed on the surface of the insulating film 2. An electroplating film with a thickness of approximately 5 μm is deposited on the base conductive film 3a to form a conductor 6a. Next, an interlayer insulating film 7 made of a negative-type photosensitive organic polymer material is formed, and then a via hole pattern is exposed using a negative-type photomask. Subsequently, via holes 8a to 8d are formed by developing this.

[0005] As shown in Figure 3(b), a second underlay conductor film 3b was formed, and a positive-type photoresist layer 4 was formed on top of it. Then, the via holes and the wiring pattern of the second layer were exposed using a positive-type photomask for the second layer. Subsequently, the via holes 8a to 8d were exposed (multiple exposure) using a positive-type photomask 5d. After that, as shown in Figures 3(c) to (d), this was developed to obtain the wiring pattern of the second layer, and then a second conductor 6b was formed by depositing an electroplated film on the exposed underlay conductor film of the second layer. After that, the portions of the photoresist layer 4 and underlay conductor film 3b where the conductor 6b was not formed were removed to obtain a two-layer wiring substrate. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 08-125332 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, the technology disclosed in Patent Document 1 requires multiple exposure processing to form the plating resist. Specifically, the technology disclosed in Patent Document 1 requires a two-stage exposure process consisting of a first exposure process to form a conductive circuit on a positive-type photoresist layer and a second exposure process to form via conductors, which has the problem of reducing the production efficiency of multilayer wiring boards.

[0008] Furthermore, when exposure processing is performed to form a plating resist, a separate exposure mask is required for each exposure process for the positive-type photoresist layer. Therefore, in the technology disclosed in Patent Document 1, if multiple exposure processing is employed, a large number of exposure masks are required. As a result, the technology disclosed in Patent Document 1 has the problem that, in order to form a plating resist, an exposure mask required for the first exposure process and an exposure mask required for the second exposure process must be prepared for the positive-type photoresist layer, which increases the production cost of the multilayer wiring substrate.

[0009] Figures 4A and 4B are cross-sectional views illustrating the manufacturing process included in the technology disclosed in Patent Document 1. As shown in Figures 4A(a) to (c), in the technology disclosed in Patent Document 1, the via hole formation portion of the plating resist 10 is subjected to both exposure 1 for forming recesses for conductor circuit formation and exposure 2 for forming via conductors. A photomask 11 is used for exposure 1, and a photomask 12 is used for exposure 2. In this case, it is difficult to make the exposure position for forming the via hole recesses and the exposure position for forming the conductor circuit recesses coincide with exposure 1 and exposure 2.

[0010] As a result, a "shift" occurs between the exposure position for forming the recesses for via hole formation and the exposure position for forming the recesses for the conductor circuit, making it impossible to accurately form the spacing of the plating resist 10 corresponding to the design value of the wiring. That is, as shown in Figure 4B(d), the "shift" between the exposure position for forming the recesses for via hole formation and the exposure position for forming the recesses for the conductor circuit results in an increase in the spacing formed between adjacent plating resists 15, or a decrease in the spacing formed between adjacent plating resists 13. Furthermore, a via hole formation portion 14 that differs from the design value is formed.

[0011] In other words, the technology disclosed in Patent Document 1 has the problem that, due to the misalignment of the exposure positions of the two, it is not possible to form a conductor circuit having a wiring width corresponding to the width between the plating resists as designed. Furthermore, the recess for forming via holes has a certain depth. If the exposure amount is increased in order to eliminate the remaining plating resist inside the recess for forming via holes, a phenomenon occurs in which the exposed light diffuses horizontally due to reflection from the seed layer and diffraction of the exposed light after passing through the photomask. As the exposed light diffuses horizontally, more plating resist is removed than the designed value.

[0012] From this technical standpoint, the present invention aims to provide a method for manufacturing printed circuit boards that can produce printed circuit boards equipped with conductor circuits having wiring widths as specified in the design, at low cost and with high productivity. [Means for solving the problem]

[0013] The method for manufacturing a printed circuit board according to the present invention involves preparing a first resin insulating layer, Forming a first conductor circuit on the first resin insulating layer, A second resin insulating layer is formed on the first resin insulating layer and on the first conductor circuit, To form an opening in the second resin insulating layer that reaches the first conductor circuit, Forming a seed layer on the aforementioned opening and the second resin insulating layer, A positive-type photoresist layer is formed on the opening where the seed layer is formed and on the second resin insulating layer. The photomask is placed between the exposure source and the positive-type photoresist, The positive-type photoresist is exposed by irradiating it with a second exposure light I1 for forming via hole formation recesses that are generated after the first exposure light I0 generated from the exposure source has passed through the photomask, and a second exposure light I2 for forming a second conductor circuit recess, respectively. Forming the recesses for the second conductor circuit and the recesses for via holes by developing the positive photoresist layer after the exposure process; Forming a second conductor circuit in the recesses for the second conductor circuit and forming via conductors for connecting the first conductor circuit and the second conductor circuit in the recesses for via holes; The transmittance X, which is the ratio of the second exposure light I1 for forming the recesses for via holes with respect to the first exposure light I0, and the transmittance Y, which is the ratio of the second exposure light I2 for forming the recesses for the second conductor circuit with respect to the first exposure light I0, satisfy the following relational expression (1).

Equation

Brief Description of the Drawings

[0014] [Figure 1] It is a top view for explaining an embodiment of a printed wiring board manufactured by the method for manufacturing a printed wiring board according to the present invention. [Figure 2A] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2B] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2C] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2D] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2E] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2F] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2G] It is a cross-sectional view for explaining an embodiment of the method for manufacturing a printed wiring board according to the present invention. [Figure 2H]It is a cross-sectional view for explaining an embodiment of a method for manufacturing a printed wiring board according to the present invention. [Figure 2I] It is a cross-sectional view for explaining an embodiment of a method for manufacturing a printed wiring board according to the present invention. [Figure 2J] It is a cross-sectional view for explaining an embodiment of a method for manufacturing a printed wiring board according to the present invention. [Figure 3] It is a cross-sectional view for explaining a manufacturing process included in a conventional method for manufacturing a multilayer wiring board. [Figure 4A] It is a cross-sectional view for explaining a manufacturing process included in a conventional method for manufacturing a multilayer wiring board. [Figure 4B] It is a cross-sectional view for explaining a manufacturing process included in a conventional method for manufacturing a multilayer wiring board.

Embodiments for Carrying Out the Invention

[0015] <Regarding the Printed Wiring Board> An embodiment of a method for manufacturing a printed wiring board according to the present invention will be described with reference to the drawings. In the examples shown in FIGS. 1 to 2, for better understanding of the features of the present invention, the dimensions of each member, particularly the dimensions in the height direction, are described with dimensions different from the actual dimensions.

[0016] FIG. 1 is a schematic diagram for explaining an embodiment of a printed wiring board manufactured by a method for manufacturing a printed wiring board according to the present invention. As shown in FIG. 1, a printed wiring board 100 manufactured by the method for manufacturing a printed wiring board according to the present invention includes a conductor circuit 102 and a resin insulating layer 101. The conductor circuit 102 included in the printed wiring board 100 is formed on the insulating layer surface of the resin insulating layer 101. Note that, in addition to the conductor circuit 102, a ground layer (not shown) may be formed on the resin insulating layer 101. The ground layer may be formed along the conductor circuit 102 and is formed so as not to be electrically connected to the conductor circuit 102.

[0017] The printed circuit board 100 may be a core-type printed circuit board in which conductive circuits 102 and resin insulating layers 101 are alternately laminated on one or both sides of a core substrate (not shown). When conductive circuits 102 are formed on both sides of the core substrate, opposing conductive circuits 100 may be connected to each other via through-hole conductors (not shown) across the core substrate. Alternatively, the printed circuit board 100 may be a coreless printed circuit board obtained by alternately laminating conductive circuits 102 and resin insulating layers 101 on a support plate (not shown) instead of a core substrate, and then removing the support plate.

[0018] In the printed circuit board 100, multiple other conductor circuits 102 and resin insulating layers 101 may be alternately arranged on top of the resin insulating layer 101. That is, the printed circuit board 100 may be a multilayer printed circuit board. Specifically, the printed circuit board 100 may be a multilayer printed circuit board comprising a first conductor circuit 102A formed on the insulating layer surface of a first resin insulating layer 101A which is a resin insulating layer 101, and a second conductor circuit 102B formed on the insulating layer surface of a second resin insulating layer 101B which covers the first resin insulating layer 101A and the first conductor circuit 102A.

[0019] In such a printed circuit board 100, the first conductor circuit 102A and the second conductor circuit 102B, which are two conductor circuits 102 formed with a second resin insulating layer 101B in between, are electrically connected via a via conductor 103. The via conductor 103 is formed in an opening 104 of the second resin insulating layer 101B formed on the upper surface of the first conductor circuit 102A. Furthermore, a solder resist layer (not shown) may be formed on the outermost layer of the printed circuit board 100. Solder resist openings (not shown) are formed in the solder resist layer that reach the upper surface of the second conductor circuit 102B located on the outermost layer, and solder bumps may be formed on the upper surface of the second conductor circuit 102B that is exposed at the bottom of the solder resist openings and located on the outermost layer.

[0020] The first resin insulating layer 101A and the second resin insulating layer 101B can be made of, for example, a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin. The first conductor circuit 102A formed on the first resin insulating layer 101A and the first conductor circuit 102B formed on the second resin insulating layer 101B may be composed of an electrolytic copper plating layer formed by, for example, a well-known semi-additive method.

[0021] The printed circuit board 100 manufactured by the printing circuit board manufacturing method according to the present invention has a technical feature in that the wiring width constituting the conductor circuit 102 and via conductor 103 formed on the insulating layer surface of the resin insulating layer 101 matches the wiring width of the design value. In other words, the wiring width constituting the conductor circuit 102 and via conductor 103 in the printed circuit board 100 manufactured by the printing circuit board manufacturing method according to the present invention is formed without any "deviation" from the wiring width of the design value. Here, in order to make the wiring widths that constitute the conductor circuit 102 and via conductor 103 of the printed circuit board 100 match the design value wiring width, the width between the plating resists, which are made up of multiple plating resists necessary to form the conductor circuit 102 and via conductor 103, is made to match the design value wiring widths that constitute the conductor circuit 102 and via conductor 103.

[0022] From this technical standpoint, the printed circuit board 100 manufactured by the printing circuit board manufacturing method according to the present invention is manufactured without employing multiple exposures, by setting the intensity of the exposure light for forming recesses for via hole formation in a single exposure process to be greater than the intensity of the exposure light for forming recesses for conductor circuit formation. In this way, by adjusting the intensity of the exposure light, the printed circuit board 100 has the wiring width of the second conductor circuit 102B and via conductor 103 as designed, by matching the spacing formed in adjacent plating resists to the line width of the wiring constituting the second conductor circuit 102B and via conductor 103.

[0023] <Regarding the manufacturing method of printed circuit boards according to the present invention> Figures 2A to 2J are diagrams illustrating one embodiment of the method for manufacturing a printed circuit board according to the present invention. Hereinafter, one embodiment of the method for manufacturing a printed circuit board according to the present invention will be described in order using Figures 2A to 2J.

[0024] Next, as shown in Figure 2A, a first resin insulating layer 101A on which the first conductor circuit 102A is formed is prepared. As mentioned above, the first resin insulating layer 101A may be a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin, and more specifically, it may be an electrical insulating material in which glass cloth is impregnated with an epoxy resin, a thermosetting resin such as bismaleimide triazine resin. The first conductor circuit 102A may be composed of an electrolytic copper plating layer formed by, for example, a well-known semi-additive method.

[0025] Next, as shown in Figure 2B, a second resin insulating layer 101B is prepared. The second resin insulating layer 101B is formed on the insulating layer surface of the first resin insulating layer 101A and the conductor circuit surface of the first conductor circuit 102A, so as to cover the insulating layer surface of the first resin insulating layer 101A and the first conductor circuit 102A. The second resin insulating layer 101B may be a resin composition containing an inorganic filler such as silica or alumina and an epoxy resin, similar to the first resin insulating layer 101A.

[0026] Next, as shown in Figure 2C, an opening 104 is formed in the second resin insulating layer 101B that reaches the first conductor circuit 102A. The opening 104 is formed by laser treatment and exposure development treatment on the cured second resin insulating layer 101B. Furthermore, the resin residue generated by forming the opening 104 may be removed by desmear treatment, or plasma treatment or the like may be applied after desmear treatment. Examples of lasers used for laser treatment include carbon dioxide lasers, ultraviolet lasers, and excimer lasers.

[0027] Next, as shown in Figure 2D, an electroless copper plating layer is formed as a seed layer 105 on the second resin insulating layer 101B in which the opening 104 is formed and on the exposed surface of the second resin insulating layer 101B. The thickness of the electroless copper plating film formed on the surface of the second resin insulating layer 101B is preferably 0.1 to 0.5 μm.

[0028] Furthermore, as shown in Figure 2E, a positive-type photoresist layer 106 is formed on the opening 104 where the seed layer 105 is formed and on the second resin insulating layer 101B. The positive-type photoresist layer 106 is composed of a polymer, a photosensitive agent, a crosslinking agent, a solvent, etc. The polymer forms the main matrix of the resist in the positive-type photoresist layer 106. The polymer may be a polyhydrostyrene-based novolac resin, a polyacrylic-based novolac resin, or a polyhydrostyrene-polyacrylic-based novolac resin.

[0029] Next, as shown in Figure 2F, a photomask 107 is placed between the exposure source (not shown) and the positive-type photoresist 106, and exposure processing is performed from the exposure source onto the positive-type photoresist layer 106. The photomask 107 may be composed of a glass mask, emulsion mask, film mask, etc. The substrate used for the photomask 107 may be composed of soda lime (SL), quartz (Qz), or polyethylene terephthalate (PET). The form of the photomask 107 can be appropriately selected according to the form of the conductor circuit 102 of the printed circuit board 100.

[0030] Furthermore, the photomask 107 may consist of a single mask or multiple masks. For example, the photomask 107 may consist of two photomasks 107, namely photomask 107R and photomask 107L. That is, two masks, namely photomask 107L and photomask 107R, may be arranged horizontally in parallel between the exposure source and the positive-type photoresist layer 106.

[0031] The exposure process on the positive-type photoresist 106 uses a first exposure light I0 irradiated from an exposure source, and the second exposure light I1 and second exposure light I2, which are generated when the first exposure light I0 passes through the photomask 107 and branches off. The first exposure light I0 irradiated from the exposure source can be appropriately selected in relation to the positive resist layer 106. The first exposure light I0 may be, for example, a semiconductor laser, a metal halide lamp, a high-pressure mercury lamp (ultraviolet g-ray, ultraviolet h-ray, ultraviolet i-ray, broad-ray), an excimer laser (KrF, ArF, F2), extreme ultraviolet (EUV), an electron beam, far ultraviolet (DUV), extreme ultraviolet, or a direct image (DI). From a technical standpoint, such as being able to form fine wiring, it is preferable to use an excimer laser (KrF, ArF, F2) as the first exposure light I0.

[0032] The exposure apparatus used for exposure processing of the positive-type photoresist layer 106 is not particularly limited, and can be used with exposure sources such as a direct image (DI) exposure apparatus, contact exposure apparatus, proximity exposure apparatus, projection exposure apparatus, stepper exposure apparatus, scanner exposure apparatus, or maskless exposure apparatus. Among these exposure sources, a direct image (DI) exposure apparatus is preferred from the viewpoint of being able to perform exposure fully automatically, quickly, and at low cost.

[0033] The photomask 107 is formed such that a second exposure light I1 is generated from the first exposure light I0 irradiated from the exposure source to irradiate the surface region R1 of the positive-type photoresist layer 106, which is the position where the via hole formation recess 181 is formed. Furthermore, the photomask 107 is formed such that a second exposure light I2 is generated from the first exposure light I0 irradiated from the exposure source to irradiate the surface region R2 of the positive-type photoresist layer 106, which is the position where the recess 182 for forming the second conductor circuit is formed.

[0034] Here, the depth D1 of the via hole formation recess 181 is deeper than the depth D2 of the second conductor circuit formation recess 182. For this reason, the intensity of the second exposure light I1 in the surface region R1 of the positive photoresist layer 106 where the via hole formation recess 181 is formed must be greater than the intensity of the second exposure light I2 in the surface region R2 of the positive photoresist layer 106 where the second conductor circuit formation recess 182 is formed.

[0035] In other words, the transmittance X(I1 / I0), which is the ratio of the second exposure light I1 for forming the via hole recess 181 to the first exposure light I0 generated from the exposure source, and the transmittance Y(I2 / I0), which is the ratio of the second exposure light I2 for forming the second conductor circuit recess 182 to the first exposure light I0, must satisfy the following relationship (1).

number

[0036] In other words, in the method for manufacturing a printed circuit board according to the present invention, by setting the transmittance X(I1 / I0), which is the ratio of the second exposure light I1 for forming the via hole recess 181 to the first exposure light I0, and the transmittance Y(I2 / I0), which is the ratio of the second exposure light I2 for forming the second conductor circuit recess 182 to the first exposure light I0, to be different, a difference can be provided between the amount of exposure for forming the via hole recess 181 and the amount of exposure for forming the second conductor circuit recess 182.

[0037] The photomask 107 may be configured as follows in order to set the transmittance X(I1 / I0), which is the ratio of the second exposure light I1 to the first exposure light I0, and the transmittance Y(I2 / I0), which is the ratio of the second exposure light I2 to the first exposure light I0, to be different. For example, the photomask 107 may consist of a photomask member 107a having a transmittance X that generates the second exposure light I1 for forming the via hole recess 181 from the first exposure light I0, a photomask member 107b having a transmittance Y that generates the second exposure light I2 for forming the second conductor circuit recess 182 from the first exposure light I0, and a photomask member 107c that does not transmit the first exposure light I0.

[0038] The first exposure light I0 that passes through the photomask member 107a having transmittance X irradiates the surface region R1 of the positive-type photoresist layer 106, where the via hole formation recess 181 is formed, as the second exposure light I1. On the other hand, the first exposure light I0 that passes through the photomask member 107b having transmittance Y irradiates the surface region R2 of the positive-type photoresist layer 106, where the second conductor circuit formation recess 182 is formed, as the second exposure light I2.

[0039] The method for manufacturing a printed circuit board according to the present invention sets the transmittance X(I1 / I0), which is the ratio of the second exposure light I1 for forming the via hole recess 181 to the first exposure light I0 generated from the exposure source, and the transmittance Y(I2 / I0), which is the ratio of the second exposure light I2 for forming the second conductor circuit recess 182 to the first exposure light I0, to satisfy the above relation (1).

[0040] As a result, the method for manufacturing a printed circuit board according to the present invention does not employ multiple exposures for the positive-type photoresist layer 106, but by creating a difference in transmittance, it is possible to selectively irradiate the surface region R1 of the positive-type photoresist layer 106 where the via hole formation recess 181 is formed and the surface region R2 of the positive-type photoresist layer 106 where the second conductor circuit formation recess 182 is formed simultaneously in a single exposure treatment.

[0041] Furthermore, by passing the first exposure light I0 generated from the exposure source through the photomask 107, the second exposure light I1 is branched and the exposure process on the positive-type photoresist layer 106 is continued. As a result, the second exposure light I1 is irradiated in the depth direction of the positive-type photoresist layer 106 in the surface region R1 of the positive-type photoresist layer 106. Similarly, by continuing the exposure process on the positive-type photoresist layer 106, the second exposure light I2 is irradiated in the depth direction of the positive-type photoresist layer 106 in the surface region R2 of the positive-type photoresist layer 106.

[0042] Of the positive-type photoresist layer 106, the recesses 181 for via hole formation in the positive-type photoresist layer 106 that have been exposed by the second exposure light I1 generated by passing through the photomask 107, and the recesses 182 for second conductor circuit formation in the positive-type photoresist layer 106 that have been exposed by the second exposure light I2, are dissolved and removed by going through the development process described later. On the other hand, the other parts of the positive-type photoresist layer 106 that have not been exposed remain without dissolving. Thus, in the method for manufacturing a printed circuit board according to the present invention, the exposure treatment of the positive-type photoresist layer 106 is a process to remove the soluble regions necessary for forming the via hole formation recesses 181 and the second conductor circuit formation recesses 182 formed in the positive-type photoresist 106, and to form a patterned positive-type photoresist layer 106 composed of the remaining positive-type resist 106.

[0043] Furthermore, the method for manufacturing a printed circuit board according to the present invention allows for the formation of via hole formation recesses 181 in a single exposure treatment by creating a difference in transmittance, without employing multiple exposures on the positive-type photoresist layer 106. Therefore, unlike conventional methods for manufacturing multilayer wiring boards, the positive-type photoresist layer 106 is not subjected to multiple exposure treatment, resulting in the accurate formation of via hole formation recesses 181 and second conductor circuit formation recesses 182, and having a form that does not deviate from the wiring width of the design value.

[0044] Furthermore, in the exposure process for the positive-type photoresist layer 106, it is necessary to set the intensity of the second exposure light I1 in the surface region R1 of the positive-type photoresist layer 106, where the via hole formation recess 181 is formed, to be greater than the intensity of the second exposure light I2 in the surface region R2 of the positive-type photoresist layer 106, where the second conductor circuit formation recess 182 is formed, thereby creating a difference. From this technical standpoint, in the exposure process for the positive-type photoresist layer 106, the ratio of the amount of exposure to the positive-type photoresist layer 106 by the second exposure light I2 for forming the via hole formation recess 181 to the amount of exposure to the positive-type photoresist layer 106 by the second exposure light I2 for forming the second conductor circuit formation recess 182 is preferably 2 to 10.

[0045] Even when DI exposure light is used as the first exposure light I0 generated from the exposure source, the ratio of the amount of exposure to the positive-type photoresist layer 106 by the second exposure light I1 for forming the via-hole-forming recess 181 to the amount of exposure to the positive-type photoresist layer 106 by the second exposure light I2 for forming the second conductor circuit-forming recess 182 is preferably 2 to 10, and more preferably 3 to 5.

[0046] Furthermore, in the exposure process for the positive-type photoresist layer 106, the exposure amount to the positive-type photoresist layer 106 by the second exposure light I1 for forming the via hole recess 181 is 200 to 1000 mJ / cm². 2It is preferable that this is the case. Furthermore, in the exposure process of the positive-type photoresist layer 106, the amount of exposure to the positive-type photoresist layer 106 by the second exposure light I2 for forming the recess 182 for forming the second conductor circuit is 100 to 500 mJ / cm². 2 It is preferable that this be the case.

[0047] Next, as shown in Figure 2G, the positive-type photoresist layer 106 after exposure treatment is developed to form the recess 182 for forming the second conductor circuit and the recess 181 for forming the via hole. That is, the positive-type photoresist layer 106 after exposure treatment is subjected to development treatment. In other words, the development treatment dissolves the exposed portion of the positive-type photoresist layer 106 that has been exposed using a developer solution, exposing the surface of the seed layer 105. On the other hand, the development treatment leaves the unexposed portion of the positive-type photoresist layer 106 that has not been exposed intact without dissolving it. Furthermore, the developing solution is preferably an alkaline aqueous solution with a pH of 12 to 13, such as tetramethylammonium hydroxide or sodium hydroxide aqueous solution.

[0048] The development process can employ any method that dissolves the exposed portion of the positive-type photoresist layer 106 using a developer and washes away any remaining developer. Dip development, paddle development, spray development, etc., may be used as the development process. The development apparatus (not shown) that can be used for the development process only needs to be capable of dropping the developer onto the positive-type resist 106, dissolving the positive-type resist 106, and washing away any remaining developer.

[0049] After development, the remaining positive-type photoresist 106 forms patterned positive-type photoresist layers 161, 162, 163, and 164. Then, between adjacent positive-type photoresist layers 160, recesses 108 for forming conductor circuits are formed to create a second conductor circuit 102B and a via conductor 103.

[0050] Specifically, the conductor circuit forming recess 108 formed between the positive-type photoresist layer 161 and the positive-type photoresist layer 162 is a second conductor circuit forming recess 182 for forming the second conductor circuit 102B, the conductor circuit forming recess 108 formed between the positive-type photoresist layer 162 and the positive-type photoresist layer 163 is a via hole forming recess 181 for forming a via conductor 103 for connecting the first conductor circuit 102A and the second conductor circuit 102B, and the conductor circuit forming recess 108 formed between the positive-type photoresist layer 163 and the positive-type photoresist layer 164 is a second conductor circuit forming recess 182 for forming the second conductor circuit 102B.

[0051] Next, as shown in Figure 2H, an electrolytic copper plating layer 109 is formed in the following order from left to right, on the multiple recesses 108 for forming conductor circuits, which are formed by multiple photoresist layers 161 to 164 formed on the seed layer 105: a second recess for forming a conductor circuit 182, a via hole forming recess 181, and the other second recess for forming a conductor circuit 182. The thickness of the electrolytic copper plating layer 109 formed in these conductor layer formation recesses 108 is preferably 5 to 50 μm. Here, a direct current is used to deposit the electrolytic copper plating layer constituting the second conductor circuit 102B and the via conductor 103. The current density of the direct current applied to form the electrolytic copper plating layer 109 is 1.0 to 10.0 A / dm 2 It is preferable that this is the case. The time for applying the DC current used to deposit the electrolytic copper plating layer 109 is sufficient to form the predetermined thickness of the second conductor circuit 102B and the via conductor 103, and can be appropriately set depending on the required form of the electrolytic copper plating layer 109.

[0052] Next, as shown in Figure 2I, the positive-type photoresist layers 161 to 164 are removed from the surface of the seed layer 105, for example, using a subtractive method. By removing the photoresist layers 161 to 164 from the surface of the seed layer 105, the seed layer surface of the seed layer 105, which was located at the bottom of the positive-type photoresist layers 161 to 164, is exposed, and the electrolytic copper plating layer 109, which constitutes the second conductor circuit 102B and the via conductor 103, is exposed from the seed layer surface of the seed layer 105. Furthermore, the removal of the positive-type photoresist layers 161 to 164 can be carried out, for example, using an alkaline aqueous solution.

[0053] Finally, as shown in Figure 2J, the second conductor circuit 102B and via conductor 103 are formed on the second resin insulating layer 101B by removing the seed layer 105 located at the bottom of the positive-type photoresists 161 to 164. The seed layer 105 can be removed by etching using an etching solution. Alternatively, the substrate on which the second conductor circuit 102B and via conductor 103 are formed on the second resin insulating layer 101B may be immersed in a dilute sulfuric acid aqueous solution for 10 seconds, rinsed with water, and then dried by air cutting.

[0054] Thus, a printed circuit board 100 is manufactured in which a first conductor circuit 102A is formed on a first resin insulating layer 101A, a second conductor circuit 102B is formed on a second resin insulating layer 101B covering the first resin insulating layer 101A, and a via conductor 103 for connecting the first conductor circuit 102A and the second conductor circuit 102B is formed. A solder resist layer (not shown) may also be formed on the second resin insulating layer 101B, covering the second conductor circuit 102B and the via conductor 103.

[0055] The solder resist layer may be formed by applying a commercially available solder resist composition to the upper surface of the uppermost second resin insulating layer 101B, the second conductor circuit 102B, and the via conductor 103 to a predetermined thickness, and then drying the solder resist composition. Furthermore, solder resist openings may be formed in the solder resist layer, and then solder bumps may be formed in the solder resist openings to complete the printed circuit board 100.

[0056] Thus, according to the method for manufacturing printed circuit boards of the present invention, by achieving a single exposure process by creating a difference in transmittance, without employing multiple exposures for the positive-type photoresist layer 106, it is possible to form via hole formation recesses 181 and second conductor circuit formation recesses 182 having the wiring width specified by the design value. As a result, the method for manufacturing printed circuit boards of the present invention can manufacture printed circuit boards equipped with conductor circuits having the wiring width specified by the design value at low cost and with high productivity. [Explanation of Symbols]

[0057] 100 Printed Wiring Boards 101 Resin insulating layer 101A First resin insulating layer 101B Second resin insulating layer 102 Conductor Circuit 102A First Conductor Circuit 102B Second Conductor Circuit 103 via conductor 104 Opening 105 Seed Layer 106 Positive-type photoresist layer 161 Positive-type photoresist 162 Positive-type photoresist 163 Positive-type photoresist 164 Positive-type photoresist 107 Photomasks 107R Photomask (Right side) 107L Photomask (left side) 107a Photomask component (transmittance X) 107b Photomask component (transmittance Y) 107c Photomask material (opaque) 108 Recess for forming conductor layer 181 Recess for via hole formation 182 Recess for forming the second conductor circuit 109 Electrolytic copper plating layer

Claims

1. To prepare the first resin insulating layer, Forming a first conductor circuit on the first resin insulating layer, A second resin insulating layer is formed on the first resin insulating layer and on the first conductor circuit, To form an opening in the second resin insulating layer that reaches the first conductor circuit, Forming a seed layer on the aforementioned opening and the aforementioned second resin insulating layer, A positive-type photoresist layer is formed on the opening where the seed layer is formed and on the second resin insulating layer. A photomask is placed between the exposure source and the positive-type photoresist layer, First exposure light I generated from the exposure source ０ A second exposure light I is used to form a recess for via hole formation that occurs after the photomask has been transmitted. １ And, a second exposure light I for forming a recess for forming a second conductor circuit ２ By irradiating the positive-type photoresist layer with and respectively, the positive-type photoresist layer is exposed. The positive-type photoresist layer after the exposure treatment is developed to form the recess for forming the second conductor circuit and the recess for forming the via hole, This includes forming a second conductor circuit in the recess for forming the second conductor circuit, and forming a via conductor in the recess for forming the via hole to connect the first conductor circuit and the second conductor circuit, The first exposure light I ０ The second exposure light I for forming a recess for via hole formation １ The ratio of transmittance X to the first exposure light I ０ Second exposure light I for forming the recess for forming the second conductor circuit ２ A method for manufacturing a printed circuit board, wherein the transmittance Y, which is the ratio of to the following, satisfies the following relation (1). [Math 1]

2. The second exposure light I ２ The ratio of the exposure amount of the second exposure light I to the exposure amount of the positive photoresist layer by １ The manufacturing method of the printed wiring board according to claim 1, wherein the ratio of the exposure amount of the positive photoresist layer by the second exposure light I is 2 to 10.

3. The second exposure light I １ The exposure amount to the positive-type photoresist layer is 200 to 1000 mJ / cm². ２ The method for manufacturing a printed circuit board according to claim 1.

4. The second exposure light I ２ The exposure amount to the positive-type photoresist layer is 100 to 500 mJ / cm². ２ The method for manufacturing a printed circuit board according to claim 1.

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