Memory device

Abstract

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer between the first conductive layer and the second conductive layer; a switching layer between the first conductive layer and the third conductive layer, comprising a first portion, a second portion, and a third portion; and a resistive switching layer between the third conductive layer and the second conductive layer. The switching layer comprises a first element and an oxide, nitride, or oxynitride of the second element, or the switching layer comprises a first element and a third element. The first element is at least one element selected from the group consisting of Te, Se, S, Sb, and As. The second element is at least one element selected from the group consisting of Zr, Al, Hf, Y, Ta, La, Ce, Mg, Si, and Ti. The third element is at least one element selected from the group consisting of Zn, Sn, Ga, In, Bi, and Mg. The lengths of the first, second, and third parts are different.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] As a large-capacity non-volatile memory device, there is a two-terminal cross-point memory device. The two-terminal cross-point memory device is easy to miniaturize and highly integrate memory cells.

[0003] A memory cell of the two-terminal cross-point memory device has, for example, a resistive change element and a switching element. By having a switching element in the memory cell, the current flowing through memory cells other than the selected memory cell is suppressed.

[0004] The switching element is required to have excellent characteristics such as a low leakage current, a high on-current, and high reliability.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a memory device having a switching element with excellent characteristics.

Means for Solving the Problems

[0007] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer, comprising a second portion in contact with the first conductive layer, a third portion in contact with the third conductive layer, and a first portion between the second portion and the third portion; and a resistive switching layer provided between the third conductive layer and the second conductive layer, wherein the switching layer comprises a first element and an oxide, nitride, or oxynitride of the second element, or the switching layer comprises the first element and the third element, and the first element is tellurium (Te), selenium (Se), sulfur (S), antimony (S) b) At least one element selected from the group consisting of and arsenic (As), wherein the second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti), and the third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg). In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in the second direction and the third length of the third portion in the second direction. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram of the storage device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 3] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 4]A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 5] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 6] A diagram illustrating the problems of the storage device according to the first embodiment. [Figure 7] A diagram illustrating the current-voltage characteristics of the switching element according to the first embodiment. [Figure 8] Schematic cross-sectional view of the memory cell of the comparative example storage device. [Figure 9] A schematic cross-sectional view of a memory cell of a first modified memory device according to the first embodiment. [Figure 10] A schematic cross-sectional view of a memory cell of a second modified memory device according to the first embodiment. [Figure 11] A schematic cross-sectional view of a memory cell of a third modified memory device according to the first embodiment. [Figure 12] A schematic cross-sectional view of a memory cell of a memory device in a fourth modified example of the first embodiment. [Figure 13] A schematic cross-sectional view of a memory cell of a memory device of a fifth modified example of the first embodiment. [Figure 14] A schematic cross-sectional view of a memory cell of a memory device of a sixth modified example of the first embodiment. [Figure 15] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 16] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 17] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 18] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 19] A schematic cross-sectional view of a memory cell of the third embodiment of the storage device. [Figure 20] A schematic cross-sectional view of the memory cell of the fourth embodiment of the storage device. [Figure 21] A schematic cross-sectional view of the memory cell of the fifth embodiment of the storage device. [Figure 22] A diagram illustrating the current-voltage characteristics of the memory element according to the fifth embodiment. [Figure 23] Explanatory drawing of the first operation example of the memory operation of the memory device according to the fifth embodiment. [Figure 24] Explanatory drawing of the second operation example of the memory operation of the memory device according to the fifth embodiment. [Figure 25] Explanatory drawing of the current-voltage characteristics of the memory element according to the first modification of the fifth embodiment. [Figure 26] Explanatory drawing of the third operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. [Figure 27] Explanatory drawing of the fourth operation example of the memory operation of the memory device according to the first modification of the fifth embodiment. [Figure 28] Explanatory drawing of the current-voltage characteristics of the memory element according to the second modification of the fifth embodiment. [Figure 29] Explanatory drawing of the fifth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. [Figure 30] Explanatory drawing of the sixth operation example of the memory operation of the memory device according to the second modification of the fifth embodiment. [Figure 31] Explanatory drawing of the current-voltage characteristics of the memory element according to the third modification of the fifth embodiment. [Figure 32] Explanatory drawing of the seventh operation example of the memory operation of the memory device according to the third modification of the fifth embodiment. [Figure 33] Explanatory drawing of the eighth operation example of the memory operation of the memory device according to the third modification of the fifth embodiment. [Figure 34] Schematic cross-sectional view of the memory cell of the memory device according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described while referring to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] Qualitative and quantitative analyses of the chemical composition constituting the memory device described herein can be performed, for example, by Rutherford backscattering spectroscopy (RBS), secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS). Furthermore, a transmission electron microscope (TEM) can be used, for example, to measure the thickness of the components constituting the memory device, the distance between components, etc. Furthermore, to identify the constituent materials of the components that make up the memory device, measure their relative abundance, bonding state, local structure (interatomic distance, coordination number), and chemical state, it is possible to use methods such as X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), or EELS.

[0011] (First embodiment) The memory device of the first embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first and second conductive layers; a switching layer provided between the first and third conductive layers and including a second portion in contact with the first conductive layer, a third portion in contact with the third conductive layer, and a first portion between the second and third portions; and a resistive switching layer provided between the third and second conductive layers. The switching layer includes a first element and an oxide, nitride, or oxynitride of the second element, or the switching layer includes a first element and a third element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg). In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in a second direction and the third length of the third portion in a second direction.

[0012] Furthermore, the storage device of the first embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0013] Figure 1 is a block diagram of the storage device according to the first embodiment.

[0014] The memory cell array 100 of the first embodiment of the memory device includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102, separated by an insulating layer on a semiconductor substrate 101. The bit lines 103 are provided, for example, on top of the word lines 102. In addition, peripheral circuits such as a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided around the memory cell array 100.

[0015] Word line 102 is an example of the first wiring. Bit line 103 is an example of the second wiring.

[0016] Multiple memory cells MC are provided in the region where the word line 102 and the bit line 103 intersect. The memory device of the first embodiment is a two-terminal magnetoresistive memory having a crosspoint structure.

[0017] Multiple word lines 102 are each connected to the first control circuit 104. Multiple bit lines 103 are each connected to the second control circuit 105. The sense circuit 106 is connected to both the first control circuit 104 and the second control circuit 105.

[0018] The first control circuit 104 and the second control circuit 105 have functions such as selecting a desired memory cell MC, writing data to the memory cell MC, reading data from the memory cell MC, and erasing data from the memory cell MC. When reading data, the data from the memory cell MC is read out as the amount of current flowing between the word line 102 and the bit line 103, or as a change in the potential of the bit line 103. The sense circuit 106 has a function to determine the polarity of the data by determining the amount of current. For example, it determines whether the data is "0" or "1".

[0019] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are composed of electronic circuits using semiconductor devices formed on a semiconductor substrate 101, for example.

[0020] Figure 2 is a schematic cross-sectional view of a memory cell of the first embodiment of the storage device. Figure 2 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0021] As shown in Figure 2, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive switching layer 50, and an interlayer insulating layer 55. The resistive switching layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0022] Figure 2 shows a cross-section parallel to the first direction connecting the lower electrode 10 and the upper electrode 20. Figure 2 is an example of the first cross-section.

[0023] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0024] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0025] The lower electrode 10 is connected to the word wire 102. The lower electrode 10 is, for example, a metal. The lower electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The lower electrode 10 may also be part of the word wire 102.

[0026] The upper electrode 20 is connected to the bit wire 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The upper electrode 20 may also be part of the bit wire 103.

[0027] The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0028] The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction connecting the lower electrode 10 and the upper electrode 20 is, for example, 5 nm to 50 nm. More preferably, the thickness of the switching layer 40 in the first direction is, for example, 5 nm to 20 nm.

[0029] The switching layer 40 has a function to suppress the increase in semi-selective leakage current flowing to the semi-selective cell. The switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

[0030] The switching layer 40 includes a constricted portion 40x. The constricted portion 40x is a part of the switching layer 40 that is narrower in width. The constricted portion 40x is, for example, sandwiched between two wide portions in a first direction. The constricted portion 40x is an example of a first portion.

[0031] For example, the first length of the constricted portion 40x in the second direction (d1 in Figure 2) is shorter than the second length of the second portion of the switching layer 40 that contacts the lower electrode 10 in the second direction (d2 in Figure 2). Also, for example, the first length of the constricted portion 40x in the second direction (d1 in Figure 2) is shorter than the third length of the third portion of the switching layer 40 that contacts the intermediate electrode 30 in the second direction (d3 in Figure 2).

[0032] For example, the first length d1 is between 10% and 70% of the second length d2 and the third length d3. For example, the first length d1 is between 20% and 50% of the second length d2 and the third length d3.

[0033] Figures 3, 4, and 5 are schematic cross-sectional views of the memory cell of the first embodiment of the storage device. Figure 3 is the AA' cross-section of Figure 2. Figure 4 is the BB' cross-section of Figure 2. Figure 5 is the CC' cross-section of Figure 2.

[0034] Figures 3, 4, and 5 show cross-sections perpendicular to the first direction. Figures 3, 4, and 5 are examples of second cross-sections.

[0035] Figure 3 is a cross-section of the switching layer 40 including the constricted portion 40x. Figure 4 is a cross-section of the switching layer 40 including the second portion in contact with the lower electrode 10. Figure 5 is a cross-section of the switching layer 40 including the third portion in contact with the intermediate electrode 30.

[0036] For example, in a second cross-section perpendicular to the first direction, the first area of ​​the constricted portion 40x (S1 in Figure 3) is smaller than the second area of ​​the second portion that contacts the lower electrode 10 of the switching layer 40 (S2 in Figure 4). Also, for example, in a second cross-section perpendicular to the first direction, the first area of ​​the constricted portion 40x (S1 in Figure 3) is smaller than the third area of ​​the third portion that contacts the intermediate electrode 30 of the switching layer 40 (S3 in Figure 5).

[0037] For example, the first area S1 is between 5% and 50% of the second area S2 and the third area S3. For example, the first area S1 is between 10% and 25% of the second area S2 and the third area S3.

[0038] The switching layer 40 includes, for example, a first element and an oxide, nitride, or oxynitride of the second element. The switching layer 40 includes, for example, at least one substance selected from the group consisting of an oxide, nitride, and oxynitride of the second element, and the first element.

[0039] The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti).

[0040] The switching layer 40 includes, for example, zirconium oxide, aluminum oxide, hafnium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, cerium oxide, magnesium oxide, silicon oxide, boron oxide, phosphorus oxide, germanium oxide, scandium oxide, vanadium oxide, niobium oxide, chromium oxide, or titanium oxide. The switching layer 40 includes, for example, zirconium nitride, aluminum nitride, hafnium nitride, yttrium nitride, tantalum nitride, lanthanum nitride, cerium nitride, magnesium nitride, silicon nitride, boron nitride, phosphorus nitride, germanium nitride, scandium nitride, vanadium nitride, niobium nitride, chromium nitride, or titanium nitride. The switching layer 40 includes, for example, zirconium oxynitride, aluminum oxynitride, hafnium oxynitride, yttrium oxynitride, tantalum oxynitride, lanthanum oxynitride, cerium oxynitride, magnesium oxynitride, silicon oxynitride, boron oxynitride, phosphorus oxynitride, germanium oxynitride, scandium oxynitride, vanadium oxynitride, niobium oxynitride, chromium oxynitride, or titanium oxynitride.

[0041] The switching layer 40 includes, for example, a first element, an oxide, nitride, or oxynitride of the second element, and a third element. The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg).

[0042] The switching layer 40 includes, for example, an oxide, nitride, or oxynitride of the second element, as well as a compound of the first and third elements.

[0043] The switching layer 40 includes, for example, a first element and a third element. The switching layer 40 does not include, for example, a second element. In this case, the switching layer 40 does not include, for example, oxides, nitrides, or oxynitrides. In this case, the switching layer 40 includes, for example, a compound of the first element and the third element.

[0044] The switching layer 40 includes, for example, a fourth element, which is at least one element selected from the group consisting of lithium (Li), sodium (Na), potassium (K), magnesium (Mg), calcium (Ca), barium (Ba), lead (Pb), aluminum (Al), vanadium (V), iron (Fe), and tungsten (W). The switching layer 40 also includes, for example, an oxide, nitride, or oxynitride of the second element, a compound of the first and third elements, and the fourth element.

[0045] The atomic concentration of the fourth element in the switching layer 40 is, for example, lower than the atomic concentration of the second element. The atomic concentration of the fourth element in the switching layer 40 is, for example, between 1% and 30%.

[0046] The switching layer 40 contains a fifth element, which is, for example, at least one element selected from the group consisting of carbon (C), boron (B), nitrogen (N), and silicon (Si). The atomic concentration of the fifth element contained in the switching layer 40 is, for example, 5% or more and 20% or less.

[0047] The constricted portion 40x of the switching layer 40 can be formed, for example, by the following manufacturing method. First, the sides of the lower electrode 10, the switching layer 40, and the intermediate electrode 30 are patterned vertically. Then, a mask material having an opening corresponding only to the central part of the switching layer 40 is formed on the side of the switching layer 40, and the switching layer 40 is etched from the side using the mask material as a mask. After that, the mask material is removed or the opening of the mask material is filled.

[0048] The resistive change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistive change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistive change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

[0049] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0050] The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change with respect to a predetermined writing voltage, and the magnetization direction is fixed in a specific direction.

[0051] The tunnel layer 52 is an insulator. Electrons pass through the tunnel layer 52 by the tunneling effect.

[0052] The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes in response to a predetermined writing voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and flowing a current between the intermediate electrode 30 and the upper electrode 20.

[0053] By changing the magnetization direction of the free layer 53, the electrical resistance of the resistance-changing layer 50 changes. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high-resistance state is achieved where current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low-resistance state is achieved where current is easy to flow. Note that the arrangement of the fixed layer 51 and the free layer 53 can be reversed. In other words, the layers may be stacked in the order of intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20.

[0054] The interlayer insulating layer 55 surrounds, for example, the lower electrode 10, the switching layer 40, the intermediate electrode 30, the resistance change layer 50, and the upper electrode 20. The interlayer insulating layer 55 is in contact with, for example, the side surface of the switching layer 40.

[0055] The interlayer insulating layer 55 is, for example, an insulator. The interlayer insulating layer 55 is, for example, silicon oxide or silicon nitride.

[0056] Next, the operation and effects of the storage device according to the first embodiment will be described.

[0057] In the first embodiment of the memory device, as described above, the resistance of the resistance change layer 50 changes by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, it becomes a high-resistance state in which current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, it becomes a low-resistance state in which current is easy to flow.

[0058] For example, the high-resistance state of the resistive change layer 50 is defined as data "1," and the low-resistance state is defined as data "0." The memory cell MC can maintain different resistance states, enabling it to store 1-bit data of "0" and "1." Writing to a single memory cell MC is performed by applying a voltage and current between the bit line 103 and the word line 102 connected to that memory cell MC.

[0059] Figure 6 is an explanatory diagram of the problems of the memory device according to the first embodiment. Figure 6 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write operation. The intersections of the word line and the bit line represent each memory cell MC.

[0060] The selected memory cell MC is memory cell A (selected cell). The write voltage Vwrite is applied to the word line connected to memory cell A. Also, 0V is applied to the bit line connected to memory cell A.

[0061] The following explanation uses the example where a voltage half the write voltage (Vwrite / 2) is applied to the word line and bit line that are not connected to memory cell A.

[0062] The voltage applied to memory cell C (unselected cell), which is connected to the word line and bit line not connected to memory cell A, is 0V. In other words, no voltage is applied.

[0063] On the other hand, a voltage half the write voltage Vwrite (Vwrite / 2) is applied to memory cell B (a semi-selective cell) that is connected to the word line or bit line connected to memory cell A. Therefore, a semi-selective leakage current flows through memory cell B (a semi-selective cell).

[0064] In addition, as an alternative application method, a method may be used in which a voltage half the write voltage (Vwrite / 2) is applied to the word line connected to memory cell A, a negative voltage half the write voltage (-Vwrite / 2) is applied to the bit line, and 0V is applied to the word line and bit line not connected to memory cell A.

[0065] Figure 7 is an explanatory diagram of the current-voltage characteristics of the switching element in the first embodiment. The horizontal axis represents the voltage applied to the switching element, and the vertical axis represents the current flowing through the switching element.

[0066] A switching element has a nonlinear current-voltage characteristic in which the current rises sharply at a threshold voltage Vth. The threshold voltage Vth is, for example, between 0.5V and 3V.

[0067] The write voltage Vwrite is set such that the write voltage Vwrite is higher than the threshold voltage Vth, and half the write voltage Vwrite (Vwrite / 2) is lower than the threshold voltage. The current that flows through the switching element when the write voltage Vwrite is applied is the on current (Ion in Figure 7). The current that flows through the switching element when half the write voltage Vwrite (Vwrite / 2) is applied is the semi-selective leakage current (Ihalf in Figure 7).

[0068] Furthermore, the read voltage Vread of the memory cell MC is set to a voltage higher than the threshold voltage Vth and lower than the write voltage Vwrite, for example, as shown in Figure 7. Therefore, the semi-selective leakage current flowing through the semi-selective cell can also be suppressed when reading from the memory cell MC.

[0069] A high semi-selective leakage current can lead to increased power consumption of the chip, for example. Also, an increased voltage drop in the wiring can prevent a sufficiently high voltage from being applied to the selected cell, resulting in unstable writing operations to the memory cell MC. Furthermore, a low on-current can lead to insufficient current flowing to the selected cell, resulting in incomplete writing to the memory cell MC. Therefore, the current-voltage characteristics of a switching element require a balance between low semi-selective leakage current and high on-current.

[0070] Furthermore, high reliability is required for the current-voltage characteristics of the switching element. Specifically, it is necessary to suppress characteristic fluctuations such as fluctuations in semi-selective leakage current and on-current when data is repeatedly written to the memory cell MC, thereby achieving high endurance characteristics and high reliability.

[0071] Figure 8 is a schematic cross-sectional view of a memory cell of a comparative example. Figure 8 corresponds to Figure 2 of the first embodiment.

[0072] The comparative memory cell MC differs from the memory device of the first embodiment in that the switching layer 40 does not include the constricted portion 40x.

[0073] For example, in the comparative example of a memory device, if we want to reduce the semi-selective leakage current of the switching element, we can consider reducing the cross-sectional area of ​​the current path by narrowing the width of the switching layer 40. In this case, if we try to flow the same on-current through the switching element as before narrowing the width, the on-current density will increase due to the reduced cross-sectional area of ​​the current path.

[0074] The inventors' investigations revealed that when the on-current density increases, the endurance characteristics of the switching element deteriorate due to the interdiffusion of elements between the switching layer 40 and the electrodes in contact with the switching layer 40. Specifically, for example, it was found that short-circuit failures in the switching element occur when data is repeatedly written to the memory cell MC.

[0075] In the first embodiment, the memory cell MC includes a constricted portion 40x in the switching layer 40. The constricted portion 40x reduces the cross-sectional area of ​​the current path within the switching layer 40. Therefore, the semi-selective leakage current of the switching element is reduced.

[0076] Furthermore, in the first embodiment, the narrowed portion 40x is provided in the switching layer 40, which increases the path on the side of the switching layer 40 between the lower electrode 10 and the intermediate electrode 30 compared to the memory cell of the comparative example. The side of the switching layer 40 can become a path for leakage current. Therefore, in the memory cell MC of the first embodiment, the semi-selective leakage current of the switching element is reduced even by the increased path on the side of the switching layer 40.

[0077] On the other hand, in the portion of the switching layer 40 that is in contact with the lower electrode 10 and the intermediate electrode 30, the wide cross-sectional area of ​​the switching layer 40 is maintained. Therefore, the on-current density remains low in the portion of the switching layer 40 that is in contact with the lower electrode 10 and the intermediate electrode 30.

[0078] The interdiffusion of elements between the switching layer 40 and the electrode is thought to be due to the high on-current density at the interface between the switching layer 40 and the electrode. Therefore, in the switching element of the memory cell MC of the first embodiment, where the interface area is large, the interdiffusion of elements between the switching layer 40 and the electrode is suppressed, and high endurance characteristics can be achieved.

[0079] As described above, according to the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized. Therefore, according to the first embodiment, a memory device having a switching element with excellent characteristics can be realized.

[0080] From the viewpoint of reducing the semi-selective leakage current of the switching element, the first length of the constricted portion 40x in the second direction (d1 in Figure 2) is preferably 70% or less, and more preferably 50% or less, of the second length of the second portion of the switching layer 40 in contact with the lower electrode 10 in the second direction (d2 in Figure 2). From a similar viewpoint, the first length of the constricted portion 40x in the second direction (d1 in Figure 2) is preferably 70% or less, and more preferably 50% or less, of the third length of the third portion of the switching layer 40 in contact with the intermediate electrode 30 in the second direction (d3 in Figure 2).

[0081] From the viewpoint of reducing the semi-selective leakage current of the switching element, the first area of ​​the constricted portion 40x (S1 in Figure 3) is preferably 50% or less, and more preferably 25% or less, of the second area of ​​the second portion in contact with the lower electrode 10 of the switching layer 40 (S2 in Figure 4). From a similar viewpoint, in a second cross section perpendicular to the first direction, the first area of ​​the constricted portion 40x (S1 in Figure 3) is preferably 50% or less, and more preferably 25% or less, of the third area of ​​the third portion in contact with the intermediate electrode 30 of the switching layer 40 (S3 in Figure 5).

[0082] From the viewpoint of increasing the on-current of the switching element, the first length of the constricted portion 40x in the second direction (d1 in Figure 2) is preferably 10% or more, and more preferably 20% or more, of the second length of the second portion of the switching layer 40 in contact with the lower electrode 10 in the second direction (d2 in Figure 2). From a similar viewpoint, the first length of the constricted portion 40x in the second direction (d1 in Figure 2) is preferably 10% or more, and more preferably 20% or more, of the third length of the third portion of the switching layer 40 in contact with the intermediate electrode 30 in the second direction (d3 in Figure 2).

[0083] From the viewpoint of increasing the on-current of the switching element, the first area of ​​the constricted portion 40x (S1 in Figure 3) is preferably 5% or more, and more preferably 10% or more, of the second area of ​​the second portion in contact with the lower electrode 10 of the switching layer 40 (S2 in Figure 4). From a similar viewpoint, in a second cross-section perpendicular to the first direction, the first area of ​​the constricted portion 40x (S1 in Figure 3) is preferably 5% or more, and more preferably 10% or more, of the third area of ​​the third portion in contact with the intermediate electrode 30 of the switching layer 40 (S3 in Figure 5).

[0084] (First variation) The first modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0085] Figure 9 is a schematic cross-sectional view of a memory cell of a first modified memory device of the first embodiment. Figure 9 corresponds to Figure 2 of the first embodiment.

[0086] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0087] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0088] The second part 12 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0089] In the first modified memory device of the first embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 does not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0090] As described above, according to the first modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0091] (Second variation) The second modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0092] Figure 10 is a schematic cross-sectional view of a memory cell of a second modified storage device of the first embodiment. Figure 10 corresponds to Figure 2 of the first embodiment.

[0093] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0094] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0095] The second part 12 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0096] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0097] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0098] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0099] The fourth portion 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 comprises, for example, borides of the above elements. The fourth portion 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0100] In the second modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0101] As described above, according to the second modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0102] (Third variation) The third modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion, a second portion, and a fifth portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0103] Figure 11 is a schematic cross-sectional view of a memory cell of a third modified memory device of the first embodiment. Figure 11 corresponds to Figure 2 of the first embodiment.

[0104] The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 40. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

[0105] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0106] The second part 12 and the fifth part 13 include, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0107] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0108] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0109] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0110] The fourth portion 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 comprises, for example, borides of the above elements. The fourth portion 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0111] In the third modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0112] As described above, according to the third modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0113] (Fourth variation) The storage device of the fourth modification of the first embodiment differs from the storage device of the first embodiment in that the position of the narrowed portion of the switching layer in the first direction is different.

[0114] Figure 12 is a schematic cross-sectional view of a memory cell of a fourth modified storage device of the first embodiment. Figure 12 corresponds to Figure 2 of the first embodiment.

[0115] The constricted portion 40x is located in the first direction at a position close to the intermediate electrode 30, rather than at an intermediate position between the lower electrode 10 and the intermediate electrode 30. However, the constricted portion 40x may also be located close to the lower electrode 10 in the first direction.

[0116] As described above, according to the fourth modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0117] (Fifth variation) The fifth modified storage device of the first embodiment differs from the storage device of the first embodiment in that the switching layer includes a plurality of constrictions.

[0118] Figure 13 is a schematic cross-sectional view of a memory cell of a fifth modified memory device of the first embodiment. Figure 13 corresponds to Figure 2 of the first embodiment.

[0119] Two constricted sections 40x are provided in the switching layer 40. By providing two constricted sections 40x, the leakage current flowing through the switching layer 40 is further suppressed, and the semi-selective leakage current of the switching elements is reduced. In addition, by providing two constricted sections 40x, the path on the side of the switching layer 40 is further lengthened, which reduces the semi-selective leakage current of the switching elements.

[0120] Furthermore, there may be three or more constricted sections 40x.

[0121] As described above, according to the fifth modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0122] (Sixth variation) The sixth modified memory device of the first embodiment differs from the memory device of the first embodiment in that, in a first cross-section parallel to the first direction connecting the first conductive layer and the second conductive layer, the atomic concentration of the first element in the first portion is different from the atomic concentration of the first element in the second portion in contact with the first conductive layer of the switching layer, and the atomic concentration of the first element in the third portion in contact with the third conductive layer of the switching layer.

[0123] Figure 14 is a schematic cross-sectional view of a memory cell of a sixth modified memory device of the first embodiment. Figure 14 corresponds to Figure 2 of the first embodiment.

[0124] The atomic concentration of the first element in the constricted portion 40x is different from the atomic concentration of the first element in the second portion of the switching layer 40 that is in contact with the lower electrode 10, and the atomic concentration of the first element in the third portion of the switching layer 40 that is in contact with the intermediate electrode 30. For example, the atomic concentration of the first element in the constricted portion 40x is higher than the atomic concentration of the first element in the second portion of the switching layer 40 that is in contact with the lower electrode 10, and the atomic concentration of the first element in the third portion of the switching layer 40 that is in contact with the intermediate electrode 30. Alternatively, for example, the atomic concentration of the first element in the constricted portion 40x is lower than the atomic concentration of the first element in the second portion of the switching layer 40 that is in contact with the lower electrode 10, and the atomic concentration of the first element in the third portion of the switching layer 40 that is in contact with the intermediate electrode 30.

[0125] When manufacturing the constricted portion 40x of the switching layer 40, it is possible to partially create a difference in the etching rate of the switching layer 40 by, for example, a difference in the atomic concentration of the first element. Therefore, for example, when etching the switching layer 40 from the side, the constricted portion 40x can be formed without using a masking material.

[0126] As described above, according to the sixth modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0127] (Second embodiment) The memory device of the second embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first and second conductive layers; a switching layer provided between the first and third conductive layers, comprising a first region including a second portion in contact with the first conductive layer, a third portion in contact with the third conductive layer, and a first portion between the second and third portions, and a second region surrounding the first region; and a resistive switching layer provided between the third and second conductive layers. The switching layer comprises a first element and an oxide, nitride, or oxynitride of the second element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The atomic concentration of the first element in the first region is higher than the atomic concentration of the first element in the second region. In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in a second direction and the third length of the third portion in a second direction. The storage device of the second embodiment differs from the storage device of the first embodiment in that the switching layer includes a first region having a first portion and a second region surrounding the first region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0128] Figure 15 is a schematic cross-sectional view of a memory cell of the second embodiment of the storage device. Figure 15 corresponds to Figure 2 of the first embodiment.

[0129] The switching layer 40 includes a first element and an oxide, nitride, or oxynitride of the second element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti).

[0130] The switching layer 40 includes, for example, a first element, an oxide, nitride, or oxynitride of the second element, and a third element. The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg).

[0131] The switching layer 40 includes a fourth element, which is, for example, at least one element selected from the group consisting of lithium (Li), sodium (Na), potassium (K), calcium (Ca), barium (Ba), lead (Pb), iron (Fe), and tungsten (W).

[0132] The switching layer 40 contains, for example, carbon (C).

[0133] The switching layer 40 includes a first region 41 and a second region 42. The second region 42 surrounds the first region 41.

[0134] The first region 41 includes a constricted portion 41x. The constricted portion 41x is a part of the first region 41 that is narrower in width. The constricted portion 41x is, for example, sandwiched between two wider portions of the first region 41 in a first direction. The constricted portion 41x is an example of the first portion.

[0135] The first region 41 and the second region 42 include a first element and an oxide, nitride, or oxynitride of the second element. Furthermore, the first region 41 and the second region 42 may also include, for example, a first element, an oxide, nitride, or oxynitride of the second element, and a third element.

[0136] The first region 41 and the second region 42 contain the first element and the second element. The first region 41 and the second region 42 also contain, for example, the first element, the second element, and the third element.

[0137] The atomic concentration of the first element in the first region 41 is higher than that of the first element in the second region 42. Due to the higher atomic concentration of the first element in the first region 41, the electrical resistance of the first region 41 is lower than that of the second region 42. Therefore, the current flowing through the switching layer 40 mainly flows through the first region 41.

[0138] Furthermore, if the switching layer 40 contains a third element, for example, the atomic concentration of the third element in the first region 41 is higher than the atomic concentration of the third element in the second region 42. Due to the higher atomic concentrations of the second and third elements in the first region 41, the electrical resistance of the first region 41 is lower than that of the second region 42. Therefore, the current flowing through the switching layer 40 mainly flows through the first region 41.

[0139] For example, the first length of the constricted portion 41x in the second direction (d1 in Figure 15) is shorter than the second length of the first region 41 of the second part that contacts the lower electrode 10 of the switching layer 40 in the second direction (d2 in Figure 15). Also, for example, the first length of the constricted portion 41x in the second direction (d1 in Figure 15) is shorter than the third length of the first region 41 of the third part that contacts the intermediate electrode 30 of the switching layer 40 in the second direction (d3 in Figure 15).

[0140] For example, the first length d1 is between 10% and 70% of the second length d2 and the third length d3. For example, the first length d1 is between 20% and 50% of the second length d2 and the third length d3.

[0141] Figures 16, 17, and 18 are schematic cross-sectional views of the memory cell of the storage device according to the second embodiment. Figure 16 is the AA' cross-section of Figure 15. Figure 17 is the BB' cross-section of Figure 15. Figure 18 is the CC' cross-section of Figure 15.

[0142] Figures 16, 17, and 18 show cross-sections perpendicular to the first direction. Figures 16, 17, and 18 are examples of second cross-sections.

[0143] Figure 16 is a cross-section of the switching layer 40 including the constricted portion 41x of the first region 41. Figure 17 is a cross-section of the switching layer 40 including the second portion in contact with the lower electrode 10. Figure 18 is a cross-section of the switching layer 40 including the third portion in contact with the intermediate electrode 30.

[0144] For example, in a second cross-section perpendicular to the first direction, the first area of ​​the constricted portion 41x (S1 in Figure 16) is smaller than the second area of ​​the first region 41 of the second part that contacts the lower electrode 10 of the switching layer 40 (S2 in Figure 17). Also, for example, in a second cross-section perpendicular to the first direction, the first area of ​​the constricted portion 41x (S1 in Figure 16) is smaller than the third area of ​​the first region 41 of the third part that contacts the intermediate electrode 30 of the switching layer 40 (S3 in Figure 18).

[0145] For example, the first area S1 is between 5% and 50% of the second area S2 and the third area S3. For example, the first area S1 is between 10% and 25% of the second area S2 and the third area S3.

[0146] The first region 41 and the second region 42 having a constricted portion 41x in the switching layer 40 can be formed, for example, by the following manufacturing method: A switching element such as the comparative example of the first embodiment is formed. Then, a predetermined bidirectional voltage stress is applied to the switching element a predetermined number of times. The application of the voltage stress causes the first element to diffuse in the switching layer 40. As a result, a switching layer 40 is formed that includes a first region 41 having a high atomic concentration of the first element and a constricted portion 41x, and a second region 42 surrounding the first region 41.

[0147] Next, the operation and effects of the storage device according to the second embodiment will be described.

[0148] In the second embodiment, the memory cell MC has a first region 41 of the switching layer 40 that includes a constricted portion 41x. The constricted portion 41x reduces the cross-sectional area of ​​the current path within the switching layer 40, thereby reducing the semi-selective leakage current of the switching element.

[0149] On the other hand, in the portion of the switching layer 40 that is in contact with the lower electrode 10 and the intermediate electrode, the wide cross-sectional area of ​​the first region 41 is maintained. As a result, the on-current density remains low in the portion of the switching layer 40 that is in contact with the lower electrode 10 and the intermediate electrode. Therefore, in the switching element of the memory cell MC of the second embodiment, the interdiffusion of elements between the switching layer 40 and the electrodes is suppressed, and high endurance characteristics can be achieved.

[0150] From the viewpoint of reducing the semi-selective leakage current of the switching element, the first length of the constricted portion 41x in the second direction (d1 in Figure 15) is preferably 70% or less, and more preferably 50% or less, of the second length of the first region 41 of the second portion in the second direction (d2 in Figure 15) that is in contact with the lower electrode 10 of the switching layer 40. From a similar viewpoint, the first length of the constricted portion 41x in the second direction (d1 in Figure 15) is preferably 70% or less, and more preferably 50% or less, of the third length of the first region 41 of the third portion in the third portion in the second direction (d3 in Figure 15) that is in contact with the intermediate electrode 30 of the switching layer 40.

[0151] From the viewpoint of reducing the semi-selective leakage current of the switching element, the first area of ​​the constricted portion 41x (S1 in Figure 16) is preferably 50% or less, and more preferably 25% or less, of the second area of ​​the first region 41 of the second portion in contact with the lower electrode 10 of the switching layer 40 (S2 in Figure 17). From a similar viewpoint, in a second cross section perpendicular to the first direction, the first area of ​​the constricted portion 41x (S1 in Figure 16) is preferably 50% or less, and more preferably 25% or less, of the third area of ​​the first region 41 of the third portion in contact with the intermediate electrode 30 of the switching layer 40 (S3 in Figure 18).

[0152] From the viewpoint of increasing the on-current of the switching element, the first length of the constricted portion 41x in the second direction (d1 in Figure 15) is preferably 10% or more, and more preferably 20% or more, of the second length of the first region 41 of the second portion in the second direction (d2 in Figure 15) that is in contact with the lower electrode 10 of the switching layer 40. From a similar viewpoint, the first length of the constricted portion 41x in the second direction (d1 in Figure 15) is preferably 10% or more, and more preferably 20% or more, of the third length of the first region 41 of the third portion in the third portion in the second direction (d3 in Figure 15) that is in contact with the intermediate electrode 30 of the switching layer 40.

[0153] From the viewpoint of increasing the on-current of the switching element, the first area of ​​the constricted portion 41x (S1 in Figure 16) is preferably 5% or more, and more preferably 10% or more, of the second area of ​​the first region 41 of the second portion that contacts the lower electrode 10 of the switching layer 40 (S2 in Figure 17). From a similar viewpoint, in a second cross section perpendicular to the first direction, the first area of ​​the constricted portion 41x (S1 in Figure 16) is preferably 5% or more, and more preferably 10% or more, of the third area of ​​the first region 41 of the third portion that contacts the intermediate electrode 30 of the switching layer 40 (S3 in Figure 18).

[0154] As described above, according to the second embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment. Therefore, according to the second embodiment, a memory device having a switching element with excellent characteristics can be realized.

[0155] (Third embodiment) The storage device of the third embodiment differs from the storage device of the first embodiment in that it is a resistive random-access memory (ReRAM). The following description will omit some parts that overlap with the first embodiment.

[0156] Figure 19 is a schematic cross-sectional view of a memory cell of a third embodiment of a storage device. Figure 19 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0157] As shown in Figure 19, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive switching layer 50, and an interlayer insulating layer 55. The resistive switching layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0158] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0159] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC. The switching layer 40 has a constricted portion 40x.

[0160] The configuration of the switching layer 40 is the same as that of the storage device in the first embodiment.

[0161] The resistance-changing layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0162] The high-resistance layer 50x is, for example, a metal oxide. The high-resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0163] The low-resistance layer 50y is, for example, a metal oxide. The low-resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0164] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0165] By applying a voltage to the resistance-changing layer 50, the resistance-changing layer 50 changes from a high-resistance state to a low-resistance state, or from a low-resistance state to a high-resistance state. The application of voltage to the resistance-changing layer 50 causes oxygen ions to move between the high-resistance layer 50x and the low-resistance layer 50y, changing the amount of oxygen vacancies in the low-resistance layer 50y. The conductivity of the resistance-changing layer 50 changes in accordance with the amount of oxygen vacancies in the low-resistance layer 50y. The low-resistance layer 50y is a so-called vacancy-modulated conductive oxide.

[0166] For example, a high-resistance state is defined as data "1," and a low-resistance state as data "0." The memory cell MC can then store 1-bit data, either "0" or "1."

[0167] As described above, the memory device of the third embodiment can realize a switching element with excellent characteristics such as low semi-selective leakage current and high reliability, similar to the first embodiment. Therefore, the third embodiment can realize a memory device having a switching element with excellent characteristics.

[0168] (Fourth embodiment) The storage device of the fourth embodiment differs from the storage device of the second embodiment in that it is a resistive random-access memory (ReRAM). Furthermore, the configuration of the storage device of the fourth embodiment is the same as that of the storage device of the third embodiment, except for the switching layer. The following description will omit some parts of the content that overlaps with the second and third embodiments.

[0169] Figure 20 is a schematic cross-sectional view of a memory cell of the fourth embodiment of the storage device. Figure 20 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0170] As shown in Figure 20, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive switching layer 50, and an interlayer insulating layer 55. The resistive switching layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0171] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer.

[0172] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC. The switching layer 40 includes a first region 41 having a constricted portion 41x and a second region 42.

[0173] The configuration of the switching layer 40 is the same as that of the storage device in the second embodiment.

[0174] The configuration of the resistive switching layer 50 is the same as in the third embodiment.

[0175] As described above, the storage device of the fourth embodiment can realize a switching element with excellent characteristics such as low semi-selective leakage current and high reliability, similar to the second embodiment. Therefore, the fourth embodiment can realize a storage device having a switching element with excellent characteristics.

[0176] (Fifth embodiment) The fifth embodiment of the memory device includes a memory cell comprising a first conductive layer, a second conductive layer, and a memory layer provided between the first and second conductive layers and including a second portion in contact with the first conductive layer, a third portion in contact with the second conductive layer, and a first portion between the second and third portions. The memory layer includes a first element and an oxide, nitride, or oxynitride of the second element, or the memory layer includes a first element and a third element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg).

[0177] Furthermore, the storage device of the fifth embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0178] The memory device of the fifth embodiment differs from the memory device of the first embodiment in that the memory cell does not include a third conductive layer and a resistive switching layer, and instead includes a memory layer with a configuration similar to that of the switching layer of the first embodiment. The following description will omit some parts that overlap with the first embodiment.

[0179] Figure 21 is a schematic cross-sectional view of a memory cell of a fifth embodiment of a storage device. Figure 21 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0180] As shown in Figure 21, the memory cell MC comprises a lower electrode 10, an upper electrode 20, and a memory layer 60.

[0181] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0182] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function to store information.

[0183] The memory layer 60 has a configuration similar to that of the switching layer 40 in the first embodiment. That is, the memory layer 60 has a constricted portion 40x. The constricted portion 40x is an example of the first portion. The memory layer 60 includes a first element and an oxide, nitride, or oxynitride of the second element, or the memory layer includes a first element and a third element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg).

[0184] The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. Furthermore, the memory layer 60 has a characteristic in which the threshold voltage changes when a predetermined voltage is applied. The memory layer 60 also has a characteristic in which its electrical resistance changes when a predetermined voltage is applied. In the fifth embodiment, the high-resistance state is a state in which the resistance of the memory layer 60 is relatively high at the read voltage. Also, in the fifth embodiment, the low-resistance state is a state in which the resistance of the memory layer 60 is relatively low at the read voltage.

[0185] The memory layer 60 has the function of suppressing the increase in semi-selective leakage current flowing to the semi-selective cells. The memory layer 60 also has the function of storing data by resistance changes. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment.

[0186] Figure 22 is an explanatory diagram of the current-voltage characteristics of the memory element of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 22, the horizontal axis shows the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. Figure 22 shows the current-voltage characteristics of the memory layer 60 of the fifth embodiment. Figure 22 shows the current-voltage characteristics of the memory cell MC of the fifth embodiment.

[0187] The memory element of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 22, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0188] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0189] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0190] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0191] The memory element of the fifth embodiment can take on both a high-resistance state and a low-resistance state under both positive and negative voltage conditions. When a predetermined positive voltage is applied to the upper electrode 20, it enters a high-resistance state under both positive and negative voltage conditions. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a low-resistance state under both positive and negative voltage conditions. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0192] Figure 23 is an explanatory diagram of a first example of the memory operation of the storage device according to the fifth embodiment. Figure 23 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0193] In the first operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the first operational example, the negative side read voltage Vrn is used as the read voltage.

[0194] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0195] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0196] In the first example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0197] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0198] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0199] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0200] In the first example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the first example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0201] Figure 24 is an explanatory diagram of a second example of memory operation of the storage device according to the fifth embodiment. Figure 24 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0202] In the second operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the second operating example, the positive side read voltage Vrp is used as the read voltage.

[0203] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0204] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0205] In the second example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0206] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0207] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0208] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0209] In the second example of operation, if the data in the selected cell is "1", no data corruption occurs when the positive read voltage Vrp is applied. In other words, in the second example of operation, if the data in the selected cell is "1", non-destructive reading is possible.

[0210] On the other hand, if the data in the selected cell is "0", applying a positive read voltage Vrp higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data in the selected cell to "1". In other words, in the second example of operation, if the data in the selected cell is "0", a destructive read may occur. Therefore, if the data in the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data in the selected cell in order to maintain the data in the selected cell.

[0211] (First variation) The first modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0212] Figure 25 is an explanatory diagram of the current-voltage characteristics of the memory element of the first modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 25, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 25 shows the current-voltage characteristics of the memory layer 60 of the first modified example of the fifth embodiment. Figure 25 shows the current-voltage characteristics of the memory cell MC of the first modified example of the fifth embodiment.

[0213] The memory element of the first modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 25, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0214] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0215] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0216] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0217] The memory element of the first modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it enters a low-resistance state on both the positive and negative voltage sides. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a high-resistance state on both the positive and negative voltage sides. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0218] Figure 26 is an explanatory diagram of a third example of the memory operation of the storage device of the first modified example of the fifth embodiment. Figure 26 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0219] In the third operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the third operational example, the negative side read voltage Vrn is used as the read voltage.

[0220] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0221] When writing the data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0222] In the third example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0223] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0224] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0225] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0226] In the third example of operation, if the data in the selected cell is "1", no data corruption will occur due to the application of the negative read voltage Vrn. In other words, in the third example of operation, if the data in the selected cell is "1", non-destructive readout is possible.

[0227] On the other hand, if the data of the selected cell is "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the third example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data.

[0228] Figure 27 is an explanatory diagram of a fourth example of the memory operation of the storage device of the first modification of the fifth embodiment. Figure 27 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0229] In the fourth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the fourth operating example, the positive side read voltage Vrp is used as the read voltage.

[0230] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0231] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0232] In the fourth example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0233] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0234] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0235] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0236] In the fourth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fourth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0237] (Second variation) The second modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0238] Figure 28 is an explanatory diagram of the current-voltage characteristics of a memory element in a second modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 28, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 28 shows the current-voltage characteristics of the memory layer 60 in a second modified example of the fifth embodiment. Figure 28 shows the current-voltage characteristics of the memory cell MC in a second modified example of the fifth embodiment.

[0239] The memory element of the second modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 28, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0240] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0241] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0242] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0243] The memory element of the second modification of the fifth embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0244] Figure 29 is an explanatory diagram of a fifth example of memory operation of a storage device in the second modification of the fifth embodiment. Figure 29 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0245] In the fifth operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the fifth operating example, the negative side read voltage Vrn is used as the read voltage.

[0246] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0247] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0248] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0249] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0250] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0251] In the fifth example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fifth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0252] Figure 30 is an explanatory diagram of a sixth example of memory operation of a storage device in the second modification of the fifth embodiment. Figure 30 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0253] In the sixth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the sixth operating example, the positive side read voltage Vrp is used as the read voltage.

[0254] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0255] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0256] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0257] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0258] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0259] In the sixth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the sixth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0260] (Third variation) The third modified memory device of the fifth embodiment differs from the memory device of the fifth embodiment in that the current-voltage characteristics of the memory elements are different.

[0261] Figure 31 is an explanatory diagram of the current-voltage characteristics of a memory element in the third modified example of the fifth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 31, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 31 shows the current-voltage characteristics of the memory layer 60 in the third modified example of the fifth embodiment. Figure 31 shows the current-voltage characteristics of the memory cell MC in the third modified example of the fifth embodiment.

[0262] The memory element of the third modified example of the fifth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 31, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0263] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0264] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0265] The first positive voltage side threshold voltage Vtpp is higher than the second positive voltage side threshold voltage Vtnp. Also, the first negative voltage side threshold voltage Vtpn is higher than the second negative voltage side threshold voltage Vtnn.

[0266] The memory element of the third modification of the fifth embodiment can take a high resistance state and a low resistance state both on the positive voltage side and on the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it becomes a high resistance state on the positive voltage side and a low resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it becomes a low resistance state on the positive voltage side and a high resistance state on the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0267] FIG. 32 is an explanatory diagram of a seventh operation example of the memory operation of the memory device of the third modification of the fifth embodiment. In FIG. 32, the positive-side write voltage Vwp, the voltage (Vwp / 2) that is half of the positive-side write voltage Vwp, the negative-side write voltage Vwn, the voltage (Vwn / 2) that is half of the negative-side write voltage Vwn, and the negative-side read voltage Vrn during the memory operation are shown.

[0268] In the seventh operation example, the high resistance state and the low resistance state on the negative voltage side are used for the memory operation. In the seventh operation example, the negative-side read voltage Vrn is used as the read voltage.

[0269] When writing data "1" to the selected cell, a negative-side write voltage Vwn is applied to the upper electrode 20. The negative-side write voltage Vwn is a voltage lower than the second negative voltage side threshold voltage Vtnn. By applying the negative-side write voltage Vwn to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

[0270] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive-side threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0271] In the seventh example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0272] Furthermore, in the seventh example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0273] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0274] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0275] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0276] In the case of the seventh operating example, if the data in the selected cell is "1", no data corruption will occur due to the application of the negative read voltage Vrn. In other words, in the case of the seventh operating example, if the data in the selected cell is "1", non-destructive readout is possible.

[0277] On the other hand, if the data of the selected cell is "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the seventh example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data.

[0278] Figure 33 is an explanatory diagram of the eighth example of memory operation of a storage device in the third modification of the fifth embodiment. Figure 33 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0279] In the eighth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the eighth operating example, the positive side read voltage Vrp is used as the read voltage.

[0280] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0281] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0282] In the eighth example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0283] Furthermore, in the eighth example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0284] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0285] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0286] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0287] In the case of the eighth operating example, if the data in the selected cell is "1", no data corruption will occur by applying the positive side read voltage Vrp. In other words, in the case of the eighth operating example, if the data in the selected cell is "1", non-destructive readout is possible.

[0288] On the other hand, if the data of the selected cell is "0", applying a positive read voltage Vrp that is higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the case of the eighth example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data of the selected cell.

[0289] In the memory device of the fifth embodiment and its modified example, the memory element of the memory cell MC has a switching function and a function of storing information. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment. Since the memory layer 60 of the fifth embodiment is a single layer and has a switching function and a memory function, the structure of the memory cell MC can be made extremely simple.

[0290] Also, the memory layer 60 of the memory device of the fifth embodiment and its modified example has the same configuration as the switching layer 40 of the first embodiment. Therefore, according to the fifth embodiment and its modified example, a memory device having excellent switching characteristics such as a low half-selection leakage current and high reliability can be realized as in the first embodiment.

[0291] Note that the plurality of current-voltage characteristics of the memory element shown in the fifth embodiment and its modified example can be realized, for example, by adopting a memory layer 60 having an appropriate chemical composition.

[0292] (Sixth Embodiment) The sixth embodiment of the memory device includes a memory layer comprising: a first conductive layer; a second conductive layer; and a memory layer provided between the first conductive layer and the second conductive layer, comprising a first region including a second portion in contact with the first conductive layer, a third portion in contact with the second conductive layer, and a first portion between the second portion and the third portion, and a second region surrounding the first region. The memory layer comprises a first element and an oxide, nitride, or oxynitride of the second element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The atomic concentration of the first element in the first region is higher than the atomic concentration of the first element in the second region. In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in a second direction and the third length of the third portion in a second direction.

[0293] Furthermore, the storage device of the sixth embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0294] The storage device of the sixth embodiment differs from the storage device of the second embodiment in that the memory cell does not include a third conductive layer and a resistive switching layer, and instead includes a memory layer with a configuration similar to that of the switching layer in the second embodiment. Furthermore, the storage device of the sixth embodiment differs from the storage device of the fifth embodiment in that the memory layer includes a configuration similar to that of the switching layer in the second embodiment. The following description will partially omit details that overlap with the second and fifth embodiments.

[0295] Figure 34 is a schematic cross-sectional view of a memory cell of a sixth embodiment of a storage device. Figure 34 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0296] As shown in Figure 34, the memory cell MC comprises a lower electrode 10, an upper electrode 20, and a memory layer 60.

[0297] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0298] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function to store information.

[0299] The memory layer 60 has a configuration similar to that of the switching layer 40 in the second embodiment. That is, the memory layer 60 includes a first region 41 having a constricted portion 41x and a second region 42 surrounding the first region 41. The constricted portion 41x is an example of the first portion. The memory layer 60 includes a first element and an oxide, nitride, or oxynitride of the second element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The atomic concentration of the first element in the first region 41 is higher than the atomic concentration of the first element in the second region 42.

[0300] In the sixth embodiment of the memory device, the memory elements of the memory cell MC have a switching function and a function for storing information. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistive switching layer 50 of the second embodiment. Because the memory layer 60 of the sixth embodiment is a single layer and has both a switching function and a memory function, the structure of the memory cell MC can be made extremely simple.

[0301] Furthermore, the memory layer 60 of the storage device in the sixth embodiment has the same configuration as the switching layer 40 of the second embodiment. Therefore, according to the sixth embodiment, a storage device with excellent switching characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the second embodiment.

[0302] In the first and second embodiments, magnetoresistive memory was described as an example of a two-terminal storage device, and in the third and fourth embodiments, resistive random-access memory was described as an example of a storage device. However, the present invention can be applied to other two-terminal storage devices. For example, the present invention can be applied to phase-change memory (PCM) or ferroelectric random-access memory (FeRAM).

[0303] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0304] 10 Lower electrode (first conductive layer) 20 Upper electrode (second conductive layer) 30 Intermediate electrode (third conductive layer) 40 Switching Layer 40x stenosis 41. First Domain 41x Stenosis (1st part) 42 Second Domain 50 Resistivity change layer 60 memory layers 102 Word line (first wiring) 103-bit line (second wiring) MC memory cell d1 First length d2 Second length d3 Third length S1 First area S2 Second area S3 Third Area

Claims

1. A first conductive layer and A second conductive layer, A third conductive layer is provided between the first conductive layer and the second conductive layer, A switching layer provided between the first conductive layer and the third conductive layer, comprising a second portion in contact with the first conductive layer, a third portion in contact with the third conductive layer, and a first portion between the second and third portions, A memory cell comprising a resistive change layer provided between the third conductive layer and the second conductive layer, The switching layer comprises a first element and an oxide, nitride, or oxynitride of the second element, or the switching layer comprises the first element and a third element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg). In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in the second direction and the third length of the third portion in the second direction. storage device.

2. The storage device according to claim 1, wherein the switching layer comprises the first element, an oxide, nitride, or oxynitride of the second element, and the third element.

3. The storage device according to claim 1, wherein the first length is 70% or less of the second length and the third length.

4. The storage device according to claim 1, wherein the first length is 50% or less of the second length and the third length.

5. The storage device according to claim 1, wherein in a second cross-section perpendicular to the first direction, the first area of ​​the first portion is smaller than the second area of ​​the second portion and the third area of ​​the third portion.

6. The storage device according to claim 5, wherein the first area is 50% or less of the second area and the third area.

7. The storage device according to claim 5, wherein the first area is 25% or less of the second area and the third area.

8. The storage device according to claim 1, wherein the switching layer includes a plurality of the first portions.

9. The storage device according to claim 1, wherein in the first cross-section, the atomic concentration of the first element in the first portion is different from the atomic concentration of the first element in the second portion and the atomic concentration of the first element in the third portion.

10. The memory device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

11. The storage device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

12. The storage device according to claim 1, wherein the resistance change layer includes a magnetic tunnel junction.

13. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 1, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

14. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 1, wherein the memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

15. A first conductive layer and A second conductive layer, A third conductive layer is provided between the first conductive layer and the second conductive layer, A switching layer provided between the first conductive layer and the third conductive layer, comprising a first region including a second portion in contact with the first conductive layer, a third portion in contact with the third conductive layer, and a first portion between the second and third portions, and a second region surrounding the first region, A memory cell comprising a resistive change layer provided between the third conductive layer and the second conductive layer, The switching layer comprises a first element and an oxide, nitride, or oxynitride of the second element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The atomic concentration of the first element in the first region is higher than the atomic concentration of the first element in the second region. In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in the second direction and the third length of the third portion in the second direction. storage device.

16. The memory device according to claim 15, wherein the switching layer further comprises a third element, the third element being at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg).

17. The storage device according to claim 15, wherein the first length is 70% or less of the second length and the third length.

18. The storage device according to claim 15, wherein the first length is 50% or less of the second length and the third length.

19. The storage device according to claim 15, wherein in a second cross-section perpendicular to the first direction, the first area of ​​the first portion is smaller than the second area of ​​the second portion and the third area of ​​the third portion.

20. The storage device according to claim 19, wherein the first area is 50% or less of the second area and the third area.

21. The storage device according to claim 19, wherein the first area is 25% or less of the second area and the third area.

22. The memory device according to claim 15, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

23. The storage device according to claim 15, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

24. The storage device according to claim 15, wherein the resistance change layer includes a magnetic tunnel junction.

25. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 15, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

26. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 15, wherein the memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

27. A first conductive layer and A second conductive layer, A memory cell is provided between the first conductive layer and the second conductive layer, and includes a memory layer comprising a second portion in contact with the first conductive layer, a third portion in contact with the second conductive layer, and a first portion between the second portion and the third portion. The memory layer comprises a first element and an oxide, nitride, or oxynitride of the second element, or the memory layer comprises the first element and a third element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The third element is at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg). In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in the second direction and the third length of the third portion in the second direction. storage device.

28. The memory device according to claim 27, wherein the memory layer comprises the first element, an oxide, nitride, or oxynitride of the second element, and the third element.

29. The storage device according to claim 27, wherein in a second cross-section perpendicular to the first direction, the first area of ​​the first portion is smaller than the second area of ​​the second portion and the third area of ​​the third portion.

30. The memory layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage, and the threshold voltage changes when a predetermined voltage is applied, as described in claim 27.

31. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 27, wherein the memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

32. A first conductive layer and A second conductive layer, A memory cell is provided between the first conductive layer and the second conductive layer, and includes a memory layer comprising a first region including a second portion in contact with the first conductive layer, a third portion in contact with the second conductive layer, and a first portion between the second portion and the third portion, and a second region surrounding the first region. The memory layer comprises a first element and an oxide, nitride, or oxynitride of the second element. The first element is at least one element selected from the group consisting of tellurium (Te), selenium (Se), sulfur (S), antimony (Sb), and arsenic (As). The second element is at least one element selected from the group consisting of zirconium (Zr), aluminum (Al), hafnium (Hf), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), magnesium (Mg), silicon (Si), boron (B), phosphorus (P), germanium (Ge), scandium (Sc), vanadium (V), niobium (Nb), chromium (Cr), and titanium (Ti). The atomic concentration of the first element in the first region is higher than the atomic concentration of the first element in the second region. In a first cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, the first length of the first portion in a second direction perpendicular to the first direction is shorter than the second length of the second portion in the second direction and the third length of the third portion in the second direction. storage device.

33. The memory device according to claim 32, wherein the memory layer further comprises a third element, the third element being at least one element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), and magnesium (Mg).

34. The storage device according to claim 32, wherein in a second cross-section perpendicular to the first direction, the first area of ​​the first portion is smaller than the second area of ​​the second portion and the third area of ​​the third portion.

35. The memory layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage, and the threshold voltage changes when a predetermined voltage is applied, as described in claim 32.

36. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 32, wherein the memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

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