Substrate for mounting semiconductor devices

Abstract

This invention provides a technology to improve corrosion resistance in substrates for mounting semiconductor devices. [Solution] The substrate for mounting semiconductor elements comprises a base material, electrodes connected to the semiconductor elements, an insulating layer disposed between the base material and the electrodes and formed of aluminum nitride, a protective layer disposed between the insulating layer and the electrodes, and a titanium layer disposed between the protective layer and the electrodes and formed of titanium, wherein the protective layer is made of a material that has higher corrosion resistance to both titanium etching solution and hot water than the insulating layer.

Description

Technical Field

[0001] The present invention relates to a substrate for mounting semiconductor elements.

[0002] Conventionally, a substrate for mounting semiconductor elements having electrodes connected to semiconductor elements has been known (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, even with the prior art such as Patent Document 1, there is still room for improvement in the technology for improving the corrosion resistance of substrates for mounting semiconductor elements.

[0005] An object of the present invention is to provide a technology for improving the corrosion resistance of a substrate for mounting semiconductor elements.

Means for Solving the Problems

[0006] The present invention has been made to solve at least a part of the above problems and can be realized in the following forms.

[0007] (1) According to one aspect of the present invention, a substrate for mounting semiconductor elements is provided. This substrate for mounting semiconductor elements includes a base material, an electrode connected to a semiconductor element, an insulating layer disposed between the base material and the electrode and formed of aluminum nitride, a protective layer disposed between the insulating layer and the electrode, and a titanium layer disposed between the protective layer and the electrode and formed of titanium. The protective layer is formed of a material having higher corrosion resistance to both a titanium etching solution and warm water than the insulating layer.

[0008] In this configuration, the protective layer placed between the insulating layer and the electrode is made of a material that has higher corrosion resistance to both titanium etching solution and hot water than the insulating layer. This suppresses corrosion of the insulating layer by the titanium etching solution and hot water used in the etching process of the titanium layer during the manufacturing of semiconductor device mounting substrates. Therefore, the corrosion resistance of the semiconductor device mounting substrate can be improved.

[0009] (2) In the semiconductor element mounting substrate of the above form, the protective layer may be amorphous. With this configuration, since the protective layer is amorphous, cracks are less likely to occur than in a crystalline material having cleavage planes. This makes it possible to suppress the occurrence of cracks caused by stress generated by differences in thermal expansion within the semiconductor element mounting substrate.

[0010] (3) In the semiconductor element mounting substrate of the above configuration, the thickness of the protective layer may be 10 nm or more and 1 μm or less. With this configuration, the thickness of the protective layer is 10 nm or more and 1 μm or less, which is relatively thin. This makes it possible to suppress the decrease in thermal conductivity between the substrate and the electrode in the semiconductor element mounting substrate. Therefore, the corrosion resistance of the semiconductor element mounting substrate can be improved without reducing the thermal conductivity of the semiconductor element mounting substrate.

[0011] (4) In the semiconductor element mounting substrate of the above configuration, the protective layer may be formed mainly of one of Al2O3, SiN, Y2O3, ZrO2, SiO2, ZnO, or SiC. With this configuration, the protective layer is formed mainly of one of Al2O3, SiN, Y2O3, ZrO2, SiO2, ZnO, or SiC, which have relatively high corrosion resistance. Here, the "main component" of the protective layer refers to the component that is present in the protective layer at a concentration of 50% by mass or more. This makes it possible to improve the corrosion resistance of the semiconductor element mounting substrate.

[0012] (5) In the semiconductor element mounting substrate of the above configuration, the protective layer is formed of Al2O3, and the oxygen atom content on the surface of the protective layer may be 60 atm% or more. With this configuration, the protective layer formed of Al2O3 has an oxygen atom content of 60 atm% or more on its surface. As a result, aluminum atoms are less likely to be exposed on the surface of the protective layer, and the corrosion resistance of the protective layer can be further improved. Therefore, the corrosion resistance of the semiconductor element mounting substrate can be improved.

[0013] (6) In the semiconductor element mounting substrate of the above configuration, the substrate may be made of a metal having a melting point of 1200°C or lower. With this configuration, since the insulating layer is covered by a protective layer, the process of forming a protective film on the surface by oxidizing the surface of the insulating layer at 1000°C or higher is unnecessary. As a result, the substrate can be made of a metal with a relatively low melting point, thus expanding the types of materials that can be applied to the substrate.

[0014] Furthermore, the present invention can be realized in various forms, for example, in the form of a substrate having an insulating layer, a product including a substrate for mounting semiconductor elements, a semiconductor package including a substrate for mounting semiconductor elements, a method for manufacturing the substrate for mounting semiconductor elements and the semiconductor package. [Brief explanation of the drawing]

[0015] [Figure 1] This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the first embodiment. [Figure 2] This is the first diagram illustrating a method for manufacturing a substrate for mounting semiconductor devices. [Figure 3] This is the second figure illustrating a method for manufacturing a substrate for mounting semiconductor devices. [Figure 4] This is the third figure illustrating a method for manufacturing a substrate for mounting semiconductor devices. [Modes for carrying out the invention]

[0016] <First Embodiment> Figure 1 is a schematic cross-sectional view of a semiconductor element mounting substrate 1 according to the first embodiment. In this embodiment, the semiconductor element mounting substrate 1 supports optical semiconductors such as light-emitting diodes (LEDs) and laser diodes (LDs) as semiconductor elements 5 via electrodes 70, and functions as a heat dissipation substrate that releases heat generated during light emission to the outside. The semiconductor element mounting substrate 1 comprises a base material 10, an adhesion layer 20, an insulating layer 30, a protective layer 40, a titanium layer 50, a seed layer 60, and electrodes 70. Note that the thickness relationships of the base material 10, adhesion layer 20, insulating layer 30, protective layer 40, titanium layer 50, seed layer 60, and electrodes 70 in Figure 1 are shown differently from the actual thickness relationships for the sake of explanation.

[0017] The base material 10 is a flat plate-shaped component that serves as the base for the semiconductor element mounting substrate 1. In this embodiment, the thickness of the base material 10 is, for example, 1 mm. The base material 10 is made of a metal having a melting point of 1200°C or lower. In this embodiment, the base material 10 is made of copper (Cu). The base material 10 may be made of a material mainly composed of copper, aluminum (Al), or a material mainly composed of aluminum. Here, "main component" refers to a component that is present in 50% by mass or more of the components contained in the component in question. The base material 10 may be made of an alloy of copper and aluminum. By making the base material 10 from these metals, the heat generated in the semiconductor element 5 can be efficiently released to the outside through the base material 10.

[0018] The adhesion layer 20 is positioned between the substrate 10 and the insulating layer 30. In this embodiment, the adhesion layer 20 is made of titanium (Ti). The thickness of the adhesion layer 20 is, for example, 0.5 μm. The adhesion layer 20 adheres the substrate 10 and the insulating layer 30 to each other and suppresses the occurrence of cracks in the insulating layer 30 due to the difference in thermal expansion coefficients between the substrate 10 and the insulating layer 30. The material forming the adhesion layer 20 is not limited to titanium, but may be chromium (Cr), molybdenum (Mo), copper, etc., which have good adhesion to the insulating layer. It is desirable that the thermal expansion coefficient of the material forming the adhesion layer 20 is between the thermal expansion coefficient of the material forming the substrate 10 and the thermal expansion coefficient of the material forming the insulating layer 30.

[0019] The insulating layer 30 is positioned between the substrate 10 and the electrode 70. In the semiconductor element mounting substrate 1 of this embodiment, as shown in Figure 1, the insulating layer 30 is positioned between the adhesion layer 20 and the protective layer 40. The insulating layer 30 is made of aluminum nitride (AlN), which has excellent thermal conductivity. The insulating layer 30 insulates the substrate 10 from the electrode 70. The thickness of the insulating layer 30 is, for example, 3 μm.

[0020] The protective layer 40 is disposed between the insulating layer 30 and the electrode 70. In the substrate 1 for mounting a semiconductor element of the present embodiment, as shown in FIG. 1, the protective layer 40 is disposed between the insulating layer 30 and the titanium layer 50. The protective layer 40 is formed of a material having higher corrosion resistance to both the titanium etching solution and warm water than the insulating layer 30. Here, the "titanium etching solution" is a liquid capable of etching the titanium layer 50 described later, and examples thereof include an etching solution containing hydrogen peroxide and tetramethylammonium hydroxide, an etching solution containing hydrogen peroxide and ammonium bifluoride, an etching solution containing hydrogen peroxide and ammonia, an etching solution containing ammonium fluoride and methanesulfonic acid, an etching solution containing hydrogen peroxide and organic acid ammonium, and the like. The "warm water" is, for example, deionized water at 30°C to 60°C used for cleaning the substrate 1 for mounting a semiconductor element after etching with the titanium etching solution. The superiority or inferiority of the corrosion resistance of the aluminum nitride forming the insulating layer 30 and the protective layer 40 to both the titanium etching solution and warm water is determined using the results of chemical treatment with the titanium etching solution and cleaning treatment with warm water. Specifically, for each of the insulating layer 30 and the protective layer 40, which are thin films of aluminum nitride, the surfaces before and after each of the chemical treatment with the titanium etching solution and the cleaning treatment with warm water are imaged at a magnification of 10,000 times using a scanning electron microscope (SEM), and the imaged images are visually observed to determine the superiority or inferiority of the corrosion resistance.

[0021] The protective layer 40 is formed mainly of any one of Al2O3, SiN, Y2O3, ZrO2, SiO2, ZnO, and SiC. Here, the "main component of the protective layer 40" refers to a component contained in the protective layer 40 and contained at 50% by mass or more. The protective layer 40 of the present embodiment is formed mainly of Al2O3. The composition of the material forming the protective layer 40 can be confirmed using an electron diffraction pattern. Note that the material forming the protective layer 40 is not limited to these.

[0022] The protective layer 40 of this embodiment is amorphous. Whether the protective layer 40 is amorphous can be determined by using the electron diffraction pattern of the cross-section of the protective layer 40 obtained by the electron beam diffraction method. Since the protective layer 40 is amorphous, cracks are less likely to occur than in the crystalline state. Thereby, the occurrence of cracks caused by the stress generated by the thermal expansion difference in the substrate 1 for mounting semiconductor elements can be suppressed.

[0023] The thickness of the protective layer 40 is 10 nm or more and 1 μm or less. By setting the thickness of the protective layer 40 to 10 nm or more, it can be confirmed that the surface of the insulating layer 30 is surely covered by the protective layer 40. By setting the thickness of the protective layer 40 to 1 μm or less, a decrease in the thermal conductivity between the base material 10 and the electrode 70 in the substrate 1 for mounting semiconductor elements can be suppressed. The thickness of the protective layer 40 of this embodiment is 0.5 μm. The thickness of the protective layer 40 can be measured using a cross-sectional photograph of the substrate 1 for mounting semiconductor elements taken by a scanning electron microscope or the like.

[0024] In this embodiment, the content rate of oxygen atoms on the surface of the protective layer 40 formed of Al2O3 is 60 atm% or more. When the content rate of oxygen atoms on the surface of the protective layer 40 becomes 60 atm% or more, it becomes difficult for aluminum atoms to be exposed on the surface of the protective layer 40. Thereby, the corrosion resistance of the protective layer 40 can be further improved. The content rate of oxygen atoms on the surface of the protective layer 40 can be measured using X-ray photoelectron spectroscopy (XPS).

[0025] The titanium layer 50 is disposed between the protective layer 40 and the electrode 70. In the substrate 1 for mounting semiconductor elements of this embodiment, as shown in FIG. 1, the titanium layer 50 is disposed between the protective layer 40 and the seed layer 60. The titanium layer 50 is formed of titanium and improves the adhesion between the protective layer 40 and the seed layer 60. The thickness of the titanium layer 50 is, for example, 0.2 μm.

[0026] As shown in Figure 1, the seed layer 60 is positioned between the titanium layer 50 and the electrode 70. The seed layer 60 is made of palladium (Pd). The seed layer 60 improves the bonding strength between the titanium layer 50, which is made of titanium, and the electrode 70, which is made of gold. The thickness of the seed layer 60 is, for example, 0.1 μm.

[0027] The electrode 70 is formed on the seed layer 60 and connected to the semiconductor element 5. The electrode 70 is made of gold (Au). The electrode 70 has a predetermined pattern shape so as to connect to a predetermined location on the semiconductor element 5 on which it is mounted. The material used to form the electrode 70 is not limited to gold, but may be made of copper. The thickness of the electrode 70 is, for example, 3.0 μm.

[0028] Next, the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment will be described. In the manufacturing of the semiconductor element mounting substrate 1, first, the material that will become the base material 10 is pre-treated. Specifically, a plate-shaped rolled copper is prepared. After the surface of the prepared rolled copper is mirror-polished, nickel or the like, which has resistance to gold etching solution, is plated onto the mirror-polished surface. As a result, the manufactured base material 10 becomes less susceptible to oxidation and its corrosion resistance is improved. Note that instead of mirror polishing, chemical polishing may be used for the surface treatment of the prepared rolled copper.

[0029] Figure 2 is the first diagram illustrating the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment. Figure 2 shows a cross-sectional view of the substrate 1a in which multiple layers have been deposited on the substrate 10. Following the pretreatment of the material that will become the substrate 10, an adhesion layer 20 and an insulating layer 30 are deposited. The adhesion layer 20 is deposited on the surface of the fabricated substrate 10 by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The insulating layer 30 is deposited on the surface of the adhesion layer 20 by reactive sputtering. The insulating layer 30 is deposited by using Al as the target and flowing argon (Ar) and nitrogen (N2) under a vacuum of 0.1 to 0.8 Pa while maintaining the temperature of the substrate 10 at 100 to 300°C.

[0030] Next, a protective layer 40 is formed on the insulating layer 30. In the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment, the protective layer 40 is formed by a physical vapor deposition (PVD) method such as sputtering with Al2O3 as the target and argon as the atmospheric gas, with the deposition temperature set to less than 300°C. As a result, the protective layer 40 becomes amorphous alumina. The method of forming the protective layer 40 is not limited to this, and the protective layer 40 may also be formed by electroplating, which can make the protective layer 40 amorphous. As a method for making the oxygen atom content on the surface of the protective layer 40 60 atm% or more, examples include a method of changing the amount of oxygen atoms by applying an RF bias during sputtering, and a method of immersing the alumina film in hot water to make the surface of the alumina film have a large amount of oxygen atoms.

[0031] Next, a titanium film 50a, which will become the titanium layer 50, a palladium film 60a, which will become the seed layer 60, and a gold film 70a, which will become the electrode 70, are deposited in order on the protective layer 40 (see Figure 2). The titanium film 50a is deposited by sputtering targeting Ti. The palladium film 60a is deposited by sputtering targeting Pd. The gold film 70a is deposited, for example, by electroplating. The gold film may also be deposited by sputtering or vapor deposition.

[0032] Figure 3 is a second diagram illustrating the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment. Figure 3 is a cross-sectional view of the substrate 1b in which the electrodes 70 and seed layer 60 have been formed, from the state shown in Figure 2. After the formation of the gold film 70a, electrode patterning is performed. Specifically, for example, the gold film 70a is coated with resist by forming a dry film resist in a laminator, and a resist pattern is formed by exposure and development. Next, using the resist pattern as a mask, the gold film 70a and a part of the palladium layer 70b are removed by etching. As a result, the electrodes 70 and seed layer 60 are formed as shown in Figure 3 (see Figure 3). The resist is removed with a stripping solution.

[0033] Figure 4 is a third diagram illustrating the manufacturing method of the semiconductor device mounting substrate 1 according to this embodiment. After the resist is removed, a titanium layer 50 is formed. Specifically, the titanium film 50a is etched using a titanium etching solution with a patterned electrode 70 as a mask. When etching the titanium film 50a, the titanium etching solution may come into contact with the protective layer 40 formed directly beneath the titanium film 50a. However, since the protective layer 40 is made of a material with relatively high corrosion resistance to the titanium etching solution, it is difficult to etch with the titanium etching solution. As a result, contact between the titanium etching solution and the insulating layer 30 is suppressed, and corrosion of the insulating layer 30 by the titanium etching solution can be suppressed. After the titanium layer 50 is formed by etching the titanium film 50a with the titanium etching solution, it is washed with hot water. This completes the manufacturing of the semiconductor device mounting substrate 1. Note that the manufacturing method of the semiconductor device mounting substrate 1 is not limited to these.

[0034] As described above, in the semiconductor element mounting substrate 1 of this embodiment, the protective layer 40 disposed between the insulating layer 30 and the electrode 70 is formed of a material that has higher corrosion resistance to both titanium etching solution and hot water than the insulating layer 30. This makes it possible to suppress corrosion of the insulating layer 30, which is made of aluminum nitride, by the titanium etching solution and hot water used in the etching process of the titanium layer 50 during the manufacturing of the semiconductor element mounting substrate 1. Therefore, the corrosion resistance of the semiconductor element mounting substrate 1 can be improved.

[0035] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, a protective layer 40 with relatively high corrosion resistance to hot water is formed on the surface of the insulating layer 30. As a result, even if the semiconductor element mounting substrate 1 is exposed to water during actual use, the insulating layer 30 does not come into contact with the water, thus suppressing corrosion of the insulating layer 30 due to water exposure. Therefore, the corrosion resistance of the semiconductor element mounting substrate 1 in actual use can be improved as an environmental resistance performance.

[0036] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, the protective layer 40 is amorphous, making it less prone to cracking than a crystalline material. This makes it possible to suppress the occurrence of cracks caused by stress generated by differences in thermal expansion within the semiconductor element mounting substrate 1.

[0037] Furthermore, in the semiconductor element mounting substrate 1 of this embodiment, the thickness of the protective layer 40 is 10 nm to 1 μm, which is relatively thin. This makes it possible to suppress a decrease in thermal conductivity between the substrate 10 and the electrode 70 in the semiconductor element mounting substrate 1. Therefore, the corrosion resistance of the semiconductor element mounting substrate 1 can be improved without reducing the thermal conductivity of the semiconductor element mounting substrate 1.

[0038] Furthermore, in the semiconductor element mounting substrate 1 of this embodiment, the protective layer 40 is formed mainly of Al2O3, which has relatively high corrosion resistance. This improves the corrosion resistance of the semiconductor element mounting substrate 1.

[0039] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, the oxygen atom content on the surface of the protective layer 40, which is formed of Al2O3, is 60 atm% or more. As a result, aluminum atoms are less likely to be exposed on the surface of the protective layer 40, and the corrosion resistance of the protective layer 40 can be further improved. Therefore, the corrosion resistance of the semiconductor element mounting substrate 1 can be improved.

[0040] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, since the insulating layer 30 is covered by the protective layer 40, the process of forming a protective film on the surface by oxidizing the surface of the insulating layer 30 at 1000°C or higher becomes unnecessary. As a result, the base material 10 can be formed from a metal with a relatively low melting point, thereby expanding the types of materials that can be applied to the base material 10.

[0041] <Modified form of this embodiment> The present invention is not limited to the embodiments described above, and can be implemented in various forms without departing from its spirit, for example, the following modifications are also possible.

[0042] [Example 1] In the above-described embodiment, the semiconductor element mounting substrate 1 comprises a base material 10, an adhesion layer 20, an insulating layer 30, a protective layer 40, a titanium layer 50, a seed layer 60, and an electrode 70. However, the configuration of the semiconductor element mounting substrate is not limited to this. It may also comprise a base material, an electrode connected to a semiconductor element, an insulating layer disposed between the base material and the electrode and formed of aluminum nitride, a protective layer disposed between the insulating layer and the electrode, and a titanium layer disposed between the protective layer and the electrode and formed of titanium.

[0043] [Differentiation 2] In the above-described embodiment, the protective layer 40 was amorphous. The protective layer may be crystalline, but if it is amorphous, there are no crystal planes that are prone to becoming cleavage planes, so it is less prone to cracking than a crystalline film with a crystal orientation.

[0044] [Difference 3] In the above-described embodiment, the thickness of the protective layer 40 was set to be between 10 nm and 1 μm. However, the thickness of the protective layer is not limited to these values. By making the protective layer 1 μm or less in thickness, the thickness between the substrate and the electrode is reduced, which can suppress a decrease in thermal conductivity between the substrate and the electrode in the semiconductor device mounting substrate.

[0045] [Differentiation Example 4] In the above-described embodiment, the protective layer 40 is formed mainly of Al2O3, and the oxygen atom content on the surface is 60 atm% or more. The material forming the protective layer and the atom content are not limited to this.

[0046] [Difference 5] In the above-described embodiment, the semiconductor element 5 mounted on the semiconductor element mounting substrate was described as a light-emitting diode or a semiconductor laser, but it is not limited to these. It may also be a power semiconductor or the like, which generates a relatively large amount of heat.

[0047] The embodiments of this specification have been described above based on the embodiments and modifications described above. The embodiments described above are for the purpose of facilitating understanding of this specification and do not limit it. This specification may be modified and improved without departing from its spirit and the scope of the claims, and equivalents thereof are included in this specification. Furthermore, any technical features that are not described as essential in this specification may be deleted as appropriate.

[0048] (Application Example 1) A substrate for mounting semiconductor devices, Substrate and semiconductor element cross-electrode, An insulating layer, formed of aluminum nitride, is disposed between the substrate and the electrode. A protective layer disposed between the insulating layer and the electrode, The protective layer and the electrode are disposed between them and a titanium layer formed of titanium, The protective layer is characterized by being formed of a material that has higher corrosion resistance to both titanium etching solution and hot water than the insulating layer. A substrate for mounting semiconductor devices. (Application Example 2) A semiconductor element mounting substrate as described in Application Example 1, The protective layer is characterized by being amorphous. A substrate for mounting semiconductor devices. (Application Example 3) A semiconductor element mounting substrate as described in Application Example 1 or Application Example 2, The thickness of the protective layer is characterized by being 10 nm or more and 1 μm or less. A substrate for mounting semiconductor devices. (Application Example 4) A semiconductor element mounting substrate as described in any one of Application Examples 1 to 3, The protective layer is characterized by being formed primarily from one of the following: Al2O3, SiN, Y2O3, ZrO2, SiO2, ZnO, and SiC. A substrate for mounting semiconductor devices. (Application Example 5) A semiconductor element mounting substrate as described in any one of Application Examples 1 to 4, The protective layer is formed of Al2O3, The oxygen atom content on the surface of the protective layer is characterized by being 60 atm% or more. A substrate for mounting semiconductor devices. (Application Example 6) A semiconductor element mounting substrate as described in any one of Application Examples 1 to 5, The aforementioned substrate is characterized by being formed from a metal having a melting point of 1200°C or lower. A substrate for mounting semiconductor devices. [Explanation of symbols]

[0049] 1…Substrate for mounting semiconductor devices 10...Base material 30…Insulating layer 40...Protective layer 50…Titanium layer 70...Electrode

Claims

1. A substrate for mounting semiconductor devices, Substrate and semiconductor element cross-electrode, An insulating layer, formed of aluminum nitride, is disposed between the substrate and the electrode. A protective layer disposed between the insulating layer and the electrode, The protective layer and the electrode are disposed between them and a titanium layer formed of titanium, The protective layer is characterized by being formed of a material that has higher corrosion resistance to both titanium etching solution and hot water than the insulating layer. A substrate for mounting semiconductor devices.

2. A semiconductor element mounting substrate according to claim 1, The protective layer is characterized by being amorphous. A substrate for mounting semiconductor devices.

3. A substrate for mounting semiconductor elements according to claim 1 or claim 2, The thickness of the protective layer is characterized by being 10 nm or more and 1 μm or less. A substrate for mounting semiconductor devices.

4. A substrate for mounting semiconductor elements according to claim 1 or claim 2, The aforementioned protective layer is Al 2 O 3 ,SIN,Y 2 O 3 , ZrO 2 , SiO 2 It is characterized by being formed mainly from one of ZnO or SiC. A substrate for mounting semiconductor devices.

5. A substrate for mounting semiconductor elements according to claim 1 or claim 2, The aforementioned protective layer is Al 2 O 3 It is formed by, The oxygen atom content on the surface of the protective layer is characterized by being 60 atm% or more. A substrate for mounting semiconductor devices.

6. A substrate for mounting semiconductor elements according to claim 1 or claim 2, The substrate is characterized by being formed from a metal having a melting point of 1200°C or lower. A substrate for mounting semiconductor devices.

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