High-thermal-conductivity and high-current-resistant multilayer circuit board preparation method and circuit board

Abstract

The invention provides a high-thermal-conductivity and high-current-resistant multilayer circuit board preparation method and a circuit board, and the method comprises the steps: providing a first metal substrate, preparing a hollow pattern on the first metal substrate to obtain a metal pattern substrate, and stacking a layer of insulating blank board on each of the upper surface and the lower surface of the metal pattern substrate to form a first board body; a layer of second metal substrate is laminated on each of the upper surface and the lower surface of the first plate body to form a second plate body; laminating the second plate body to embed the metal pattern substrate in the second plate body into the insulating green plate to obtain a third plate body; the third plate body is positioned and sintered in the manufacturing tool pressing plate, and a fourth plate body with an embedded metal structure is obtained; and performing graphical processing on the first metal layer and the second metal layer on the surface of the fourth board body to form a surface circuit, thereby obtaining a target circuit board, and further realizing cooperative improvement of the multi-layer circuit board in large current bearing, high-voltage breakdown resistance and high heat conduction efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, and the circuit board itself. Background Technology

[0002] Traditional multilayer circuit boards are mainly fabricated using organic resin substrates (such as FR-4) through lamination and chemical copper plating processes. The layers are bonded together using prepreg and electrically interconnected via metallized vias. This type of structure has inherent limitations in high-frequency, high-power applications: organic resins have extremely low thermal conductivity (typically <0.5 W / mK), leading to heat accumulation and failing to meet heat dissipation requirements under high current; their interlayer dielectric strength is limited, making them prone to dielectric breakdown under high voltages (e.g., up to 1200KV in high-speed rail systems); and the interconnect interfaces formed by soldering or lamination are susceptible to fatigue failure under long-term high-current thermal cycling. Although direct copper-clad ceramic substrates improve thermal conductivity and voltage resistance, they are only single-layer or double-layer structures, making it difficult to achieve complex multilayer interconnects, and the metal layers are typically thin, limiting current carrying capacity.

[0003] Therefore, existing technologies struggle to fabricate highly reliable multilayer circuit boards that combine excellent vertical insulation, high horizontal thermal diffusion and current conduction capabilities, and complex three-dimensional interconnection structures. This has become a key technological bottleneck restricting the performance and reliability of high-voltage, high-power electronic systems (such as traction converters in high-speed railways and high-voltage direct current transmission). Summary of the Invention

[0004] The main objective of this application is to propose a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, and a circuit board that can achieve a synergistic improvement in high current carrying capacity, high voltage breakdown resistance, and high thermal conductivity, thereby solving the reliability bottleneck of high-power power electronic modules in extreme electrical environments.

[0005] To achieve the above objectives, a first aspect of this application proposes a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, comprising: A first metal substrate is provided, and a hollow pattern is formed on the first metal substrate to obtain a metal pattern substrate. An insulating green board is stacked on the upper and lower surfaces of the metal pattern substrate to form the first plate of the sandwich structure; A second metal substrate is stacked on the upper and lower surfaces of the first plate to form a second plate. The second plate is pressed to embed the metal pattern substrate inside the second plate into the insulating green plate to obtain the third plate. The third plate includes an embedded layer, a first metal layer above the embedded layer, and a second metal layer below the embedded layer. The embedded layer includes a metal pattern substrate and an insulating green plate. The insulating green plate deforms and fills into the hollow pattern of the metal pattern substrate under the pressing action. The third plate is positioned and sintered in the mold plate to densify the insulating green plate, and the metal pattern substrate is sintered together with the insulating green plate, the first metal layer and the second metal layer to obtain the fourth plate with an embedded metal structure. The first and second metal layers on the surface of the fourth board are patterned to form surface circuits, thus obtaining the target circuit board.

[0006] Furthermore, in some embodiments, the first metal layer and the second metal layer on the surface of the fourth board are patterned to form surface circuits to obtain the target circuit board, including: The first metal layer on the upper surface of the fourth plate and the second metal layer on the lower surface are made to form a conductive connection, thus obtaining the fifth plate. Patterning is performed on the first and second metal layers on the surface of the fifth board to obtain the target circuit board.

[0007] Furthermore, in some embodiments, a fifth plate is obtained by making the first metal layer on the upper surface of the fourth plate and the second metal layer on the lower surface conductive, including: A through-hole is prepared on the fourth plate, the through-hole exposing the area to be connected in the first metal layer and / or the second metal layer; A conductor is formed in the through hole of the fourth plate to electrically connect the first metal layer and the second metal layer, thus obtaining the fifth plate.

[0008] Furthermore, in some embodiments, the first metal layer and the second metal layer on the surface of the fifth board are patterned to obtain the target circuit board, including: Patterned resist layers are formed on the first metal layer and the second metal layer on the surface of the fifth plate. The resist layers are used to define the line areas to be retained on the surface of the fifth plate. Using the resist layer as a barrier, the metal areas not covered by the resist layer are selectively removed within the first and second metal layers to obtain the sixth plate. The resist layer is removed from the sixth board to form the target circuit board with interconnect pattern.

[0009] Furthermore, in some embodiments, an insulating green plate is stacked on the upper and lower surfaces of the metal pattern substrate to obtain a first plate body, including: coating or printing a first adhesive medium layer on the upper and lower surfaces of the metal pattern substrate, and pasting the insulating green plate on the first adhesive medium layer to form the first plate body; The method of stacking a second metal substrate on the upper and lower surfaces of the first plate to form a second plate includes: coating or printing a second adhesive medium layer on the upper and lower surfaces of the first plate, and attaching the second metal substrate on the second adhesive medium layer to form the second plate.

[0010] Furthermore, in some embodiments, the first or second adhesive medium layer comprises a thermally decomposable organic polymer or a metal oxide powder.

[0011] Furthermore, in some embodiments, the metal material of the metal substrate includes at least one of the following: copper, copper alloy, aluminum, aluminum alloy; wherein the metal material of the metal oxide powder is consistent with the metal material of the first metal substrate or the second metal substrate.

[0012] Furthermore, in some embodiments, the insulating green board is a ceramic green board, and the insulating green board contains at least one of the following materials: alumina, silicon oxide, boron oxide, aluminum nitride, silicon nitride, and boron nitride.

[0013] Furthermore, in some embodiments, the hollow pattern on the metal substrate includes at least one of the following: through-hole array, mesh structure or preset line channel, and the hollow pattern is prepared by one of the following methods: etching, laser cutting, stamping or mechanical drilling.

[0014] To achieve the above objectives, a second aspect of the present application provides a circuit board manufactured by the multilayer circuit board preparation method of the first aspect.

[0015] The embodiments of this application have the following beneficial effects: By using a metal patterned substrate as an embedded conductive and thermally conductive framework, the metal framework provides a planar current path with extremely low resistance, capable of carrying large currents of hundreds of amperes (above 600A). Simultaneously, its planar current path can rapidly diffuse the heat generated by the chip laterally, greatly reducing the temperature under high current conditions. Secondly, by pressing an insulating green board into the hollow areas of the metal pattern and co-firing it to achieve densification, an insulating region is formed. This insulating region and the metal region are microscopically interlocked, and their bonding surface does not require organic adhesives, thereby achieving extremely high interlayer dielectric strength and breakdown voltage. The voltage is sufficient to withstand extreme high-voltage environments of 1200KV and above. Furthermore, the integrated lamination and sintering process enables the metal layer and insulating layer to form a strong metallurgical or chemical bond at the interface, reducing the risk of delamination and interface thermal resistance in traditional circuit boards. Finally, this method is also compatible with high-precision patterning on the surface metal layer of the sintered board and can be extended to more layers of embedded metal structure, realizing the multi-layer three-dimensional packaging capability of integrating high-power circuits, communication control circuits and heat dissipation channels in a single substrate. It is particularly suitable for power electronic modules in fields such as high-speed rail and new energy vehicles that require high power density, high withstand voltage and long life. Attached Figure Description

[0016] Figure 1 This is a flowchart of a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, provided in some embodiments of this application; Figure 2 This is a cross-sectional view of a metal patterned substrate provided in some embodiments of this application; Figure 3 This is a cross-sectional view of the formation of the first plate body provided in some embodiments of this application; Figure 4 This is a cross-sectional view of the formation of the second plate body provided in some embodiments of this application; Figure 5 This is a cross-sectional view of the formation of the third plate body provided in some embodiments of this application; Figure 6 This is a cross-sectional view of the fourth plate body provided in some embodiments of this application; Figure 7 This is a cross-sectional view of the third plate body within the fixture pressure plate provided in some embodiments of this application; Figure 8 This is a cross-sectional view of the target circuit board provided in some embodiments of this application; Figure 9 This is provided by some embodiments of this application. Figure 1 Flowchart of step S106; Figure 10 This is a cross-sectional view of the fifth plate body provided in some embodiments of this application; Figure 11This is provided by some embodiments of this application. Figure 9 Flowchart of step S201; Figure 12 This is provided by some embodiments of this application. Figure 9 Flowchart of step S202; Figure 13 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application.

[0017] Figure description: 10 metal patterned substrate, 20 insulating green plate, 30 second metal substrate, 40 embedded layer, 50 fixture pressure plate. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] It should also be noted that in the description of this application, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. If the terms "first" and "second" are used, they are only for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0023] Traditional multilayer circuit boards are mainly fabricated using organic resin substrates through lamination and chemical copper plating. Interlayer bonding relies on prepregs, and electrical interconnection is achieved through metallized vias. This type of structure has inherent limitations in high-frequency, high-power applications: organic resins have extremely low thermal conductivity (typically <0.5 W / mK), leading to heat accumulation and failing to meet heat dissipation requirements under high current; their interlayer dielectric strength is limited, making them prone to dielectric breakdown under high voltages (e.g., up to 1200KV in high-speed rail systems); and the interconnect interfaces formed by soldering or lamination are susceptible to fatigue failure under long-term high-current thermal cycling. Although direct copper-clad ceramic substrates improve thermal conductivity and voltage resistance, they are only single-layer or double-layer structures, making it difficult to achieve complex multilayer interconnections, and the metal layers are typically thin, limiting current carrying capacity.

[0024] Furthermore, during the development of high-power-density modules for extreme electrical environments such as high-speed rail traction systems, prototype testing using a conventional multilayer PCB solution revealed severe dielectric breakdown and thermal failure under currents exceeding 600A and voltage pulses of 1200KV. Further analysis revealed the following problems: Firstly, a thick copper layer (>300μm) is required to carry the high current, but this leads to uneven resin filling and easy delamination between layers in the traditional prepreg lamination process. Secondly, increasing the thickness of the ceramic substrate to improve the withstand voltage rating drastically worsens the thermal resistance, causing the chip junction temperature to exceed the limit. To solve these problems, existing alternatives include: 1. Direct bonding of a copper-ceramic substrate, which, while having good thermal conductivity, cannot achieve multilayer wiring; 2. Using active metal to braze the ceramic substrate, but while this method can achieve multilayer wiring, the solder layer is prone to electromigration and insulation degradation under high temperature and high voltage. Therefore, the existing technology system has a structural bottleneck—the heat dissipation path, current channel and insulation barrier cannot work together efficiently in a multi-layer three-dimensional space. The functional layers are highly dependent on the intermediate bonding medium, which forms a weak link in thermal, electrical and mechanical properties. It is difficult to manufacture highly reliable multilayer circuit boards that have excellent vertical insulation, high horizontal thermal diffusion and current conduction capabilities, and complex three-dimensional interconnection structure. This has become a key technical bottleneck restricting the performance and reliability of high-voltage, high-power electronic systems (such as traction converters in high-speed railways and high-voltage direct current transmission).

[0025] Based on this, this application provides a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, as well as the circuit board itself. This fabrication method is not a simple improvement on existing processes, but rather a redefinition of the "function-structure-material-process" relationship of the circuit board. By transforming the traditional concept of a "circuit board as a wiring carrier" into a "miniaturized power electronic structural component," a "embedded metal skeleton" design is created. The thick metal substrate, which carries current and heat, is pre-processed into a hollow skeleton structure, allowing insulating ceramic material to flow under high pressure and fill the spaces. Then, through integrated sintering, they are fused into a coupled whole. The innovation lies in firstly, using the embedded metal patterned substrate as a continuous metal pathway, while simultaneously optimizing the current... Conductivity and in-plane heat diffusion resolve the contradiction between thick copper and multilayer structures. Secondly, the insulating green board forms a mechanically interlocked insulating barrier after filling the hollow areas. Its thickness is controllable and there is no interface bonding layer, which fundamentally eliminates the risk of surface discharge and delamination. Furthermore, the ceramic-insulating interface formed by sintering is a diffusion bond, and its thermomechanical stability is far superior to any bonded or brazed interface. This paradigm shift from "laminated composite" to "structural fusion" enables the three performance indicators that were originally mutually restrictive—high thermal conductivity, high current resistance, and high voltage resistance—to be synergistically achieved in the same structure.

[0026] This application provides a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, as well as the circuit board itself, which will be specifically described through the following embodiments.

[0027] Reference Figure 1 As shown, Figure 1 This is a flowchart of a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance provided in some embodiments of this application. The dual-layer packaging method of the circuit board may include, but is not limited to, steps S101 to S106.

[0028] Step S101: Provide a first metal substrate and prepare a hollow pattern on the first metal substrate to obtain a metal pattern substrate.

[0029] Furthermore, in some embodiments, the metal material of the first metal substrate includes at least one of the following: copper, copper alloy, aluminum, and aluminum alloy.

[0030] Specifically, a first metal substrate with high thermal conductivity and high electrical conductivity is first provided. Preferably, the first metal substrate can be a thick copper, copper alloy, or aluminum substrate with a thickness of 100 μm to 2 mm. Subsequently, a predetermined perforation pattern is formed on the metal substrate using a high-precision processing technique: typically a combination of photolithography and chemical etching, or direct laser cutting, or stamping, or mechanical drilling, to prepare a precise pattern including, but not limited to, through-hole arrays, mesh structures, or predetermined circuit channels. (Refer to...) Figure 2 As shown, Figure 2 This is a cross-sectional view of the metal patterned substrate provided in some embodiments of this application. The solid portion of the metal patterned substrate 10 obtained in this step will serve as the embedded conductive and heat-conducting skeleton in the subsequent circuit, while the hollow portion is reserved for filling with insulating ceramic material. It is a basic prefabricated component for realizing efficient current transmission, lateral heat diffusion, and ceramic-mechanical interlocking structure. As a core embedded layer, the design of this patterned metal substrate 10 directly determines the current distribution, heat dissipation path, and mechanical strength of the final circuit board.

[0031] Step S102: An insulating green plate is stacked on the upper and lower surfaces of the metal pattern substrate to form the first plate of the sandwich structure.

[0032] Reference Figure 3 As shown, Figure 3 This is a cross-sectional view of a first plate body provided in some embodiments of this application. The first plate body includes two insulating green plates 20, with a metal patterned substrate 10 sandwiched between the two insulating green plates 20.

[0033] In a preferred embodiment, the insulating green board 20 is a ceramic green board, and the insulating green board 20 contains at least one of the following materials: alumina, silicon oxide, boron oxide, aluminum nitride, silicon nitride, and boron nitride.

[0034] In a preferred embodiment, an insulating green plate 20 is laminated on the upper and lower surfaces of the metal pattern substrate 10 to obtain a first plate body. Specifically, the steps include: coating or printing a first adhesive medium layer on the upper and lower surfaces of the metal pattern substrate 10, and pasting the insulating green plate 20 on the first adhesive medium layer to form the first plate body.

[0035] In one embodiment, the first adhesive medium layer comprises a thermally decomposable organic polymer and a metal oxide powder. The metal oxide powder has the same metallic material as the first metal substrate.

[0036] Specifically, in step S102 above, before lamination, the bonding surfaces of the insulating green plate 20 and the metal pattern substrate 10 are typically plasma-cleaned or coated with an extremely thin first adhesive medium layer to enhance temporary bonding strength. Subsequently, in a precision alignment platform or mold, an insulating green plate 20 is first laid flat, and then the metal pattern substrate 10 is precisely placed in its central area, ensuring that the outline of the metal pattern substrate 10 maintains a specific margin with the edge of the first insulating green plate 20. Finally, a second insulating green plate 20 is placed on top. During this process, the key is to ensure the accurate relative position of the metal pattern substrate 10 and the upper and lower insulating green plates 20 without misalignment through optical alignment or physical positioning pins. The formed first plate is an unsintered, flexible composite sandwich structure in which the metal pattern substrate 10 is completely encapsulated, laying the foundation for the insulating material to flow into the metal cutout area under pressure and form a three-dimensional interlocking structure in the subsequent lamination step.

[0037] Step S103: A second metal substrate is stacked on the upper and lower surfaces of the first plate to form a second plate.

[0038] Reference Figure 4 As shown, Figure 4 This is a cross-sectional view of a second plate body provided in some embodiments of this application. The second plate body includes two insulating green plates 20, with a metal pattern substrate 10 sandwiched between the two insulating green plates 20. A second metal substrate 30 is stacked on the upper surface of the upper insulating green plate 20, and a second metal substrate 30 is stacked on the lower surface of the lower insulating green plate 20.

[0039] In a preferred embodiment, a second metal substrate 30 is stacked on the upper and lower surfaces of the first plate to form a second plate. Specifically, the steps include: coating or printing a second adhesive medium layer on the upper and lower surfaces of the first plate, and attaching the second metal substrate 30 to the second adhesive medium layer to form the second plate.

[0040] In one embodiment, the second adhesive medium layer comprises a thermally decomposable organic polymer and a metal oxide powder. The metal material of the metal oxide powder is consistent with the metal material of the second metal substrate.

[0041] Specifically, in step S103 above, before lamination, the bonding surface of the second metal substrate 30 (i.e., the side in contact with the first plate) needs to be roughened by micro-etching or coated with an extremely thin second adhesive dielectric layer to significantly enhance its initial adhesion to the green plate on the surface of the first plate. Subsequently, in a precision alignment system, the first plate is placed in the middle, and a processed second metal substrate 30 is placed on top and bottom. By using positioning holes pre-punched on the edge of the first plate and engaging with alignment pins, or by using an optical vision system to align preset alignment marks, the three-layer structure is precisely aligned, ensuring that the outer second metal substrate 30 completely covers the inner layer without any misalignment. The final second plate is an unsintered composite laminate composed of an outer metal layer, an intermediate insulating green layer, and an inner embedded metal pattern layer. The outer second metal substrate 30 will provide the original conductor material for subsequent surface patterning after sintering.

[0042] Step S104: The second plate is pressed to embed the metal pattern substrate in the second plate into the insulating green plate, thus obtaining the third plate.

[0043] Among them, reference Figure 5 As shown, Figure 5 This is a cross-sectional view of a third plate body provided in some embodiments of this application. The third plate body includes an embedded layer, a first metal layer (i.e., a second metal substrate 30) located above the embedded layer, and a second metal layer (i.e., a second metal substrate 30) located below the embedded layer. The embedded layer includes a metal pattern substrate 10 and an insulating green plate 20. The insulating green plate 20 deforms and fills into the hollow pattern of the metal pattern substrate 10 under the pressing action.

[0044] In practice, the second sheet is placed between the hot plates of a laminator or loaded into an isostatic pressing mold and pressed at a relatively low temperature (e.g., 50°C to 120°C) and a relatively high pressure (e.g., 5MPa to 20MPa). Under these mild heating conditions, the organic binder in the insulating green sheet 20 softens, causing it to exhibit a plastic flow dynamic; simultaneously, the applied uniform pressure drives the upper and lower soft insulating green sheets 20 to produce controllable deformation, flowing towards the central metal pattern substrate 10 and fully filling all its perforated patterns, thereby forming a tight mechanical wrapping and interlocking around the metal skeleton. This process effectively eliminates residual air between layers, significantly enhances the physical bonding strength between the metal pattern substrate 10 and the insulating green sheet 20, and presses the entire laminate into a tightly structured, uniformly thick third sheet.

[0045] Step S105: Position and sinter the third plate in the die plate to densify the insulating green plate, and sinter the metal pattern substrate, the insulating green plate, the first metal layer, and the second metal layer into one piece to obtain the fourth plate with an embedded metal structure.

[0046] Among them, reference Figure 6 As shown, Figure 6 This is a cross-sectional view of a fourth plate provided in some embodiments of this application. The fourth plate includes an embedded layer, a first metal layer (i.e., a second metal substrate 30) located above the embedded layer, and a second metal layer (i.e., a second metal substrate 30) located below the embedded layer. The embedded layer includes a metal pattern substrate 10 and an insulating green plate 20, which are bonded to each other.

[0047] Specifically, refer to Figure 7 As shown, Figure 7 This is a cross-sectional view of the third plate provided in some embodiments of this application within a fixture pressure plate. First, the pre-pressed third plate is precisely installed into a dedicated high-temperature sintering fixture pressure plate 50. The graphite positioning pins on the fixture pressure plate 50 engage with the positioning holes on the edge of the plate to achieve precise positioning and constraint in three-dimensional space. Then, it is clamped and fixed by the upper and lower pressure plates with high flatness. This entire assembly is placed in a sintering furnace with a multi-atmosphere controllable atmosphere (usually nitrogen or argon) and processed according to a precisely set temperature-pressure curve: in the low-temperature stage (300-500°C), the organic binder in the insulating green plate 20 is fully decomposed and volatilized (removed adhesive) at a slow heating rate to avoid internal defects; then, the temperature is raised to the sintering temperature of the insulating green plate 20 (1600-1800°C), and a certain downward pressure is applied simultaneously. Under this high temperature and pressure, the ceramic powder particles in the insulating green plate 20 undergo melting diffusion and grain growth, achieving complete densification. Simultaneously, the metal layer (metal patterned substrate 10 and the second metal substrate 30 as the first metal layer, and the second metal substrate 30 as the second metal layer) and the densified ceramic form a strong metallurgical or chemical bond at the interface through atomic diffusion. The fourth plate obtained after final cooling has its embedded metal structure and ceramic insulating layer integrated, possessing extremely high thermal conductivity, mechanical strength, and interlayer insulation reliability.

[0048] Step S106: The first and second metal layers on the surface of the fourth board are patterned to form surface circuits, thus obtaining the target circuit board.

[0049] Among them, reference Figure 8 As shown, Figure 8 This is a cross-sectional view of a target circuit board provided in some embodiments of this application. The target circuit board includes an embedded layer, a first metal layer (i.e., a second metal substrate 30) located above the embedded layer, and a second metal layer (i.e., a second metal substrate 30) located below the embedded layer. The first metal layer and the second metal layer are interconnected and patterned. The embedded layer includes a metal pattern substrate 10 and an insulating green board 20. The insulating green board 20 and the metal pattern substrate 10 are bonded to each other.

[0050] It should be noted that during steps S101 to S106, the metal patterned substrate 10 is used as an embedded conductive and thermally conductive framework. This metal framework provides a planar current path with extremely low resistance, capable of carrying large currents of hundreds of amperes (above 600A). Simultaneously, its planar current path can rapidly diffuse the heat generated by the chip laterally, greatly reducing the temperature under high current conditions. Secondly, by pressing the insulating green board 20 into the hollow areas of the metal patterned substrate 10 and co-firing it to achieve densification, an insulating region is formed. This insulating region and the metal region are microscopically interlocked, and their bonding surface does not require organic adhesives, thereby achieving extremely high layer density. The dielectric strength and breakdown voltage are sufficient to withstand extreme high-voltage environments of 1200KV and above. Furthermore, the integrated lamination and sintering process enables the metal layer and insulating layer to form a strong metallurgical or chemical bond at the interface, reducing the risk of delamination and interface thermal resistance in traditional circuit boards. Finally, this method is also compatible with high-precision patterning on the surface metal layer of the sintered board and can be extended to more layers of embedded metal structure, realizing the multi-layer three-dimensional packaging capability of integrating high-power circuits, communication control circuits and heat dissipation channels in a single substrate. It is particularly suitable for power electronic modules in fields such as high-speed rail and new energy vehicles that require high power density, high withstand voltage and long life.

[0051] Reference Figure 9 As shown, Figure 9 This is provided by some embodiments of this application. Figure 1 The flowchart of step S106 shows that the method may include, but is not limited to, steps S201 to S202.

[0052] Step S201: Perform a conductive process on the first metal layer on the upper surface and the second metal layer on the lower surface of the fourth plate to obtain the fifth plate.

[0053] Specifically, micro-through holes penetrating the upper and lower metal layers can be drilled on the fourth plate. Subsequently, the hole walls of the fourth plate are subjected to plasma cleaning or chemical activation treatment to remove residues and enhance adhesion. Finally, a dense metal layer is deposited inside the holes using chemical copper plating or electroplating, forming a low-resistance, high-reliability conductive channel, thus obtaining the fifth plate. (Refer to...) Figure 10 As shown, Figure 10 This is a cross-sectional view of the fifth plate body provided in some embodiments of this application. In the fifth plate body, the first metal layer (i.e., the second metal substrate 30) is connected to the metal pattern substrate 10, and the second metal layer (i.e., the second metal substrate 30) is connected to the metal pattern substrate 10.

[0054] Step S202: Perform pattern processing on the first metal layer and the second metal layer on the surface of the fifth board to obtain the target circuit board.

[0055] Specifically, a patterned photoresist layer is first formed on the first and second metal layers on the surface of the fifth board. Then, using the photoresist layer as a mask, wet chemical etching or dry plasma etching is used to selectively remove unprotected metal areas. After etching, the photoresist layer is completely removed by chemical stripping or plasma ashing. Finally, a high-density interconnect pattern that is precisely aligned with the embedded structure and vertical vias is formed on the surface of the ceramic substrate, resulting in the target circuit board.

[0056] Reference Figure 11 As shown, Figure 11 This is provided by some embodiments of this application. Figure 9 The flowchart of step S201 includes, but is not limited to, step S301 or step S302.

[0057] Step S301: Prepare a through hole on the fourth plate.

[0058] The via exposes the areas of the first metal layer and / or the second metal layer to be connected.

[0059] In one possible embodiment, the through-hole on the fourth plate can be prepared by high-precision laser drilling, preferably ultraviolet laser. By precisely controlling the pulse energy and scanning path, micropores with steep walls and minimal heat-affected zones can be processed on the sintered ceramic-metal composite (fourth plate).

[0060] In one possible embodiment, the through-hole in the fourth plate can be prepared by mechanical drilling, using a CNC drilling machine to drill holes in the sintered ceramic-metal composite (fourth plate).

[0061] Step S302: A conductor is formed in the through hole of the fourth plate to electrically connect the first metal layer and the second metal layer, thus obtaining the fifth plate.

[0062] In a preferred embodiment, a conductive seed layer (such as chemical copper or chemical nickel) is first deposited on the hole wall by chemical plating, and then copper is electroplated to thicken the hole, so that the hole is filled with dense metallic copper, forming a low-resistance conductive channel. The thickness of the electroplated copper can be adjusted according to the current carrying requirements.

[0063] In a preferred embodiment, full filling is achieved first by chemical plating. For micropores with small pore sizes (such as less than 100 μm), full filling of the pores can be achieved directly by chemical copper plating without the need for an electroplating step. The process is simpler but the deposition rate is slower.

[0064] Reference Figure 12 As shown, Figure 12 This is provided by some embodiments of this application. Figure 9The flowchart of step S202 is provided. This method includes, but is not limited to, steps S401 to S403.

[0065] Step S401: Patterned resist layers are formed on the first metal layer and the second metal layer on the surface of the fifth board, respectively. The resist layers are used to determine the line areas to be retained on the surface of the fifth board.

[0066] In a preferred embodiment, the surfaces of the first and second metal layers are first pretreated by degreasing, micro-etching, and acid washing to enhance adhesion. Then, liquid photoresist is uniformly coated by coating or spin coating. After low-temperature pre-baking, contact or projection ultraviolet exposure is performed using a glass photomask with circuit patterns. Finally, the uncured areas are dissolved by alkaline or organic solvent developer to form a refined resist pattern.

[0067] In a preferred embodiment, a solid photopolymer dry film is hot-pressed onto the surfaces of the first metal layer and the second metal layer in a vacuum laminator, and a resist pattern is formed through the same exposure and development process.

[0068] Step S402: Using the resist layer as a barrier, selectively remove the metal areas not covered by the resist layer within the first and second metal layers to obtain the sixth plate.

[0069] Specifically, the above steps are mainly achieved through wet or dry etching processes. In wet etching, the plate with the resist pattern is immersed in or sprayed with an etching solution. The exposed metal is dissolved through a chemical oxidation-reduction reaction. During this process, the solution concentration and temperature must be precisely controlled, and mechanical agitation or bubbling is often used to ensure etching uniformity and prevent over-etching or under-etching due to uneven solute diffusion. In dry etching, reactive ion etching technology is used. A chlorine or fluorine-containing gas is introduced into a vacuum chamber, and a highly active plasma is generated by an RF power supply. The metal is removed through a combination of physical bombardment and chemical reaction.

[0070] Step S403: Remove the resist layer on the sixth board to form a target circuit board with interconnect pattern.

[0071] Specifically, this step is mainly achieved through two methods: chemical dissolution or physical stripping. In the chemical removal embodiment, the board is immersed in or sprayed with a special stripping solution (typically a strongly alkaline solution or a special organic solvent for organic photoresists), causing the resist layer to detach from the metal surface through swelling and decomposition. In the physical removal embodiment, oxygen plasma ashing technology is used. Oxygen is introduced into a vacuum reaction chamber, and highly reactive oxygen plasma is generated by a radio frequency power supply to oxidize and decompose the organic resist layer into gaseous carbon dioxide and water vapor, which are then removed.

[0072] This application also provides a circuit board manufactured by the multilayer circuit board preparation method of the first aspect described above.

[0073] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method for manufacturing multilayer circuit boards.

[0074] Please see Figure 13 , Figure 13 This is a schematic diagram of the hardware structure of an electronic device provided in one embodiment of this application. The electronic device includes: The processor 1301 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to realize the high thermal conductivity and high current resistance multilayer circuit board fabrication method provided in the embodiments of this application. The memory 1302 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 1302 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1302 and is called and executed by the processor 1301 to implement the high thermal conductivity, high current resistance multilayer circuit board fabrication method provided in the embodiments of this application. The input / output interface 1303 is used to implement information input and output; The communication interface 1304 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 1305 transmits information between various components of the device (e.g., processor 1301, memory 1302, input / output interface 1303, and communication interface 1304); The processor 1301, memory 1302, input / output interface 1303 and communication interface 1304 are connected to each other within the device via bus 1305.

[0075] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, provides a method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, as provided in this application.

[0076] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0077] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0078] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0079] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0080] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0081] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0082] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0083] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0084] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0086] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for fabricating a multilayer circuit board with high thermal conductivity and high current resistance, characterized in that, include: A first metal substrate is provided, and a hollow pattern is prepared on the first metal substrate to obtain a metal pattern substrate; An insulating green board is stacked on the upper and lower surfaces of the metal pattern substrate to form a first plate with a sandwich structure. A second metal substrate is stacked on the upper and lower surfaces of the first plate to form a second plate. The second plate is pressed to embed the metal pattern substrate within the second plate into the insulating green plate, resulting in a third plate. The third plate includes an embedded layer, a first metal layer above the embedded layer, and a second metal layer below the embedded layer. The embedded layer includes a metal pattern substrate and an insulating green plate. The insulating green plate deforms and fills the hollow pattern of the metal pattern substrate under the pressing action. The third plate is positioned and sintered in the die plate to densify the insulating green plate, and the metal pattern substrate is sintered together with the insulating green plate, the first metal layer and the second metal layer to obtain a fourth plate with an embedded metal structure. The first metal layer and the second metal layer on the surface of the fourth board are patterned to form surface circuits, thereby obtaining the target circuit board.

2. The method for fabricating a multilayer circuit board according to claim 1, characterized in that, The step of patterning the first metal layer and the second metal layer on the surface of the fourth board to form surface circuitry to obtain the target circuit board includes: The first metal layer on the upper surface of the fourth plate and the second metal layer on the lower surface are made conductive to obtain the fifth plate; The first metal layer and the second metal layer on the surface of the fifth plate are patterned to obtain the target circuit board.

3. The method for fabricating a multilayer circuit board according to claim 2, characterized in that, The step of making the first metal layer on the upper surface of the fourth plate and the second metal layer on the lower surface conductive to obtain the fifth plate includes: A through-hole is formed on the fourth plate, the through-hole exposing the area to be connected in the first metal layer and / or the second metal layer; A conductor is formed in the through hole of the fourth plate to electrically connect the first metal layer and the second metal layer, thereby obtaining the fifth plate.

4. The method for fabricating a multilayer circuit board according to claim 2, characterized in that, The process of patterning the first metal layer and the second metal layer on the surface of the fifth board to obtain the target circuit board includes: Patterned resist layers are formed on the first metal layer and the second metal layer on the surface of the fifth plate, and the resist layers are used to define the line areas to be retained on the surface of the fifth plate. Using the anti-corrosion layer as a barrier, the metal areas not covered by the anti-corrosion layer are selectively removed within the first metal layer and the second metal layer to obtain the sixth plate. The resist layer is removed from the sixth plate to form the target circuit board with interconnect circuit patterns.

5. The method for fabricating a multilayer circuit board according to claim 1, characterized in that, The method of stacking an insulating green plate on the upper and lower surfaces of the metal pattern substrate to obtain a first plate body includes: coating or printing a first adhesive medium layer on the upper and lower surfaces of the metal pattern substrate, and pasting the insulating green plate on the first adhesive medium layer to form the first plate body; The step of stacking a second metal substrate on the upper and lower surfaces of the first plate to form a second plate includes: coating or printing a second adhesive medium layer on the upper and lower surfaces of the first plate, and attaching the second metal substrate on the second adhesive medium layer to form the second plate.

6. The method for fabricating a multilayer circuit board according to claim 5, characterized in that, The first or second adhesive medium layer comprises a thermally decomposable organic polymer or a metal oxide powder.

7. The method for fabricating a multilayer circuit board according to claim 6, characterized in that, The metal material of the metal substrate includes at least one of the following: copper, copper alloy, aluminum, and aluminum alloy; wherein the metal material of the metal oxide powder is the same as the metal material of the first metal substrate or the second metal substrate.

8. The method for fabricating a multilayer circuit board according to claim 1, characterized in that, The insulating green board is a ceramic green board, and the insulating green board contains at least one of the following materials: alumina, silicon oxide, boron oxide, aluminum nitride, silicon nitride, and boron nitride.

9. The method for fabricating a multilayer circuit board according to claim 1, characterized in that, The hollow pattern on the metal substrate includes at least one of the following: through-hole array, grid structure, and preset line channel; the method of preparing the hollow pattern includes one of the following: etching method, laser cutting method, stamping method, and mechanical drilling method.

10. A circuit board, characterized in that, include: It is manufactured by the method of preparing a multilayer circuit board according to any one of claims 1 to 9.

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