Manufacturing method of wiring boards

Abstract

To provide a wiring board with precisely formed via conductors. [Solution] The wiring board of the embodiment includes: preparing a support substrate on which a metal film layer ML2 is formed on the surface; forming a plating film layer 122 including an alignment pattern AP on the metal film layer ML2; forming an insulating layer 11 covering the plating film layer 122; forming through holes penetrating the insulating layer 11 in the thickness direction by irradiating the insulating layer 11 with laser light LL by referring to position information obtained from the alignment pattern AP; and forming via conductors by filling the through holes with a conductor. Forming the plating film layer 122 includes making the specular reflectance on the upper surface of the metal film layer ML2 and the specular reflectance on the upper surface of the plating film layer 122 different for light of a predetermined wavelength.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a wiring board.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a wiring board. In the method for manufacturing a wiring board disclosed in Patent Document 1, for example, a resist layer having an opening is formed on a support such as a copper foil, and a first wiring layer is formed in the opening of the resist layer. After the first wiring layer is formed, the resist layer is removed, and a first insulating layer is formed on the first wiring layer and the copper foil exposed from the pattern of the first wiring layer. A via hole is formed by laser processing on the first insulating layer, and a via wiring is formed in the via hole.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, it is considered that there may be a case where it is difficult to accurately form a via hole at a position where the via hole of the first insulating layer should be formed.

Means for Solving the Problems

[0005] The wiring board of the present invention includes: preparing a support substrate having a metal film layer formed on its surface; forming a plating film layer including an alignment pattern on the metal film layer; forming an insulating layer covering the plating film layer; forming through holes penetrating the insulating layer in the thickness direction by irradiating the insulating layer with laser light with reference to positional information obtained from the alignment pattern; and forming via conductors by filling the through holes with a conductor. The formation of the plating film layer includes making the specular reflectance of light of a predetermined wavelength on the upper surface of the metal film layer different from the specular reflectance on the upper surface of the plating film layer.

[0006] According to embodiments of the present invention, the specular reflectance of light of a predetermined wavelength is made different on the upper surface of the metal film layer and on the upper surface of the plating film, thereby allowing for more precise recognition of the alignment pattern and thus obtaining accurate positional information. A wiring board can be provided that includes via conductors formed at more precise positions. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example of a wiring board manufactured by a manufacturing method according to one embodiment of the present invention. [Figure 2] A cross-sectional view showing another example of a wiring board manufactured by the manufacturing method of one embodiment of the present invention. [Figure 3A] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3B] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3C] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3D] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3E] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3F] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3G] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3H] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3I] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3J] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3K] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3L] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3M] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3N] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3O] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3P] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3Q] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Figure 3R] A diagram showing an example of a method for manufacturing a wiring board, which is one embodiment of the present invention. [Modes for carrying out the invention]

[0008] The method for manufacturing a wiring board according to the present invention will be described below with reference to the drawings. Figure 1 is a cross-sectional view showing a wiring board 1, which is an example of a wiring board manufactured by the manufacturing method of one embodiment. Note that wiring board 1 is merely an example of a wiring board that can be manufactured. The laminated structure of the manufactured wiring board, as well as the number of conductor layers and insulating layers, are not limited to the laminated structure of wiring board 1 in Figure 1, or the number of conductor layers and insulating layers included in wiring board 1. Furthermore, the referenced drawings are not intended to show the exact proportions of each component, but are drawn in a way that makes it easy to understand the features of the present invention.

[0009] The wiring board 1 has a laminated structure including a build-up portion composed of a plurality of alternately laminated conductor layers and insulating layers. The build-up portion constituting the wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) orthogonal to its thickness direction. The surface of the first build-up portion 10 constitutes the first surface 1F. The surface of the third build-up portion 30 constitutes the second surface 1B.

[0010] The wiring board 1 in the example shown in FIG. 1 further includes a second build-up portion 20 and a third build-up portion 30 composed of insulating layers and conductor layers alternately laminated on the second surface 10B side of the first build-up portion 10.

[0011] In the description of the wiring board 1 of the present embodiment shown in FIG. 1, the first surface 10F of the first build-up portion 10, that is, the first surface 1F side of the wiring board 1, is referred to as "up" or "upper side", and the second surface 1B side of the wiring board 1 is referred to as "down" or "lower side". Also, in each component, the surface facing the first surface 1F side of the wiring board 1 is also referred to as the "upper surface", and the surface facing the second surface 1B side of the wiring board 1 is also referred to as the "lower surface".

[0012] In the illustrated example, each of the first build-up portion 10, the second build-up portion 20, and the third build-up portion 30 includes a plurality of insulating layers and a plurality of conductor layers. As shown in the figure, the first build-up portion 10 has insulating layers (first insulating layers) 11 and conductor layers (first conductor layers) 12 that are alternately laminated. Conductor layers facing each other with one insulating layer 11 interposed therebetween are connected by via conductors (first via conductors) 13. The second build-up portion 20 has insulating layers (second insulating layers) 21 and conductor layers (second conductor layers) 22 that are alternately laminated. Conductor layers facing each other with one insulating layer 21 interposed therebetween are connected by via conductors (second via conductors) 23. The third build-up portion 30 has insulating layers (third insulating layers) 31 and conductor layers (third conductor layers) 32 that are alternately laminated. Conductor layers facing each other with one insulating layer 31 interposed therebetween are connected by via conductors (third via conductors) 33.

[0013] Each of the conductor layers 12, 22, 32 is patterned to have a predetermined conductor pattern. In the illustrated example, the first conductor layer 12 that constitutes the first surface 10F is formed in a pattern having a plurality of conductor pads 12p. As shown in the figure, on the first surface 10F, for example, a solder resist layer SR1 formed using a photosensitive polyimide resin or an epoxy resin is formed. An opening SR1a is formed in the solder resist layer SR1, and conductor bumps BP are formed on the conductor pads 12p exposed within the opening SR1a. The first surface 1F of the wiring board 1 is a component mounting surface on which electronic components E1, E2, which are active components such as, for example, semiconductor integrated circuit devices and transistors, are mounted, as shown in the example of FIG. 1, and the conductor pads 12p can be connected to the electronic components E1, E2 via the conductor bumps BP. Specifically, the electronic components E1, E2 can be, for example, integrated circuits such as logic chips incorporating logic circuits, or processing devices such as MPUs (Micro Processor Units), or memory elements such as HBMs (High Bandwidth Memories).

[0014] In the illustrated example, the wiring board 1 further includes a solder resist layer SR2 formed on a second surface 1B, which consists of the surfaces of an insulating layer 31 and a conductor layer 32. The solder resist layer SR2 is formed using, for example, a photosensitive polyimide resin or epoxy resin. An opening SR2a is formed in the solder resist layer SR2, and the conductor pads 32p of the conductor layer 32 of the third build-up portion 30 are exposed through the opening SR2a. The second surface 1B of the wiring board 1, opposite to the component mounting surface, may be a connection surface that connects to an external element when the wiring board 1 itself is mounted to an external element such as an external wiring board (e.g., a motherboard of any electrical device). The conductor pads 32p may be connected to any substrate, electrical component, or mechanical component.

[0015] The first insulating layer 11 of the first build-up section 10 may be formed using an insulating resin such as epoxy resin or phenolic resin. The insulating layer 11 may also contain any of the following: fluororesin, liquid crystal polymer (LCP), fluoroethylene fluoride (PTFE), polyester resin (PE), or modified polyimide resin (MPI).

[0016] Examples of conductors that make up the conductor layer 12 and via conductor 13 of the first build-up section 10 include copper and nickel, with copper being preferred. In Figure 1, the conductor layer 12 and via conductor 13 are shown as single layers for clarity, but the conductor layer 12 and via conductor 13 may have a multilayer structure. For example, the conductor layer 12 and via conductor 13 may have a two-layer structure including a metal film layer (e.g., a sputtering film layer or an electroless plating film layer) and a plating film layer (e.g., an electroplating film layer).

[0017] The second insulating layer 21 constituting the second build-up section 20 and the third insulating layer 31 constituting the third build-up section 30 can be formed using the same insulating resin as the first insulating layer 11. Each insulating layer 11, 21, and 31 may contain the same insulating resin within each build-up section, or they may contain different insulating resins. Each insulating layer 21 and 31 may contain a core material (reinforcement) made of glass fibers or aramid fibers.

[0018] The second conductor layer 22 of the second build-up section 20 and the third conductor layer 32 of the third build-up section 30, as well as each via conductor 23, 33, may be formed using any metal such as copper or nickel, similar to the first conductor layer 12 and the first via conductor 13. Each conductor layer 22, 32 is patterned to have a predetermined conductor pattern. The conductor layers 22, 32 and the via conductors 23, 33 may be configured in a multilayer structure, for example, having a two-layer structure including a metal film layer and a plating film layer.

[0019] Figure 2 shows a wiring board 1a as another example of a wiring board manufactured by the manufacturing method of the embodiment. The wiring board 1a comprises a first build-up section 10 having a first surface 10F and a second surface 10B, and a solder resist layer SR1 covering the first surface 10F and a solder resist layer SR2 covering the second surface 10B. Conductor pads 12p are exposed in an opening SR1a formed in the solder resist layer SR1, and conductor bumps BP are formed on the conductor pads 12p. The lowest conductor layer 12 is exposed in an opening SR2a formed in the solder resist layer SR2. If the wiring board manufactured by the manufacturing method of the embodiment does not have build-up sections other than the first build-up section 10, it may have the configuration of the illustrated wiring board 1a. The wiring boards 1 and 1a described above have a rectangular shape, for example, in a plan view, with the dimensions of each side being 80 mm or more and less than 240 mm. Here, "planar view" means viewing the object from a line of sight parallel to the thickness direction of the wiring board 1.

[0020] Next, referring to Figures 3A to 3R, the manufacturing method of the wiring board of the embodiment will be explained using the case where the wiring board 1 shown in Figure 1 is manufactured as an example. In the manufacturing method described below, each component formed may be formed using the materials exemplified as the materials for the corresponding components in the description of the wiring board 1 in Figure 1, unless otherwise specified. In the following description of the manufacturing method of the wiring board 1, the side of the first build-up portion 10 that is closer to the core material GS1 that constitutes the first support substrate SP1 formed thereon will be referred to as "bottom" or "lower side," and the side further from the core material GS1 will be referred to as "top" or "upper side." Therefore, the surface of each element constituting the wiring board 1 that faces the first support substrate SP1 will be referred to as the "bottom surface," and the surface that faces away from the first support substrate SP1 will also be referred to as the "top surface."

[0021] First, as shown in Figure 3A, a first support substrate SP1 is prepared. The first support substrate SP1 has two surfaces perpendicular to its thickness direction: a first surface SP1a and a second surface SP1b opposite to the first surface SP1a. The first support substrate SP1 includes a core material GS1 having one surface GS1a and the other surface GS1b opposite to the first surface GS1a. The core material GS1 may be, for example, a glass substrate, a ceramic substrate, or a silicon substrate. In addition to the core material GS1, the first support substrate SP1 includes a first metal film layer ML1 laminated on the surface of one surface GS1a of the core material GS1, and a second metal film layer ML2 laminated on the first metal film layer ML1 via an adhesive layer AL1. The first and second metal film layers ML1 and ML2 are metal film layers formed by, for example, electroless plating or sputtering. Although the first and second metal film layers ML1 and ML2 are depicted as single layers in the figures, they may contain multiple layers. For example, the first and second metal film layers ML1 and ML2 may each have a two-layer structure (not shown) consisting of a titanium layer and a copper layer. In this case, the copper layer is positioned outside the titanium layer in both the first and second metal film layers ML1 and ML2. Therefore, in this case, the first surface SP1a of the first support substrate SP1 is composed of the surface of the copper layer constituting the second metal film layer ML2.

[0022] In the following, Figures 3A and 3B to 3R describe an example in which the first surface SP1a of the first support substrate SP1 has one product area MA, and one wiring board is formed in this product area MA. However, the first support substrate may have one or more product area MAs, each on which one wiring board is formed. When the first surface SP1a of the first support substrate SP1 has multiple product area MAs, the laminate formed continuously across the multiple product area MAs is divided according to each product area MA to manufacture the wiring boards. For example, the product area MA on the first surface SP1a of the first support substrate SP1 has a rectangular shape with dimensions of 80 mm or more and 240 mm or less on each side in a plan view. Therefore, the laminate (build-up portion) constituting the wiring board, formed across one or more product area MAs on the first surface SP1a of the first support substrate SP1, may have at least a rectangular shape with dimensions of 80 mm or more and 240 mm or less on each side in a plan view. As shown in the figures, the first surface SP1a of the support substrate SP1 includes a peripheral area SA located around the product area MA, in addition to the product area MA. An alignment pattern is formed in the peripheral area SA, which serves as a reference for positional information referenced in the manufacturing process of the wiring board 1, as will be described later with reference to Figures 3B to 3H.

[0023] Next, Figures 3B to 3J will be referenced to describe the formation of the first build-up portion 10 (see Figure 1) on the first support substrate SP1. The first build-up portion 10 is formed only on the upper side of the first surface SP1a of the first support substrate SP1.

[0024] As shown in Figure 3B, a resist layer RL having an aperture RLa is formed on the surface of the metal film layer ML2 that constitutes the first surface SP1a of the first support substrate SP1. First, a dry film resist containing, for example, a photosensitive epoxy resin is bonded to the upper surface of the metal film layer ML2 to form the resist layer RL. Subsequently, exposure is performed on the resist layer RL. In the process of exposing the resist layer RL, direct imaging exposure with relatively high resolution may be performed. In direct imaging exposure, no photomask is used, and exposure light is directly irradiated onto the resist layer RL. The exposure light is scanned according to a drawing pattern corresponding to the conductor pattern of the first conductor layer 12 to be formed on the metal film layer ML2 (see Figure 3D). Subsequently, the resist layer RL is developed with a developer. Development forms a resist layer RL having an aperture RLa corresponding to the conductor pad 12p in the product area MA and the alignment pattern AP in the peripheral area SA (see Figure 3D), which are the conductor patterns of the first conductor layer 12 to be formed on the metal film layer ML2.

[0025] Next, as shown in Figure 3C, a plating layer 122 constituting the first conductor layer 12 is formed within the opening RLa by electroplating with the metal film layer ML2 as the power supply layer. A plating layer 122 constituting the conductor pad 12p is formed within the opening RLa located within the product area MA, and a plating layer 122 constituting the alignment pattern AP is formed within the opening RLa located within the peripheral area SA. The plating layer 122 is formed to have a thickness of, for example, 3 μm or more and 6 μm or less (the shortest distance between the upper surface of the metal film layer ML2 and the upper surface of the plating layer 122). The plating layer 122 may be formed from the same material (e.g., copper) as the material constituting the metal film layer ML2.

[0026] Next, the upper surface of the plating film layer 122 is subjected to a roughening treatment. For example, the upper surface of the plating film layer 122 is roughened by a wet etching treatment using a chemical solution such as a manganate solution, or by a dry etching treatment using a plasma gas such as oxygen plasma. Specifically, as will be described later with reference to Figure 3G, the upper surface of the plating film layer 122 is roughened so that the specular reflectance on the upper surface of the plating film layer 122 and the specular reflectance on the upper surface of the metal film layer ML2 are different for light of a predetermined wavelength that can be detected by an imaging device for the alignment pattern AP. This roughening treatment is carried out while the plating film layer 122 is filling the openings RLa in the resist layer RL formed on the metal film layer ML2.

[0027] Next, the resist layer RL is removed, and the upper surface of the metal film layer ML2 is exposed, as shown in Figure 3D. Figure 3E shows a top view of the state shown in Figure 3D, with the upper surfaces of the metal film layer ML2 and the plating film layer 122 exposed. Figure 3D shows a cross-section along the line DD in Figure 3E. The alignment pattern AP, formed of the plating film layer 122 in the peripheral area SA as shown in Figures 3D and 3E, has a circular central part C and an annular peripheral part P surrounding the central part C. The upper surface of the metal film layer ML2 is exposed in the gap G between the central part C and the peripheral part P. Note that the planar shape of the alignment pattern AP is not limited to the shape described above, and may have a cross-shaped planar shape composed of the plating film layer 122, for example.

[0028] The surface state of the alignment pattern AP will be explained with reference to Figure 3F, which is an enlarged view of the region e enclosed by the dashed line in Figure 3D, corresponding to the region e enclosed by the dashed line in Figure 3E. The upper surfaces of the plating film layers 122 that constitute the central part C and the peripheral part P are subjected to the roughening treatment described above with reference to Figure 3C. This roughening treatment causes the specular reflectance of light of a predetermined wavelength detectable by the device that images the alignment mark AP to be different on the upper surface of the plating film layer 122 (central part C and peripheral part P) and the upper surface of the metal film layer ML2 (gap G). For example, the specular reflectance of light of a predetermined wavelength detectable by the device that images the alignment mark AP to be 30% or more and 50% or less on the upper surface of the plating film layer 122, and the specular reflectance of light of a predetermined wavelength detectable by the device that images the alignment mark AP to be 60% or more on the upper surface of the metal film layer ML2. Specifically, the surface roughness of the upper surface of the plating film layer 122 is 0.35 μm or more and 0.6 μm or less in arithmetic mean roughness, and the surface roughness of the upper surface of the metal film layer ML2 may be 0.05 μm or more and less than 0.3 μm in arithmetic mean roughness. Furthermore, the specular reflectance on the upper surface of the plating film layer 122 before the roughening treatment may be 60% or more.

[0029] Next, as shown in Figure 3G, a first insulating layer 11 is laminated to cover the top and side surfaces of the plating layer 122, as well as the metal film layer ML2 exposed from the conductive pattern of the plating layer 122. As the first insulating layer 11, an insulating resin such as epoxy resin or phenolic resin may be used. Fluoropolymer, liquid crystal polymer (LCP), fluoroethylene fluoride (PTFE), polyester resin (PE), or modified polyimide resin (MPI) may also be used. The first insulating layer 11 is formed by heat-pressing a resin molded into a film.

[0030] After the first insulating layer 11 is formed, a laser beam LL, such as a carbon dioxide laser beam or a UV laser beam, is irradiated into the first insulating layer 11 to form through-holes 11a (see Figure 3H). The position in the first insulating layer 11 where the laser beam LL is irradiated is determined by referring to position information obtained from the alignment pattern AP. Specifically, for example, the alignment pattern AP is imaged by an alignment camera AC equipped with coaxial illumination. Specular reflection of light of a predetermined wavelength from the alignment pattern AP that passes through the first insulating layer 11 is detected by the device AC. The position information obtained from the imaged alignment pattern AP is referred to to calculate the position where the through-holes 11a should be formed (the position where the laser beam LL should be irradiated).

[0031] As described above, due to the roughening of the upper surface of the plating film layer 122, the specular reflectance of the light detected by the device AC differs between the upper surface of the central part C and the peripheral part P and the upper surface of the gap G. As a result, in the image of the acquired alignment pattern AP, there is a high contrast between the brightness of the central part C and the peripheral part P and the brightness of the gap G. In particular, as described above, when the plating film layer 122 has a relatively thin thickness of about 3 μm or more and 6 μm or less, or when the plating film layer 122 is formed from the same material as the material constituting the metal film layer ML2, there is little difference between the brightness of the central part C and the peripheral part P and the brightness of the gap G. In such cases, a high brightness contrast can be effectively obtained by roughening the upper surface of the plating film layer 122. Therefore, when obtaining positional information from the captured alignment pattern AP, the boundary between the gap G and the central part C, as well as the boundary between the gap G and the surrounding part P, are clearly recognized, and thus the center position of the alignment pattern AP can be recognized with high accuracy. Highly accurate positional information can be obtained. As a result, the laser beam LL is irradiated relatively accurately to the position where the through-hole 11a should be formed.

[0032] Although not shown in the diagram, irradiation with laser light LL, such as carbon dioxide laser light, may be performed by protecting the upper surface of the first insulating layer 11 with a protective film such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN) film while irradiating with laser light LL. The first insulating layer 11 may be formed to have a thickness of approximately 7 μm to 15 μm. From the viewpoint of accurately imaging the alignment pattern AP, it is desirable that the shortest distance from the upper surface of the first conductor layer 12 (the upper surface of the plating film layer 122) to the upper surface of the first insulating layer 11 be 10 μm or less.

[0033] As shown in Figure 3H, a through-hole 11a is formed in the first insulating layer 11. The through-hole 11a may be formed on the upper surface of the first insulating layer 11 with a diameter of 5 μm or more and 15 μm or less. By irradiation with laser light LL, which references the highly accurate positional information described above, the through-hole 11a can be formed relatively accurately at the position where the first via conductor 13 should be formed. The through-hole 11a may be formed such that the depth of the through-hole 11a / the diameter of the through-hole 11a is approximately 0.5 or more and approximately 1.5 or less. Here, "depth of the through-hole 11a" means the shortest distance between the upper surface of the first conductor layer 12 and the upper surface of the first insulating layer 11, and "diameter of the through-hole 11a" means the distance between the two longest points on the outer circumference of the through-hole 11a in a plan view on the upper surface of the first insulating layer 11.

[0034] Desmearing may be performed after the formation of the through-hole 11a. The desmearing may preferably be a dry desmearing treatment using plasma gas. Desmearing may also be performed while protecting the surface of the first insulating layer 11, with a protective film such as a PET film formed on the surface of the first insulating layer 11.

[0035] Next, as shown in Figure 3I, a first via conductor 13 that fills the through-hole 11a and a first conductor layer 12 on the first insulating layer 11 are formed. A metal film layer 121 is formed on the inner wall of the through-hole 11a and the surface of the first insulating layer 11 by electroless plating or sputtering. If a protective film is provided on the surface of the first insulating layer 11 during the formation of the through-hole 11a and / or during the desmear treatment, the protective film may be peeled off before the formation of the metal film layer 121. Subsequently, a plating film layer 122 is formed within the opening of the resist layer formed on the metal film layer 121 by electroplating with the metal film layer 121 as the power supply layer. The inside of the through-hole 11a is completely filled with the electroplating film, and the first via conductor 13 is formed. After the resist layer is removed using an alkaline stripping solution, the portion of the metal film layer 121 not covered by the plating film layer 122 is removed by etching. As a result, as shown in Figure 3I, a first conductor layer 12 having a two-layer structure consisting of a metal film layer 121 and a plating film layer 122, with wiring FW, is formed. The wiring FW may be formed such that the minimum wiring width is 2 μm or less and the minimum wiring spacing is 2 μm or less. As shown in the figure, the first conductor layer 12 is formed to include an alignment pattern AP in the peripheral area SA, similar to the first conductor layer 12 formed in contact with the first support substrate SP1.

[0036] Next, as shown in Figure 3J, a desired number of first insulating layers 11 and first conductor layers 12, as well as first via conductors 13 penetrating each first insulating layer 11, are formed in the same manner as the method for forming the first insulating layer 11, first conductor layer 12, and first via conductor 13 described above with reference to Figure 3I. In forming the through holes 11a in the first via conductor 13, positional information obtained from the alignment pattern AP covered by the insulating layer 11 in which the through holes 11a are formed is referenced. The formation of the first build-up portion 10 on the first surface SP1a of the first support substrate SP1 is completed.

[0037] Next, as shown in Figure 3K, the lowest second insulating layer 21 of the second build-up section 20 (see Figure 3N) is laminated on top of the uppermost first insulating layer 11 and first conductor layer 12 of the first build-up section 10. The thickness of the second insulating layer 21 may differ from the thickness of the first insulating layer 11 that constitutes the first build-up section 10. The second insulating layer 21 may be formed to have a thickness of, for example, about 20 μm to 30 μm. The second insulating layer 21 may be made of an insulating resin similar to the insulating resin that constitutes the first insulating layer 11. A film 21F made of a resin such as PET is laminated on top of the second insulating layer 21, and is peelably bonded to the second insulating layer 21.

[0038] Next, as shown in Figure 3L, the first build-up portion 10, comprising the second insulating layer 21 and the film 21F, is attached to both sides of the two main surfaces (surfaces perpendicular to the thickness direction) of the second support substrate SP2 via the first support substrate SP1. The main surfaces of the second support substrate SP2 and the second surface SP1b of the first support substrate SP1 are joined via an adhesive layer ALC made of any adhesive. The second support substrate SP2 may be, for example, a glass substrate, a ceramic substrate, or a silicon substrate, similar to the core material GS1 of the first support substrate SP1.

[0039] Next, as shown in Figure 3M, a second via conductor 23 penetrating the second insulating layer 21 and a second conductor layer 22 in contact with the upper surface of the second insulating layer 21 are formed. The film 21F is peeled off from the second insulating layer 21. Subsequently, for example, through holes 21a in the second insulating layer 21 are formed by irradiation with laser light, and the second via conductor 23 and the second conductor layer 22 on the second insulating layer 21, which have a two-layer structure of a metal film layer 221 and a plating film layer 222, are formed by a so-called semi-additive method. The second conductor layer 22 may be formed to have a thickness of, for example, about 10 μm to 15 μm.

[0040] Note that Figure 3M, and Figures 3N to 3R referenced below, show the laminate formed on one surface of the second support substrate SP2, and the illustration of the laminate that may be formed on the opposite surface is omitted. However, the laminates shown in the illustrations and in the number shown are formed simultaneously on the opposite surface of the second support substrate SP2. Therefore, warping is unlikely to occur in the process described with reference to Figures 3M to 3P.

[0041] Next, as shown in Figure 3N, the process of forming the second insulating layer 21, the second conductor layer 22, and the second via conductor 23 described above is repeated to form the desired number of second insulating layers 21 and second conductor layers 22, as well as second via conductors 23 that penetrate each second insulating layer 21. The formation of the second build-up section 20 on the first build-up section 10 is completed. Note that in Figure 3N and the following Figures 3O to 3R, the metal film layers 121, 221 and the plating film layers 122, 222 are not depicted, and the conductor layers 12 and 22 are depicted as single layers, as in Figure 1.

[0042] Next, as shown in Figure 3O, the third insulating layer 31, the third conductor layer 32, and the third via conductor 33 penetrating the third insulating layer 31 of the third build-up section 30 are formed on the uppermost second insulating layer 21 and second conductor layer 22 of the second build-up section 20 in the same manner as the formation of the second insulating layer 21, the second conductor layer 22, and the second via conductor 23. As the insulating resin for forming the third insulating layer 31, a prepreg containing an insulating resin such as epoxy resin or BT resin impregnated into a reinforcing material (core material) made of glass fiber can be used. As shown, the third build-up section 30 is formed, including two layers of the third insulating layer 31 and two layers of the third conductor layer 32.

[0043] Next, as shown in Figure 3P, the first to third build-up sections 10, 20, and 30 within the product area MA are separated from the laminate of the surrounding area SA. For example, a groove V reaching the core material GS1 of the first support substrate SP1 is formed along the perimeter of the product area MA by laser light. If multiple product areas MA are included on the first support substrate SP1, groove V is also formed at the boundary between adjacent product areas MA, and the first to third build-up sections 10, 20, and 30 are divided into each product area MA.

[0044] Next, as shown in Figure 3Q, the first support substrate SP1 and the second support substrate SP2 are removed from the laminate in the product area MA. When removing the first support substrate SP1, the second metal film layer ML2 of the first support substrate SP1 is peeled off from the adhesive layer AL1. The second metal film layer ML2 and the adhesive layer AL1 are relatively strongly adhered in the peripheral area SA, and relatively weakly adhered in the product area MA. Therefore, as the laminate in the product area MA separated from the peripheral area SA is lifted upward, the second metal film layer ML2 is peeled off from the adhesive layer AL1, as shown in the figure. The lower surface of the second metal film layer ML2 under the conductor pad 12p is exposed. Although not shown in Figure 3Q, the removal of the first support substrate SP1 is also performed on the side of the second support substrate SP2 opposite to the side shown.

[0045] Next, the second metal film layer ML2 is removed by etching, exposing the underside of the conductor pad 12p and the underside of the first insulating layer 11. Subsequently, as shown in Figure 3R, the solder resist layer SR1 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the first insulating layer 11 and the first conductor layer 12. An opening SR1a that exposes the conductor pad 12p is formed in the solder resist layer SR1 by photolithography. The solder resist layer SR2 is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 31 and the conductor layer 32. An opening SR2a that exposes the conductor pad 32p is formed in the solder resist layer SR2 by photolithography. A conductor bump BP is formed on the conductor pad 12p exposed within the opening SR1a of the solder resist layer SR1. A plating layer including a nickel layer and a tin layer may be formed on the surface of the conductor bump BP. The wiring board 1 is completed as shown in Figure 3R. [Explanation of symbols]

[0046] 1, 1a Wiring board 10. First Build-up Department 20. Second Build-up Department 30. Third Build-up Department 11. Insulating layer (first insulating layer) 12 Conductor layer (First conductor layer) 21. Insulating layer (second insulating layer) 22 Conductor layer (second conductor layer) 31. Insulating layer (third insulating layer) 32 Conductor layer (3rd conductor layer) 13 Via conductor (first via conductor) 23 Via conductor (2nd via conductor) 33 Via conductor (3rd via conductor) 121, 221 Metal film layer 122, 222 Plating film layer 12p, 32p Conductor Pads AP Alignment Pattern C central part P surrounding area FW wiring MA Product Area SA surrounding area SP1 1st support board SP1a, Page 1 SP1b 2nd page SP2 2nd support board GS1 core material GS1a One side GS1b The other side

Claims

1. A support substrate is prepared with a metal film layer formed on its surface, Forming a plating film layer including an alignment pattern on the aforementioned metal film layer, Forming an insulating layer that covers the aforementioned plating film layer, By irradiating the insulating layer with laser light while referring to the positional information obtained from the alignment pattern, through holes are formed that penetrate the insulating layer in the thickness direction. A via conductor is formed by filling the aforementioned through hole with a conductor, A method for manufacturing a wiring board, including, Forming the aforementioned plating layer involves ensuring that the specular reflectance of light of a predetermined wavelength on the upper surface of the metal film layer is different from the specular reflectance of light on the upper surface of the plating layer.

2. A method for manufacturing a wiring board according to claim 1, wherein forming the plating film layer includes roughening the upper surface of the plating film layer.

3. A method for manufacturing a wiring substrate according to claim 2, wherein roughening the upper surface of the plating film includes roughening the upper surface of the plating film while the plating film layer is filling the openings in the resist layer formed on the metal film layer.

4. A method for manufacturing a wiring board according to claim 2, wherein the upper surface of the plating film layer is roughened such that the specular reflectance of light of the predetermined wavelength is 30% or more and 50% or less.

5. A method for manufacturing a wiring board according to claim 4, wherein the upper surface of the plating film layer is roughened to an arithmetic mean roughness of 0.35 μm or more and 0.6 μm or less.

6. A method for manufacturing a wiring board according to claim 4, wherein the upper surface of the metal film layer is formed such that the specular reflectance of light of the predetermined wavelength is 60% or more.

7. A method for manufacturing a wiring board according to claim 1, wherein the position information is obtained by detecting light of a predetermined wavelength using a device that images the alignment pattern.

8. A method for manufacturing a wiring board according to claim 1, wherein the metal film layer and the plating film layer are formed from the same material.

9. A method for manufacturing a wiring board according to claim 1, wherein the plating film layer is formed to a thickness of 3 μm or more and 6 μm or less.

10. A method for manufacturing a wiring board according to claim 1, wherein the through-hole is formed such that its diameter on the upper surface of the insulating layer is 5 μm or more and 15 μm or less.

11. A method for manufacturing a wiring substrate according to claim 3, wherein forming the opening in the resist layer includes exposing the resist layer by direct imaging exposure.

12. A method for manufacturing a wiring board according to claim 11, wherein the surface of the support board includes one or more product areas that are rectangles with side dimensions of 80 mm or more and 240 mm or less in a plan view, and the plating film layer and the insulating layer are formed over the one or more product areas.

13. A method for manufacturing a wiring board according to claim 1, wherein the support substrate includes a glass substrate, a ceramic substrate, or a silicon substrate.

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