Wiring board

Abstract

This invention discloses a wiring board technology that can accommodate multiple types of mounted components with differing requirements for high integration. [Solution] The wiring board of the present disclosure has a plurality of wiring structures that incorporate a plurality of relay lines and whose ends are exposed on the upper surface as a plurality of connection points, and a cavity that receives the plurality of wiring structures, wherein the plurality of wiring structures include two or more types from a first wiring structure whose lower part is a silicon layer, a second wiring structure whose lower part is a glass layer, and a third wiring structure whose lower part is a resin layer and does not include a glass layer or a silicon layer, and the two or more types of wiring structures differ in at least one of their planar size or the minimum L / S of the plurality of relay lines.

Description

Technical Field

[0001] The present disclosure relates to a wiring board.

Background Art

[0002] As a conventional wiring board, there is known one in which a wiring structure called a patch is embedded in order to highly integrate some wirings according to the electronic components to be mounted (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0044] , FIG. 1)

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, the degree of high integration required for the wiring structure and the width of the range of high integration (that is, the area of the upper surface of the wiring structure) required for the wiring structure differ depending on the type of electronic component. Therefore, the present application discloses a technology related to a wiring board capable of corresponding to a plurality of types of mounting components having different requirements for high integration.

Means for Solving the Problems

[0005] One aspect of the invention is a wiring board having a plurality of wiring structures incorporating a plurality of relay lines and both ends of the plurality of relay lines exposed on the upper surface as a plurality of connection points, and a cavity in which the plurality of wiring structures are received. In the plurality of wiring structures, there are included two or more types of a first wiring structure having a silicon layer at the lower part, a second wiring structure having a glass layer at the lower part, and a third wiring structure having a resin layer at the lower part and not including a glass layer and a silicon layer. The two or more types of wiring structures differ in at least one of their planar sizes or the minimum L / S of the plurality of relay lines.

Brief Description of the Drawings

[0006] [Figure 1] Figure 1 is a side cross-sectional view of a wiring board according to the first embodiment. [Figure 2] Figure 2A is a plan view of the wiring board. [Figure 3] Figures 3A and 3B are plan views of electronic components. [Figure 4] Figures 4A, 4B, and 4C are plan views of the wiring structure. [Figure 5] Figures 5A, 5B, and 5C are side cross-sectional views of the wiring structure. [Figure 6] Figure 6A is a side cross-sectional view of the wiring board before the cavity is formed, Figure 6B is a side cross-sectional view of the wiring board after the cavity is formed, and Figure 6C is a side cross-sectional view of the wiring board with the wiring structure arranged inside the cavity. [Figure 7] Figure 7A is a side cross-sectional view of a wiring board with via holes formed in the outermost insulating layer, Figure 7B is a side cross-sectional view of a wiring board with via conductors formed in the via holes, and Figure 7C is a side cross-sectional view of a wiring board with metal posts formed on it. [Figure 8] Figure 8 is a side cross-sectional view of the wiring board according to the second embodiment. [Figure 9] Figure 9 is a plan view of the wiring board according to the second embodiment. [Figure 10] Figures 10A, 10B, and 10C are plan views of the wiring structure according to the second embodiment. [Modes for carrying out the invention]

[0007] [First Embodiment] The wiring board 10 of this embodiment will be described with reference to Figures 1 to 5. The wiring board 10 shown in Figure 1 is a multilayer wiring board and includes a build-up section 12 in which a plurality of insulating layers 13 and a plurality of conductive layers 14 are alternately laminated on both the front and back surfaces of a core substrate 11. Note that only a portion of the surface side of the core substrate 11 of the wiring board 10 is shown in an enlarged view in Figure 1.

[0008] The insulating layer 13 is provided with multiple via conductors 15, and these via conductors 15 connect adjacent conductive layers 14 in the build-up section 12, with the insulating layer 13 in between. The core substrate 11 is provided with multiple through-hole conductors 18, and these through-hole conductors 18 connect the innermost conductive layers 14.

[0009] Of the insulating layer 13 and conductive layer 14, the outermost layer furthest from the core substrate 11 is, for example, the conductive layer 14. Furthermore, the insulating layer 13 one layer inward from the outermost insulating layer 13 has a two-layer structure with a lower insulating layer 13A and an upper insulating layer 13B overlapping. Additionally, a portion of the conductive layer 14, the fifth layer from the core substrate 11 side, is a solid plain layer 14P.

[0010] In the outermost insulating layer 13, metal posts 19 are provided inside all of the multiple openings 13H shown in Figure 1, and via conductors 15 are also provided directly below these metal posts 19, forming a stacked structure.

[0011] The upper surfaces of the multiple metal posts 19 are made up of multiple pads 19A. The multiple pads 19A are arranged in the same plane and are divided into multiple regions, with each region being arranged in a matrix.

[0012] As shown in Figure 2, the mounted components on the wiring board 10 include multiple chip-type electronic components 100X, 100Y, ..., each having multiple pads 101 arranged in a matrix on its underside. These multiple electronic components 100X, 100Y, ... are, for example, semiconductor elements and consist of multiple types with different functions, such as CPU elements, memory elements, and sensor elements. The multiple pads 101 of the multiple electronic components 100X, 100Y, ... are connected to the multiple pads 19A mentioned above using a flip-chip connection. Hereafter, when the electronic components 100X, 100Y, ... are not distinguished from each other, they will be collectively referred to as electronic component 100.

[0013] In Figure 2, the outline of the electronic component 100 and the pad 101 are shown with dashed lines, the pad 19A is shown with a solid line, and the outline of the wiring structure 20 and the connection point 22, which will be described later, are shown with a dashed line. Since the lines showing the connection point 22 and pads 19A and 101 are difficult to distinguish, some of the connection points 22 and pads 19A and 101 are shown enlarged in the upper left of Figure 2. In addition, the lines showing the connection points 22 and pads 19A and 101 are of different sizes to prevent them from overlapping, but the planar shapes of the connection points 22 and pads 19A and 101 may be the same or different.

[0014] All planar shapes of the electronic component 100 are rectangular, and as described above, multiple pads 101 are arranged in a matrix across the entire bottom surface. Furthermore, the pitch of the multiple pads 101 (hereinafter referred to as "pad pitch") differs between certain regions of each electronic component 100. Specifically, as shown in Figures 3A and 3B, the electronic component 100 has a first region R1 located near one of a pair of opposing outer edges, and a second region R2 located near the other, with the pad pitch of the second region R2 being larger than that of the first region R1. The second region R2 of electronic component 100X and the first region R1 of electronic component 100Y have the same pad pitch. That is, listing the pad pitches in ascending order, we have the first region R1 of electronic component 100X, followed by the second region R2 of electronic component 100X and the first region R1 of electronic component 100Y, and then the second region R2 of electronic component 100Y.

[0015] As shown in Figure 2, the aforementioned electronic components 100 are arranged symmetrically, for example, with their vertical and horizontal outer edges parallel or perpendicular to each other, and one pair of electronic components 100X is sandwiched between one pair of electronic components 100Y. Adjacent electronic components 100 are arranged so that areas with the same pad pitch are located close to each other's outer edges. The multiple pads 19A on the upper surface of the wiring board 10 are located directly below the pads 101 of the multiple electronic components 100.

[0016] Note that, in the wiring board 10 of the present embodiment, a plurality of electronic components 100 are arranged symmetrically. However, the arrangement of the plurality of electronic components 100 is arbitrary and may not be arranged symmetrically, and the orientations of the plurality of electronic components 100 may not be unified. Further, the above-described electronic component 100 may be a single semiconductor chip or a semiconductor chip package in which an interposer substrate and a semiconductor chip are combined. That is, any semiconductor component for surface mounting may be used. Furthermore, although the electronic component 100 of the present embodiment is assumed to be of the BGA (Ball Grid Array) type, it may be of the LGA (Land Grid Array) type.

[0017] In order to connect the plurality of pads 101 of adjacent electronic components 100 among the plurality of electronic components 100 shown in FIG. 2, three types of wiring structures 20X, 20Y, and 20Z of the first to third are embedded in the upper part of the build-up 12 on the upper side of the wiring board 10. When these first to third wiring structures 20X, 20Y, and 20Z are not distinguished, they are collectively referred to as a wiring structure 20. First, the common structure of all the wiring structures 20 will be described.

[0018] As shown in FIG. 4, the wiring structure 20 has, for example, a plate shape with a rectangular planar shape. Further, as shown in FIG. 5, a plurality of relay lines 23 are incorporated inside the wiring structure 20. Both ends of the plurality of relay lines 23 are exposed on the upper surface of the wiring structure 20 as a plurality of connection points 22. These plurality of connection points 22 are separately arranged in a first array region R3 corresponding to the first region R1 of two adjacent electronic components 100 and a second array region R4 corresponding to the second region R2. In the first array region R3 and the second array region R4, the pitch between the connection points 22 is constant. Further, as shown in FIG. 1, the connection point 22 and the pad 101 that overlap in the vertical direction are connected via the above-described metal post 19.

[0019] As shown in Figure 1, the wiring board 10 is provided with a cavity 30 that penetrates the lower insulating layer 13A of the outermost insulating layer 13 and the insulating layer 13 below it, with the plain layer 14P as its bottom surface. The cavity 30 is further divided into three cavities: one cavity 30 that houses a pair of first wiring structures 20X and a pair of second wiring structures 20Y together, and another cavity 30 that houses each of the third wiring structures 20Z. Alternatively, all wiring structures 20 may be housed together in one cavity 30, or each wiring structure 20 may be housed in a separate cavity 30.

[0020] Each wiring structure 20 is housed with its lower surface overlapping the bottom surface of the cavity 30. The upper surface of each wiring structure 20 is covered with the upper insulating layer 13B of the outermost insulating layer 13, and the resin constituting the upper insulating layer 13B fills the gap between the inner surface of the cavity 30 and the wiring structure 20, fixing the wiring structure 20 within the cavity 30. Metal posts 19 are connected to connection points 22 of the wiring structure 20 via via conductors 15 formed in the upper insulating layer 13B and the insulating layer 13 covering it from above. The upper ends of these multiple metal posts 19 become the aforementioned pads 19A, which are connected to multiple pads 101 of the electronic component 100. In other words, the connection points 22 of the vertically overlapping wiring structures 20 and the pads 101 of the electronic component 100 are connected via the metal posts 19.

[0021] As shown in Figure 1, some of the metal posts 19 are positioned on the opposite side of each third wiring structure 20Z from the second wiring structure 20Y and are connected to the third conductive layer 14 from the top of the wiring board 10 via via conductors 15. In addition, the pads 19A at the upper ends of these metal posts 19 are connected to a number of pads 101 located on the underside of the portion of the electronic component 100Z that is detached from the third wiring structure 20Z.

[0022] If we refer to the insulating layer 13 located at the bottom of the cavity 30 and having an upper surface as the "first insulating layer," and the lower insulating layer 13A as the "third insulating layer," then the wiring board 10 of this embodiment has a structure in which "a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer are stacked in order from bottom to top, and the cavity housing the wiring structure is formed to penetrate both the second insulating layer and the third insulating layer."

[0023] The detailed structure of the wiring structure 20 is as follows: The first wiring structure 20X is sometimes called a silicone patch and has a silicone layer 25 as a support layer at its bottom. The second wiring structure 20Y is sometimes called a glass patch and has a glass layer 26 as a support layer at its bottom. The third wiring structure 20Z is sometimes called a resin patch and has no support layer and does not include a glass layer or a silicone layer. An adhesive layer 28 is attached to the bottom surface of each wiring structure to fix the wiring structure 20 to the bottom of the cavity 30.

[0024] More specifically, as shown in Figure 5A, the first wiring structure 20X is provided with conductive layers 21B and insulating layers 21A alternately laminated on a silicon layer 25, with the uppermost layer being the insulating layer 21A. Each conductive layer 21B is provided with, for example, multiple lines 21D that do not intersect with each other (in Figure 5A, the uppermost line 21D is omitted). One or more stages of via conductors 21C that penetrate one or more insulating layers 21A are provided on both ends of each line 21D in the layers below the uppermost layer, and each of the uppermost via conductors 21C is connected to the uppermost conductive layer 21B. The relay line 23 is composed of each line 21D in the uppermost layer individually, as well as each line 21D in the layers below the uppermost layer and the via conductors 21C on both ends of them, and a part of the uppermost conductive layer 21B on those via conductors 21C. Then, both ends of each relay line 23 are exposed on the first wiring structure 20X through through holes 21K formed in the uppermost insulating layer 21A, forming the aforementioned connection points 22.

[0025] As simplified in Figures 5B and 5C, the second and third wiring structures 20Y and 20Z have the same basic configuration as the first wiring structure 20X, except that they either have a glass layer 26 instead of a silicon layer 25, or neither a silicon layer 25 nor a glass layer 26.

[0026] The planar size of the wiring structure 20 is smallest in the order of the first wiring structure 20X, the second wiring structure 20Y, and the third wiring structure 20Z. Also, the minimum L / S value of line 21D is smallest in the order of the first wiring structure 20X, the second wiring structure 20Y, and the third wiring structure 20Z. Specifically, the width L of line 21D is 0.5~2μm for the first wiring structure 20X, 2~3μm for the second wiring structure 20Y, and 3~5μm for the third wiring structure 20Z. Also, the width S of the space between lines 21D is 0.5~2μm for the first wiring structure 20X, 2~3μm for the second wiring structure 20Y, and 3~5μm for the third wiring structure 20Z.

[0027] In this embodiment, the wiring board 10 has multiple wiring structures 20 arranged symmetrically, but they do not have to be arranged symmetrically, and the orientation of the multiple wiring structures 20 does not have to be uniform. Also, although the wiring board 10 is provided with three types of wiring structures 20, the number of types of wiring structures 20 provided on the wiring board 10 may be two or four or more. Furthermore, not all electronic components 100 are connected by wiring structures 20; for example, a portion of the pads 101 of an electronic component 100 may be connected to the third conductive layer 14 from the top of the wiring board 10 via a metal post 19 and a via conductor 15.

[0028] This concludes the description of the wiring board 10 of this embodiment. Next, the manufacturing method of the wiring board will be described with reference to Figures 6 and 7. (1) A core substrate 11 is prepared. The core substrate 11 is a typical one in which copper foil is laminated on both sides of a resin-impregnated glass cloth, and through-hole conductors 18 and conductive layers 14 are formed on it. Next, an insulating layer 13 is laminated on the core substrate 11, and a conductive layer 14 is laminated on top of that by a known method (e.g., semi-additive method). Then, six layers each of insulating layers 13 and conductive layers 14 are laminated in the same manner. At this time, a solid plain layer 14P is formed on the fifth conductive layer 14 from the core substrate 11 side. In addition, multiple via conductors 15 are formed on each of the multiple insulating layers 13 (see Figure 6A).

[0029] (2) Another insulating layer 13 is added. This insulating layer 13 corresponds to the lower insulating layer 13A of the outermost insulating layer 13. Next, the portion of the lower insulating layer 13A that is superimposed on the plane layer 14P is irradiated with a CO2 laser, and a cavity 30 is formed that penetrates the lower insulating layer 13A and the adjacent insulating layer 13 (see Figure 6B).

[0030] (3) The walls and bottom of the cavity 30 are desmeared by permanganate treatment, and the surface of the plain layer 14P is treated with CZ. Next, the wiring structures 20 are placed inside the cavity 30. These wiring structures 20 are heated and pressurized by a bonding head (not shown), and the adhesive layer 28 on the bottom of the wiring structures 20 adheres tightly to the plain layer 14P (see Figure 6C).

[0031] (4) An insulating resin film (e.g., ABF) is placed on the upper surface of the wiring structure 20 and the cavity 30, and when heated and pressurized, the molten resin enters the gap between the side surface of the wiring structure 20 and the wall surface of the cavity 30, and the upper insulating layer 13B of the outermost insulating layer 13 is laminated. Next, a UV laser is irradiated onto the portion of the outermost insulating layer 13 that overlaps with the multiple connection points 22 of the wiring structure 20, and multiple via holes 15H are formed (see Figure 7A).

[0032] (5) After electroless plating, plating resist treatment, and electroplating treatment are performed and the plating resist is removed, a conductive layer 14 is laminated on the insulating layer 13, and via conductors 15 are formed in via holes 15H, and via lands 15A are formed at the upper end of the via conductors 15 (see Figure 7B).

[0033] (6) Furthermore, the outermost insulating layer 13 as a solder resist layer is laminated on the conductive layer 14, and an opening 13H is formed to expose the via lands 15A of the via conductor 15 by a known method such as photolithography. Next, electroless plating, plating resist treatment, and electrolytic plating treatment are applied to the outermost insulating layer 13 in order, and when the plating resist is removed, a metal post 19 is formed in the opening 13H, and a pad 19A at the upper end of the metal post 19 is formed on its upper surface (see Figure 7C).

[0034] (7) After the electronic components 100 are placed on the metal posts 19 by a chip mounter (not shown), a reflow process is performed to mount the electronic components 100 onto the metal posts 19.

[0035] In this embodiment, the metal post 19 was formed by plating, but instead of the metal post 19, solder may be formed in the opening 13H.

[0036] This concludes the explanation regarding the manufacturing method of the wiring board 10. The configuration of the wiring board 10 of this embodiment provides the following effects. In the current technology, the minimum achievable L / S and the maximum achievable planar size differ among the three types of wiring structures 20: the first wiring structure 20X including a silicon layer 25, the second wiring structure 20Y including a glass layer 26, and the third wiring structure 20Z not including a silicon layer or a glass layer. In the current technology, the minimum achievable L / S and the maximum achievable planar size decrease in the order of the first, second, third wiring structures 20X, 20Y, and 20Z.

[0037] On the other hand, the requirements for the electronic components 100 mounted on the wiring board 10 vary depending on their type, including the desired degree of high integration and the degree of large planar size. However, even if one tries to make the wiring of the wiring structure 20 denser to match the electronic components 100, which have many closely spaced pads, it may be difficult to meet the high integration requirements with wiring structures that have a glass layer or wiring structures that do not have a support layer. Furthermore, even if one tries to enlarge the wiring structure 20 to mount large electronic components 100, it is difficult to enlarge the planar size with wiring structures that have a silicon layer formed by cutting from a circular silicon wafer, and even if enlargement is possible, they are prone to breakage and have durability problems. In other words, if one tries to mount multiple types of electronic components 100 on a wiring board 10 equipped with only one type of wiring structure 20, problems such as reduced durability may occur.

[0038] In contrast, the wiring board 10 of this embodiment includes two or more types of wiring structures 20 that differ in planar size and minimum L / S, such as the first to third wiring structures 20X, 20Y, and 20Z, making it possible to mount multiple types of electronic components 100 that have different requirements for high integration.

[0039] [Second Embodiment] In the second embodiment described above, multiple electronic components 100 are each provided with a first region R1 and a second region R2 with different pad pitches, and the first region R1 and the second region R2 of adjacent electronic components 100 are connected by a wiring structure 20. In the wiring structure 20, the pitch of multiple connection points 22 arranged in the first array region R3 and the second array region R4 is the same in order to make the connection points 22 correspond to the pads 101. In this embodiment, the arrangement pitch of multiple connection points 22 differs between the first array region R3 and the second array region R4, which is a major difference from the above embodiment. The differences from the first embodiment will be explained below with reference to Figures 8 to 12.

[0040] As shown in Figure 9, electronic components 100A, 100B, 100C, and 100D are mounted on the wiring board 10 of this embodiment. For electronic components 100, except for electronic component 100A, multiple pads 101 are arranged in a matrix across the entire lower surface, while for electronic component 100A, multiple pads 101 are arranged in a matrix across the entire lower surface except for the central rectangular area. Furthermore, the pitch of the pads 101 of the electronic components 100 differs depending on the type of electronic component 100, for example, the arrangement pitch decreases in the order of electronic components 100D, 100A, 100B, and 100C.

[0041] Furthermore, the planar size of the pads 101 is approximately the same for electronic components 100A, 100B, and 100C other than electronic component 100D, while the planar size of the pad 101 of electronic component 100D is smaller than those of the others. In this embodiment, the relative sizes of the overall planar sizes of electronic components 100A, 100B, 100C, and 100D are similar to the relative sizes of the pad pitches described above. That is, for example, the planar sizes of electronic components 100D, 100A, 100B, and 100C are in decreasing order.

[0042] As shown in Figure 9, adjacent electronic components 100A and 100B, and electronic components 100B and 100C have different pad pitches. Therefore, the multiple connection points 22 of the wiring structure 20 connected to multiple pads 101 of these electronic components 100 have different pitches in the first array region R3 and the second array region R4, with the array pitch in the second array region R4 being larger than that in the first array region R3.

[0043] Specifically, the arrangement pitch of connection points 22 (hereinafter referred to as "connection point pitch" as appropriate) is the same for the second array region R4 of the first wiring structure 20A and the first array region R3 of the second wiring structure 20B (see Figures 10A and 10B), and the same for the second array region R4 of the second wiring structure 20B and the first array region R3 of the third wiring structure 20C (see Figures 10B and 10C). In other words, the connection point pitch is smallest in the first array region R3 of the first wiring structure 20A, followed by the second array region R4 of the first wiring structure 20A and the first array region R3 of the second wiring structure 20B, followed by the second array region R4 of the second wiring structure 20B and the first array region R3 of the third wiring structure 20C, and finally the second array region R4 of the third wiring structure 20C is the largest. Furthermore, the planar size of the wiring structures 20 is smallest for the first wiring structure 20A, followed by the second wiring structure 20B, and then the third wiring structure 20C, which is the largest.

[0044] In Figure 9, a pair of second wiring structures 20B are symmetrically arranged on both the left and right sides of a central region directly below the portion of the electronic component 100A that does not have a pad 101, and a pair of third wiring structures 20C are arranged on the opposite side of the central region from the pair of second wiring structures 20B (only one of the third wiring structures 20C is shown in Figure 9). Also, a pair of first wiring structures 20A are symmetrically arranged above and below the central region in Figure 9. In other words, a pair of first wiring structures 20A, a pair of second wiring structures 20B, and a pair of third wiring structures 20C are symmetrically arranged around the central region.

[0045] As shown in Figure 8, the multiple connection points 22 of the second array region R4 of one pair of first wiring structures 20A and the multiple connection points 22 of the first array region R3 of one pair of second wiring structures 20B are positioned directly below the multiple pads 101 of the electronic component 100A, the multiple connection points 22 of the second array region R4 of each second wiring structure 20B and the multiple connection points 22 of the first array region R3 of the third wiring structure 20C adjacent to each second wiring structure 20B are positioned directly below the multiple pads 101 of each electronic component 100B, and furthermore, the multiple connection points 22 of the second array region R4 of each third wiring structure 20C are positioned directly below the multiple pads 101 of each electronic component 100C closer to the electronic component 100B.

[0046] According to the wiring structure 20 of the second embodiment, the pitch of the connection points 22 differs between the first array region R3 and the second array region R4, so that electronic components 100 with different pad 101 arrangement pitches can be connected via the wiring structure 20.

[0047] Furthermore, by making the arrangement pitch of the connection points 22 the same in the second array region R4 of one wiring structure 20 and the first array region R3 of the other wiring structure 20, as in the relationship between the first and second wiring structures 20A and 20B, and the relationship between the second and third wiring structures 20B and 20C, electronic components 100 with different arrangement pitches of pads 101 can be connected via the wiring structure 20.

[0048] Furthermore, in the wiring board 10 of this embodiment, the arrangement pitch of the connection points 22 of the first, second, and third wiring structures 20A, 20B, and 20C has a relationship in which the arrangement pitch increases in two stages. That is, the arrangement pitch of the connection points 22 is the same for the second array region R4 of the first wiring structure 20A and the first array region R3 of the second wiring structure 20B, and the same for the second array region R4 of the second wiring structure 20B and the first array region R3 of the third wiring structure 20C. In this way, by configuring the arrangement pitch of the connection points 22 to increase in multiple stages among three or more types of wiring structures 20, three or more types of electronic components 100 with different pad arrangement pitches 101 can be connected via multiple wiring structures 20.

[0049] [Other embodiments]

[0050] (1) In the above embodiment, all of the first, second, and third wiring structures 20X, 20Y, and 20Z were provided, but only two of these three types may be provided. For example, the wiring board 10 may be provided only with the first and second wiring structures 20X and 20Y, and the minimum L / S of the relay lines 23 may be smallest and the planar size may be smallest in the order of the first and second wiring structures 20X and 20Y. Alternatively, the wiring board 10 may be provided only with the second and third wiring structures 20Y and 20Z, and the minimum L / S of the multiple relay lines 23 may be smallest and the planar size may be smallest in the order of the second and third wiring structures 20Y and 20Z. Furthermore, the wiring board 10 may be provided only with the first and third wiring structures 20X and 20Z, and the minimum L / S of the multiple relay lines 23 may be smallest and the planar size may be smallest in the order of the first and third wiring structures 20X and 20Z.

[0051] (2) Furthermore, wiring structures 20X, 20Y, 20Z, in which all connection points 22 have the same arrangement pitch, and wiring structures 20A, 20B, 20C, in which the arrangement pitch differs between the first array region R3 and the second array region R4, may be mixed together.

[0052] (3) As described above, with current technology, the minimum L / S and maximum planar size are smallest in the order of the first wiring structure 20X including the silicon layer 25, the second wiring structure 20Y including the glass layer 26, and the third wiring structure 20Z not including either the silicon layer or the glass layer. However, the minimum L / S and planar size of the first, second, and third wiring structures 20X, 20Y, and 20Z provided on the wiring board 10 do not have to be in the order of feasibility. As long as at least one of the minimum L / S or planar size differs between two of the multiple types of wiring structures 20 provided on the wiring board 10, the minimum L / S and planar size may be the same or reversed from the order of feasibility among different types of wiring structures 20.

[0053] Specifically, the L / S of the relay lines 23 may be the same for a wiring structure 20X equipped with a silicon layer 25 and a wiring structure 20Y equipped with a glass layer 26, and the planar size of a wiring structure 20Y equipped with a glass layer 26 may be the same as that of a wiring structure 20Z equipped with neither a silicon layer 25 nor a glass layer 26. Furthermore, for example, the minimum L / S of a wiring structure 20Y equipped with a glass layer 26 may be smaller than that of a wiring structure 20X equipped with a silicon layer 25, and the planar size of a wiring structure 20Z equipped with neither a silicon layer 25 nor a glass layer 26 may be smaller than that of a wiring structure 20Y equipped with a glass layer 26. In other words, by considering the types of electronic components 100 to be mounted and the space available for arranging the wiring structure 20, it is possible to select the most suitable one for the wiring structure 20 from among those equipped with a silicon layer 25, a glass layer 26, or neither a silicon layer 25 nor a glass layer 26.

[0054] (4) In the above embodiment, as shown in Figure 2, the electronic component 100X and the electronic component 100Y located to the right of the electronic component 100X, and the electronic component 100X and the electronic component 100Y located to the left of the electronic component 100X were each individually connected by two second wiring structures 20Y. However, they may also be connected by a single second wiring structure 20Y extending from the right electronic component 100Y to the left electronic component 100Y. Specifically, the relay line 23 connecting the electronic component 100X and the right electronic component 100Y, and the relay line 23 connecting the electronic component 100X and the left electronic component 100Y, may be formed together within the second wiring structure 20Y.

[0055] (5) In the above embodiment, the multiple relay lines 23 of each wiring structure 20 are structured to relay some of the total pads 101 of two electronic components 100 to each other. However, for example, they may be structured to relay all the pads 101 of one electronic component 100 to some of the pads 101 of the other electronic component 100. Also, in the above embodiment, the wiring structure 20 is structured to relay two electronic components 100 to each other. However, it may also be structured to relay the pads 101 of three or more electronic components 100 to each other.

[0056] (6) Two or more insulating layers 13 may be laminated on the wiring structure 20, or only one layer may be laminated. Also, adjacent wiring structures 20 may be arranged at different heights in the lamination direction.

[0057] (7) The wiring structure 20 does not have to be a laminated structure. For example, it may be a configuration in which glass or silicon is used as the base material and relay wires 23 are formed inside it.

[0058] While this specification and drawings disclose specific examples of the technology included in the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and changes to these examples, as well as parts of the examples taken individually. [Explanation of Symbols]

[0059] 10 Wiring board 13. Insulating layer 14. Conductive layer 15 via conductors 19 Metal Post 20X, 20Y, 20Z, 20W Wiring Structure 21D Line 22 connection points 23 relay lines 25 Silicon layer 26 glass layer 30 Cavity 100X, 100Y, 100Z, 100W Electronic Components R1 First Array Region R2 Second Array Region

Claims

1. A wiring board having multiple wiring structures that incorporate multiple relay lines and whose ends are exposed on the upper surface as multiple connection points, and a cavity that receives the multiple wiring structures, The aforementioned plurality of wiring structures include: A first wiring structure whose lower part is a silicon layer, A second wiring structure, the lower part of which is a glass layer, The system includes two or more types of third wiring structures, the lower part of which is a resin layer and which does not include a glass layer or a silicon layer, and the two or more types of wiring structures differ in at least one of their planar size or the minimum L / S of the plurality of relay lines.

2. A wiring board according to claim 1, The device is provided with a multilayer structure in which a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer are stacked in order from bottom to top. The cavity is formed to penetrate both the second insulating layer and the third insulating layer.

3. A wiring board according to claim 1, The system comprises two types of wiring structures, the first and second wiring structures described above. In the order of the first and second wiring structures, the minimum L / S of the plurality of relay lines is small and the planar size is small.

4. A wiring board according to claim 1, The system comprises two types of wiring structures, the second and third wiring structures described above. In the order of the second and third wiring structures, the minimum L / S of the multiple relay lines is small and the planar size is small.

5. A wiring board according to claim 1, The system comprises two types of wiring structures, the first and third wiring structures described above. In the order of the first and third wiring structures, the minimum L / S of the multiple relay lines is small and the planar size is small.

6. A wiring board according to claim 1, The system comprises three types of wiring structures: the first, second, and third wiring structures described above. In the order of the first, second, and third wiring structures, the minimum L / S of the multiple relay lines is small and the planar size is small.

7. A wiring board according to claim 1, The wiring structure is one of the first, second, and third wiring structures and comprises a first array region in which the plurality of connection points are arranged in a matrix and connected to the pads of a first electronic component, and a second array region in which the plurality of connection points are arranged in a matrix with the same arrangement pitch as the first array region and connected to the pads of a second electronic component.

8. A wiring board according to claim 1, The plurality of connection points are arranged in a matrix, and the arrangement pitch of the plurality of connection points differs among different types of wiring structures.

9. A wiring board according to any one of claims 1 to 8, It is equipped with an electronic component that has multiple pads on its underside. The plurality of pads of the electronic component are positioned and connected to the plurality of connection points of the two or more types of wiring structures, overlapping them from above.

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