Capacitive load drive circuit, and control method for a capacitive load drive circuit

Abstract

To provide a capacitive load drive circuit that can improve the waveform accuracy of the drive signal. [Solution] A capacitive load drive circuit comprising: a modulation circuit that outputs a modulated signal obtained by modulating a base drive signal; an amplification circuit that outputs a first amplified modulated signal obtained by amplified the modulated signal; a level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential; a level shift circuit that outputs a signal obtained by shifting the reference potential of the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the first potential, and outputs the first amplified modulated signal as a second amplified modulated signal when the level switching signal is at the second potential; and a demodulation circuit that demodulates the second amplified modulated signal and outputs a drive signal, wherein the level switching signal output circuit switches the potential of the level switching signal according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of a plurality of capacitive loads driven by the drive signal.

Description

Technical Field

[0001] The present invention relates to a capacitive load driving circuit and a method for controlling the capacitive load driving circuit.

Background Art

[0002] In a liquid ejection device that ejects liquid to form an image or a document on a medium, a device using a piezoelectric element is known. In such a liquid ejection device, piezoelectric elements are provided corresponding to each of a plurality of nozzles that eject liquid, and each is driven according to a drive signal. Then, when the piezoelectric element is driven, liquid is ejected from the nozzle provided corresponding to the piezoelectric element. In order to operate such a piezoelectric element, it is necessary to supply sufficient current. Therefore, a drive circuit that outputs a drive signal for driving the piezoelectric element includes an amplifier circuit that amplifies a source signal serving as a basis of the drive signal by an amplifier circuit.

[0003] Patent Document 1 discloses a circuit that pulse-modulates a base drive signal serving as a basis of a drive signal, amplifies the pulse-modulated modulation signal, and outputs it as a drive signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, from the viewpoint of improving the waveform accuracy of the output drive signal, the technique described in Patent Document 1 alone is not sufficient, and there is room for improvement.

Means for Solving the Problems

[0006] One aspect of the capacitive load driving circuit according to the present invention is A capacitive load drive circuit that outputs drive signals to drive multiple capacitive loads, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs a first amplified modulated signal obtained by amplifying the aforementioned modulated signal, A level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential, A level shift circuit that outputs a signal obtained by shifting the reference potential of the first amplification modulation signal as a second amplification modulation signal when the level switching signal is at the first potential, and outputs the first amplification modulation signal as a second amplification modulation signal when the level switching signal is at the second potential, A demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal, Equipped with, The level switching signal output circuit switches the potential of the level switching signal according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of the plurality of capacitive loads driven by the drive signal.

[0007] One aspect of the control method for a capacitive load drive circuit according to the present invention is: A control method for a capacitive load drive circuit that outputs drive signals to drive multiple capacitive loads, A modulation step that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification step which outputs a first amplified modulated signal obtained by amplifying the modulated signal, A level switching signal output process that outputs a level switching signal that changes between a first potential and a second potential, A level shifting step in which, when the level switching signal is at the first potential, a signal obtained by shifting the reference potential of the first amplification modulation signal is output as the second amplification modulation signal, and when the level switching signal is at the second potential, the first amplification modulation signal is output as the second amplification modulation signal, A demodulation step which demodulates the second amplified modulated signal and outputs the drive signal, It has, In the level switching signal output step, the potential of the level switching signal is switched according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of the plurality of capacitive loads driven by the drive signal.

Brief Description of Drawings

[0008] [Figure 1] It is a diagram showing an example of the structure of a liquid ejection device. [Figure 2] It is a diagram showing the functional configuration of a liquid ejection device. [Figure 3] It is a diagram showing an example of the arrangement of a plurality of ejection parts in a head unit. [Figure 4] It is a diagram showing an example of the configuration of an ejection part. [Figure 5] It is a diagram showing an example of the signal waveform of the drive signal COM. [Figure 6] It is a diagram showing an example of the configuration of a drive signal selection circuit. [Figure 7] It is a diagram showing an example of the decoding content in a decoder. [Figure 8] It is a diagram showing an example of the configuration of a selection circuit. [Figure 9] It is a diagram for explaining the operation of a drive signal selection circuit. [Figure 10] It is a diagram showing an example of the functional configuration of a drive circuit. [Figure 11] It is a diagram for explaining the operation of a drive circuit. [Figure 12] It is a diagram showing an example of the configuration of a level switching signal output circuit. [Figure 13] It is a diagram showing an example of the configuration of a high-pass filter included in a feedback circuit. [Figure 14] It is a diagram for explaining the operation of a level switching signal output circuit. [Figure 15] It is a diagram for explaining the mechanism in which overshoot occurs. [Figure 16] It is a diagram for explaining the mechanism in which undershoot occurs. [Figure 17] It is a diagram showing a liquid ejection device and a control method of a drive circuit. [Figure 18] It is a diagram showing an example of a driving piezoelectric element number calculation process.

Mode for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0010] In the following description, as an example of the liquid ejection device according to the present invention, a serial printing type inkjet printer for consumers is used. However, the liquid ejection device is not limited to the serial printing type, and may be a line printing type. Also, the liquid ejection device is not limited to an inkjet printer for consumers, and may be a business inkjet printer for offices, or a portable inkjet printer that can be driven by a battery or the like and can be carried. Further, the liquid ejection device is not limited to an inkjet printer, and for example, a color material ejection device used for manufacturing a color filter such as a liquid crystal display, an electrode material ejection device used for forming electrodes such as an organic EL display and a surface emission display, a biological organic matter ejection device used for manufacturing a biochip, etc. may also be used.

[0011] 1. Outline of the liquid ejection device FIG. 1 is a diagram showing an example of the structure of a liquid ejection device 1. As shown in FIG. 1, the liquid ejection device 1 includes a moving body 2 and a moving unit 3 that reciprocates the moving body 2 along the main scanning direction.

[0012] The moving unit 3 includes a carriage motor 31 which serves as the driving source for the reciprocating movement of the moving body 2 along the main scanning direction, a carriage guide shaft 32 with both ends fixed, and a timing belt 33 which extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31.

[0013] The mobile body 2 has a carriage 24. The carriage 24 is supported on a carriage guide shaft 32 so as to be able to move back and forth and is also fixed to a part of the timing belt 33. The timing belt 33 is moved in forward and reverse directions by the carriage motor 31, and the mobile body 2 having the carriage 24 is guided by the carriage guide shaft 32 to move back and forth. A head unit 20 is located on the part of the mobile body 2 that faces the medium P. That is, the head unit 20 is mounted on the carriage 24. Numerous nozzles for ejecting ink, which is an example of a liquid, are located on the surface of the head unit 20 that faces the medium P. Various control signals that control the operation of the head unit 20 are supplied to the head unit 20 via a cable 190. As such a cable 190, a flexible flat cable that can slide in accordance with the reciprocating movement of the mobile body 2 can be used.

[0014] Furthermore, the liquid dispensing device 1 includes a conveying unit 4 that conveys the medium P on the platen 40 along the conveying direction. The conveying unit 4 has a conveying motor 41 which is the driving source for conveying the medium P, and a conveying roller 42 which conveys the medium P along the conveying direction by rotating in accordance with the driving force of the conveying motor 41.

[0015] In the liquid dispensing device 1 configured as described above, the head unit 20 dispenses ink onto the medium P in synchronization with the timing of the medium P being transported by the transport unit 4. As a result, the ink dispensed by the head unit 20 lands at a desired position on the medium P, forming a desired image or characters on the surface of the medium P.

[0016] Next, the functional configuration of the liquid dispensing device 1 will be described. Figure 2 is a diagram showing the functional configuration of the liquid dispensing device 1. As shown in Figure 2, the liquid dispensing device 1 comprises a control unit 10, a head unit 20, a moving unit 3, a transport unit 4, and a cable 190. The cable 190 electrically connects the control unit 10 and the head unit 20.

[0017] The control unit 10 has a control circuit 100.

[0018] The control circuit 100 receives image data from an external device (not shown) located outside the liquid dispensing device 1, such as a host computer. The control circuit 100 performs various image processing operations on the supplied image data to generate various control signals for controlling each part of the liquid dispensing device 1, and outputs these signals to each part. Such a control circuit 100 is configured to include a processor, such as a CPU.

[0019] Specifically, the control circuit 100 generates a control signal Ctrl1 to control the reciprocating movement of the mobile body 2 based on image data and outputs it to the carriage motor 31 included in the mobile unit 3. The control circuit 100 also generates a control signal Ctrl2 to control the transport of the medium P based on image data and outputs it to the transport motor 41 included in the transport unit 4. As a result, the reciprocating movement of the mobile body 2 along the main scanning direction and the transport of the medium P along the transport direction are controlled by the control circuit 100. In other words, the head unit 20 can eject ink onto the medium P at a predetermined timing synchronized with the transport of the medium P. This makes it possible to land the ink at a desired position on the medium P and form a desired image or character on the medium P.

[0020] The control circuit 100 may also supply the control signal Ctrl1 for controlling the reciprocating movement of the mobile body 2 to the mobile unit 3 after it has been converted by a carriage motor driver (not shown), and similarly, it may supply the control signal Ctrl2 for controlling the transport of the medium P to the transport unit 4 after it has been converted by a transport motor driver (not shown).

[0021] Furthermore, the control circuit 100 generates a clock signal SCK, a print data signal SI, a latch signal LAT, a base drive signal dA, a waveform information signal WAV, and a drive element count information signal CNT for controlling the operation of the head unit 20, and outputs them to the head unit 20.

[0022] The head unit 20 includes a drive circuit 50, a drive signal selection circuit 200, and a discharge head 21. The drive signal selection circuit 200 includes a selection control circuit 210 and a plurality of selection circuits 230, and the discharge head 21 has a plurality of discharge sections 600, each containing a piezoelectric element 60. In this case, each of the plurality of selection circuits 230 in the drive signal selection circuit 200 is provided in correspondence with the piezoelectric element 60 included in each of the plurality of discharge sections 600 in the discharge head 21.

[0023] The base drive signal dA, waveform information signal WAV, and drive element count information signal CNT output by the control unit 10 are input to the drive circuit 50. The base drive signal dA is a digital signal containing information that defines the signal waveform of the drive signal COM that drives the piezoelectric element 60, which will be described later. The waveform information signal WAV is the waveform information of the output drive signal COM, and includes, for example, information on the voltage value of the drive signal COM and information on the amount of change of the voltage value of the drive signal COM per unit time. The drive element count information signal CNT includes the number of piezoelectric elements 60 driven by the drive signal COM output by the drive circuit 50 during the dot formation period T, which will be described later.

[0024] In other words, the control circuit 100 outputs a waveform information signal WAV containing waveform information of the drive signal COM, and a drive element number information signal CNT containing information on the number of piezoelectric elements 60 driven by the drive signal COM.

[0025] The drive circuit 50 converts the base drive signal dA into an analog signal, and then generates and outputs a drive signal COM by amplifying the converted analog signal based on the waveform information signal WAV and the drive element number information signal CNT.

[0026] The clock signal SCK, print data signal SI, and latch signal LAT output by the control unit 10 are input to the selection control circuit 210 of the drive signal selection circuit 200. The selection control circuit 210 generates a selection signal S corresponding to each of the multiple selection circuits 230, which defines whether to select or deselect the drive signal COM based on the clock signal SCK, print data signal SI, and latch signal LAT, and outputs the generated selection signal S to the corresponding selection circuit 230.

[0027] Each of the multiple selection circuits 230 receives a drive signal COM and a corresponding selection signal S. Each of the multiple selection circuits 230 generates a drive signal VOUT by selecting or deselecting the drive signal COM based on the input selection signal S. The multiple selection circuits 230 then supply the generated drive signal VOUT to one end of the piezoelectric element 60 included in the corresponding discharge section 600 included in the discharge head 21.

[0028] A reference voltage signal VBS is supplied in common to the other end of each piezoelectric element 60 included in the multiple discharge units 600. The reference voltage signal VBS is a signal with a constant voltage value that functions as the reference potential for driving the piezoelectric element 60 driven by the drive signal VOUT. For example, it may be a DC voltage signal such as 5.5V or 6V, or it may be a signal with a constant voltage value at ground potential.

[0029] Multiple piezoelectric elements 60 are provided corresponding to each of the multiple nozzles in the head unit 20. The piezoelectric elements 60 are driven according to the potential difference between a drive signal VOUT supplied to one end and a reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the amount of drive of the piezoelectric elements 60 is ejected from the ejection unit 600 which includes the piezoelectric elements 60.

[0030] Although Figure 2 illustrates a case where the head unit 20 has one ejection head 21, the head unit 20 may have multiple ejection heads 21 depending on the type and number of inks to be ejected.

[0031] Here, we will describe the configuration of the multiple discharge sections 600 that the discharge head 21 has and an example of the arrangement of the multiple discharge sections 600 in the head unit 20. Figure 3 is a diagram showing an example of the arrangement of the multiple discharge sections 600 in the head unit 20. Figure 3 illustrates the case where the head unit 20 has four discharge heads 21.

[0032] As shown in Figure 3, each of the four discharge heads 21 has a plurality of discharge sections 600 arranged in a row in one direction. That is, each discharge head 21 includes a nozzle row L in which nozzles 651, which will be described later, included in the discharge section 600 are arranged in one direction. Furthermore, in the head unit 20, the discharge heads 21 are positioned in a direction intersecting the nozzle row L. That is, the head unit 20 has the same number of nozzle rows L as the number of discharge heads 21. Note that the arrangement of nozzles 651 in the nozzle row L is not limited to a single row. For example, they may be arranged in a staggered pattern such that the positions of the even-numbered nozzles 651 counted from one end of the plurality of nozzles 651 and the odd-numbered nozzles 651 counted from one end of the plurality of nozzles 651 are different, or a single nozzle row L may be formed by arranging multiple nozzles 651 in two or more rows.

[0033] Next, an example of the configuration of the dispensing unit 600 will be described. Figure 4 is a diagram showing an example of the configuration of the dispensing unit 600. As shown in Figure 4, the dispensing unit 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651. The diaphragm 621 is displaced in conjunction with the driving of the piezoelectric element 60, which is located on the upper surface in Figure 4. The diaphragm 621 functions as a diaphragm that expands / contracts the internal volume of the cavity 631. The inside of the cavity 631 is filled with ink. The cavity 631 functions as a pressure chamber whose internal volume changes due to the displacement of the diaphragm 621 caused by the driving of the piezoelectric element 60. The nozzle 651 is formed in the nozzle plate 632 and is an opening that communicates with the cavity 631. Then, as the internal volume of the cavity 631 changes, the ink stored inside the cavity 631 is dispensed from the nozzle 651.

[0034] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In this structure, the piezoelectric body 601, electrodes 611 and 612, and the central part of the diaphragm 621, flex in the vertical direction shown in Figure 4 relative to both ends, depending on the potential difference between electrodes 611 and 612.

[0035] Specifically, a drive signal VOUT is supplied to electrode 611 at one end of the piezoelectric element 60, and a reference voltage signal VBS is supplied to electrode 612 at the other end. When the piezoelectric element 60 is driven upward in response to a change in the voltage of the drive signal VOUT, the diaphragm 621 is displaced upward. As a result, the internal volume of the cavity 631 expands. Therefore, the ink stored in the reservoir 641 is drawn into the cavity 631. On the other hand, when the piezoelectric element 60 is driven downward in response to a change in the voltage value of the drive signal VOUT, the diaphragm 621 is displaced downward. As a result, the internal volume of the cavity 631 shrinks. Therefore, an amount of ink corresponding to the degree of reduction in the internal volume of the cavity 631 is ejected from the nozzle 651.

[0036] As described above, the ejection head 21 includes a piezoelectric element 60, and ejects ink onto the medium P by driving the piezoelectric element 60. Note that the ejection unit 600 and the piezoelectric element 60 included in the ejection unit 600 are not limited to the illustrated configuration, and any structure in which the piezoelectric element 60 is driven based on the drive signal VOUT and ink is ejected from the corresponding nozzle 651 by driving the piezoelectric element 60 is acceptable.

[0037] As described above, the liquid dispensing device 1 of this embodiment includes a dispensing head 21 that dispenses ink by driving a plurality of piezoelectric elements 60 which are driven when a drive signal COM is supplied, a drive circuit 50 that outputs a drive signal COM, and a control circuit 100 that controls the dispensing head 21 and the drive circuit 50.

[0038] 2. Configuration and Operation of the Drive Signal Selection Circuit Next, the configuration and operation of the drive signal selection circuit 200 will be described.

[0039] In order to explain the configuration and operation of the drive signal selection circuit 200, first, an example of the signal waveform of the drive signal COM output by the drive circuit 50 and input to the drive signal selection circuit 200 will be described. Figure 5 is a diagram showing an example of the signal waveform of the drive signal COM. As shown in Figure 5, the drive signal COM includes a drive waveform Adp at each dot formation period T from the rising edge of the latch signal LAT until the next rising edge of the latch signal LAT. The drive waveform Adp includes a period of constant voltage vc, followed by a period of constant voltage vb at a voltage lower than voltage vc, followed by a period of constant voltage vb at a voltage higher than voltage vc, followed by a period of constant voltage vt at a voltage of constant voltage vc. In other words, the drive signal COM includes a drive waveform Adp that starts and ends at voltage vc in the dot formation period T, as the voltage changes between voltage vt and voltage vb.

[0040] Voltage vc corresponds to the reference potential for the displacement of the piezoelectric element 60. When the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vc to voltage vb, the piezoelectric element 60 is driven upward as shown in Figure 4. As a result, the diaphragm 621 is displaced upward as shown in Figure 4. As the diaphragm 621 is displaced upward as shown in Figure 4, the internal volume of the cavity 631 expands, and ink is drawn from the reservoir 641 into the cavity 631. Subsequently, when the voltage of the drive signal COM supplied to the piezoelectric element 60 changes from voltage vb to voltage vt, the piezoelectric element 60 is driven downward as shown in Figure 4. As a result, the diaphragm 621 is displaced downward as shown in Figure 4. As the diaphragm 621 is displaced downward as shown in Figure 4, the internal volume of the cavity 631 decreases, and the ink stored in the cavity 631 is ejected from the nozzle 651.

[0041] Furthermore, for a certain period after ink is ejected from the nozzle 651 by the drive of the piezoelectric element 60, the ink near the nozzle 651 and the diaphragm 621 may continue to vibrate. The voltages vc, vt, and vb included in the drive signal COM for a certain period also function as a period to stop such vibrations in the ink and diaphragm 621 that do not contribute to ink ejection.

[0042] Here, the signal waveform of the drive signal COM shown in Figure 5 is just one example and is not limited to this. Various signal waveforms with different shapes may be included, depending on the physical properties of the ink ejected by the ejection head 21, the length of the dot formation period T, the transport speed of the medium P, etc.

[0043] Next, the configuration and operation of the drive signal selection circuit 200, which generates the drive signal VOUT by selecting or deselecting the drive signal COM and outputs it to the corresponding discharge unit 600, will be described. Figure 6 shows an example of the configuration of the drive signal selection circuit 200.

[0044] The drive signal selection circuit 200 includes a selection control circuit 210 and a selection circuit 230. The selection control circuit 210 receives a clock signal SCK, a print data signal SI, and a latch signal LAT. The selection control circuit 210 is also provided with a set of a shift register (S / R) 212, a latch circuit 214, and a decoder 216, corresponding to each of the n piezoelectric elements 60. That is, the selection control circuit 210 includes n shift registers 212, n latch circuits 214, and n decoders 216.

[0045] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. The print data signal SI also serially includes 1-bit print data SId for selecting "eject Dt" and "non-eject nDt," corresponding to each of the n piezoelectric elements 60. The print data SId included in the print data signal SI is held in n shift registers 212 corresponding to the n piezoelectric elements 60. Specifically, the n shift registers 212 corresponding to the piezoelectric elements 60 are connected in cascading, and the serially input print data signal SI is sequentially transferred to the subsequent shift registers 212 according to the clock signal SCK. When the print data SId is held in the corresponding shift register 212, the clock signal SCK stops. As a result, the print data SId included in the print data signal SI is held in the corresponding shift register 212. In Figure 6, the n shift registers 212 are labeled as stage 1, stage 2, ..., n in order from the upstream side where the print data signal SI is input, in order to distinguish them. Furthermore, in the following explanation, the print data SId corresponding to stage 1, stage 2, ..., n may be referred to as print data SId-1, SId-2, ..., SId-n.

[0046] Each of the n latch circuits 214 simultaneously latches the print data Sid held in the corresponding shift register 212 on the rising edge of the latch signal LAT. The print data Sid latched by the latch circuits 214 is then input to the corresponding decoder 216. Figure 7 shows an example of the decoding content in the decoder 216. The decoder 216 outputs a logic level selection signal S defined by the input print data Sid during the dot formation period T. Specifically, when print data Sid=[1] is input, the decoder 216 outputs a signal obtained by level-shifting an H-level signal to a high-amplitude logic signal as the H-level selection signal S during the dot formation period T. When print data Sid=[0] is input, the decoder 216 outputs a signal obtained by level-shifting an L-level signal to a high-amplitude logic signal as the L-level selection signal S during the dot formation period T.

[0047] The selection signal S output by the decoder 216 is input to the corresponding selection circuit 230. The selection circuit 230 is provided for each of the n output units 600. Figure 8 shows an example of the configuration of the selection circuit 230. As shown in Figure 8, the selection circuit 230 includes an inverter 232 which is a NOT gate and a transfer gate 234.

[0048] The selection signal S is input to the positive control terminal of the transfer gate 234 that is not marked with a circle, and after its logic level is inverted by the inverter 232, it is also input to the negative control terminal of the transfer gate 234 that is marked with a circle. In addition, the drive signal COM is supplied to the input terminal of the transfer gate 234. The transfer gate 234 conducts between its input terminal and output terminal when a high-level selection signal S is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S is input. That is, when the selection signal S is at a high level, the transfer gate 234 outputs the drive waveform Adp included in the drive signal COM from its output terminal, and does not output the drive waveform Adp included in the drive signal COM from its output terminal when the selection signal S is at a low level. The signal at the output terminal of the transfer gate 234 is then output from the selection circuit 230 as the drive signal VOUT.

[0049] The operation of the drive signal selection circuit 200 will now be explained. Figure 9 is a diagram illustrating the operation of the drive signal selection circuit 200. The print data signal SI is input to the selection control circuit 210 as a serial signal containing the print data Sid serially, and in synchronization with the clock signal SCK, it is sequentially transferred to the n shift registers 212 corresponding to the n piezoelectric elements 60. After that, when the supply of the clock signal SCK is stopped, the shift registers 212 hold the print data Sid corresponding to each of the n piezoelectric elements 60. The print data signal SI is input as a signal containing the print data Sid in the order corresponding to the nth, ..., 2nd, and 1st stages of the piezoelectric elements 60 in the shift registers 212.

[0050] Then, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data Sid held in the shift register 212. Note that LT1, LT2, ..., LTn shown in Figure 9 represent the print data Sid latched by the latch circuits 214 corresponding to the 1st, 2nd, ..., nth stage shift register 212. That is, LT1 corresponds to print data Sid-1, and LTn corresponds to print data Sid-n.

[0051] The decoder 216 outputs a selection signal S with a logic level defined by the latched print data Sid at each dot formation period T. The selection circuit 230 then generates the drive signal VOUT by selecting or deselecting the drive signal COM according to the logic level of the selection signal S output by the decoder 216.

[0052] Specifically, when print data Sid=[1] is input to the decoder 216, the decoder 216 sets the selection signal S at the dot formation period T to the H level. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Adp, to the piezoelectric element 60 of the corresponding ejection unit 600 at the dot formation period T. Consequently, ink is ejected from the corresponding ejection unit 600. When this ink ejected from the ejection unit 600 lands on the medium P, dots are formed on the medium P.

[0053] Furthermore, when print data Sid=[0] is input to the decoder 216, the decoder 216 sets the selection signal S at the dot formation period T to a low level. As a result, the selection circuit 230 does not output the drive signal VOUT, which includes the drive waveform Adp, at the dot formation period T. At this time, the piezoelectric element 60 of the corresponding ejection unit 600 is supplied with a signal of a constant voltage value held by the capacitive component of the piezoelectric element 60. In other words, the selection circuit 230 supplies the drive signal VOUT of the corresponding ejection unit 600 to the piezoelectric element 60 at the dot formation period T. As a result, the piezoelectric element 60 of the corresponding ejection unit 600 is not driven, and ink is not ejected from the corresponding ejection unit 600. Therefore, no dots are formed on the medium P.

[0054] As described above, the drive signal selection circuit 200 generates a drive signal VOUT by selecting or deselecting the drive signal COM output by the drive circuit 50, and outputs it to the piezoelectric element 60 of the corresponding discharge unit 600.

[0055] 3. Drive Circuit Configuration Next, the configuration of the drive circuit 50 will be described. Figure 10 is a diagram showing an example of the functional configuration of the drive circuit 50. As shown in Figure 10, the drive circuit 50 includes a D / A conversion circuit 510, an adder 511, a modulation circuit 520, an inverter 521, an amplification circuit 550, a demodulation circuit 560, a feedback circuit 570, a level switching signal output circuit 710, and a level shift circuit 750.

[0056] The D / A conversion circuit 510 receives a digital signal, the base drive signal dA, from the control circuit 100. The D / A conversion circuit 510 performs a digital-to-analog conversion on the input base drive signal dA, and then outputs the converted analog signal as the base drive signal aA. The voltage amplitude of this base drive signal aA is, for example, 1 to 2V, and the drive circuit 50 outputs an amplified signal of the base drive signal aA as the drive signal COM. In other words, the base drive signal aA corresponds to the target signal before amplification of the drive signal COM.

[0057] The base drive signal aA is input to the positive input terminal of adder 511. The feedback signal VFB2, which is the drive signal COM fed back via the feedback circuit 570 described later, is input to the negative input terminal of adder 511. Adder 511 outputs a signal obtained by subtracting the feedback signal VFB2 from the base drive signal aA to the modulation circuit 520.

[0058] The modulation circuit 520 generates a modulated signal MS by pulse modulating the signal output by the adder 511. The modulation circuit 520 then outputs the generated modulated signal MS to the amplifier circuit 550. Such a modulation circuit 520 generates a pulse density modulated signal (PDM signal) by modulating the signal output by the adder 511 using the pulse density modulation (PDM) method, and outputs this PDM signal as the modulated signal MS to the amplifier circuit 550. Specifically, the modulation circuit 520 compares the voltage of the output signal of the adder 511 with a predetermined reference voltage. The modulation circuit 520 then generates a modulated signal MS that is high level when the voltage of the output signal of the adder 511 is greater than the reference voltage, and low level when the voltage of the output signal of the adder 511 is less than the reference voltage, and outputs this to the amplifier circuit 550.

[0059] The amplification circuit 550 includes a gate drive circuit 530, a diode D1, a capacitor C1, and transistors M1 and M2. The amplification circuit 550 generates a first amplified modulated signal AMS1 by amplifying the input modulated signal MS and outputs it from the first output point OP1.

[0060] The gate drive circuit 530 outputs gate drive signals HGD1 and LGD1 based on the modulated signal MS. Specifically, the modulated signal MS is input to the gate driver 531 of the gate drive circuit 530. The gate driver 531 generates the gate drive signal HGD1 by level-shifting the input modulated signal MS and outputs it to transistor M1. The modulated signal MS is also input to the gate driver 532 of the gate drive circuit 530 after its logic level is inverted in the inverter 521. The gate driver 532 generates the gate drive signal LGD1 by level-shifting the signal whose logic level has been inverted from the input modulated signal MS and outputs it to transistor M2.

[0061] Transistors M1 and M2 are both N-channel MOSFETs. Transistor M1 operates based on a gate drive signal HGD1, which is input to its gate terminal, with its source terminal electrically connected to the first output point OP1 and a voltage signal VD1 supplied to its drain terminal. Transistor M2 operates based on a gate drive signal LGD1, which is input to its gate terminal, with its drain terminal electrically connected to the first output point OP1 and a ground potential supplied to its source terminal. As transistors M1 and M2 operate based on the gate drive signal HGD1 and LGD1, a first amplified modulated signal AMS1 is generated at the first output point OP1 by amplifying the modulated signal MS with a voltage vd1, which is the voltage value of the voltage signal VD1. Here, the voltage vd1 is a voltage value that is about half the maximum voltage value of the drive signal COM output by the drive circuit 50. For example, if the maximum voltage value of the drive signal COM output by the drive circuit 50 is 40V, then the voltage vd1 is a DC voltage in the range of 15V to 25V.

[0062] The operation of the gate drive circuit 530 will now be described. The gate drive circuit 530 includes gate drivers 531 and 532. As mentioned above, the modulated signal MS is input to gate driver 531, and the signal obtained by inverting the logic level of the modulated signal MS by inverter 521 is input to gate driver 532. That is, the signal input to gate driver 531 and the signal input to gate driver 532 are exclusively at high level. Here, being exclusively at high level includes the case where high-level signals are not input to gate driver 531 and gate driver 532 simultaneously. In other words, it does not exclude the case where low-level signals are input to gate driver 531 and gate driver 532 simultaneously.

[0063] The low-potential power supply terminal of the gate driver 531 is electrically connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 generated at the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 531 as a voltage signal HVS1. The high-potential power supply terminal of the gate driver 531 is electrically connected to the cathode terminal of diode D1 and one end of capacitor C1. A voltage signal VM is supplied to the anode terminal of diode D1, and the other end of capacitor C1 is electrically connected to the first output point OP1. In other words, diode D1 and capacitor C1 constitute a bootstrap circuit, and the output voltage of this bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 531. Therefore, a voltage signal HVD1 with a voltage value vm, which is the voltage value of voltage signal VM, is supplied to the high-potential power supply terminal of the gate driver 531, which is higher than the voltage value of voltage signal HVS1 input to the low-potential power supply terminal of the gate driver 531.

[0064] Therefore, when a high-level modulated signal MS is input to the gate driver 531, it outputs a gate drive signal HGD1 based on a voltage signal HVD1 with a voltage value vm higher than the voltage value of the first output point OP1. When a low-level modulated signal MS is input to the gate driver 531, it outputs a gate drive signal HGD1 based on the voltage signal HVS1, which is the voltage value of the first output point OP1. Here, the voltage vm can be any voltage value that is capable of driving transistors M1, M2 and transistors M3, M4 (described later), for example, a DC voltage of 7.5V.

[0065] The low-potential power supply terminal of the gate driver 532 is supplied with ground potential as the voltage signal LVS1. The high-potential power supply terminal of the gate driver 532 is supplied with voltage vm, which is the voltage value of the voltage signal VM, as the voltage signal LVD1. Therefore, when the gate driver 532 receives an H-level signal, which is the logic level of an L-level modulated signal MS inverted by the inverter 521, it outputs a gate drive signal LGD1 with a voltage value based on the voltage signal LVD1 with a voltage value of voltage vm. When the gate driver 532 receives an L-level signal, which is the logic level of an H-level modulated signal MS inverted by the inverter 521, it outputs a gate drive signal LGD1 with a voltage value based on the ground potential voltage signal LVS1. Then, transistor M1 operates based on the gate drive signal HGD1, and transistor M2 operates based on the gate drive signal LGD1, so that the first amplified modulated signal AMS1, which is the modulated signal MS amplified by voltage vd1, which is the voltage value of the voltage signal VD1, is output from the first output point OP1.

[0066] The level switching signal output circuit 710 receives the base drive signal aA, the waveform information signal WAV, the drive element count information signal CNT, and the feedback signal VFB1 output by the feedback circuit 570, which will be described later. The level switching signal output circuit 710 outputs a level switching signal LS whose logic level changes based on the input base drive signal aA, waveform information signal WAV, drive element count information signal CNT, and feedback signal VFB1. Specifically, the level switching signal output circuit 710 outputs a high-level level switching signal LS during periods when the value of the base drive signal aA is constant and greater than a predetermined threshold, and outputs a low-level level switching signal LS during periods when the value of the base drive signal aA is constant and less than a predetermined threshold. Furthermore, the level switching signal output circuit 710 outputs a level switching signal LS whose logic level changes based on the base drive signal aA, the waveform information signal WAV, the drive element count information signal CNT, and the feedback signal VFB1 during periods when the value of the base drive signal aA changes, and immediately after the value of the base drive signal aA changes and becomes constant. The configuration and operation details of the level switching signal output circuit 710 will be described later.

[0067] The level shift circuit 750 includes a gate drive circuit 730, diodes D11 and D12, capacitors C11 and C12, transistors M3 and M4, and a boost circuit BS. Depending on the input level switching signal LS, the level shift circuit 750 outputs a first amplified modulation signal AMS1, or a signal obtained by level shifting the reference potential of the first amplified modulation signal AMS1, as a second amplified modulation signal AMS2 from the second output point OP2.

[0068] The gate drive circuit 730 outputs gate drive signals HGD2 and LGD2 based on the level switching signal LS. Specifically, the level switching signal LS is input to the gate driver 731 of the gate drive circuit 730. The gate driver 731 generates the gate drive signal HGD2 by level-shifting the input level switching signal LS and outputs it to transistor M3. After the logic level of the level switching signal LS is inverted in the inverter 721, it is input to the gate driver 732 of the gate drive circuit 730. The gate driver 732 generates the gate drive signal LGD2 by level-shifting the signal whose logic level has been inverted from the input level switching signal LS and outputs it to transistor M4.

[0069] Transistors M3 and M4 are both N-channel MOSFETs. Transistor M3 operates based on a gate drive signal HGD2, which is input to the gate terminal, with its source terminal electrically connected to the second output point OP2, a voltage signal VBST supplied to its drain terminal, and the drain terminal electrically connected to the second output point OP2, with the first amplification modulation signal AMS1 supplied to its source terminal, and the gate drive signal LGD2 input to its gate terminal. As a result of transistor M3 operating based on the gate drive signal HGD2 and transistor M4 operating based on the gate drive signal LGD2, the first amplification modulation signal AMS1 or a signal obtained by level-shifting the reference potential of the first amplification modulation signal AMS1 is output from the second output point OP2 as the second amplification modulation signal AMS2.

[0070] The boost circuit BS includes a diode D13 and a capacitor C13. One end of the capacitor C13 is electrically connected to the first output point OP1, and the other end is electrically connected to the drain terminal of the transistor M3. A voltage signal VD2 is supplied to the anode terminal of diode D13, and the cathode terminal of diode D13 is electrically connected to the other end of capacitor C13 and the drain terminal of transistor M3. Although Figure 10 illustrates the boost circuit BS having one diode D13, the boost circuit BS may include multiple diodes D13 connected in series.

[0071] The boost circuit BS generates a voltage signal VBST by adding the voltage value of the first amplification modulation signal AMS1 to the voltage vd2, which is the voltage value across capacitor 13, and outputs it to the drain terminal of transistor M3. In other words, the boost circuit BS generates a voltage signal VBST by level-shifting the reference potential of the first amplification modulation signal AMS1 by the voltage value of voltage signal VD2, which is voltage vd2, and outputs it to the drain terminal of transistor M3. Here, the voltage signal VBST supplied to the drain terminal of transistor M3 is actually based on the voltage value obtained by subtracting the forward voltage drop of diode D13 from the voltage vd2, which is the voltage value of voltage signal VD2, but in the following explanation, we will assume that the forward voltage drop of diode D13 is 0V. Furthermore, the voltage vd2 is approximately half the maximum voltage value of the drive signal COM output by the drive circuit 50. For example, if the maximum voltage value of the drive signal COM output by the drive circuit 50 is 40V, then the voltage vd2 is a DC voltage in the range of 15V to 25V.

[0072] The operation of the gate drive circuit 730 will now be described. The gate drive circuit 730 includes gate drivers 731 and 732. As mentioned above, the level switching signal LS is input to gate driver 731, and the logic level of the level switching signal LS is inverted by the inverter 721 and input to gate driver 732. That is, the signal input to gate driver 731 and the signal input to gate driver 732 are exclusively at high level. Here, being exclusively at high level includes the case where high-level signals are not input to gate driver 731 and gate driver 732 simultaneously. In other words, it does not exclude the case where low-level signals are input to gate driver 731 and gate driver 732 simultaneously.

[0073] The low-potential power supply terminal of the gate driver 731 is electrically connected to the second output point OP2. Therefore, the signal generated at the second output point OP2 is supplied to the low-potential power supply terminal of the gate driver 731 as a voltage signal HVS2. The high-potential power supply terminal of the gate driver 731 is electrically connected to the cathode terminal of diode D11 and one end of capacitor C11. A voltage signal VM is supplied to the anode terminal of diode D11, and the other end of capacitor C11 is electrically connected to the second output point OP2. In other words, diode D11 and capacitor C11 form a bootstrap circuit, and the output voltage of this bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 731. Therefore, a voltage signal HVD2 with a voltage value vm higher than the voltage value of the voltage signal HVS2 input to the low-potential power supply terminal of the gate driver 731 is supplied to the high-potential power supply terminal of the gate driver 731.

[0074] Therefore, when a high-level level switching signal LS is input to the gate driver 731, it outputs a gate drive signal HGD2 based on a voltage signal HVD2 with a voltage value vm higher than the voltage value of the second output point OP2. When a low-level level switching signal LS is input to the gate driver 731, it outputs a gate drive signal HGD2 based on the voltage value of the second output point OP2 and the voltage signal HVS2.

[0075] The low-potential power supply terminal of the gate driver 732 is connected to the first output point OP1. Therefore, the first amplified modulation signal AMS1 output from the first output point OP1 is supplied to the low-potential power supply terminal of the gate driver 732 as a voltage signal LVS2. The high-potential power supply terminal of the gate driver 732 is electrically connected to the cathode terminal of diode D12 and one end of capacitor C12. A voltage signal VM is supplied to the anode terminal of diode D12, and the other end of capacitor C12 is electrically connected to the first output point OP1. In other words, diode D12 and capacitor C12 constitute a bootstrap circuit, and the output voltage of this bootstrap circuit is supplied to the high-potential power supply terminal of the gate driver 732. Therefore, a voltage signal LVD2 with a voltage value vm higher than the voltage value of the voltage signal LVS2 input to the low-potential power supply terminal of the gate driver 732 is supplied to the high-potential power supply terminal of the gate driver 732.

[0076] Therefore, when the gate driver 732 receives an H-level signal, which is the logic level of the L-level level switching signal LS inverted by the inverter 721, it outputs a gate drive signal LGD2 based on a voltage signal LVD2 with a voltage value vm higher than the voltage value of the first output point OP1. When the gate driver 732 receives an L-level signal, which is the logic level of the H-level level switching signal LS inverted by the inverter 721, it outputs a gate drive signal HGD2 based on the voltage value of the first output point OP1 and the voltage signal LVS2.

[0077] When a level switching signal LS at an L level is input to the level shift circuit 750 configured as described above, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via transistor M4. Therefore, when the input level switching signal LS is at an L level, the level shift circuit 750 outputs the first amplification-modulated signal AMS1 as the second amplification-modulated signal AMS2 from the second output point OP2.

[0078] On the other hand, when a high-level level switching signal LS is input to the level shift circuit 750, the first output point OP1 of the amplifier circuit 550 and the second output point OP2 of the level shift circuit 750 are electrically connected via the boost circuit BS and transistor M3. Therefore, when the level switching signal LS is at a high level, the level shift circuit 750 outputs a voltage signal VBST, which is a signal obtained by level-shifting the reference potential of the first amplification-modulated signal AMS1 by a voltage vd2 (the voltage value of the voltage signal VD2), as the second amplification-modulated signal AMS2 from the second output point OP2.

[0079] The second amplified modulation signal AMS2 output by the level shift circuit 750 is input to the demodulation circuit 560. The demodulation circuit 560 demodulates the second amplified modulation signal AMS2 output by the level shift circuit 750 by smoothing it, and outputs the demodulated signal as the drive signal COM.

[0080] The demodulation circuit 560 includes an inductor 561 and a capacitor 562. One end of the inductor 561 is electrically connected to the second output point OP2. The other end of the inductor 561 is electrically connected to one end of the capacitor 562. The other end of the capacitor 562 is supplied with ground potential. In other words, the inductor 561 and the capacitor 562 constitute a low-pass filter circuit. This low-pass filter circuit smooths the second amplified modulation signal AMS2 output from the level shift circuit 750. The smoothed signal of the second amplified modulation signal AMS2 is then output from the drive circuit 50 as a drive signal COM.

[0081] The feedback circuit 570 generates a feedback signal VFB1 corresponding to the drive signal COM generated by the demodulation circuit 560 and outputs it to the level switching signal output circuit 710. The feedback signal VFB1 output by the feedback circuit 570 is a signal obtained by dividing the drive signal COM using a voltage divider circuit (not shown) and extracting the high-frequency components of the divided signal using a high-pass filter (not shown).

[0082] Furthermore, the feedback circuit 570 generates a feedback signal VFB2 corresponding to the drive signal COM generated by the demodulation circuit 560 and outputs it to the adder 511. The feedback signal VFB2 output by the feedback circuit 570 includes a signal obtained by dividing the drive signal COM, or a signal obtained by dividing the drive signal COM using a voltage divider circuit (not shown) and extracting the high-frequency components of the divided signal using a high-pass filter (not shown). The adder 511 then outputs a signal obtained by subtracting the feedback signal VFB2 from the base drive signal aA to the modulation circuit 520, and the modulation circuit 520 outputs a modulated signal MS based on the feedback signal VFB2 according to the output of the adder 511. This improves the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0083] Here, in the feedback circuit 570, the circuit for generating the feedback signal VFB2 and the circuit for generating the feedback signal VFB1 may be composed of some or all common circuits. For example, the high-pass filter for generating the feedback signal VFB2 and the high-pass filter for generating the feedback signal VFB1 may be common circuits. Of course, the circuit for generating the feedback signal VFB2 and the circuit for generating the feedback signal VFB1 may all be composed of different circuits.

[0084] As described above, the drive circuit 50 includes a modulation circuit 520 that outputs a modulated signal MS obtained by modulating a base drive signal aA corresponding to the base drive signal dA which is the basis of the drive signal COM; an amplification circuit 550 that outputs a first amplified modulated signal AMS1 obtained by amplified the modulated signal MS; a level switching signal output circuit 710 that outputs a level switching signal LS which changes between high and low levels; a level shift circuit 750 that outputs a signal with the reference potential of the first amplified modulated signal AMS1 shifted as a second amplified modulated signal AMS2 when the level switching signal LS is at a high level, and outputs the first amplified modulated signal AMS1 as a second amplified modulated signal AMS2 when the level switching signal LS is at a low level; a demodulation circuit 560 that demodulates the second amplified modulated signal AMS2 and outputs a drive signal COM; and a feedback circuit 570 that outputs feedback signals VFB1 and VFB2 corresponding to the drive signal COM. The level shift circuit 750 of the drive circuit 50 includes a gate drive circuit 730 that outputs gate drive signals HGD2 and LGD2 corresponding to a level switching signal LS, a transistor M3 whose conduction state between its drain terminal and source terminal is controlled according to the gate drive signal HGD2, a transistor M4 whose conduction state between its drain terminal and source terminal is controlled according to the gate drive signal LGD2, and a boost circuit BS which receives a first amplification modulation signal AMS1 and a voltage signal VD2 and outputs a voltage signal VBST obtained by shifting the reference potential of the first amplification modulation signal AMS1 according to the voltage signal VD2, and the drain terminal of transistor M3 has a voltage When the signal VBST is input, the first amplification-modulated signal AMS1 is input to the source terminal of transistor M4, the source terminal of transistor M3 and the drain terminal of transistor M4 are electrically connected at the second output point OP2, the gate drive circuit 730 outputs a gate drive signal HGD2 that controls the connection between the drain terminal and source terminal of transistor M3 to conduction when the level switching signal LS is at a high level, and outputs a gate drive signal LGD2 that controls the connection between the drain terminal and source terminal of transistor M4 to conduction when the level switching signal LS is at a low level, and the level shift circuit 750 outputs the signal at the second output point OP2 as the second amplification-modulated signal AMS2.

[0085] 4. Operation of the drive circuit 4.1 Operation of the drive circuit Next, the operation of the drive circuit 50 will be described. Figure 11 is a diagram illustrating the operation of the drive circuit 50. In Figure 11, only the drive signal COM output by the drive circuit 50 at an arbitrary dot formation period T is shown. For the convenience of illustration and explanation, Figure 11 shows the signal waveform in the ideal case where there is no circuit delay or wiring delay. Also in Figure 11, the threshold dvth of the base drive signal aA that switches the logic level of the level switching signal LS output by the level switching signal output circuit 710 is shown, and the voltage value of the drive signal COM corresponding to the threshold dvth is shown as voltage vth. Furthermore, in Figure 11, the values ​​of the base drive signal aA corresponding to the voltage values ​​of the drive signal COM, voltages vt, vb, and vc, are shown as voltages dvt, dvb, and dvc, respectively. Note that in Figure 11, the case where voltage vth is lower than voltage vc and threshold dvth is smaller than voltage dvc is shown, but voltage vth may be higher than voltage vc and threshold dvth may be higher than voltage dvc.

[0086] Furthermore, in the following description, the operating mode of the drive circuit 50 during the period when the level switching signal output circuit 710 outputs a level switching signal LS at an L level, causing the level shift circuit 750 to output the first amplification modulation signal AMS1 as the second amplification modulation signal AMS2, and the value of the base drive signal aA is constant, is referred to as the first mode MD1; the operating mode of the drive circuit 50 during the period when the level switching signal output circuit 710 outputs a level switching signal LS at an H level, causing the level shift circuit 750 to output a signal obtained by level shifting the reference potential of the first amplification modulation signal AMS1 as the second amplification modulation signal AMS2, and the value of the base drive signal aA is constant, is referred to as the second mode MD2; and the operating mode of the drive circuit 50 during the period when the value of the base drive signal aA changes, regardless of the logic level of the level switching signal LS output by the level switching signal output circuit 710, is sometimes referred to as the third mode MD3.

[0087] As shown in Figure 11, during the period from time t0 to time t10, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is greater than the threshold dvth and constant at voltage dvc, in response to the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value is greater than the voltage vth and constant at voltage vc, in response to the base drive signal dA and the base drive signal aA. In other words, during the period from time t0 to time t10, the operating mode of the drive circuit 50 is the second mode MD2.

[0088] During the period from time t10 to time t20, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value changes from voltage dvc to voltage dvb, falling below the threshold dvth, in response to the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value changes from voltage vc to voltage vb, falling below the voltage vth, in response to the base drive signal dA and base drive signal aA. In other words, during the period from time t10 to time t20, the operating mode of the drive circuit 50 is the third mode MD3.

[0089] During the period from time t20 to time t30, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is less than the threshold dvth and constant at voltage dvb, in response to the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value is less than the voltage vth and constant at voltage vb, in response to the base drive signal dA and the base drive signal aA. In other words, during the period from time t20 to time t30, the operating mode of the drive circuit 50 is the first mode MD1.

[0090] During the period from time t30 to time t40, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value changes from voltage dvb to voltage dvt, exceeding the threshold dvth, in response to the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value changes from voltage vb to voltage vt, exceeding the voltage vth, in response to the base drive signal dA and base drive signal aA. In other words, during the period from time t30 to time t40, the operating mode of the drive circuit 50 is the third mode MD3.

[0091] During the period from time t40 to time t50, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is greater than the threshold dvth and constant at voltage dvt, in accordance with the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value is greater than the voltage vth and constant at voltage vt, in accordance with the base drive signal dA and base drive signal aA. In other words, during the period from time t40 to time t50, the operating mode of the drive circuit 50 is the second mode MD2.

[0092] During the period from time t50 to time t60, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value changes from voltage dvt to voltage dvc in response to the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value changes from voltage vt to voltage vc in response to the base drive signal dA and base drive signal aA. In other words, during the period from time t50 to time t60, the operating mode of the drive circuit 50 is the third mode MD3.

[0093] During the period from time t60 to time t70, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is greater than the threshold dvth and constant at voltage dvc, in accordance with the input base drive signal dA, and the drive circuit 50 outputs a drive signal COM whose voltage value is greater than the voltage vth and constant at voltage vc, in accordance with the base drive signal dA and base drive signal aA. In other words, during the period from time t60 to time t70, the operating mode of the drive circuit 50 is the second mode MD2.

[0094] Here, time t70 corresponds to time t0 as described above, and the period from time t0 to time t70 corresponds to the dot formation period T. The operating mode of the drive circuit 50 is switched between the first mode MD1, the second mode MD2, and the third mode MD3 according to the input base drive signals dA and aA.

[0095] Here, we will explain the operation of the drive circuit 50 in each operating mode.

[0096] In the first mode MD1, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is less than the threshold dvth and constant. At this time, the modulation circuit 520 outputs a modulation signal MS with a nearly constant duty cycle because the voltage value of the input base drive signal aA is constant and the voltage value of the drive signal COM output by the drive circuit 50 is constant. Therefore, the amplification circuit 550 generates and outputs a first amplified modulation signal AMS1 with a nearly constant duty cycle, which is amplified based on the voltage vd1 of the modulation signal MS.

[0097] Furthermore, in the first mode MD1, the D / A conversion circuit 510 outputs a constant base drive signal aA with a voltage value smaller than the threshold dvth, and therefore the level switching signal output circuit 710 outputs a low level switching signal LS. Consequently, the level shift circuit 750 outputs the first amplification modulation signal AMS1 as the second amplification modulation signal AMS2. That is, in the first mode MD1, the level shift circuit 750 outputs the first amplification modulation signal AMS1 with a duty cycle of approximately constant as the second amplification modulation signal AMS2. Then, the second amplification modulation signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, and in the first mode MD1, the drive circuit 50 outputs a constant drive signal COM with a voltage value smaller than the voltage vth.

[0098] In the second mode MD2, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value is greater than the threshold dvth and constant. At this time, the modulation circuit 520 outputs a modulation signal MS with a nearly constant duty cycle because the voltage value of the input base drive signal aA is constant and the voltage value of the drive signal COM output by the drive circuit 50 is constant. Therefore, the amplification circuit 550 generates and outputs a first amplified modulation signal AMS1 with a nearly constant duty cycle, which is amplified based on the voltage vd1 of the modulation signal MS.

[0099] Furthermore, in the second mode MD2, the D / A conversion circuit 510 outputs a constant base drive signal aA with a voltage value greater than the threshold dvth, and the level switching signal output circuit 710 outputs a high-level level switching signal LS. Therefore, the level shift circuit 750 outputs a signal obtained by level shifting the reference potential of the first amplification modulation signal AMS1 by a voltage vd2 as the second amplification modulation signal AMS2. In other words, in the second mode MD2, the level shift circuit 750 outputs a signal obtained by level shifting the reference potential of the first amplification modulation signal AMS1, which has a nearly constant duty cycle, from ground potential to voltage vb2 as the second amplification modulation signal AMS2. Then, the second amplification modulation signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, and in the second mode MD2, the drive circuit 50 outputs a constant drive signal COM with a voltage value greater than the voltage vth.

[0100] In the third mode MD3, the D / A conversion circuit 510 outputs a base drive signal aA whose voltage value changes. At this time, the modulation circuit 520 outputs a modulation signal MS whose duty cycle changes based on the difference between the voltage value of the input changing base drive signal aA and the feedback signal VFB2 corresponding to the drive signal COM output by the drive circuit 50. Therefore, the amplification circuit 550 amplifies the modulation signal MS based on the voltage vd1 to generate and output a first amplified modulation signal AMS1 whose duty cycle changes based on the difference between the voltage value of the changing base drive signal aA and the feedback signal VFB2.

[0101] Furthermore, in the third mode MD3 in which the voltage value of the base drive signal aA changes, if both the voltage value of the base drive signal aA before the change and the voltage value of the base drive signal aA after the change are smaller than the threshold dvth, the level switching signal output circuit 710 continues to output the L level level switching signal LS. At this time, the level shift circuit 750 outputs the first amplification modulation signal AMS1, whose duty cycle changes in accordance with the change in the base drive signal aA, as the second amplification modulation signal AMS2. Then, the second amplification modulation signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, so that the drive circuit 50 outputs a drive signal COM whose voltage value changes in accordance with the change in the voltage value of the base drive signal aA, while its voltage value is smaller than the voltage vth. In addition, in the third mode MD3 in which the voltage value of the base drive signal aA changes, if both the voltage value of the base drive signal aA before the change and the voltage value of the base drive signal aA after the change are smaller than the threshold dvth, the level switching signal output circuit 710 may output a level switching signal LS whose logic level changes based on the base drive signal aA and the feedback signal VFB1.

[0102] Furthermore, in the third mode MD3, where the voltage value of the base drive signal aA changes, if both the voltage value of the base drive signal aA before the change and the voltage value of the base drive signal aA after the change are greater than the threshold dvth, the level switching signal output circuit 710 continues to output the H-level level switching signal LS. At this time, the level shift circuit 750 outputs a signal as the second amplification modulation signal AMS2, which is obtained by level shifting the reference potential of the first amplification modulation signal AMS1, whose duty cycle changes according to the change in the base drive signal aA, by a voltage vd2. Then, the second amplification modulation signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, so that the drive circuit 50 outputs a drive signal COM, whose voltage value changes while being greater than the voltage vth, according to the change in the voltage value of the base drive signal aA. In addition, in the third mode MD3 in which the voltage value of the base drive signal aA changes, if both the voltage value of the base drive signal aA before the change and the voltage value of the base drive signal aA after the change are greater than the threshold dvth, the level switching signal output circuit 710 may output a level switching signal LS whose logic level changes based on the base drive signal aA and the feedback signal VFB1.

[0103] Furthermore, in the third mode MD3 in which the voltage value of the base drive signal aA changes, if the voltage value of the base drive signal aA before the change is less than the threshold dvth and the voltage value of the base drive signal aA after the change is greater than the threshold dvth, and if the voltage value of the base drive signal aA before the change is greater than the threshold dvth and the voltage value of the base drive signal aA after the change is less than the threshold dvth, that is, if the voltage value of the base drive signal aA changes across the threshold dvth, the level switching signal output circuit 710 outputs a level switching signal LS whose logic level changes based on the base drive signal aA and the feedback signal VFB1. At this time, the level shift circuit 750 outputs a second amplification modulation signal AMS2 in which the reference potential of the first amplification modulation signal AMS1, whose duty cycle changes in accordance with the change in the base drive signal aA, changes between the ground potential and the voltage vd2 based on the base drive signal aA and the feedback signal VFB1. Then, the second amplified modulation signal AMS2 output by the level shift circuit 750 is smoothed by the demodulation circuit 560, and the drive circuit 50 outputs a drive signal COM whose voltage value changes across voltage vth in accordance with the change in the voltage value of the base drive signal aA.

[0104] If the voltage value of the base drive signal aA changes across the threshold dvth, and the level switching signal output circuit 710 changes the logic level of the output level switching signal LS solely based on the comparison result between the value of the base drive signal aA and the threshold dvth, the reference potential of the second amplified modulation signal AMS2 output by the level shift circuit 750 will change abruptly from ground potential to voltage vd2, or from voltage vb2 to ground potential. If the response speed of the drive circuit 50 cannot keep up with this abrupt change in reference potential, distortion may occur in the signal waveform of the drive signal COM, potentially degrading the waveform accuracy of the drive signal COM. In contrast, in the drive circuit 50 of this embodiment, the level switching signal output circuit 710 generates a level switching signal LS using the base drive signal aA and a feedback signal VFB2 which is a feedback of the drive signal COM. This reduces the risk that the reference potential of the second amplified modulation signal AMS2 output by the level shift circuit 750 will change abruptly, and reduces the risk that the waveform accuracy of the drive signal COM will deteriorate.

[0105] Furthermore, in the liquid dispensing device 1 of this embodiment, when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the level switching signal output circuit 710 sets the logic level of the output level switching signal LS to a high level for a predetermined period of time, and then to a low level. Similarly, when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the level switching signal output circuit 710 sets the logic level of the output level switching signal LS to a low level for a predetermined period of time, and then to a high level. This reduces the risk of undershoot and overshoot superimposed on the drive signal COM when the voltage value of the drive signal COM changes from a state of change to a state of constant value.

[0106] 4.2 Configuration and Operation of Level Switching Signal Output Circuit Here, an example of the configuration of the level switching signal output circuit 710 will be described. Figure 12 is a diagram showing an example of the configuration of the level switching signal output circuit 710. As shown in Figure 12, the level switching signal output circuit 710 includes a differentiator circuit 712, a comparator circuit 714, a level switching control circuit 716, a memory circuit 718, and an output switching circuit 720.

[0107] The differential circuit 712 receives the base drive signal aA as input. The differential circuit 712 outputs a signal obtained by differentiating the input base drive signal aA, which corresponds to the time change in the voltage value of the input base drive signal aA, as a reference signal REF to the comparator circuit 714. Such a differential circuit 712 may be composed of capacitor elements and resistor elements, or it may include an operational amplifier or the like.

[0108] The comparison circuit 714 is composed of a comparator, for example. The reference signal REF output by the differentiating circuit 712 is input to the + side input terminal of the comparison circuit 714. The feedback signal VFB1 is input to the - side input terminal of the comparison circuit 714. The comparison circuit 714 compares the voltage value of the reference signal REF with the voltage value of the feedback signal VFB1. The comparison circuit 714 then generates a pulse signal LSP, which is high level if the voltage value of the reference signal REF is greater than the voltage value of the feedback signal VFB1, and low level if the voltage value of the reference signal REF is less than the voltage value of the feedback signal VFB1, and outputs this pulse signal LSP to the output switching circuit 720.

[0109] Here, we will explain the relationship between the reference signal REF input to the comparator circuit 714 and the feedback signal VFB1. Figure 13 shows an example of the configuration of a high-pass filter included in the feedback circuit 570. As shown in Figure 13, the high-pass filter included in the feedback circuit 570 includes a resistor 572 and a capacitor 574. A signal obtained by dividing the voltage value of the drive signal COM is input to this high-pass filter. In this high-pass filter, if the capacitance of the capacitor 574 is C and the resistance of the resistor 572 is R, and a current i(t) flows through the capacitor 574, then if the voltage vfb1, which is the voltage value of the feedback signal VFB1, satisfies equation (1), then a proportional relationship holds between the drive signal COM and the base drive signal aA. Here, in equation (1), α is a constant and v(t) is the voltage value of the base drive signal aA.

[0110]

number

[0111] In such a high-pass filter, if the product RC of the resistance R and capacitance C is made sufficiently smaller than the time tx during which the voltage v(t) changes, the feedback signal VFB1 can be considered a signal containing a so-called square wave, where when the voltage v(t), which is the voltage value of the base drive signal aA, changes, a voltage vfb1 corresponding to the amount of change in voltage v(t) is generated. Here, the product RC of the resistance R and capacitance C being sufficiently smaller than the time tx during which the voltage v(t) changes means, for example, that when the time tx is about 1 μs, the product RC is 100 × 10⁻¹⁰. -9 The following cases are included.

[0112] Furthermore, if the voltage value of the square wave based on the feedback signal VFB1, obtained by making the product RC of the resistance value R and the capacitance value C sufficiently smaller than the time tx during which the voltage v(t) changes, is denoted as voltage vb, then this voltage vb can be expressed as shown in equation (2). Here, in equation (2), the voltage va is the amount of change in the voltage of the base drive signal aA at time tx.

[0113]

number

[0114] In other words, the feedback signal VFB1 can be considered a square wave by making the product RC of the resistance value R and the capacitance value C sufficiently small with respect to the time tx during which the voltage v(t) changes. The voltage vb of this square wave is proportional to the voltage va, which is the change in the voltage of the base drive signal aA at time tx. Therefore, the reference signal REF, which is a signal corresponding to the time change in the voltage value of the base drive signal aA output by the differentiating circuit 712 and is the derivative of the base drive signal aA, is proportional to the feedback signal VFB1.

[0115] The comparison circuit 714 takes the proportionality coefficient into account and compares the voltage value of the reference signal REF with the voltage value of the feedback signal VFB1, and outputs a logic level pulse signal LSP according to the comparison result. Here, taking the proportionality coefficient between the voltage value of the reference signal REF and the voltage value of the feedback signal VFB1 into account means that, based on the proportionality coefficient, at least one of the voltage value of the reference signal REF and the voltage value of the feedback signal VFB1 corresponding to the voltage value of the reference signal REF may be corrected, or the voltage division ratio of the drive signal COM in the feedback circuit 570 may be adjusted.

[0116] Returning to Figure 12, the memory circuit 718 stores timing information ST that defines the timing of the logic level switching of the level switching control signals SIG1 and SIG2 output by the level switching control circuit 716, which will be described later.

[0117] The level switching control circuit 716 receives the reference signal REF, the base drive signal aA, the waveform information signal WAV, and the drive element number information signal CNT as inputs. The level switching control circuit 716 acquires timing information ST from the memory circuit 718 according to the input waveform information signal WAV and drive element number information signal CNT.

[0118] The level switching control circuit 716 determines the operating mode of the drive circuit 50 by determining whether the value of the input base drive signal aA is greater than or less than a predetermined threshold, and whether the value of the base drive signal aA is constant or changing, based on the input base drive signal aA. Then, the level switching control circuit 716 generates level switching control signals SIG1 and SIG2 that switch the logic level based on the determined operating mode of the drive circuit 50 and the acquired timing information ST, and outputs them to the output switching circuit 720.

[0119] The output switching circuit 720 includes an AND circuit 722 and an OR circuit 724. The output switching circuit 720 receives level switching control signals SIG1 and SIG2, and a pulse signal LSP as inputs. The output switching circuit 720 then generates a level switching signal LS corresponding to the level switching control signals SIG1 and SIG2 and the pulse signal LSP, and outputs it to the level shift circuit 750.

[0120] The AND gate 722 receives the level switching control signal SIG1 and the pulse signal LSP as inputs. When the level switching control signal SIG1 is at a low level, the AND gate 722 outputs a low-level signal, and when the level switching control signal SIG1 is at a high level, it outputs a signal whose logic level is switched according to the pulse signal LSP. The OR gate 724 receives the level switching control signal SIG2 and the output signal of the AND gate 722 as inputs. When the level switching control signal SIG2 is at a low level, the OR gate 724 outputs the output signal of the AND gate 722, and when the level switching control signal SIG2 is at a low level, it outputs a low-level signal. The signal output by the OR gate 724 is then output from the level switching signal output circuit 710 as the level switching signal LS. In other words, the output switching circuit 720 outputs a high-level level switching signal LS when the level switching control signal SIG1 is at a high level and the level switching control signal SIG2 is at a high level; outputs a pulse signal LSP as the level switching signal LS when the level switching control signal SIG1 is at a high level and the level switching control signal SIG2 is at a low level; outputs a high-level level switching signal LS when the level switching control signal SIG1 is at a low level and the level switching control signal SIG2 is at a high level; and outputs a low-level level switching signal LS when the level switching control signal SIG1 is at a low level and the level switching control signal SIG2 is at a low level.

[0121] The operation of the level switching signal output circuit 710 will now be explained. Figure 14 is a diagram illustrating the operation of the level switching signal output circuit 710. Figure 14 shows an example of the operation of the level switching signal output circuit 710 when the voltage value of the base drive signal aA changes across the threshold dvth in the third mode MD3, illustrating the operation of the level switching signal output circuit 710 when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, before and after the third mode MD3.

[0122] The comparison circuit 714 compares the voltage value of the reference signal REF with the voltage value of the feedback signal VFB1. The comparison circuit 714 then outputs a pulse signal LSP that is high level when the voltage value of the reference signal REF is higher than the voltage value of the feedback signal VFB1, and low level when the voltage value of the reference signal REF is lower than the voltage value of the feedback signal VFB1.

[0123] The level switching control circuit 716 acquires timing information ST corresponding to the input waveform information signal WAV and the number of driving elements information signal CNT, including timing times ta1 and ta2 that define the timing for controlling the logic level of the level switching control signal SIG1 in the third mode MD3 when transitioning from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, and timing times tb1 and tb2 that define the timing for controlling the logic level of the level switching control signal SIG2, timing time tp1 that defines the timing for controlling the logic levels of the level switching control signals SIG1 and TSIG2 immediately after transitioning from the third mode MD3 to the second mode MD2, and timing time tp2 that defines the timing for controlling the logic levels of the level switching control signals SIG1 and TSIG2 immediately after transitioning from the third mode MD3 to the first mode MD1. The level switching control circuit 716 then outputs level switching control signals SIG1 and SIG2, whose logic levels change according to the acquired timing times ta1, ta2, tb1, tb2, tp1, tp2, the reference signal REF, and the base drive signal aA.

[0124] Specifically, in the third mode MD3, when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, the voltage value of the base drive signal aA increases. At this time, the level switching control circuit 716 detects that the operating mode of the drive circuit 50 has transitioned from the first mode MD1 to the third mode MD3 by detecting the rising edge of the reference signal REF, which is the voltage value of the base drive signal aA. The level switching control circuit 716 then starts measuring the elapsed time since the operating mode of the drive circuit 50 transitioned to the third mode MD3.

[0125] Furthermore, the level switching control circuit 716 detects the voltage value of the base drive signal aA immediately before or after the operating mode of the drive circuit 50 transitions from the first mode MD1 to the third mode MD3. At this time, the voltage value of the base drive signal aA is smaller than the threshold dvth because the operating mode of the drive circuit 50 is either the first mode MD1 or has just transitioned from the first mode MD1 to the third mode MD3. If the voltage value of the base drive signal aA is smaller than the threshold dvth, the level switching control circuit 716 sets the level switching control signal SIG1 to L level and the level switching control signal SIG2 to L level. Therefore, the output switching circuit 720 and the level switching signal output circuit 710 output a level switching signal LS at L level.

[0126] Subsequently, when the elapsed time since the drive circuit 50 transitioned to the third mode MD3 reaches the timing time ta1, the level switching control circuit 716 sets the level switching control signal SIG1 to the H level and the level switching control signal SIG2 to the L level. Therefore, the output switching circuit 720 and the level switching signal output circuit 710 output the pulse signal LSP output by the comparator circuit 714 as the level switching signal LS.

[0127] Furthermore, when the elapsed time since the operating mode of the drive circuit 50 transitioned to the third mode MD3 reaches the timing time tb1, the level switching control circuit 716 detects the voltage value of the base drive signal aA. Here, the timing time tb1 is set to be longer than the time from when the operating mode of the drive circuit 50 transitioned to the third mode MD3 until the voltage value of the base drive signal aA becomes greater than the threshold dvth. Therefore, the voltage value of the base drive signal aA at timing time tb1 is greater than the threshold dvth. If the detected voltage value of the base drive signal aA is greater than the threshold dvth, the level switching control circuit 716 sets the level switching control signal SIG1 to the L level and the level switching control signal SIG2 to the H level. Therefore, the output switching circuit 720 and the level switching signal output circuit 710 output the H level level switching signal LS.

[0128] Subsequently, when the voltage value of the base drive signal aA reaches a predetermined voltage value, the voltage value of the base drive signal aA becomes constant, and the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2. At this time, the level switching control circuit 716 detects that the operating mode of the drive circuit 50 has transitioned from the third mode MD3 to the second mode MD2 by detecting the falling edge of the reference signal REF, which indicates that the voltage value of the base drive signal aA has become constant. Then, as the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the level switching control circuit 716 sets the level switching control signal SIG1 to L level and the level switching control signal SIG2 to L level. That is, immediately after the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the output switching circuit 720 and the level switching signal output circuit 710 output a level switching signal LS at L level.

[0129] At this time, the level switching control circuit 716 starts measuring the elapsed time since the operating mode of the drive circuit 50 transitioned from the third mode MD3 to the second mode MD2. When the elapsed time since the operating mode of the drive circuit 50 transitioned from the third mode MD3 to the second mode MD2 reaches the measured time tp1, the level switching control circuit 716 sets the level switching control signal SIG1 to the L level and the level switching control signal SIG2 to the H level. Consequently, the output switching circuit 720 and the level switching signal output circuit 710 output the H level level switching signal LS.

[0130] When the operating mode of the drive circuit 50 transitions from the second mode MD2 to the first mode MD1, in the third mode MD3, the voltage value of the base drive signal aA decreases. At this time, the level switching control circuit 716 detects that the operating mode of the drive circuit 50 has transitioned from the second mode MD2 to the third mode MD3 by detecting the falling edge of the reference signal REF, which is the voltage value of the base drive signal aA. The level switching control circuit 716 then starts measuring the elapsed time since the operating mode of the drive circuit 50 transitioned to the third mode MD3.

[0131] Furthermore, the level switching control circuit 716 detects the voltage value of the base drive signal aA immediately before or after the operating mode of the drive circuit 50 transitions from the second mode MD2 to the third mode MD3. At this time, the voltage value of the base drive signal aA is greater than the threshold dvth because the operating mode of the drive circuit 50 is either in the second mode MD2 or has just transitioned from the second mode MD2 to the third mode MD3. If the voltage value of the base drive signal aA is greater than the threshold dvth, the level switching control circuit 716 sets the level switching control signal SIG1 to the L level and the level switching control signal SIG2 to the H level. Therefore, the output switching circuit 720 and the level switching signal output circuit 710 output the H level level switching signal LS.

[0132] Subsequently, when the elapsed time since the drive circuit 50 transitioned to the third mode MD3 reaches the timing time ta2, the level switching control circuit 716 sets the level switching control signal SIG1 to the H level and the level switching control signal SIG2 to the L level. Therefore, the output switching circuit 720 and the level switching signal output circuit 710 output the pulse signal LSP output by the comparator circuit 714 as the level switching signal LS.

[0133] Furthermore, when the elapsed time since the operating mode of the drive circuit 50 transitioned to the third mode MD3 reaches the timing time tb2, the level switching control circuit 716 detects the voltage value of the base drive signal aA. Here, the timing time tb2 is set to be longer than the time from when the operating mode of the drive circuit 50 transitioned to the third mode MD3 until the voltage value of the base drive signal aA becomes less than the threshold dvth. Therefore, the voltage value of the base drive signal aA at timing time tb2 is less than the threshold dvth. If the detected voltage value of the base drive signal aA is less than the threshold dvth, the level switching control circuit 716 sets the level switching control signal SIG1 to L level and the level switching control signal SIG2 to L level. Therefore, the output switching circuit 720 and the level switching signal output circuit 710 output a level switching signal LS at L level.

[0134] Subsequently, when the voltage value of the base drive signal aA reaches a predetermined voltage value, the voltage value of the base drive signal aA becomes constant, and the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1. At this time, the level switching control circuit 716 detects that the operating mode of the drive circuit 50 has transitioned from the third mode MD3 to the first mode MD1 by detecting the rising edge of the reference signal REF, which is the voltage value of the base drive signal aA becoming constant. Then, as the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the level switching control circuit 716 sets the level switching control signal SIG1 to the L level and the level switching control signal SIG2 to the H level. That is, immediately after the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the output switching circuit 720 and the level switching signal output circuit 710 output a level switching signal LS at the H level.

[0135] At this time, the level switching control circuit 716 starts measuring the elapsed time since the operating mode of the drive circuit 50 transitioned from the third mode MD3 to the first mode MD1. When the elapsed time since the operating mode of the drive circuit 50 transitioned from the third mode MD3 to the first mode MD1 reaches the measured time tp2, the level switching control circuit 716 sets the level switching control signal SIG1 to L level and the level switching control signal SIG2 to L level. Consequently, the output switching circuit 720 and the level switching signal output circuit 710 output a level switching signal LS at L level.

[0136] As described above, during the period in the third mode MD3 when the voltage value of the signal waveform defined by the base drive signal dA changes, the level switching signal output circuit 710 switches the potential of the logic level of the level switching signal LS in accordance with the feedback signal VFB1.

[0137] As described above, the level switching signal output circuit 710 includes a period during which a constant level switching signal LS is output at an L level, a period during which a pulse signal LSP is output as the level switching signal LS, and a period during which a constant level switching signal LS is output at an H level, when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, in the third mode MD3.

[0138] Specifically, the level switching signal output circuit 710 switches the logic level of the level switching control signal SIG1 and the logic level of the level switching control signal SIG2 based on timing information ST acquired from the memory circuit 718 in accordance with the waveform information signal WAV and the number of driving elements information signal CNT. In the third mode MD3 in which the value of the base driving signal aA changes, when the voltage value of the base driving signal aA changes across the threshold dvth, the circuit includes a state in which it outputs a level switching signal LS that changes between L level and H level in accordance with the feedback signal VFB1, and a state in which it outputs a constant level switching signal LS at L level or H level.

[0139] In the level switching signal output circuit 710 configured as described above, the pulse signal LSP is a signal obtained by comparing the voltage value of the feedback signal VFB1 with the voltage value of the reference signal REF, and is generated so that the voltage value of the feedback signal VFB1 follows the voltage value of the reference signal REF. By generating the level switching signal LS using such a pulse signal LSP, even if the load capacitance of the piezoelectric element 60 or the like to which the drive signal COM to be output is supplied changes in the drive circuit 50, the influence of the change in load capacitance is reduced, and the waveform accuracy of the drive signal COM is improved.

[0140] On the other hand, if the level switching signal output circuit 710 outputs a level switching signal LS corresponding to the pulse signal LSP for the entire duration of the third mode MD3 when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, the power consumption of the drive circuit 50 may increase because the period during which the switching operation in the amplification circuit 550 and the switching operation in the level shift circuit 750 are performed in parallel increases. In contrast, in the drive circuit 50 of this embodiment, in the third mode MD3 when the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, or from the second mode MD2 to the first mode MD1, the waveform accuracy of the drive signal COM can be improved, and the risk of increased power consumption in the drive circuit 50 can be reduced.

[0141] Furthermore, in the third mode MD3, the timing times ta1, ta2, tb1, and tb2 that define the period during which a constant level switching signal LS is output at L level, the period during which a pulse signal LSP is output as the level switching signal LS, and the period during which a constant level switching signal LS is output at H level are determined according to the waveform information signal WAV and the number of drive elements information signal CNT, and are determined according to the signal waveform of the drive signal COM output by the drive circuit 50 and the number of piezoelectric elements 60 driven by the drive signal COM. This makes it possible to use optimal timing times ta1, ta2, tb1, and tb2 according to the operation of the liquid discharge device 1, and further improves the waveform accuracy of the drive signal COM.

[0142] For example, if it is determined based on the waveform information signal WAV that the period during which the voltage value of the base drive signal aA changes is long, timing information ST may be selected such that the timing time ta1 is long and the timing time ta2 is short. This reduces the period during which the switching operation in the amplification circuit 550 and the switching operation in the level shift circuit 750 are performed in parallel, further reducing the risk of increased power consumption in the drive circuit 50. Also, for example, if it is determined based on the number of drive elements information signal CNT that there are many piezoelectric elements 60 to which the drive signal COM output by the drive circuit 50 is supplied, timing information ST may be selected such that the timing time ta1 is short and the timing time ta2 is long. This increases the period during which the pulse signal LSP is output as a level switching signal LS, further improving the waveform accuracy of the drive signal COM output by the drive circuit 50. Also, for example, if it is determined based on the waveform information signal WAV that the amount of change per unit time of the drive signal COM in the third mode MD3 is large, timing information ST may be selected such that the timing time ta1 is short and the timing time ta2 is long. This increases the period during which the pulse signal LSP is output as the level switching signal LS, further improving the waveform accuracy of the drive signal COM output by the drive circuit 50.

[0143] Furthermore, it is preferable that the timing times ta1 and ta2 are shorter than the time from the transition to the third mode MD3 until the voltage value of the base drive signal aA crosses the threshold dvth, and that the timing times tb1 and tb2 are longer than the time from the transition to the third mode MD3 until the voltage value of the base drive signal aA crosses the threshold dvth. In other words, it is preferable that the level switching signal output circuit 710 outputs the pulse signal LSP as the level switching signal LS at the timing when the voltage value of the base drive signal aA crosses the threshold dvth.

[0144] As described above, the drive circuit 50 operates in first mode MD1 during the period when the voltage value of the base drive signal aA is less than the threshold dvth, and operates in second mode MD2 during the period when the voltage value of the base drive signal aA is greater than the threshold dvth. Therefore, at the timing when the voltage value of the base drive signal aA crosses the threshold dvth, the reference potential of the first amplified modulation signal AMS1, which is output as the second amplified modulation signal AMS2, changes sharply. At such operating mode switching timings, when the reference potential of the first amplified modulation signal AMS1, which is output as the second amplified modulation signal AMS2, changes sharply, the level switching signal output circuit 710 outputs a level switching signal LS corresponding to the pulse signal LSP, thereby reducing the risk of distortion in the signal waveform of the drive signal COM due to the switching of the operating mode of the drive circuit 50.

[0145] Furthermore, as described above, when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the level switching signal output circuit 710 outputs a low-level level switching signal LS for a timing time tp1 based on the timing information ST acquired from the memory circuit 718 in accordance with the waveform information signal WAV and the number of drive elements information signal CNT, and then outputs a high-level level switching signal LS. When the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the level switching signal LS outputs a high-level level switching signal LS for a timing time tp2 based on the timing information ST acquired from the memory circuit 718 in accordance with the waveform information signal WAV and the number of drive elements information signal CNT, and then outputs a low-level level switching signal LS. This reduces the risk of overshoot superimposed on the signal waveform of the drive signal COM when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, and also reduces the risk of undershoot occurring in the signal waveform of the drive signal COM when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1.

[0146] In explaining the reduction mechanism of this embodiment, the overshoot superimposed on the drive signal output by the comparative example drive circuit will be explained using the comparative example drive circuit. The comparative example drive circuit is a circuit that outputs a drive signal to drive a capacitive load such as a piezoelectric element, similar to the drive circuit 50 of this embodiment. The only difference from the drive circuit 50 of this embodiment is that it does not have the characteristic configuration of the liquid dispensing device 1 of this embodiment, which outputs an L-level level switching signal LS for a predetermined time when the voltage value of the signal waveform defined by the base drive signal transitions from a state in which it is rising to a state in which it is constant. In other words, the comparative example drive circuit is a circuit that outputs a drive signal to drive a capacitive load, and outputs an H-level level switching signal LS when the voltage value of the signal waveform defined by the base drive signal transitions from a state in which it is rising to a state in which it is constant.

[0147] Figure 15 is a diagram illustrating the mechanism by which overshoot occurs. Figure 15 illustrates a case where the voltage value of the drive signal output by the comparative example's drive circuit rises from voltage V1 to voltage V2, crossing a predetermined threshold voltage vct at which the logic level of the level switching signal switches. In Figure 15, the voltage value of the drive signal output by the comparative example's drive circuit is shown as the output drive voltage with a solid line, the current value supplied to a capacitive load such as a piezoelectric element by the drive signal output by the comparative example's drive circuit is shown as the output drive current with a solid line, the voltage value of an ideal drive signal corresponding to the signal waveform defined by the base drive signal input to the comparative example's drive circuit is shown as the ideal drive voltage with a dashed line, and the ideal current value supplied to the capacitive load by the ideal drive signal is shown as the ideal drive current with a dashed line.

[0148] As shown in Figure 15, before time t0, when the voltage value of the signal waveform defined by the base drive signal is constant, both the output drive voltage and the ideal drive voltage are constant at voltage V1. Therefore, before time t0, no current is supplied to the capacitive load, and consequently, both the output drive current and the ideal drive current are "0".

[0149] At time t0, when the voltage value of the signal waveform defined by the base drive signal begins to rise, the ideal drive current becomes current Ic1, and the ideal drive voltage begins to rise from voltage V1 to voltage V2 along the slope of the signal waveform defined by the base drive signal. Then, at time t2, as the voltage value of the signal waveform defined by the base drive signal becomes constant, the ideal drive current becomes "0", and the ideal drive voltage becomes constant at voltage V2, which is the voltage value of the signal waveform defined by the base drive signal.

[0150] On the other hand, at time t0, when the voltage value of the signal waveform defined by the base drive signal begins to rise, the output drive current begins to rise with a predetermined slope due to the influence of the inductance component of the inductor in the demodulation circuit, and reaches current Ic1 at time t1. At this time, the output drive voltage gradually rises from voltage V1 in accordance with the slope of the output drive current, and at time t1 when the output drive current reaches current Ic1, it rises toward voltage V2 with a slope that is approximately equal to the slope of the signal waveform defined by the base drive signal and is approximately equal to the slope of the ideal drive voltage.

[0151] Then, at time t2, when the voltage value of the signal waveform defined by the base drive signal becomes constant, the output drive current decreases with a predetermined slope due to the release of energy stored in the inductor of the demodulation circuit, and becomes "0" at time t3. At this time, because the output drive voltage changes from voltage V1 to voltage V2 across the threshold voltage vct, the logic level of the level switching signal is switched from L level to H level. Therefore, the potential difference between the two terminals of the inductor of the demodulation circuit at time t2 is smaller than the potential difference between the two terminals of the inductor at time t0. Consequently, the slope of the output drive current from time t2 to time t3 is smaller than the slope of the output drive current from time t0 to time t1. As a result, the amount of charge supplied to the capacitive load by the output drive current between time t0 and time t3 is greater than the amount of charge supplied to the capacitive load by the ideal drive current between time t0 and time t3. The voltage corresponding to the difference between the amount of charge supplied to the capacitive load by this output drive current and the amount of charge supplied to the capacitive load by the ideal drive current is superimposed on the output drive voltage as an overshoot voltage (OVP).

[0152] As described above, the overshoot voltage OVP superimposed on the output drive voltage occurs because the slope of the output drive current decreases from time t2 to time t3, resulting in an increase in the charge supplied to the capacitive load. In other words, the overshoot voltage OVP superimposed on the output drive voltage can be reduced by increasing the slope of the output drive current from time t2 to time t3.

[0153] Here, in the comparative example drive circuit, if the output drive current is current ioc1, the voltage value of the drive signal is voltage vcom, the voltage value of the signal output by the boost circuit is voltage vbt, and the inductance value of the inductor of the demodulation circuit is Ldm, then the slope of the output drive current, current ioc1, from time t2 to time t3 can be expressed as shown in equation (3) below.

[0154]

number

[0155] In contrast to the comparative example drive circuit, if the characteristic configuration of this embodiment described above is applied, where the level switching signal output circuit 710 outputs an L-level level switching signal LS for a timing time tp1 when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, and then outputs an H-level level switching signal LS, and when the voltage value of the signal waveform defined by the base drive signal transitions from a state in which it is rising to a state in which it is constant, an L-level level switching signal is output for a predetermined period, then the slope of the output drive current from time t2 to time t3 can be shown by the following equation (4). As a result, the slope of the output drive current from time t2 to time t3 can be increased, and the overshoot voltage OVP superimposed on the output drive voltage can be reduced.

[0156]

number

[0157] In other words, in the liquid dispensing device 1 of this embodiment, when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the level switching signal output circuit 710 outputs a L-level level switching signal LS for a timing time tp1, and then outputs an H-level level switching signal LS, thereby reducing the overshoot superimposed on the drive signal COM.

[0158] Next, we will explain the timing time tp1 during which the level switching signal output circuit 710 outputs a low-level level switching signal LS when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2.

[0159] The timing time tp1 is ideally set to the time until the current supplied to the piezoelectric element 60, which is a capacitive load, decreases based on equation (4) when the level switching signal output circuit 710 starts outputting a level switching signal LS at the L level, and the current value of said current becomes "0". Here, the current value of the current supplied to the piezoelectric element 60 becoming "0" is not limited to the measured value being "0", but includes a range that can be considered substantially "0" when taking into account variations in the characteristics of various elements, changes in characteristics due to the surrounding environment such as temperature and humidity, and the operating state of the liquid ejection device 1 and the drive circuit 50. Furthermore, the current value of the current supplied to the piezoelectric element 60 becoming "0" is not limited to the measured value and the design value being "0", but is sufficient if the distortion and overshoot occurring in the signal waveform of the drive signal COM approaches "0" to an acceptable degree for the driving of the piezoelectric element 60 and the ejection of ink associated with the driving of the piezoelectric element 60.

[0160] Here, when the operating mode of the drive circuit 50 is the third mode MD3, the current Icm1, which is the current value of the current supplied to the piezoelectric element 60 via the capacitor 562 of the demodulation circuit 560, can be expressed as follows, given that Cload is the total capacitance of the multiple piezoelectric elements 60 which are a capacitive load to which the drive signal COM is supplied, Cfilter is the capacitance of the capacitor C562 of the demodulation circuit 560, voltage vmd1 is the voltage value of the drive signal COM in the first mode MD1 just before transitioning to the third mode MD3, voltage vmd2 is the voltage value of the drive signal COM in the second mode MD2 transitioning from the third mode MD3, and time tr is the time spent in the third mode MD3 when transitioning from the first mode MD1 to the second mode MD2.

[0161]

number

[0162] In other words, the current Icm1, which is the current value supplied to the piezoelectric element 60, changes depending on the number of piezoelectric elements 60 driven by the drive signal COM, the voltage vmd1 which is the voltage value of the drive signal COM in the first mode MD1 just before transitioning to the third mode MD3, the voltage vmd2 which is the voltage value of the drive signal COM in the second mode MD2 transitioning from the third mode MD3, and the voltage change per unit time in the third mode MD3 when transitioning from the first mode MD1 to the second mode MD2, and other waveform information of the drive signal COM.

[0163] On the other hand, as shown in equation (4) above, during the period when the level switching signal output circuit 710 outputs a L-level level switching signal LS when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the slope of the current supplied to the piezoelectric element 60 remains constant regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above.

[0164] Therefore, if the timing time tp1 is set to a constant value regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above, at the time the timing time tp1 has elapsed, the current value supplied to the piezoelectric elements 60, which are capacitive loads, will deviate from "0," and there is a risk that the overshoot superimposed on the signal waveform of the drive signal COM will not be sufficiently reduced. Furthermore, the voltage value of the drive signal COM may not rise sufficiently, and as a result, there is a risk that different waveform distortions will occur in the signal waveform of the drive signal COM.

[0165] Specifically, if the timing time tp1 is a constant value regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above, and the current Icm1, which is the current value of the current supplied to the piezoelectric elements 60, is small, and the time it takes for the current supplied to the piezoelectric elements 60 to decrease to "0" based on equation (4) is short, then when the timing time tp1 has elapsed, if the current supplied to the piezoelectric elements 60 is increasing in the negative direction and deviating from "0", then when the timing time tp1 has elapsed, the voltage value of the drive signal COM may not rise sufficiently, and distortion may occur in the signal waveform of the drive signal COM.

[0166] On the other hand, if the timing time tp1 is set to a constant value regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above, and the current Icm1, which is the current value of the current supplied to the piezoelectric elements 60, is large, and the time it takes for the current supplied to the piezoelectric elements 60 to decrease to "0" based on equation (4) is long, then when the timing time tp1 has elapsed, if the current supplied to the piezoelectric elements 60 has not decreased sufficiently and deviates from "0", then excess charge may be supplied to the piezoelectric elements 60, and there is a risk that the overshoot superimposed on the drive signal COM cannot be sufficiently reduced.

[0167] In contrast, in the liquid dispensing device 1 of this embodiment, the level switching control circuit 716 acquires timing information ST, including timing time tp1, from the storage circuit 718 based on a waveform information signal WAV which includes waveform information of the drive signal COM such as voltage vmd1, which is the voltage value of the drive signal COM in the first mode MD1 immediately before transitioning to the third mode MD3; voltage vmd2, which is the voltage value of the drive signal COM in the second mode MD2 transitioning from the third mode MD3; and the amount of voltage change per unit time in the third mode MD3 when transitioning from the first mode MD1 to the second mode MD2; and a drive element number information signal CNT which includes the number of piezoelectric elements 60 driven by the drive signal COM. As a result, the length of timing time tp1 is determined according to the number of piezoelectric elements 60 driven by the drive signal COM and the waveform information described above.

[0168] In other words, the level switching signal output circuit 710 switches the logic level, which is the potential of the level switching signal LS, according to at least one of the waveform information signal WAV and the number of driving elements information signal CNT. Specifically, when the voltage value of the signal waveform defined by the base driving signals dA and aA rises and then becomes constant, and the operating mode of the driving circuit 50 transitions from the third mode MD3 to the second mode MD2, the level switching signal output circuit 710 outputs a level switching signal LS at a high level with a timing time tp1 defined according to at least one of the waveform information signal WAV and the number of driving elements information signal CNT. At this time, the level switching signal output circuit 710 sets the timing time tp1 to be longer when the number of piezoelectric elements 60 driven by the driving signal COM determined based on the number of driving elements information signal CNT increases, and sets the timing time tp1 to be shorter when the number of piezoelectric elements 60 driven by the driving signal COM determined based on the number of driving elements information signal CNT decreases.

[0169] Next, using the comparative example's drive circuit, we will explain the undershoot superimposed on the drive signal output by the drive circuit. The comparative example's drive circuit is a circuit that outputs a drive signal to drive a capacitive load such as a piezoelectric element, similar to the drive circuit 50 of this embodiment. The only difference from the drive circuit 50 of this embodiment is that it does not have the characteristic configuration of the liquid dispensing device 1 of this embodiment, which outputs an H-level level switching signal LS for a predetermined time when the voltage value of the signal waveform defined by the base drive signal transitions from a state in which it decreases to a state in which it becomes constant. In other words, the comparative example's drive circuit is a circuit that outputs a drive signal to drive a capacitive load, and outputs an L-level level switching signal LS when the voltage value of the signal waveform defined by the base drive signal transitions from a state in which it decreases to a state in which it becomes constant.

[0170] Figure 16 is a diagram illustrating the mechanism by which undershoot occurs. Figure 16 illustrates a case where the voltage value of the drive signal output by the comparative example's drive circuit decreases from voltage V3 to voltage V4, crossing a predetermined threshold voltage vct at which the logic level of the level switching signal switches. In Figure 16, the voltage value of the drive signal output by the comparative example's drive circuit is shown as the output drive voltage with a solid line, the current value supplied to a capacitive load such as a piezoelectric element by the drive signal output by the comparative example's drive circuit is shown as the output drive current with a solid line, the voltage value of an ideal drive signal corresponding to the signal waveform defined by the base drive signal input to the comparative example's drive circuit is shown as the ideal drive voltage with a dashed line, and the ideal current value supplied to the capacitive load by the ideal drive signal is shown as the ideal drive current with a dashed line.

[0171] As shown in Figure 16, before time t4, when the voltage value of the signal waveform defined by the base drive signal is constant, both the output drive voltage and the ideal drive voltage are constant at voltage V3. Therefore, before time t4, no current is supplied to the capacitive load, and consequently, both the output drive current and the ideal drive current are "0".

[0172] At time t4, when the voltage value of the signal waveform defined by the base drive signal begins to decrease, the ideal drive current becomes current Ic2, and the ideal drive voltage begins to decrease from voltage V3 to voltage V4 along the slope of the signal waveform defined by the base drive signal. Then, at time t5, as the voltage value of the signal waveform defined by the base drive signal becomes constant, the ideal drive current becomes "0", and the ideal drive voltage becomes constant at voltage V4, which is the voltage value of the signal waveform defined by the base drive signal.

[0173] On the other hand, at time t4, when the voltage value of the signal waveform defined by the base drive signal begins to decrease, the output drive current begins to decrease with a predetermined slope due to the influence of the inductance component of the inductor in the demodulation circuit, and reaches current Ic2 at time t5. At this time, the output drive voltage gradually decreases from voltage V3 in accordance with the slope of the output drive current, and at time t4 when the output drive current reaches current Ic2, it decreases toward voltage V4 with a slope that is approximately equal to the slope of the signal waveform defined by the base drive signal and is approximately equal to the slope of the ideal drive voltage.

[0174] Then, at time t6, when the voltage value of the signal waveform defined by the base drive signal becomes constant, the output drive current decreases with a predetermined slope due to the release of energy stored in the inductor of the demodulation circuit, and becomes "0" at time t7. At this time, because the output drive voltage changes from voltage V3 to voltage V4, crossing the threshold voltage vct, the logic level of the level switching signal is switched from H level to L level. Therefore, the potential difference between the two terminals of the inductor of the demodulation circuit at time t6 is smaller than the potential difference between the two terminals of the inductor at time t4. Consequently, the slope of the output drive current from time t6 to time t7 is smaller than the slope of the output drive current from time t4 to time t5. As a result, the amount of charge released from the capacitive load by the output drive current between time t4 and time t7 is greater than the amount of charge released from the capacitive load by the ideal drive current between time t4 and time t7. The voltage corresponding to the difference between the amount of charge released from the capacitive load by this output drive current and the amount of charge released from the capacitive load by the ideal drive current is superimposed on the output drive voltage as an undershoot voltage (UVP).

[0175] As described above, the undershoot voltage UVP superimposed on the output drive voltage occurs because the slope of the output drive current decreases from time t6 to time t7, resulting in an increase in the charge released from the capacitive load. In other words, the undershoot voltage UVP superimposed on the output drive voltage can be reduced by increasing the slope of the output drive current from time t6 to time t7.

[0176] Here, in the comparative example's drive circuit, if the output drive current is current ioc2, the voltage value of the drive signal is voltage vcom, the voltage value of the voltage signal VD1 input to the amplifier circuit is voltage vd1, and the inductance value of the inductor of the demodulation circuit is Ldm, then the slope of the output drive current, current ioc2, from time t6 to time t7 can be expressed by the following equation (6).

[0177]

number

[0178] In contrast to the comparative example drive circuit, if the characteristic configuration of this embodiment described above is applied, where the level switching signal output circuit 710 outputs an H-level level switching signal LS for a timing time tp2 when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, and then outputs an L-level level switching signal LS, and when the voltage value of the signal waveform defined by the base drive signal transitions from a state in which it is rising to a state in which it is constant, an H-level level switching signal is output for a predetermined period, then the slope of the output drive current from time t6 to time t7 can be shown by the following equation (7). This makes it possible to increase the slope of the output drive current from time t6 to time t7, and to reduce the undershoot voltage UVP superimposed on the output drive voltage. Here, in equation (7), the voltage value of the signal output by the boost circuit is expressed as voltage vbt.

[0179]

number

[0180] In other words, in the liquid dispensing device 1 of this embodiment, when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the level switching signal output circuit 710 outputs a H-level level switching signal LS for a timing time tp2, and then outputs an L-level level switching signal LS, thereby reducing the undershoot superimposed on the drive signal COM.

[0181] Next, we will explain the timing time tp2 during which the level switching signal output circuit 710 outputs an H-level level switching signal LS when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1.

[0182] The timing time tp2 is ideally set to the time it takes for the current associated with the charge emitted from the piezoelectric element 60, which is a capacitive load, to increase according to equation (6) when the level switching signal output circuit 710 starts outputting a level switching signal LS at the H level, until the current value of that current becomes "0".

[0183] Here, when the operating mode of the drive circuit 50 is the third mode MD3, the current Icm2, which is the current value of the current supplied to the piezoelectric element 60 via the capacitor 562 of the demodulation circuit 560, can be expressed as follows, given that Cload is the total capacitance of the multiple piezoelectric elements 60 which are a capacitive load to which the drive signal COM is supplied, Cfilter is the capacitance of the capacitor C562 of the demodulation circuit 560, voltage vmd2 is the voltage value of the drive signal COM in the second mode MD2 just before transitioning to the third mode MD3, voltage vmd1 is the voltage value of the drive signal COM in the first mode MD1 transitioning from the third mode MD3, and time tr is the time spent in the third mode MD3 when transitioning from the second mode MD2 to the first mode MD1, then it can be expressed as shown in equation (8) below.

[0184]

number

[0185] In other words, the current Icm2, which is the current value of the current supplied to the piezoelectric element 60, changes depending on the number of piezoelectric elements 60 driven by the drive signal COM, the voltage vmd2, which is the voltage value of the drive signal COM in the second mode MD2 just before transitioning to the third mode MD3, the voltage vmd1, which is the voltage value of the drive signal COM in the first mode MD1 transitioning from the third mode MD3, and the voltage change per unit time in the third mode MD3 when transitioning from the second mode MD2 to the first mode MD1, and other waveform information of the drive signal COM.

[0186] On the other hand, as shown in equation (7) above, during the period when the level switching signal output circuit 710 outputs a high-level level switching signal LS when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the slope of the current supplied to the piezoelectric element 60 remains constant regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above.

[0187] Therefore, if the timing time tp2 is set to a constant value regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above, at the time the timing time tp2 has elapsed, the current value based on the charge emitted from the piezoelectric elements 60, which are capacitive loads, will deviate from "0," and there is a risk that the undershoot superimposed on the signal waveform of the drive signal COM will not be sufficiently reduced. Furthermore, the voltage value of the drive signal COM may not decrease sufficiently, and as a result, there is a risk that different waveform distortions will occur in the signal waveform of the drive signal COM.

[0188] Specifically, if the timing time tp2 is a constant value regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above, and the current Icm2, which is the current value of the current supplied to the piezoelectric elements 60, is small, and the time it takes for the current supplied to the piezoelectric elements 60 to decrease to "0" based on equation (7) is short, then when the timing time tp2 has elapsed, if the current supplied to the piezoelectric elements 60 is increasing in the positive direction and deviating from "0", then when the timing time tp2 has elapsed, the voltage value of the drive signal COM may not decrease sufficiently, and distortion may occur in the signal waveform of the drive signal COM.

[0189] On the other hand, if the timing time tp2 is set to a constant value regardless of the number of piezoelectric elements 60 driven by the drive signal COM or the waveform information described above, then the current Icm2, which is the current value of the current based on the charge emitted from the piezoelectric elements 60, is large, and the time it takes for the current supplied to the piezoelectric elements 60 to decrease to "0" based on equation (6) is long. As a result, when the timing time tp2 has elapsed, if the current supplied to the piezoelectric elements 60 has not increased sufficiently and deviates from "0", then excess charge may be emitted from the piezoelectric elements 60, and the undershoot superimposed on the drive signal COM may not be sufficiently reduced.

[0190] In contrast, in the liquid dispensing device 1 of this embodiment, the level switching control circuit 716 acquires timing information ST, including timing time tp2, from the storage circuit 718 based on a waveform information signal WAV which includes waveform information of the drive signal COM such as voltage vmd2, which is the voltage value of the drive signal COM in the second mode MD2 immediately before transitioning to the third mode MD3; voltage vmd1, which is the voltage value of the drive signal COM in the first mode MD1 transitioning from the third mode MD3; and the amount of voltage change per unit time in the third mode MD3 when transitioning from the second mode MD2 to the first mode MD1; and a drive element number information signal CNT which includes the number of piezoelectric elements 60 driven by the drive signal COM. As a result, the length of timing time tp2 is determined according to the number of piezoelectric elements 60 driven by the drive signal COM and the waveform information described above.

[0191] In other words, the level switching signal output circuit 710 switches the logic level, which is the potential of the level switching signal LS, according to at least one of the waveform information signal WAV and the number of driving elements information signal CNT. Specifically, when the voltage value of the signal waveform defined by the base driving signals dA and aA decreases and then becomes constant, and the operating mode of the driving circuit 50 transitions from the third mode MD3 to the first mode MD1, the level switching signal output circuit 710 outputs a level switching signal LS at a timing time tp2 and an L level, which is defined according to at least one of the waveform information signal WAV and the number of driving elements information signal CNT. At this time, the level switching signal output circuit 710 sets the timing time tp2 to be longer when the number of piezoelectric elements 60 driven by the driving signal COM determined based on the number of driving elements information signal CNT increases, and sets the timing time tp2 to be shorter when the number of piezoelectric elements 60 driven by the driving signal COM determined based on the number of driving elements information signal CNT decreases.

[0192] 5. Control method for the drive circuit of a liquid dispensing device and liquid dispensing device. Here, the control method for the liquid dispensing device 1 and the drive circuit 50 of the liquid dispensing device 1 will be described. Figure 17 is a diagram showing the control method for the liquid dispensing device 1 and the drive circuit 50. As shown in Figure 17, the control of the liquid dispensing device 1 and the drive circuit 50 starts when image data is input to the control circuit 100 of the liquid dispensing device 1 (step S10). The control circuit 100 then generates various signals, including the print data signal SI, by applying various image processing to the input image data (step S20). Subsequently, the control circuit 100 performs a drive piezoelectric element number calculation process based on the generated print data signal SI to calculate the number of piezoelectric elements 60 to which the drive signal COM is supplied at each dot formation period T defined by the latch signal LAT (step S30).

[0193] Here, a specific example of the process for calculating the number of driving piezoelectric elements in step S30 will be described. Figure 18 shows an example of the process for calculating the number of driving piezoelectric elements. As shown in Figure 18, when the process for calculating the number of driving piezoelectric elements is executed, the control circuit 100 assigns "0" to the variable i as an initial setting (step S310). Then, the control circuit 100 determines whether the variable i is less than the total dot formation period Ttotal (step S320). Here, the total dot formation period Ttotal is a value calculated based on the image data, and is the total number of dot formation periods T required to form an image on the medium according to the image data.

[0194] If the control circuit 100 determines that the variable i is less than the total dot formation period Ttotal (Y in step S320), the control circuit 100 sets the number of drive nozzles N-Count[i] in the i-th dot formation period T to "0" as an initial setting (step S330) and also sets the variable j to "0" (step S340).

[0195] Subsequently, the control circuit 100 determines whether the variable j is less than the total number of drive elements Ntotal, which is the total number of piezoelectric elements 60 to which the drive signal COM can be supplied (step S350). If the control circuit 100 determines that the variable j is less than the total number of drive elements Ntotal (Y in step S350), the control circuit 100 determines whether the print data Sid-j is [1] (step S360). If the control circuit 100 determines that the print data Sid-j is [1] (Y in step S360), the control circuit 100 adds "1" to the number of drive nozzles N-Count[i] (step S370). In other words, the control circuit 100 adds "1" to the number of drive nozzles N-Count[i] when the drive signal COM is supplied to the piezoelectric element 60 of the ejection unit 600 corresponding to the print data Sid-j. Then, after adding 1 to the number of drive nozzles N-Count[i], or if the control circuit 100 determines that the print data Sid-j is not [1] (N in step S360), the control circuit 100 adds 1 to the variable j (step S380), and repeats steps S350 to S380 described above.

[0196] In other words, the control circuit 100 checks whether the print data Sid corresponding to all piezoelectric elements 60 to which the drive signal COM can be supplied is supplied [1] or not supplied [0], and if the print data Sid is [1], it adds "1" to the number of drive nozzles N-Count[i]. As a result, the number of drive nozzles N-Count[i] holds the total number of piezoelectric elements 60 driven by the drive signal COM in the i-th dot formation period T.

[0197] Then, the control circuit 100 determines that the variable j is not less than the total number of drive elements Ntotal (N in step S350), and the verification of the print data Sid information corresponding to all piezoelectric elements 60 to which the drive signal COM can be supplied in the i-th dot formation period T is completed. At this time, the control circuit 100 stores the number of drive nozzles N-Count[i] in a memory circuit not shown (step S390). Thus, the number of piezoelectric elements 60 to which the drive signal COM is supplied in the i-th dot formation period T is stored as the number of drive nozzles N-Count[i].

[0198] Subsequently, the control circuit 100 adds "1" to the variable i (step S400) and repeatedly executes steps S320 to S400 described above. That is, the control circuit 100 calculates the total number of piezoelectric elements 60 driven by the drive signal COM for each of the dot formation periods T required to form an image on the medium according to the image data, and stores this as the number of drive nozzles N-Count[i] corresponding to each of the dot formation periods T. Then, the control circuit 100 determines that the variable i is not less than the total dot formation period Ttotal (N in step S320), and thus completes the calculation of the total number of piezoelectric elements 60 driven by the drive signal COM for all of the dot formation periods T required to form an image on the medium according to the image data, and terminates the drive piezoelectric element number calculation process.

[0199] As described above, the control circuit 100 calculates the number of piezoelectric elements 60 driven by the drive signal COM during the dot formation period T, based on the print data signal SI which switches whether or not to supply a drive signal COM to a plurality of piezoelectric elements 60.

[0200] Returning to Figure 17, once the drive piezoelectric element number calculation process is complete, the control circuit 100 outputs the print data signal SI generated based on the image data to the drive signal selection circuit 200, and also outputs the waveform information signal WAV, which includes the waveform information of the drive signal COM output by the drive circuit 50, and the drive element number information signal CNT, which includes the drive nozzle number N-Count[i] calculated in the drive piezoelectric element number calculation process, to the drive circuit 50 (step S40). Subsequently, the control circuit 100 outputs the base drive signal dA, which defines the signal waveform of the drive signal COM, to the drive circuit 50 (step S50). The base drive signal dA output by the control circuit 100 is converted to a base drive signal aA in the D / A conversion circuit 510 and then input to the modulation circuit 520. The modulation circuit 520 generates a modulated signal MS by modulating the base drive signal aA according to the input base drive signal dA, and performs a modulation process that outputs the generated modulated signal MS to the amplification circuit 550 (step S60). Then, the amplification circuit 550 amplifies the modulated signal MS based on the voltage signal VD1 to generate a first amplified modulated signal AMS1, which is an amplified modulated signal MS, and performs amplification processing to output it to the level shift circuit 750 (step S70).

[0201] The base drive signal aA, which is obtained by converting the base drive signal dA output by the control circuit 100 in the D / A conversion circuit 510, the waveform information signal WAV, which includes the waveform information of the drive signal COM output by the drive circuit 50 output by the control circuit 100, and the drive element number information signal CNT, which includes the number of drive nozzles N-Count[i] calculated in the drive piezoelectric element number calculation process, are input to the level switching signal output circuit 710. The level switching signal output circuit 710 also receives a feedback signal VFB1 corresponding to the drive signal COM output by the feedback circuit 570. The level switching signal output circuit 710 performs a level switching signal output process that outputs a level switching signal LS, which changes between H level and L level, to the level shift circuit 750 according to the base drive signal aA, the waveform information signal WAV, the drive element number information signal CNT, and the feedback signal VFB1 (step S80).

[0202] In other words, the level switching signal output circuit 710 switches the logic level of the level switching signal LS in accordance with the feedback signal VFB1 during the period when the voltage value of the signal waveform defined by the base drive signals dA and aA changes. When the voltage value of the signal waveform defined by the base drive signals dA and aA rises and then becomes constant, and the operating mode of the drive circuit 50 transitions from the third mode MD3 to the second mode MD2, the level switching signal output circuit 710 outputs a level switching signal LS at H level with a timing time tp1 defined according to at least one of the waveform information signal WAV and the number of drive elements information signal CNT. When the voltage value of the signal waveform defined by the base drive signals dA and aA falls and then becomes constant, and the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, the level switching signal output circuit 710 outputs a level switching signal LS at L level with a timing time tp2 defined according to at least one of the waveform information signal WAV and the number of drive elements information signal CNT. Here, the level switching signal output processing may be performed before the modulation processing in step S60 and the amplification processing in step S70, or it may be performed in parallel with the modulation processing in step S60 and the amplification processing in step S70.

[0203] After the modulation processing in step S60, the amplification processing in step S70, and the level switching signal output processing in step S80 are completed, the level shift circuit 750 generates a second amplified modulation signal AMS2 according to the logic level of the input level switching signal LS and performs level shift processing to output it to the demodulation circuit 560 (step S90). The demodulation circuit 560 then performs demodulation processing to demodulate the input second amplified modulation signal AMS2 (step S100). The demodulation circuit 560 then outputs the demodulated signal of the second amplified modulation signal AMS2 as the drive signal COM. Specifically, the level shift circuit 750 outputs a signal obtained by shifting the reference potential of the first amplification modulation signal AMS1 as the second amplification modulation signal AMS2 when the level switching signal LS is at a high level, and outputs the first amplification modulation signal AMS1 as the second amplification modulation signal AMS2 when the level switching signal LS is at a low level. The demodulation circuit 560 demodulates the second amplification modulation signal AMS2 and outputs it as the drive signal COM.

[0204] Subsequently, the control circuit 100 determines whether the dot formation period T has ended (step S110). If the control circuit 100 determines that the dot formation period T has not ended (step S110, step N), it repeats steps S50 to S110 described above. As a result, the drive circuit 50 generates and outputs a drive signal COM as shown in Figure 5 during the dot formation period T.

[0205] On the other hand, if the control circuit 100 determines that the dot formation period T has ended (Y in step S110), the control circuit 100 determines whether or not the formation of the image corresponding to the image data has ended (step S130). If the control circuit 100 determines that the formation of the image corresponding to the image data has not ended (N in step S120), it executes steps S40 to S120 described above, which correspond to the next dot formation period T. On the other hand, if the control circuit 100 determines that the formation of the image corresponding to the image data has ended (N in step S120), the liquid dispensing device 1 and the drive circuit 50 stop operating. This terminates the control of the liquid dispensing device 1 and the drive circuit 50 of the liquid dispensing device 1.

[0206] Here, the multiple piezoelectric elements 60 are an example of multiple capacitive loads, the drive circuit 50 is an example of a capacitive load drive circuit, the base drive signal aA corresponding to the base drive signal dA is an example of a base drive signal, the H level is an example of a first potential, the L level is an example of a second potential, the timing time tp1 is an example of a first period, the timing time tp2 is an example of a second period, the gate drive signal HGD2 is an example of a first gate signal, the gate drive signal LGD2 is an example of a second gate signal, the gate drive circuit 730 is an example of a gate driver, the transistor M3 is an example of a first transistor, the transistor M4 is an example of a second transistor, the voltage signal VD2 is an example of a level shift voltage signal, the voltage signal VBST is an example of a bootstrap voltage signal, the boost circuit BS is an example of a bootstrap circuit, and the second output point OP2 is an example of a connection point. Furthermore, step S40 is an example of a switching information output process, step S60 is an example of a modulation process, step S70 is an example of an amplification process, step S80 is an example of a level switching process, step S90 is an example of a level shift process, and step S100 is an example of a demodulation process.

[0207] 6. Effects In the liquid dispensing device 1, the number of piezoelectric elements 60 driven by the drive signal COM changes significantly, which causes the load capacity supplied to the drive signal COM output by the drive circuit 50 to change significantly. As a result, there was a risk that the waveform accuracy of the signal waveform of the drive signal COM would decrease.

[0208] In contrast, the liquid discharge device 1 and drive circuit 50 of this embodiment include a modulation circuit 520 that outputs a modulated signal MS obtained by modulating the base drive signal aA which is the basis of the drive signal COM, an amplification circuit 550 that outputs a first amplified modulation signal AMS1 which is amplified from the modulated signal MS, a level switching signal output circuit 710 that outputs a level switching signal LS which changes between H level and L level, and when the level switching signal LS is at the H level, a signal obtained by shifting the reference potential of the first amplified modulation signal AMS1 is output as the second amplified modulation signal AMS2, and when the level switching signal LS is at the L level, the first amplified modulation signal AMS1 is converted to the second amplified modulation signal AMS2. The level switching signal output circuit 710 includes a level shift circuit 750 that outputs as MS2, and a demodulation circuit 560 that demodulates the second amplified modulation signal AMS2 and outputs a drive signal COM. The level switching signal output circuit 710 switches the potential of the level switching signal LS according to at least one of a waveform information signal WAV containing waveform information of the drive signal COM, and a drive element number information signal CNT containing information on the number of piezoelectric elements 60 driven by the drive signal COM. This allows the number of piezoelectric elements 60 driven by the drive signal COM, which corresponds to the load capacitance supplied by the drive signal COM, to be determined by feedforward control. As a result, the waveform accuracy of the signal waveform of the drive signal COM output by the drive circuit 50 is reduced due to fluctuations in load capacitance. In other words, the waveform accuracy of the drive signal COM output by the drive circuit 50 can be improved.

[0209] Furthermore, the control method for the liquid discharge device 1 and the control method for the drive circuit 50 of this embodiment includes the steps of: outputting a waveform information signal WAV containing waveform information of the drive signal COM, and a drive element number information signal CNT containing information on the number of piezoelectric elements 60 driven by the drive signal COM; outputting a modulated signal MS obtained by modulating the base drive signal aA which is the basis of the drive signal COM; outputting a first amplified modulated signal AMS1 obtained by amplifying the modulated signal MS; outputting a level switching signal LS which changes between H level and L level; and when the level switching signal LS is at the H level, outputting a signal obtained by shifting the reference potential of the first amplified modulated signal AMS1 to a second amplified modulated signal The process includes outputting a signal as AMS2, outputting the first amplified modulation signal AMS1 as the second amplified modulation signal AMS2 when the level switching signal LS is at the L level, and demodulating the second amplified modulation signal AMS2 and outputting a drive signal COM. In the process of outputting a level switching signal LS that changes between H level and L level, the potential of the level switching signal LS is switched according to at least one of the waveform information signal WAV and the number of drive elements information signal CNT. This allows the number of piezoelectric elements 60 driven by the drive signal COM, which is the load capacitance supplied by the drive signal COM, to be determined by feedforward control. As a result, the waveform accuracy of the signal waveform of the drive signal COM output by the drive circuit 50 is reduced due to fluctuations in load capacitance. In other words, the waveform accuracy of the drive signal COM output by the drive circuit 50 can be improved.

[0210] 7. Variations In the liquid discharge device 1 and drive circuit 50 described above, the level switching signal output circuit 710 was described as switching the logic level of the level switching signal LS in accordance with the feedback signal VFB1 output by the feedback circuit 570 during the period when the value of the base drive signal aA changes and the operating mode of the drive circuit 50 is in the third mode MD3. However, the level switching signal output circuit 710 may, regardless of the feedback signal VFB1, have a total time during which the level switching signal LS is at an H level when the number of piezoelectric elements 60 driven by the drive signal COM is p1, during the period when the voltage value of the signal waveform defined by the base drive signal aA increases and the operating mode of the drive circuit 50 transitions from the first mode MD1 to the second mode MD2, that is, is longer than the total time during which the level switching signal LS is at an H level when the number of piezoelectric elements 60 driven by the drive signal COM is less than p1, namely p2. This makes it possible to supply sufficient current to the piezoelectric elements 60 even when there are many piezoelectric elements 60 to which the drive signal COM output by the drive circuit 50 is supplied, thereby improving the waveform accuracy of the drive signal COM.

[0211] Furthermore, the level switching signal output circuit 710 may, regardless of the feedback signal VFB1, extend the total time during which the level switching signal LS is at an L level when the number of piezoelectric elements 60 driven by the drive signal COM is q1, during the period when the voltage value of the signal waveform defined by the base drive signal aA decreases, and in the third mode MD3 when the operating mode of the drive circuit 50 transitions from the second mode MD2 to the first mode MD1, to an L level, compared with the total time when the number of piezoelectric elements 60 driven by the drive signal COM is less than q1, namely q2. This makes it possible to draw sufficient current from the piezoelectric elements 60 even when there are many piezoelectric elements 60 to which the drive signal COM output by the drive circuit 50 is supplied, thereby improving the waveform accuracy of the drive signal COM.

[0212] Furthermore, in the liquid discharge device 1 and drive circuit 50 described above, the level switching signal output circuit 710 may switch the potential of the output level switching signal LS according to the potential difference between one end and the other end of the capacitor C13 of the boost circuit BS. As shown in equation (7) above, when the operating mode of the drive circuit 50 transitions from the third mode MD3 to the first mode MD1, and a level switching signal LS of H level is output at the timing time tp2, the slope of the current associated with the charge discharged from the piezoelectric element 60 is the voltage value of the voltage signal VBST output by the boost circuit BS, and the potential difference between the ends of the capacitor C13 of the boost circuit BS also contributes. By switching the potential of the output level switching signal LS according to the potential difference between one end and the other end of the capacitor C13 of the boost circuit BS, the timing time tp2 can be set more appropriately, and the risk of undershoot in the output drive signal COM is further reduced.

[0213] Here, capacitor C13 is an example of a bootstrap capacitor.

[0214] Although embodiments have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0215] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0216] The following conclusions can be drawn from the embodiments described above.

[0217] One embodiment of a capacitive load drive circuit is: A capacitive load drive circuit that outputs drive signals to drive multiple capacitive loads, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs a first amplified modulated signal obtained by amplifying the aforementioned modulated signal, A level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential, A level shift circuit that outputs a signal obtained by shifting the reference potential of the first amplification modulation signal as a second amplification modulation signal when the level switching signal is at the first potential, and outputs the first amplification modulation signal as a second amplification modulation signal when the level switching signal is at the second potential, A demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal, Equipped with, The level switching signal output circuit switches the potential of the level switching signal according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of the plurality of capacitive loads driven by the drive signal.

[0218] In this capacitive load drive circuit, the level switching signal output circuit switches the potential of the level switching signal according to at least one of a waveform information signal containing waveform information of the drive signal and a drive element number information signal containing information on the number of drive elements of the multiple capacitive loads driven by the drive signal. The level shift circuit outputs a signal obtained by shifting the reference potential of the first amplified modulation signal as the second amplified modulation signal when the level switching signal is at the first potential, and outputs the first amplified modulation signal as the second amplified modulation signal when the level switching signal is at the second potential, thereby performing feedforward control according to the number of drive elements of the multiple capacitive loads driven by the drive signal. As a result, the waveform accuracy of the drive signal can be improved even when the load capacitance to which the drive signal is supplied changes. In other words, the waveform accuracy of the output drive signal can be improved.

[0219] In one embodiment of the capacitive load drive circuit, The drive element number information signal may be generated based on a switching control signal that switches whether or not to supply the drive signal to the plurality of capacitive loads.

[0220] In one embodiment of the capacitive load drive circuit, The aforementioned drive element number information signal may be input at each dot formation cycle in which dots are formed on the medium by the liquid discharged by driving the plurality of capacitive loads.

[0221] In this capacitive load drive circuit, the waveform accuracy of the drive signal can be improved even when the load capacitance to which the drive signal is supplied changes with each dot formation cycle. In other words, the waveform accuracy of the output drive signal can be improved.

[0222] In one embodiment of the capacitive load drive circuit, When the voltage value of the signal waveform defined by the aforementioned drive signal rises and then becomes constant, The level switching signal output circuit may output the level switching signal of the first potential for a first period defined according to at least one of the waveform information signal and the number of drive elements information signal.

[0223] This capacitive load drive circuit reduces the risk of overshoot superimposed on the drive signal, further improving the waveform accuracy of the drive signal.

[0224] In one embodiment of the capacitive load drive circuit, When the voltage value of the signal waveform defined by the aforementioned drive signal decreases and then becomes constant, The level switching signal output circuit may output the level switching signal of the second potential for a second period defined according to at least one of the waveform information signal and the number of drive elements information signal.

[0225] This capacitive load drive circuit reduces the risk of undershoot superimposed on the drive signal, further improving the waveform accuracy of the drive signal.

[0226] In one embodiment of the capacitive load drive circuit, During the period in which the voltage value of the signal waveform defined by the base drive signal rises, the total time for the level switching signal output circuit to output the level switching signal at the first potential when the number of drive elements is p1 may be longer than the total time for the level switching signal output circuit to output the level switching signal at the first potential when the number of drive elements is less than p1, namely p2.

[0227] In this capacitive load drive circuit, the tracking ability of the drive signal to the signal waveform defined by the base drive signal is improved, and the waveform accuracy of the drive signal is further enhanced.

[0228] In one embodiment of the capacitive load drive circuit, During the period in which the voltage value of the signal waveform defined by the base drive signal decreases, the total time for the level switching signal output circuit to output the level switching signal at the second potential when there are q1 drive elements may be longer than the total time for the level switching signal output circuit to output the level switching signal at the second potential when there are q2 drive elements, which is less than q1.

[0229] In this capacitive load drive circuit, the tracking ability of the drive signal to the signal waveform defined by the base drive signal is improved, and the waveform accuracy of the drive signal is further enhanced.

[0230] In one embodiment of the capacitive load drive circuit, It has a feedback circuit that outputs a feedback signal corresponding to the drive signal, During the period in which the voltage value of the signal waveform defined by the base drive signal changes, the level switching signal output circuit may switch the potential of the level switching signal in accordance with the feedback signal.

[0231] In this capacitive load drive circuit, the tracking ability of the drive signal to the signal waveform defined by the base drive signal is improved, and the waveform accuracy of the drive signal is further enhanced.

[0232] In one embodiment of the capacitive load drive circuit, The level shift circuit described above is A gate driver that outputs a first gate signal and a second gate signal corresponding to the level switching signal, A first transistor whose conduction state between the drain terminal and the source terminal is controlled according to the first gate signal, A second transistor whose conduction state between the drain terminal and the source terminal is controlled according to the second gate signal, A bootstrap circuit receives the first amplified modulation signal and a level-shift voltage signal as inputs and outputs a bootstrap voltage signal obtained by shifting the reference potential of the first amplified modulation signal according to the level-shift voltage signal, It has, The bootstrap voltage signal is input to the drain terminal of the first transistor. The first amplified and modulated signal is input to the source terminal of the second transistor. The source terminal of the first transistor and the drain terminal of the second transistor are electrically connected at the connection point. The gate driver outputs a first gate signal that controls the drain terminal and source terminal of the first transistor to conduct when the level switching signal is at the first potential, and outputs a second gate signal that controls the drain terminal and source terminal of the second transistor to conduct when the level switching signal is at the second potential. The level shift circuit outputs the signal at the connection point as the second amplified modulated signal.

[0233] In one embodiment of the capacitive load drive circuit, The bootstrap circuit includes a bootstrap capacitor, one end of which is electrically connected to the drain terminal of the first transistor and the other end of which is electrically connected to the connection point. The level switching signal output circuit may switch the potential of the output level switching signal according to the potential difference between one end and the other end of the bootstrap capacitor.

[0234] This capacitive load drive circuit reduces the risk of undershoot superimposed on the drive signal, further improving the waveform accuracy of the drive signal.

[0235] One aspect of a control method for a capacitive load drive circuit is: A control method for a capacitive load drive circuit that outputs drive signals to drive multiple capacitive loads, A modulation step that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification step which outputs a first amplified modulated signal obtained by amplifying the modulated signal, A level switching signal output process that outputs a level switching signal that changes between a first potential and a second potential, A level shifting step in which, when the level switching signal is at the first potential, a signal obtained by shifting the reference potential of the first amplification modulation signal is output as the second amplification modulation signal, and when the level switching signal is at the second potential, the first amplification modulation signal is output as the second amplification modulation signal, A demodulation step which demodulates the second amplified modulated signal and outputs the drive signal, It has, In the level switching signal output step, the potential of the level switching signal is switched according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of the plurality of capacitive loads driven by the drive signal.

[0236] In this control method for a capacitive load drive circuit, in the level switching signal output step, the potential of the level switching signal is switched according to at least one of a waveform information signal containing waveform information of the drive signal and a drive element number information signal containing information on the number of drive elements of a plurality of capacitive loads driven by the drive signal. In the level shift step, when the level switching signal is at the first potential, a signal obtained by shifting the reference potential of the first amplification modulation signal is output as the second amplification modulation signal, and when the level switching signal is at the second potential, the first amplification modulation signal is output as the second amplification modulation signal, thereby performing feedforward control according to the number of drive elements of a plurality of capacitive loads driven by the drive signal. As a result, the waveform accuracy of the drive signal can be improved even when the load capacitance to which the drive signal is supplied changes. In other words, the waveform accuracy of the output drive signal can be improved.

[0237] In one embodiment of the control method for the capacitive load drive circuit, The drive element number information signal may be generated based on a switching control signal that switches whether or not to supply the drive signal to the plurality of capacitive loads.

[0238] In one embodiment of the control method for the capacitive load drive circuit, The drive element number information signal may be output for each dot formation cycle in which dots are formed on the medium by the liquid discharged by driving the plurality of capacitive loads.

[0239] This control method for a capacitive load drive circuit can improve the waveform accuracy of the drive signal even when the load capacitance to which the drive signal is supplied changes with each dot formation cycle. In other words, it can improve the waveform accuracy of the output drive signal.

[0240] In one embodiment of the control method for the capacitive load drive circuit, In the level switching signal output process, After the voltage value of the signal waveform defined by the base drive signal has risen and then become constant, a first period defined according to at least one of the waveform information signal and the drive element number information signal, and the level switching signal of the first potential may be output.

[0241] In this control method of the capacitive load drive circuit, the possibility of overshoot being superimposed on the drive signal can be reduced, and the waveform accuracy of the drive signal is further improved.

[0242] In one aspect of the control method of the capacitive load drive circuit, In the level switching signal output step, After the voltage value of the signal waveform defined by the base drive signal has decreased and then become constant, a second period defined according to at least one of the waveform information signal and the drive element number information signal, and the level switching signal of the second potential may be output.

[0243] In this control method of the capacitive load drive circuit, the possibility of undershoot being superimposed on the drive signal can be reduced, and the waveform accuracy of the drive signal is further improved.

[0244] In one aspect of the control method of the capacitive load drive circuit, In the level switching signal output step, During the period when the voltage value of the signal waveform defined by the base drive signal rises, the total time for which the level switching signal of the first potential is output may be longer when the number of drive elements is p1 than when the number of drive elements is p2, which is less than p1.

[0245] In this control method of the capacitive load drive circuit, the followability of the signal waveform defined by the base drive signal by the drive signal is improved, and the waveform accuracy of the drive signal is further improved.

[0246] In one aspect of the control method of the capacitive load drive circuit, In the level switching signal output step, During a period in which the voltage value of the signal waveform defined by the base drive signal decreases, the total time during which the level switching signal of the second potential is output may be longer when the number of drive elements is q1 than when the number of drive elements is q2, where q2 is less than q1.

[0247] In this control method for the capacitive load driving circuit, the followability of the signal waveform defined by the base drive signal with respect to the drive signal is improved, and the waveform accuracy of the drive signal is further improved.

[0248] In one aspect of the control method for the capacitive load driving circuit, In the level switching signal output step, During a period in which the voltage value of the signal waveform defined by the base drive signal changes, the potential of the level switching signal may be switched in accordance with a feedback signal corresponding to the drive signal.

[0249] In this control method for the capacitive load driving circuit, the followability of the signal waveform defined by the base drive signal with respect to the drive signal is improved, and the waveform accuracy of the drive signal is further improved.

[0250] In one aspect of the control method for the capacitive load driving circuit, The capacitive load driving circuit includes a gate driver that outputs a first gate signal and a second gate signal corresponding to the level switching signal, a first transistor whose conduction state between a drain terminal and a source terminal is controlled in accordance with the first gate signal, a second transistor whose conduction state between a drain terminal and a source terminal is controlled in accordance with the second gate signal, a bootstrap circuit to which the first amplified modulation signal and a level shift voltage signal are input and that outputs a bootstrap voltage signal obtained by shifting the reference potential of the first amplified modulation signal in accordance with the level shift voltage signal, and the bootstrap voltage signal is input to the drain terminal of the first transistor. The first amplified and modulated signal is input to the source terminal of the second transistor. The source terminal of the first transistor and the drain terminal of the second transistor are electrically connected at the connection point. The gate driver outputs a first gate signal that controls the drain terminal and source terminal of the first transistor to conduct when the level switching signal is at the first potential, and outputs a second gate signal that controls the drain terminal and source terminal of the second transistor to conduct when the level switching signal is at the second potential. The signal at the connection point may be output as the second amplified and modulated signal.

[0251] In one embodiment of the control method for the capacitive load drive circuit, The bootstrap circuit comprises a bootstrap capacitor, one end of which is electrically connected to the drain terminal of the first transistor and the other end of which is electrically connected to the connection point. In the level switching signal output step, the potential of the output level switching signal may be switched according to the potential difference between one end and the other end of the bootstrap capacitor.

[0252] This control method for capacitive load drive circuits reduces the risk of undershoot superimposed on the drive signal, further improving the waveform accuracy of the drive signal. [Explanation of Symbols]

[0253] 1…Liquid dispensing device, 2…Mobile body, 3…Mobile unit, 4…Transport unit, 10…Control unit, 13…Capacitor, 20…Head unit, 21…Dispensing head, 24…Carriage, 31…Carriage motor, 32…Carriage guide shaft, 33…Timing belt, 40…Platen, 41…Transport motor, 42…Transport roller, 50…Drive circuit, 60…Piezoelectric element, 100…Control circuit, 190…Cable, 200…Drive signal selection circuit, 210…Selection control circuit, 212…Shift register, 214…Latch circuit, 216…Decoder, 230…Selection circuit, 232…Inverter, 234…Transfer gate, 510…D / A conversion circuit, 511…Adder, 520…Modulation circuit, 521…Inverter, 530…Gate drive circuit, 531,532…Gate driver, 550…Amplification circuit, 560…Demodulation circuit, 56 1...Inductor, 562...Capacitor, 570...Feedback circuit, 572...Resistor, 574...Capacitor, 600...Discharge section, 601...Piezoelectric element, 611, 612...Electrode, 621...Diaphragm, 631...Cavity, 632...Nozzle plate, 641...Reservoir, 651...Nozzle, 710...Level switching signal output circuit, 712...Differentiation circuit, 714...Comparator circuit, 716...Level switching control circuit, 718...Memory circuit, 720 ...Output switching circuit, 721...Inverter, 722...AND circuit, 724...OR circuit, 730...Gate drive circuit, 731,732...Gate driver, 750...Level shift circuit, BS...Boost circuit, C1,C11~C13,C562...Capacitors, D1,D11~D13...Diodes, L...Nozzle row, M1,M2,M3,M4...Transistors, OP1...First output point, OP2...Second output point, P...Medium

Claims

1. A capacitive load drive circuit that outputs drive signals to drive multiple capacitive loads, A modulation circuit that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification circuit that outputs a first amplified modulated signal obtained by amplifying the aforementioned modulated signal, A level switching signal output circuit that outputs a level switching signal that changes between a first potential and a second potential, A level shift circuit that outputs a signal obtained by shifting the reference potential of the first amplification modulation signal as a second amplification modulation signal when the level switching signal is at the first potential, and outputs the first amplification modulation signal as a second amplification modulation signal when the level switching signal is at the second potential, A demodulation circuit that demodulates the second amplified modulated signal and outputs the drive signal, Equipped with, The level switching signal output circuit switches the potential of the level switching signal according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of the plurality of capacitive loads driven by the drive signal. A capacitive load drive circuit characterized by the following features.

2. The drive element number information signal is generated based on a switching control signal that switches whether or not to supply the drive signal to the plurality of capacitive loads. Capacitive load drive circuit according to feature 1.

3. The aforementioned drive element number information signal is input at each dot formation cycle in which dots are formed on the medium by the liquid discharged by the driving of the plurality of capacitive loads. Capacitive load drive circuit according to feature 2.

4. When the voltage value of the signal waveform defined by the aforementioned drive signal rises and then becomes constant, The level switching signal output circuit outputs the level switching signal of the first potential for a first period defined according to at least one of the waveform information signal and the number of drive elements information signal. Capacitive load drive circuit according to feature 1.

5. When the voltage value of the signal waveform defined by the aforementioned drive signal decreases and then becomes constant, The level switching signal output circuit outputs the level switching signal of the second potential for a second period defined according to at least one of the waveform information signal and the number of drive elements information signal. Capacitive load drive circuit according to feature 1.

6. During the period in which the voltage value of the signal waveform defined by the base drive signal rises, the total time for the level switching signal output circuit to output the level switching signal at the first potential when the number of drive elements is p1 is longer than the total time for the level switching signal output circuit to output the level switching signal at the first potential when the number of drive elements is p2, which is less than p1. Capacitive load drive circuit according to feature 1.

7. During the period in which the voltage value of the signal waveform defined by the aforementioned drive signal decreases, the total time for which the level switching signal output circuit outputs the level switching signal at the second potential when the number of drive elements is q1 is longer than the total time for which the level switching signal output circuit outputs the level switching signal at the second potential when the number of drive elements is q2, which is less than q1. Capacitive load drive circuit according to feature 1.

8. It has a feedback circuit that outputs a feedback signal corresponding to the drive signal, During the period in which the voltage value of the signal waveform defined by the base drive signal changes, the level switching signal output circuit switches the potential of the level switching signal in accordance with the feedback signal. Capacitive load drive circuit according to feature 1.

9. The level shift circuit described above is A gate driver that outputs a first gate signal and a second gate signal corresponding to the level switching signal, A first transistor whose conduction state between the drain terminal and the source terminal is controlled according to the first gate signal, A second transistor whose conduction state between the drain terminal and the source terminal is controlled according to the second gate signal, A bootstrap circuit receives the first amplified modulation signal and a level-shift voltage signal as inputs and outputs a bootstrap voltage signal obtained by shifting the reference potential of the first amplified modulation signal according to the level-shift voltage signal, It has, The bootstrap voltage signal is input to the drain terminal of the first transistor. The first amplified and modulated signal is input to the source terminal of the second transistor. The source terminal of the first transistor and the drain terminal of the second transistor are electrically connected at the connection point. The gate driver outputs a first gate signal that controls the drain terminal and source terminal of the first transistor to conduct when the level switching signal is at the first potential, and outputs a second gate signal that controls the drain terminal and source terminal of the second transistor to conduct when the level switching signal is at the second potential. The level shift circuit outputs the signal at the connection point as the second amplified modulated signal. A capacitive load drive circuit according to any one of claims 1 to 8.

10. The bootstrap circuit includes a bootstrap capacitor, one end of which is electrically connected to the drain terminal of the first transistor and the other end of which is electrically connected to the connection point. The level switching signal output circuit switches the potential of the output level switching signal according to the potential difference between one end and the other end of the bootstrap capacitor. Capacitive load drive circuit according to feature 9.

11. A control method for a capacitive load drive circuit that outputs drive signals to drive multiple capacitive loads, A modulation step that outputs a modulated signal obtained by modulating the base drive signal which is the basis of the drive signal, An amplification step which outputs a first amplified modulated signal obtained by amplifying the modulated signal, A level switching signal output process that outputs a level switching signal that changes between a first potential and a second potential, A level shifting step is performed in which, when the level switching signal is at the first potential, a signal obtained by shifting the reference potential of the first amplification modulation signal is output as the second amplification modulation signal, and when the level switching signal is at the second potential, the first amplification modulation signal is output as the second amplification modulation signal. A demodulation step which demodulates the second amplified modulated signal and outputs the drive signal, It has, In the level switching signal output step, the potential of the level switching signal is switched according to at least one of a waveform information signal including waveform information of the drive signal and a drive element number information signal including information on the number of drive elements of the plurality of capacitive loads driven by the drive signal. A method for controlling a capacitive load drive circuit, characterized by the features described above.

12. The drive element number information signal is generated based on a switching control signal that switches whether or not to supply the drive signal to the plurality of capacitive loads. A control method for a capacitive load drive circuit according to feature 11.

13. The aforementioned drive element number information signal is output at each dot formation cycle in which dots are formed on the medium by the liquid discharged by the driving of the plurality of capacitive loads. A control method for a capacitive load drive circuit according to feature 12.

14. In the level switching signal output process, When the voltage value of the signal waveform defined by the aforementioned drive signal rises and then becomes constant, the level switching signal of the first potential is output for a first period defined according to at least one of the waveform information signal and the drive element number information signal. A control method for a capacitive load drive circuit according to feature 11.

15. In the level switching signal output process, When the voltage value of the signal waveform defined by the aforementioned drive signal decreases and then becomes constant, the level switching signal of the second potential is output for a second period defined according to at least one of the waveform information signal and the drive element number information signal. A control method for a capacitive load drive circuit according to feature 11.

16. In the level switching signal output process, During the period in which the voltage value of the signal waveform defined by the base drive signal rises, the total time for which the level switching signal of the first potential is output is longer when there is p1 drive element than when there are p2 drive elements (which is less than p1). A control method for a capacitive load drive circuit according to feature 11.

17. In the level switching signal output process, During the period in which the voltage value of the signal waveform defined by the aforementioned drive signal decreases, the total time for which the level switching signal of the second potential is output is longer when there is one drive element than when there are two drive elements (q2). A control method for a capacitive load drive circuit according to feature 11.

18. In the level switching signal output process, During the period in which the voltage value of the signal waveform defined by the aforementioned drive signal changes, the potential of the level switching signal is switched in accordance with the feedback signal corresponding to the drive signal. A control method for a capacitive load drive circuit according to feature 11.

19. The capacitive load drive circuit is, A gate driver that outputs a first gate signal and a second gate signal corresponding to the level switching signal, A first transistor whose conduction state between the drain terminal and the source terminal is controlled according to the first gate signal, A second transistor whose conduction state between the drain terminal and the source terminal is controlled according to the second gate signal, A bootstrap circuit receives the first amplified modulation signal and a level-shift voltage signal as inputs and outputs a bootstrap voltage signal obtained by shifting the reference potential of the first amplified modulation signal according to the level-shift voltage signal, It has, The bootstrap voltage signal is input to the drain terminal of the first transistor. The first amplified and modulated signal is input to the source terminal of the second transistor. The source terminal of the first transistor and the drain terminal of the second transistor are electrically connected at the connection point. The gate driver outputs a first gate signal that controls the drain terminal and source terminal of the first transistor to conduct when the level switching signal is at the first potential, and outputs a second gate signal that controls the drain terminal and source terminal of the second transistor to conduct when the level switching signal is at the second potential. The signal at the aforementioned connection point is output as the second amplified modulated signal. A method for controlling a capacitive load drive circuit according to any one of claims 11 to 18.

20. The bootstrap circuit comprises a bootstrap capacitor, one end of which is electrically connected to the drain terminal of the first transistor and the other end of which is electrically connected to the connection point. In the level switching signal output step, the potential of the output level switching signal is switched according to the potential difference between one end and the other end of the bootstrap capacitor. A control method for a capacitive load drive circuit according to feature 19.

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