Semiconductor equipment

Abstract

To provide semiconductor devices with good electrical characteristics. To provide highly reliable semiconductor devices. To provide semiconductor devices with stable electrical characteristics. [Solution] The semiconductor device comprises a semiconductor layer, a gate insulating layer, a gate electrode, a first insulating layer, a second insulating layer, and a conductive layer. The gate insulating layer is in contact with the top and side surfaces of the semiconductor layer, and the gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer. The first insulating layer is made of an inorganic material and is in contact with the top surface of the gate insulating layer, as well as the top and side surfaces of the gate electrode. The gate insulating layer and the first insulating layer have a first opening in the region that overlaps with the semiconductor layer. The second insulating layer is made of an organic material and has a second opening inside the first opening. The second insulating layer is also in contact with the top and side surfaces of the first insulating layer, as well as the side surfaces of the gate insulating layer. The conductive layer is electrically connected to the semiconductor layer via the second opening.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a display device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving them, or methods for manufacturing them. A semiconductor device refers to any device that can function by utilizing semiconductor properties. [Background technology]

[0003] Oxide semiconductors using metal oxides are attracting attention as semiconductor materials applicable to transistors. For example, Patent Document 1 discloses a semiconductor device in which multiple oxide semiconductor layers are stacked, and in which the channel oxide semiconductor layer among the multiple oxide semiconductor layers contains indium and gallium, and the proportion of indium is greater than the proportion of gallium, thereby increasing the field-effect mobility (sometimes simply called mobility or μFE).

[0004] Metal oxides that can be used in semiconductor layers can be formed using methods such as sputtering, making them suitable for use in the semiconductor layers of transistors that constitute large-scale display devices. Furthermore, since it is possible to modify and utilize some of the production equipment for transistors using polycrystalline silicon or amorphous silicon, capital investment can be reduced. In addition, transistors using metal oxides have higher field-effect mobility compared to those using amorphous silicon, enabling the realization of high-performance display devices equipped with drive circuits. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. One aspect of the present invention aims to provide a highly reliable semiconductor device. One aspect of the present invention aims to provide a semiconductor device with stable electrical characteristics. One aspect of the present invention aims to provide a novel semiconductor device. One aspect of the present invention aims to provide a highly reliable display device. One aspect of the present invention aims to provide a novel display device.

[0007] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems can be identified from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0008] One aspect of the present invention is a semiconductor device comprising a semiconductor layer, a gate insulating layer, a gate electrode, a first insulating layer, a second insulating layer, and a conductive layer. The gate insulating layer is in contact with the upper and side surfaces of the semiconductor layer, and the gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer. The first insulating layer is made of an inorganic material and is in contact with the upper surface of the gate insulating layer, as well as the upper and side surfaces of the gate electrode. The gate insulating layer and the first insulating layer have a first opening in the region that overlaps with the semiconductor layer. The second insulating layer is made of an organic material and has a second opening inside the first opening. The second insulating layer is also in contact with the upper and side surfaces of the first insulating layer, as well as the side surfaces of the gate insulating layer. The conductive layer is electrically connected to the semiconductor layer via the second opening.

[0009] One aspect of the present invention is a semiconductor device comprising a semiconductor layer, a gate insulating layer, a gate electrode, a first insulating layer, a second insulating layer, and a conductive layer. The gate insulating layer is in contact with the upper surface of the semiconductor layer, and the gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer. The first insulating layer is made of an inorganic material and is in contact with the upper and side surfaces of the semiconductor layer, the side surfaces of the gate insulating layer, and the upper and side surfaces of the gate electrode. The first insulating layer has a first opening in the region that overlaps with the semiconductor layer. The second insulating layer is made of an organic material and has a second opening inside the first opening. The second insulating layer is also in contact with the upper and side surfaces of the first insulating layer. The conductive layer is electrically connected to the semiconductor layer via the second opening.

[0010] In the semiconductor device described above, the angle formed by the side surface of the second insulating layer and the upper surface of the semiconductor layer is preferably 45 degrees or more and less than 90 degrees.

[0011] In the semiconductor device described above, the second insulating layer preferably has a region in contact with the upper surface of the semiconductor layer. Furthermore, the width of the region is preferably 50 nm or more and 3000 nm or less.

[0012] In the aforementioned semiconductor device, the transmittance of the second insulating layer in the wavelength range of 200 nm to 350 nm is preferably 0.01% to 70%.

[0013] In the aforementioned semiconductor device, the transmittance of the organic material in the wavelength range of 200 nm to 350 nm is preferably 0.01% to 70%.

[0014] In the aforementioned semiconductor device, the organic material preferably comprises one or more of the following: acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, novolac resin, and precursors of these resins.

[0015] In the aforementioned semiconductor device, it is preferable to have a third insulating layer. The third insulating layer is preferably made of an inorganic material and has a third opening inside the second opening. Furthermore, it is preferable that the third insulating layer is in contact with the upper surface and side surface of the second insulating layer. [Effects of the Invention]

[0016] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, a highly reliable semiconductor device can be provided. Or, a semiconductor device with stable electrical characteristics can be provided. Or, a novel semiconductor device can be provided. Or, a highly reliable display device can be provided. Or, a novel display device can be provided.

[0017] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawing]

[0018] [Figure 1] Figures 1A to 1C show examples of transistor configurations. [Figure 2] Figure 2 shows an example of a transistor configuration. [Figure 3] Figures 3A and 3B show examples of transistor configurations. [Figure 4] Figures 4A and 4B show examples of transistor configurations. [Figure 5] Figures 5A and 5B show comparative examples. [Figure 6] Figures 6A and 6B show examples of transistor configurations. [Figure 7] Figure 7 shows an example of a transistor configuration. [Figure 8] Figures 8A to 8C show examples of transistor configurations. [Figure 9] Figures 9A and 9B show examples of transistor configurations. [Figure 10] Figure 10 shows an example of a transistor configuration. [Figure 11] Figures 11A and 11B show examples of transistor configurations. [Figure 12] Figures 12A and 12B show examples of transistor configurations. [Figure 13] Figures 13A to 13C show examples of transistor configurations. [Figure 14] Figures 14A and 14B show examples of transistor configurations. [Figure 15] Figures 15A and 15B show examples of transistor configurations. [Figure 16] Figures 16A to 16C show examples of transistor configurations. [Figure 17] Figures 17A and 17B show examples of transistor configurations. [Figure 18] Figures 18A to 18C show examples of transistor configurations. [Figure 19] Figure 19 shows an example of a transistor configuration. [Figure 20] Figures 20A and 20B show examples of transistor configurations. [Figure 21] Figures 21A to 21D show the method for fabricating a transistor. [Figure 22] Figures 22A to 22D illustrate the method for fabricating a transistor. [Figure 23] Figures 23A to 23C illustrate the method for fabricating a transistor. [Figure 24] Figures 24A to 24C illustrate the method for fabricating a transistor. [Figure 25] Figures 25A to 25D illustrate the method for fabricating a transistor. [Figure 26] Figures 26A to 26C illustrate the method for fabricating a transistor. [Figure 27]Figures 27A to 27C illustrate the method for fabricating a transistor. [Figure 28] Figures 28A to 28C illustrate the method for fabricating a transistor. [Figure 29] Figures 29A and 29B illustrate the method for fabricating a transistor. [Figure 30] Figures 30A to 30C illustrate the method for fabricating a transistor. [Figure 31] Figures 31A to 31C illustrate the method for fabricating a transistor. [Figure 32] Figures 32A to 32C are top views of the display device. [Figure 33] Figure 33 is a cross-sectional view of the display device. [Figure 34] Figure 34 is a cross-sectional view of the display device. [Figure 35] Figure 35 is a cross-sectional view of the display device. [Figure 36] Figure 36 is a cross-sectional view of the display device. [Figure 37] Figures 37A and 37B show examples of display device configurations. [Figure 38] Figure 38A is a block diagram of the display device. Figures 38B and 38C are circuit diagrams of the display device. [Figure 39] Figures 39A, 39C, and 39D are circuit diagrams of the display device. Figure 39B is a timing chart. [Figure 40] Figures 40A and 40B show examples of the configuration of a display module. [Figure 41] Figures 41A and 41B show examples of the configuration of electronic equipment. [Figure 42] Figures 42A to 42E show examples of the configuration of electronic equipment. [Figure 43] Figures 43A to 43G show examples of electronic device configurations. [Figure 44] Figures 44A to 44D show examples of electronic device configurations. [Figure 45]Figures 45A to 45C are schematic diagrams showing the structure of the sample according to the example. [Figure 46] Figure 46 shows the resistance of the sample according to the example. [Figure 47] Figure 47 shows the transmittance of the sample according to the example. [Figure 48] Figure 48 shows the transmittance of the sample according to the example. [Figure 49] Figures 49A to 49C show the structure of the sample according to the example. [Figure 50] Figure 50 shows the threshold voltage of the transistor according to the embodiment. [Figure 51] Figure 51 shows the Id-Vg characteristics of a transistor according to an embodiment. [Figure 52] Figures 52A and 52B are cross-sectional STEM images of the sample according to the example. [Figure 53] Figures 53A and 53B are cross-sectional STEM images of the sample according to the example. [Figure 54] Figures 54A and 54B are cross-sectional STEM images of the sample according to the example. [Figure 55] Figures 55A and 55B show the transmittance of the samples according to the examples. [Figure 56] Figure 56 shows the resistance of the sample according to the example. [Figure 57] Figure 57 shows the resistance of the sample according to the example. [Figure 58] Figure 58 shows the resistance of the sample according to the example. [Modes for carrying out the invention]

[0019] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope thereof. Accordingly, the present invention shall not be construed as being limited to the contents of the following embodiments.

[0020] In the figures described herein, the size of each component, the thickness of the layers, or the area may be exaggerated for clarity.

[0021] The ordinal numbers "1st," "2nd," and "3rd" used in this specification are added to avoid confusion of constituent elements and do not imply any numerical limitation.

[0022] In this specification, terms such as "above" and "below" are used for convenience to explain the positional relationships between components with reference to the drawings. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in the specification and can be appropriately rephrased depending on the situation.

[0023] In this specification, the source and drain functions of a transistor may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. Therefore, the terms source and drain may be used interchangeably.

[0024] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region by the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the ON state. The channel width direction refers to the direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and channel width direction may not be uniquely determined.

[0025] In this specification, "electrically connected" includes cases where connections are made via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements with various functions.

[0026] In this specification, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" may be interchangeable with the term "conductive film." The term "insulating layer" may be interchangeable with the term "insulating film."

[0027] In this specification, unless otherwise specified, off-current refers to the drain current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state in an n-channel transistor is defined as the voltage V between the gate and source. gs The threshold voltage V th Lower than (in p-channel transistors, V th This refers to a state that is higher than [a certain value].

[0028] In this specification, a display panel, which is one form of a display device, has the function of displaying (outputting) images or the like on its display surface. Therefore, a display panel is one form of an output device.

[0029] In this specification, a display panel on which a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) is attached, or on which an IC (Integrated Circuit) is mounted on the circuit board using a COG (Chip On Glass) method, may be referred to as a display panel module, display module, or simply a display panel.

[0030] In this specification, a touch panel, which is one form of a display device, has the function of displaying images or the like on its display surface, and the function of a touch sensor that detects when an object to be detected touches, presses, or approaches the display surface. Therefore, a touch panel is one form of an input / output device. Examples of objects to be detected include fingers and styluses.

[0031] A touch panel can also be called, for example, a display panel (or display device) with a touch sensor, or a display panel (or display device) with touch sensor functionality. A touch panel can also have a configuration comprising a display panel and a touch sensor panel. Alternatively, the display panel may have a touch sensor function located inside or on its surface.

[0032] In this specification, a touch panel circuit board on which one or more connectors or ICs are mounted may be referred to as a touch panel module, display module, or simply a touch panel.

[0033] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention and a method for manufacturing the same. In particular, this embodiment describes a transistor using an oxide semiconductor in the semiconductor layer where the channel is formed, as an example of a semiconductor device.

[0034] One aspect of the present invention is a transistor having a semiconductor layer, a gate insulating layer, a gate electrode, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer is preferably composed of a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. The gate insulating layer is in contact with the top and side surfaces of the semiconductor layer, and the gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer.

[0035] The first insulating layer preferably has an inorganic material and is in contact with the upper surface of the gate insulating layer, as well as the upper and side surfaces of the gate electrode. The gate insulating layer and the first insulating layer also have a first opening in the region that overlaps with the semiconductor layer.

[0036] The second insulating layer preferably has a second opening inside the first opening. Furthermore, the second insulating layer is in contact with the top and side surfaces of the first insulating layer, as well as the side surfaces of the gate insulating layer. In other words, the second insulating layer is provided so as to cover the first insulating layer and the gate insulating layer. The second insulating layer preferably has a low transmittance of ultraviolet light (also called ultraviolet light). For example, an organic material can be suitably used for the second insulating layer.

[0037] A conductive layer, functioning as a source electrode or drain electrode, is electrically connected to the semiconductor layer through a second opening. The conductive layer has a region in contact with the second insulating layer. On the other hand, it is preferable that the conductive layer does not have a region in contact with either the first insulating layer or the gate insulating layer.

[0038] In this process, ultraviolet light may be generated within the deposition apparatus when a conductive film is formed to form the conductive layer. If this ultraviolet light reaches the channel formation region, it may adversely affect the electrical characteristics and reliability of the transistor. In one embodiment of the present invention, the amount of ultraviolet light reaching the channel formation region can be reduced by covering the first insulating layer and the gate insulating layer with a second insulating layer that has low ultraviolet light transmittance. Therefore, a transistor with good electrical characteristics and reliability can be obtained.

[0039] The following section will describe more specific examples of transistor configurations.

[0040] <Configuration Example 1> Figure 1A is a top view of transistor 100, Figure 1B corresponds to a cross-sectional view of the section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 1C corresponds to a cross-sectional view of the section along the dashed-dotted line B1-B2 shown in Figure 1A. Note that in Figure 1A, some components of transistor 100 (such as the gate insulating layer) are omitted from the illustration. The direction of the dashed-dotted line A1-A2 corresponds to the channel length direction, and the direction of the dashed-dotted line B1-B2 corresponds to the channel width direction. In subsequent drawings, as in Figure 1A, some components of the transistor's top view will also be omitted from the illustration. Figure 2 shows an enlarged view of the region P enclosed by the dashed-dotted line in Figure 1B.

[0041] The transistor 100 is provided on a substrate 102 and has a semiconductor layer 108, an insulating layer 110, a conductive layer 112, an insulating layer 118, an insulating layer 130, etc. The island-shaped semiconductor layer 108 is provided on the substrate 102. The insulating layer 110 is provided in contact with the upper surface of the substrate 102 and the upper and side surfaces of the semiconductor layer 108. The conductive layer 112 is provided on the insulating layer 110 and has a region that overlaps with the semiconductor layer 108. The insulating layer 110 functions as a gate insulating layer. The conductive layer 112 functions as a gate electrode. The transistor 100 is a so-called top-gate type transistor in which the gate electrode is provided on the semiconductor layer 108.

[0042] The semiconductor layer 108 contains a metal oxide exhibiting semiconductor properties (hereinafter also referred to as an oxide semiconductor). Preferably, the semiconductor layer 108 contains at least indium and oxygen. By including an indium oxide in the semiconductor layer 108, carrier mobility can be increased. For example, a transistor capable of carrying a larger current than one using amorphous silicon can be realized.

[0043] The region of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel-forming region. Furthermore, it is preferable that the semiconductor layer 108 has a pair of low-resistance regions 108N flanking the channel-forming region. These low-resistance regions 108N have a higher carrier concentration than the channel-forming region and function as a source region and a drain region.

[0044] The low-resistance region 10⁸N can also be described as a region with lower resistance than the channel-forming region, a region with a high carrier concentration, a region with a large oxygen deficiency, a region with a high hydrogen concentration, a region with a high impurity concentration, or an n-type region.

[0045] As shown in Figures 1A, 1B, 1C, and 2, the insulating layer 118 is provided covering the upper surface of the insulating layer 110 and the upper and side surfaces of the conductive layer 112. The insulating layer 110 and the insulating layer 118 have openings 141a and 141b in the region overlapping with the low-resistance region 108N.

[0046] The insulating layer 118 functions as a protective layer to protect the transistor 100. The insulating layer 118 can preferably be made of an inorganic material. Suitable inorganic materials include, for example, oxides or nitrides. More specifically, the insulating layer 118 can be made of one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon oxide nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. The insulating layer 118 may also be made by laminating the aforementioned materials.

[0047] In this specification, "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0048] In this specification, when oxidogenic nitrides and nitride oxides containing the same elements are described, oxidogenic nitrides include materials that have a higher oxygen content and a lower nitrogen content than nitride oxides, or both. Similarly, nitride oxides include materials that have a lower oxygen content and a higher nitrogen content than oxidogenic nitrides, or both. For example, when silicon oxidogenic nitride and silicon nitride oxides are described, silicon oxidogenic nitrides include materials that have a higher oxygen content and a lower nitrogen content than silicon nitride oxides. Similarly, silicon nitride oxides include materials that have a lower oxygen content and a higher nitrogen content than silicon oxidogenic nitride oxides.

[0049] The insulating layer 118 can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma-enhanced CVD (PECVD) and thermal CVD. One type of thermal CVD is metal-organic CVD (MOCVD).

[0050] In particular, the insulating layer 118 is preferably formed by the PECVD method.

[0051] Figures 1A, 1B, 1C, and 2 show examples where the top surface shape of the insulating layer 110 and the top surface shape of the insulating layer 118 are roughly the same.

[0052] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, too, it is said that the "top surface shapes are approximately matching."

[0053] The insulating layer 130 is provided covering the top and side surfaces of the insulating layer 118, as well as the side surfaces of the insulating layer 110. The insulating layer 130 functions as a protective layer to protect the transistor 100. The insulating layer 130 has openings 143a and 143b. Opening 143a is located inside opening 141a, and opening 143b is located inside opening 141b. Furthermore, the insulating layer 130 may have a region in contact with the top surface of the semiconductor layer 108. It can also be said that the insulating layer 130 has an edge on the semiconductor layer 108.

[0054] The transistor 100 may have conductive layers 120a and 120b on the insulating layer 130. Conductive layers 120a and 120b function as source electrodes or drain electrodes. Conductive layers 120a and 120b are each electrically connected to a low-resistance region 108N through an opening 143a or opening 143b provided in the insulating layer 130. Conductive layers 120a and 120b each have a region in contact with the insulating layer 130. Furthermore, conductive layers 120a and 120b each do not have a region in contact with the insulating layer 110, nor do they have a region in contact with the insulating layer 118.

[0055] Here, we will explain the deposition of the conductive films that will become the conductive layer 120a and conductive layer 120b. When depositing the conductive films that will become the conductive layer 120a and conductive layer 120b on the insulating layer 130, ultraviolet light is generated inside the deposition apparatus, and when this ultraviolet light reaches the semiconductor layer 108, oxygen vacancies V are created in the semiconductor layer 108. O In some cases, a vacancy may be formed. Also, if hydrogen is present in the semiconductor layer 108, an oxygen vacancy V may form. O A state in which hydrogen is present (hereinafter, V OThere may be a case where it is formed (denoted as H). V O H becomes a carrier generation source and may have an adverse effect on the electrical characteristics and reliability of the transistor. In particular, oxygen deficiency V in the channel formation region O , and V O It is preferable that H is small.

[0056] In addition, an apparatus that generates ultraviolet light during processing includes, for example, an apparatus that generates plasma in a processing chamber. Specifically, examples of an apparatus that generates ultraviolet light during processing include a dry etching apparatus, a sputtering apparatus, a plasma CVD apparatus, and the like.

[0057] The insulating layer 130 preferably has a low transmittance of ultraviolet light. By covering the insulating layer 118 and the insulating layer 110 with the insulating layer 130 having a low transmittance of ultraviolet light, the amount of ultraviolet light reaching the semiconductor layer 108 can be reduced. Therefore, oxygen deficiency V in the channel formation region O , and V O The increase of H can be suppressed, and a transistor with good electrical characteristics and reliability can be obtained.

[0058] In this specification and the like, ultraviolet light refers to light having one or more peaks in the wavelength range of 200 nm or more and 400 nm or less.

[0059] The insulating layer 130 preferably has a material with a low transmittance of ultraviolet light. For example, the insulating layer 130 can preferably use a material that absorbs ultraviolet light.

[0060] The insulating layer 130 can preferably be made of an organic material. It is particularly preferable to use an organic material with low ultraviolet light transmittance for the insulating layer 130. For example, the insulating layer 130 can be made of one or more photocurable resins or thermosetting resins. More specifically, the insulating layer 130 can be made of one or more acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, novolac resins, and precursors of these resins. The insulating layer 130 may be made by laminating the aforementioned multiple materials. Furthermore, the insulating layer 130 may have a laminated structure of the aforementioned organic material and an inorganic material.

[0061] Furthermore, since a lower ultraviolet light transmittance is preferable for the material used in the insulating layer 130, there is no need to specifically set a lower limit for the transmittance. However, if a lower limit is set, for example, the ultraviolet light transmittance of the material used in the insulating layer 130 is preferably 0.01% or higher.

[0062] The transmittance of the material used for the insulating layer 130 in the wavelength range of 200 nm to 400 nm is preferably 0.01% to 80%, more preferably 0.01% to 75%, and even more preferably 0.01% to 70%.

[0063] Furthermore, the transmittance of the material used for the insulating layer 130 in the wavelength range of 200 nm to 350 nm is preferably 0.01% to 70%, more preferably 0.01% to 60%, more preferably 0.01% to 50%, more preferably 0.01% to 40%, more preferably 0.01% to 30%, more preferably 0.01% to 20%, and more preferably 0.01% to 10%.

[0064] If the insulating layer 130 has a laminated structure, it is preferable that the transmittance of at least one of the constituent layers is within the range described above.

[0065] Furthermore, since the transmittance decreases as the thickness of the material increases, in this specification, the transmittance of the material at a thickness of 2 μm is used. If the transmittance at a thickness of less than 2 μm is a certain value, then the transmittance at a thickness of 2 μm can be said to be less than or equal to that value.

[0066] Enlarged views of openings 141a and 143a, and their vicinity, are shown in Figures 3A and 3B. Figure 3A is a top view, and Figure 3B corresponds to a cross-sectional view of the section along the dashed line D1-D2 shown in Figure 3A. To avoid making the drawings cluttered, hatching has been omitted in Figure 3B. Detailed explanations of openings 141b and 143b are omitted as they can be found in the descriptions of openings 141a and 143a.

[0067] In any straight line crossing the openings 141a and 143a, the width 143W at the bottom of the opening 143a is preferably smaller than the width 141W at the bottom of the opening 141a. Furthermore, in the low-resistance region 108N, the width 151 of the region in contact with the insulating layer 130 is preferably 50 nm to 3000 nm, more preferably 100 nm to 2500 nm, more preferably 200 nm to 2000 nm, more preferably 300 nm to 1500 nm, more preferably 300 nm to 1200 nm, more preferably 300 nm to 1000 nm, more preferably 400 nm to 1000 nm, more preferably 400 nm to 800 nm, and more preferably 450 nm to 800 nm.

[0068] If the width value 151 is too small, the effect of reducing ultraviolet light will be insufficient, which may worsen the electrical characteristics and reliability of transistor 100. On the other hand, if the width value 151 is too large, the size of transistor 100 may increase. By setting the width value 151 within the aforementioned range, it is possible to create a miniaturized transistor with good electrical characteristics and reliability. Furthermore, the width value 151 should be determined considering the alignment accuracy of the equipment used to form the insulating layer 130.

[0069] Furthermore, by using a material with low ultraviolet light transmittance for the insulating layer 130, the amount of ultraviolet light reaching the semiconductor layer 108 can be reduced even if the width 151 is small. If the width 151 can be increased, a material with high ultraviolet light transmittance may be used for the insulating layer 130. Also, the width 151 may be determined according to the transmittance of the material used for the insulating layer 130. The material used for the insulating layer 130 may be determined according to the width 151.

[0070] The transmittance of the insulating layer 130 in the wavelength range of 200 nm to 400 nm is preferably 0.01% to 80%, more preferably 0.01% to 75%, and even more preferably 0.01% to 70%.

[0071] Furthermore, the transmittance of the insulating layer 130 in the wavelength range of 200 nm to 350 nm is preferably 0.01% to 70%, more preferably 0.01% to 60%, more preferably 0.01% to 50%, more preferably 0.01% to 40%, more preferably 0.01% to 30%, more preferably 0.01% to 20%, and more preferably 0.01% to 10%.

[0072] Since it is preferable that the amount of ultraviolet light transmitted through the insulating layer 130 be as small as possible, it is preferable that the transmittance in the region where the thickness of the insulating layer 130 is minimized in the aperture 141a is within the aforementioned range. Similarly, it is preferable that the transmittance in the region where the thickness of the insulating layer 130 is minimized in the aperture 141b is within the aforementioned range.

[0073] The edges of the insulating layer 110 are preferably tapered. Specifically, the angle θ1 at the edge of the insulating layer 110 is preferably less than 90 degrees. The angle θ1 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and 85 degrees or less, more preferably 55 degrees or more and 85 degrees or less, more preferably 60 degrees or more and 85 degrees or less, more preferably 60 degrees or more and 80 degrees or less, more preferably 65 degrees or more and 80 degrees or less, and more preferably 70 degrees or more and 80 degrees or less. By setting the angle θ1 at the edge of the insulating layer 110 within the above range, the step coverage of the layer formed on the insulating layer 110 (for example, insulating layer 130) is improved, and defects such as step breakage or porosity in the layer can be suppressed.

[0074] Similarly, the edges of the insulating layer 130 are preferably tapered. Specifically, the angle θ2 at the edge of the insulating layer 130 is preferably less than 90 degrees. The angle θ2 is preferably 45 degrees or more and less than 90 degrees, more preferably 50 degrees or more and 85 degrees or less, more preferably 55 degrees or more and 85 degrees or less, more preferably 60 degrees or more and 85 degrees or less, more preferably 60 degrees or more and 80 degrees or less, more preferably 65 degrees or more and 80 degrees or less, and more preferably 70 degrees or more and 80 degrees or less. By setting the angle θ2 at the edge of the insulating layer 130 within the above range, the step coverage of the layers formed on the insulating layer 130 (for example, conductive layer 120a and conductive layer 120b) is improved, and defects such as step breaks or porosity in the layers can be suppressed.

[0075] In this specification, the term "corner at the end of a layer" refers to the angle formed between the side surface of the layer and the surface on which the layer is formed.

[0076] Here, we will explain the effect of ultraviolet light on the semiconductor layer 108.

[0077] Figure 4A shows a cross-sectional view of transistor 100 before the formation of conductive layers 120a and 120b. Figure 4B shows an enlarged view of the region Q enclosed by the dashed line in Figure 4A. Figure 4B schematically shows how ultraviolet light generated in the deposition apparatus when forming the conductive films that will become conductive layers 120a and 120b enters apertures 141a and 143a, represented by white arrows.

[0078] As shown in Figure 4B, when ultraviolet light enters the aperture 143a, it is absorbed by the insulating layer 130 upon contact with it, preventing it from reaching the semiconductor layer 108. Therefore, only ultraviolet light directly incident on the region of the semiconductor layer 108 exposed in the aperture 143a reaches the semiconductor layer 108, thus reducing the amount of ultraviolet light reaching the semiconductor layer 108.

[0079] Comparative transistors are shown in Figures 5A and 5B. Figure 5A is a cross-sectional view of the comparative transistor. Figure 5B shows an enlarged view of the region R enclosed by the dashed line in Figure 5A.

[0080] In the comparative example transistors shown in Figures 5A and 5B, the openings 143a and 143b of the insulating layer 130 are provided on the insulating layer 118. Unlike the transistor of one embodiment of the present invention, the insulating layer 130 does not cover the sides of the insulating layer 110 and the insulating layer 118, and the sides of the insulating layer 110 and the insulating layer 118 are exposed at the openings 143a and 143b.

[0081] As shown in Figure 5B, ultraviolet light incident in the aperture 141a passes through the insulating layer 110 or the insulating layer 118. Furthermore, this ultraviolet light may reach the semiconductor layer 108 due to refraction at the interface between the insulating layer 110, the insulating layer 118, or the semiconductor layer 108. Therefore, the transistor of the comparative example has a greater amount of ultraviolet light reaching the semiconductor layer 108 than the transistor of one embodiment of the present invention.

[0082] In one aspect of the present invention, the transistor 100 has an insulating layer 130 that covers the sides of the insulating layer 110 and the sides of the insulating layer 118, thereby reducing the amount of ultraviolet light reaching the semiconductor layer 108, and thus enabling a transistor with good electrical characteristics and reliability.

[0083] Figure 1A and others show an example where the width 151 is approximately the same value in openings 143a and 143b, but the present invention is not limited to this. The width 151 may have different values ​​in opening 143a. Similarly, the width 151 may have different values ​​in opening 143b.

[0084] Enlarged views of openings 141a and 143a, and their vicinity, are shown in Figures 6A and 6B. Figure 6A is a top view, and Figure 6B corresponds to a cross-sectional view of the section along the dashed line D1-D2 shown in Figure 6A. Note that hatching has been omitted in Figure 6B to avoid making the drawing too complex.

[0085] As shown in Figures 6A and 6B, the width 151 in opening 143a may have different values. It is preferable that the minimum width 151 in openings 143a and 143b is within the aforementioned range. Furthermore, the width 151 may differ between openings 143a and 143b.

[0086] Figure 3B shows an example where the angle θ1 at the end of the insulating layer 110 and the angle θ2 at the end of the insulating layer 130 are approximately the same value, but the present invention is not limited to this. The angles θ1 and θ2 may have different values.

[0087] Enlarged views of openings 141a and 143a, and their vicinity, are shown in Figure 7. A top view can be found in Figure 3A. Figure 7 corresponds to a cross-sectional view of the section along the dashed line D1-D2 shown in Figure 3A. Note that hatching has been omitted in Figure 7 to avoid cluttering the drawing.

[0088] As shown in Figure 7, the angle θ1 at the end of the insulating layer 110 and the angle θ2 at the end of the insulating layer 130 may have different values. For example, angle θ2 can be set to a larger value than angle θ1. By setting angle θ2 to a larger value than angle θ1, the step coverage of the layer formed on the insulating layer 130 (for example, the conductive layer 120a) is improved, and defects such as step breaks or porosity in the layer can be suppressed.

[0089] Although Figure 1A and other figures show an example where the shape of openings 141a, 141b, 143a, and 143b in plan view is a rectangle with arc-shaped corners, the present invention is not limited to this. The shapes of openings 141a, 141b, 143a, and 143b may be rectangles, polygons, circles, or ellipses. Furthermore, the shapes of openings 141a, 141b, 143a, and 143b may be a combination of curves and straight lines.

[0090] The crystallinity of the semiconductor material used in the semiconductor layer 108 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) may be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0091] The semiconductor layer 108 preferably contains a metal oxide (also called an oxide semiconductor). Alternatively, the semiconductor layer 108 may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystal silicon).

[0092] When a metal oxide is used as the semiconductor layer 108, it is preferable that it contains, for example, indium, element M (where element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin.

[0093] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (hereinafter also referred to as IGZO) as the semiconductor layer 108.

[0094] As the semiconductor layer 108, in addition to indium, gallium, and zinc, an oxide containing one or more of the following can be used: aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. In particular, using an oxide containing one or more of tin, aluminum, or silicon in addition to indium, gallium, and zinc as the semiconductor layer is preferable because it can result in a transistor with high field-effect mobility.

[0095] When the semiconductor layer 108 is an In-M-Zn oxide, it is preferable that the atomic ratio of In to element M is 1 or greater. Specifically, examples include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:8, etc. Furthermore, if element M includes two or more elements as described above, the proportion of M in the atomic ratio shall correspond to the sum of the atomic numbers of those two or more metallic elements.

[0096] Furthermore, when the atomic ratio is stated as In:M:Zn=4:2:3 or nearby, it includes the case where, when In is set to 4, M is between 1 and 3 and Zn is between 2 and 4. Also, when the atomic ratio is stated as In:M:Zn=5:1:6 or nearby, it includes the case where, when In is set to 5, M is greater than 0.1 and 2 or less and Zn is between 5 and 7. Also, when the atomic ratio is stated as In:M:Zn=1:1:1 or nearby, it includes the case where, when In is set to 1, M is greater than 0.1 and 2 or less and Zn is greater than 0.1 and 2 or less.

[0097] The composition of the semiconductor layer 108 will now be described. Preferably, the semiconductor layer 108 contains at least indium and a metal oxide containing oxygen. In addition, the semiconductor layer 108 may also contain zinc. Furthermore, the semiconductor layer 108 may contain gallium.

[0098] Here, the composition of the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100. For example, by increasing the indium content in the semiconductor layer 108, carrier mobility is improved, and a transistor with high field-effect mobility can be realized.

[0099] One indicator used to evaluate the reliability of a transistor is the gate bias stress test (GBT), which involves applying an electric field to the gate and holding the transistor in that state. Among these, a test in which a positive potential is applied to the gate relative to the source and drain potentials and the transistor is held at a high temperature is called the PBTS (Positive Bias Temperature Stress) test, and a test in which a negative potential is applied to the gate and the transistor is held at a high temperature is called the NBTS (Negative Bias Temperature Stress) test. Furthermore, PBTS and NBTS tests performed under illumination, such as with white LED light, are called PBTIS (Positive Bias Temperature Illumination Stress) and NBTIS (Negative Bias Temperature Illumination Stress) tests, respectively.

[0100] In particular, in n-type transistors using oxide semiconductors, a positive potential is applied to the gate when the transistor is turned on (current is flowing), so the amount of variation in the threshold voltage during PBTS testing is one of the important items to focus on as an indicator of transistor reliability.

[0101] Here, by using a metal oxide film that does not contain gallium or has a low gallium content as the composition of the semiconductor layer 108, the fluctuation in the threshold voltage in the PBTS test can be reduced. Furthermore, if gallium is included, it is preferable that the gallium content of the semiconductor layer 108 be less than the indium content. This makes it possible to realize a highly reliable transistor.

[0102] One factor contributing to the fluctuation in threshold voltage during PBTS testing is the presence of defect levels at or near the interface between the semiconductor layer and the gate insulating layer. The higher the density of defect levels, the more pronounced the degradation in PBTS testing becomes. The generation of these defect levels can be suppressed by reducing the gallium content in the portion of the semiconductor layer that contacts the gate insulating layer.

[0103] One possible reason why PBTS degradation can be suppressed by omitting gallium or reducing its gallium content is as follows: The gallium contained in the semiconductor layer 108 has a property that attracts oxygen more readily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that at the interface between the metal oxide film containing a large amount of gallium and the insulating layer 110 containing oxide, the gallium combines with excess oxygen in the insulating layer 110, making it easier to create carrier (electron) trap sites. Therefore, when a positive potential is applied to the gate, it is thought that the threshold voltage fluctuates as carriers are trapped at the interface between the semiconductor layer and the gate insulating layer.

[0104] More specifically, when an In-Ga-Zn oxide is used for the semiconductor layer 108, a metal oxide film in which the atomic ratio of In is greater than that of Ga can be applied to the semiconductor layer 108. Furthermore, it is more preferable to use a metal oxide film in which the atomic ratio of Zn is greater than that of Ga. In other words, it is preferable to apply a metal oxide film to the semiconductor layer 108 that satisfies the conditions that the atomic ratio of metal elements is In > Ga and Zn > Ga.

[0105] For example, as the semiconductor layer 108, a metal oxide film can be used in which the atomic ratio of metal elements is In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, or close to these values.

[0106] When a metal oxide film containing indium and gallium is used as the semiconductor layer 108, the ratio of the number of gallium atoms to the number of metal element atoms contained in the metal oxide (atomic ratio) can be greater than 0 and less than 50%, preferably 0.05% to 30%, more preferably 0.1% to 15%, and more preferably 0.1% to 5%. Furthermore, including gallium in the semiconductor layer 108 has the effect of reducing the likelihood of oxygen deficiencies.

[0107] A gallium-free metal oxide film may be applied to the semiconductor layer 108. For example, an In-Zn oxide can be applied to the semiconductor layer 108. In this case, increasing the ratio of In atoms to the total number of metal elements in the metal oxide film can increase the field-effect mobility of the transistor. On the other hand, increasing the ratio of Zn atoms to the total number of metal elements in the metal oxide results in a highly crystalline metal oxide film, which suppresses fluctuations in the electrical characteristics of the transistor and improves reliability. Alternatively, a gallium- and zinc-free metal oxide film, such as indium oxide, may be applied to the semiconductor layer 108. By using a metal oxide film that contains no gallium at all, fluctuations in the threshold voltage, particularly in PBTS testing, can be made extremely small.

[0108] For example, an oxide containing indium and zinc can be used for the semiconductor layer 108. In this case, a metal oxide film can be used with an atomic ratio of metal elements of, for example, In:Zn=2:3, In:Zn=4:1, or close to these values.

[0109] In one embodiment of the present invention, a transistor 100 is made in which a metal oxide film with a low gallium content or a metal oxide film without gallium is applied to the semiconductor layer 108, and furthermore, an insulating layer 110 in contact with the upper surface of the semiconductor layer 108 is made of a film formed by a film deposition method that reduces damage to the semiconductor layer 108. As a result, the defect level density at the interface between the semiconductor layer 108 and the insulating layer 110 is reduced, making the transistor 100 highly reliable.

[0110] Although gallium has been used as a representative example here, the method can also be applied when element M (where M is one or more elements selected from aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) is used instead of gallium. In particular, it is preferable that M be one or more elements selected from gallium, aluminum, yttrium, or tin.

[0111] In particular, it is preferable to apply a metal oxide film to the semiconductor layer 108 in which the atomic ratio of In is greater than that of element M. It is also preferable to apply a metal oxide film in which the atomic ratio of Zn is greater than that of element M.

[0112] It is preferable to use a crystalline metal oxide film for the semiconductor layer 108. For example, metal oxide films having structures such as CAAC (c-axis aligned crystal), nc (nano crystal), polycrystalline, or microcrystalline structures, as described later, can be used. By using a crystalline metal oxide film for the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0113] The higher the crystallinity of the semiconductor layer 108, the lower the defect level density in the film. On the other hand, by using a metal oxide film with low crystallinity, it is possible to realize a transistor that can carry a large current.

[0114] When depositing a metal oxide film by sputtering, a higher substrate temperature (stage temperature) during deposition results in a more crystalline metal oxide film. Furthermore, a higher ratio of oxygen gas flow rate to the total deposition gas flow rate (also known as the oxygen flow rate ratio) also results in a more crystalline metal oxide film. Thus, the crystallinity of the deposited metal oxide film can be controlled by the substrate temperature and the oxygen flow rate ratio in the deposition gas.

[0115] The low-resistance region 108N of the semiconductor layer 108 may contain impurity elements. Examples of such impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, or noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. The low-resistance region 108N is particularly preferably composed of boron or phosphorus. It may also contain two or more of these elements.

[0116] The process of adding impurities to the low-resistance region 108N can be carried out via the insulating layer 110, using the conductive layer 112 as a mask.

[0117] In the low resistance region of 10⁸N, the impurity concentration is 1 × 10⁻⁶. 19 atoms / cm 3 The above is 1 x 10 23 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The above 5 x 10 22 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 The above is 1 x 10 22 atoms / cm 3 Preferably, the region includes the following:

[0118] The concentration of impurities in the low-resistance region 10⁸N can be analyzed by analytical methods such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When using XPS analysis, the concentration distribution in the depth direction can be analyzed by combining ion sputtering from the surface or back side with XPS analysis.

[0119] In the low-resistance region 108N, it is preferable that impurity elements exist in an oxidized state. For example, it is preferable to use easily oxidizable elements such as boron, phosphorus, magnesium, aluminum, and silicon as impurity elements. Since such easily oxidizable elements can exist stably in an oxidized state by bonding with oxygen in the semiconductor layer 108, their desorption is suppressed even when high temperatures (e.g., 400°C or higher, 600°C or higher, or 800°C or higher) are applied in later processes. In addition, the impurity elements remove oxygen from the semiconductor layer 108, creating many oxygen vacancies in the low-resistance region 108N. These oxygen vacancies combine with hydrogen in the film to become a carrier source, so the low-resistance region 108N becomes an extremely low-resistance state.

[0120] For example, when boron is used as an impurity element, boron contained in the low-resistance region 10⁸N may exist bonded to oxygen. This can be confirmed by observing a spectral peak caused by the B₂O₃ bond in XPS analysis. Alternatively, in XPS analysis, a spectral peak caused by the element boron existing in its pure form may not be observed, or its peak intensity may be so small that it is buried in background noise observed near the lower limit of the detection range.

[0121] The insulating layer 110, which functions as a gate insulating layer, has a region that is in contact with the channel formation region of the semiconductor layer 108, that is, a region that overlaps with the conductive layer 112. In addition, the insulating layer 110 has a region that is in contact with the low-resistance region 108N of the semiconductor layer 108 and does not overlap with the conductive layer 112.

[0122] The insulating layer 110 in contact with the semiconductor layer 108 preferably has an oxide insulating film. More preferably, the insulating layer 110 has a region containing oxygen in excess of its stoichiometric composition. In other words, it is preferable that the insulating layer 110 has an insulating film capable of releasing oxygen. For example, oxygen can be supplied into the insulating layer 110 by forming the insulating layer 110 in an oxygen-containing atmosphere, performing heat treatment on the insulating layer 110 after film formation in an oxygen-containing atmosphere, performing plasma treatment, or forming an oxide film on the insulating layer 110 in an oxygen-containing atmosphere.

[0123] The insulating layer 110 can be formed using a method that can be used to form the insulating layer 118. In particular, it is preferable to form the insulating layer 110 by the PECVD method.

[0124] The region of the insulating layer 110 that overlaps with the low-resistance region 108N may contain the aforementioned impurity elements. In this case, it is preferable that the impurity elements in the insulating layer 110 also exist in a state of being bonded with oxygen, similar to the low-resistance region 108N. Since such easily oxidized elements can exist stably in an oxidized state bonded with oxygen in the insulating layer 110, their desorption is suppressed even when high temperatures are applied in later processes. In particular, if the insulating layer 110 contains oxygen that can be desorbed by heating (also called excess oxygen), the excess oxygen and the impurity elements bond and stabilize, thereby suppressing the supply of oxygen from the insulating layer 110 to the low-resistance region 108N. Furthermore, since a portion of the insulating layer 110 containing oxidized impurity elements becomes less permeable to oxygen diffusion, the supply of oxygen from above the insulating layer 110 to the low-resistance region 108N via the insulating layer 110 is suppressed, and the increase in resistance of the low-resistance region 108N can also be prevented.

[0125] It is preferable to use a conductive film containing a metal or alloy for the conductive layer 112, as this suppresses electrical resistance. Alternatively, a conductive film containing an oxide may be used for the conductive layer 112.

[0126] Similar to the deposition of conductive films that will become conductive layers 120a and 120b, ultraviolet light may be generated inside the deposition apparatus when depositing the conductive film that will become conductive layer 112. When this ultraviolet light penetrates the insulating layer 110 and reaches the semiconductor layer 108, oxygen vacancies V in the semiconductor layer 108 may occur. O , and V O In some cases, H levels may increase. In particular, oxygen deficiency V occurs in the channel formation region. O , and V O H can adversely affect the electrical characteristics and reliability of the transistor. Therefore, when forming the conductive film that will become the conductive layer 112, it is preferable to minimize the amount of ultraviolet light reaching the semiconductor layer 108.

[0127] Figure 8A shows a cross-sectional view of the transistor 100 before the conductive film that will become the conductive layer 112 is deposited. In Figure 8A, the ultraviolet light generated in the deposition apparatus when the conductive film that will become the conductive layer 112 is deposited is represented by white arrows, and the process of the ultraviolet light passing through the insulating layer 110 and reaching the semiconductor layer 108 is schematically shown.

[0128] The amount of ultraviolet light reaching the semiconductor layer 108 is determined by the product of the intensity (also called illuminance) of the ultraviolet light and the time it takes for the ultraviolet light to reach the semiconductor layer 108. In other words, a higher intensity of ultraviolet light results in a larger amount of ultraviolet light reaching the semiconductor layer 108, and a longer time for the ultraviolet light to reach the semiconductor layer 108 also results in a larger amount of ultraviolet light. When ultraviolet light is generated in a film deposition apparatus for depositing a conductive film that will become the conductive layer 112, it is preferable to use a material with low ultraviolet light transmittance for the conductive layer 112. By using a material with low transmittance for the conductive layer 112, when a conductive film of a certain thickness is deposited on the semiconductor layer 108, the ultraviolet light is shielded by the conductive film, and the amount of ultraviolet light reaching the semiconductor layer 108 can be reduced.

[0129] Figure 8B schematically shows the initial state of film formation, where the thickness of the conductive film 112m, which will become the conductive layer 112, has not yet reached a thickness sufficient to block ultraviolet light. During the period when the thickness of the conductive film 112m has not yet reached a thickness sufficient to block ultraviolet light, ultraviolet light passes through the conductive film 112m and reaches the semiconductor layer 108. Figure 8C schematically shows the state after the thickness of the conductive film 112m has reached a thickness sufficient to block ultraviolet light. After the thickness of the conductive film 112m has reached a thickness sufficient to block ultraviolet light, ultraviolet light is blocked by the conductive film 112m and does not reach the semiconductor layer 108.

[0130] Next, we will explain the conditions for depositing the conductive film. If the power used during film deposition is high, the intensity of the ultraviolet light generated may increase. However, increasing the power during film deposition increases the deposition rate, thus shortening the time required to form a conductive film of sufficient thickness to block ultraviolet light. Therefore, the time it takes for ultraviolet light to reach the semiconductor layer 108 is shortened, and the amount of ultraviolet light reaching the semiconductor layer 108 can be reduced.

[0131] Furthermore, if the power used during film deposition is low, the deposition rate will be slow, which may increase the time required to form a conductive film of sufficient thickness to block ultraviolet light. However, lowering the power during deposition may reduce the intensity of the generated ultraviolet light, potentially reducing the amount of ultraviolet light reaching the semiconductor layer 108. Therefore, the power during deposition should be set to minimize the amount of ultraviolet light reaching the semiconductor layer 108, taking into account the intensity of the generated ultraviolet light and the deposition rate. While power during deposition has been used as an example here, other conditions (e.g., pressure) should also be set similarly, taking into account the intensity of the generated ultraviolet light and the deposition rate.

[0132] The case where the conductive layer 112 has a laminated structure will be explained. Here, we will explain using as an example a configuration in which the conductive layer 112 has a two-layer laminated structure, and the conductive film that becomes the conductive layer 112 has a laminated structure of a first conductive film and a second conductive film on the first conductive film.

[0133] As mentioned above, the first conductive film is preferably deposited using conditions that reduce the amount of ultraviolet light reaching the semiconductor layer 108. Furthermore, it is preferable to use a material and thickness that can shield ultraviolet light for the first conductive film. When the second conductive film is deposited, the amount of ultraviolet light reaching the semiconductor layer 108 can be reduced by the first conductive film shielding ultraviolet light. The first conductive film can be made of one or more metal elements selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, alloys composed of the above metal elements, or alloys combining the above metal elements.

[0134] Since a lower ultraviolet light transmittance of the first conductive film is preferable, there is no need to set a lower limit for the transmittance. However, if a lower limit is set, for example, the ultraviolet light transmittance of the first conductive film is preferably 0.01% or higher.

[0135] The transmittance of the first conductive film in the wavelength range of 200 nm to 400 nm is preferably 0.01% to 80%, more preferably 0.01% to 75%, and even more preferably 0.01% to 70%.

[0136] Furthermore, the transmittance of the first conductive film in the wavelength range of 200 nm to 350 nm is preferably 0.01% to 70%, more preferably 0.01% to 60%, more preferably 0.01% to 50%, more preferably 0.01% to 40%, more preferably 0.01% to 30%, more preferably 0.01% to 20%, and more preferably 0.01% to 10%.

[0137] The thickness of the first conductive film is preferably set so that the transmittance of ultraviolet light falls within the aforementioned range. Furthermore, the thickness of the first conductive film is preferably set considering the resistance required for the conductive layer 112, which functions as a gate electrode. In addition, if the thickness of the first conductive film is increased, the conductive layer 112 becomes thicker, which may cause defects such as step breaks or porosity in the insulating layer 118 formed on the conductive layer 112. The thickness of the first conductive film is preferably 20 nm to 200 nm, more preferably 30 nm to 150 nm, more preferably 40 nm to 120 nm, more preferably 50 nm to 100 nm, and more preferably 70 nm to 100 nm. By setting the thickness of the first conductive film within the aforementioned range, the amount of ultraviolet light reaching the semiconductor layer 108 can be reduced, the step coverage of the insulating layer 118 can be improved, and defects such as step breaks or porosity in the insulating layer 118 can be suppressed.

[0138] This section describes a transistor configuration example that differs in some aspects from the previously mentioned Configuration Example 1. Note that in the following, explanations of parts that overlap with Configuration Example 1 may be omitted. Also, in the diagrams shown below, parts having the same function as Configuration Example 1 may use the same hatching pattern and may not be labeled.

[0139] <Configuration Example 2> Figure 9A is a top view of transistor 100A, and Figure 9B is a cross-sectional view of transistor 100A in the channel length direction. A cross-sectional view of transistor 100A in the channel width direction can be found in Figure 1C. Figure 10 shows an enlarged view of the region S enclosed by the dashed line in Figure 9B.

[0140] Transistor 100A differs from transistor 100 shown in Figure 1A, etc., mainly in that the top surface shape of the insulating layer 110 and the top surface shape of the insulating layer 118 do not match.

[0141] The insulating layer 110 has openings 145a and 145b in the region overlapping with the low-resistance region 108N. The insulating layer 118 has openings 147a and 147b in the region overlapping with the low-resistance region 108N. In addition, opening 145a is located inside opening 147a, and opening 145b is located inside opening 147b.

[0142] The insulating layer 130 is provided covering the upper and side surfaces of the insulating layer 118, and the upper and side surfaces of the insulating layer 110. The insulating layer 130 has openings 143a and 143b, with opening 143a located inside opening 145a and opening 143b located inside opening 145b.

[0143] Enlarged views of openings 143a, 145a, and 147a, and their vicinity, are shown in Figures 11A and 11B. Figure 11A is a top view, and Figure 11B corresponds to a cross-sectional view of the section along the dashed line D1-D2 shown in Figure 11A. Note that hatching has been omitted in Figure 11B to avoid making the drawing too complex.

[0144] In any straight line crossing openings 143a, 145a, and 147a, it is preferable that the width 145W at the bottom of opening 145a is smaller than the width 147W at the bottom of opening 147a. This configuration improves the step coverage of the layer formed on the insulating layer 118 and the insulating layer 110 (for example, the insulating layer 130), and suppresses the occurrence of defects such as step breaks or porosity in the layer. Furthermore, it is preferable that the width 143W at the bottom of opening 143a is smaller than the width 145W at the bottom of opening 145a.

[0145] Detailed explanations of angles θ1, θ2, and width 151 are omitted as they can be found in the previously mentioned description.

[0146] <Configuration Example 3> Figure 12A is a cross-sectional view of transistor 100B in the channel length direction, and Figure 12B is a cross-sectional view of transistor 100B in the channel width direction. A top view of transistor 100B can be found in Figure 1A.

[0147] Transistor 100B differs from transistor 100 shown in Figure 1 mainly in the configuration of its insulating layer 110.

[0148] The insulating layer 110 has a laminated structure in which insulating film 110a, insulating film 110b, and insulating film 110c are stacked in this order from the substrate 102 side. Insulating film 110a has a region in contact with the channel formation region of the semiconductor layer 108. Insulating film 110c has a region in contact with the conductive layer 112. Insulating film 110b is located between insulating film 110a and insulating film 110c.

[0149] It is preferable that insulating films 110a, 110b, and 110c each contain an oxide. In this case, it is preferable that insulating films 110a, 110b, and 110c are deposited continuously using the same deposition apparatus.

[0150] The insulating film 110a, insulating film 110b, and insulating film 110c can be insulating layers containing, for example, one or more silicon oxide films, silicon oxide nitride films, silicon nitride films, aluminum oxide films, hafnium oxide films, yttrium oxide films, zirconium oxide films, gallium oxide films, tantalum oxide films, magnesium oxide films, lanthanum oxide films, cerium oxide films, and neodymium oxide films.

[0151] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of oxide insulating films. More preferably, the insulating layer 110 has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 has an insulating film capable of releasing oxygen. For example, oxygen can be supplied into the insulating layer 110 by forming the insulating layer 110 in an oxygen-containing atmosphere, performing heat treatment in an oxygen-containing atmosphere after the deposition of the insulating layer 110, performing plasma treatment in an oxygen-containing atmosphere after the deposition of the insulating layer 110, or forming an oxide film on the insulating layer 110 in an oxygen-containing atmosphere. In each of the above oxygen supply processes, an oxidizing gas may be used instead of or in addition to oxygen. Examples of oxidizing gases include nitrous oxide or ozone. Multiple types of oxidizing gases may be used.

[0152] The insulating film 110a, insulating film 110b, and insulating film 110c can be formed using, for example, sputtering, CVD, vacuum deposition, PLD, ALD, or the like.

[0153] In particular, insulating films 110a, 110b, and 110c are preferably formed by plasma CVD.

[0154] Since the insulating film 110a is deposited on the semiconductor layer 108, it is preferable that the film be deposited under conditions that minimize damage to the semiconductor layer 108. For example, it can be deposited under conditions where the deposition rate (also called the deposition rate) is sufficiently low.

[0155] For example, when forming a silicon oxidizride film as the insulating film 110a by plasma CVD, the damage to the semiconductor layer 108 can be made extremely small by forming it under low power conditions.

[0156] For forming silicon oxidnitride films, the deposition gas can include a silicon-containing depositing gas such as silane or disilane, and an oxidizing gas such as oxygen, ozone, nitrous oxide, or nitrogen dioxide. In addition to the source gas, a diluent gas such as argon, helium, or nitrogen may also be included.

[0157] For example, by reducing the ratio of the deposition gas flow rate to the total deposition gas flow rate (hereinafter also simply referred to as the flow rate ratio), the deposition rate can be lowered, and a dense film with fewer defects can be deposited.

[0158] It is preferable that the insulating film 110b is a film deposited under conditions with a higher deposition rate than that of insulating film 110a. This can improve productivity.

[0159] For example, insulating film 110b can be deposited under conditions that increase the deposition rate compared to insulating film 110a.

[0160] The insulating film 110c is preferably an extremely dense film with reduced surface defects and resistance to adsorption of impurities contained in the atmosphere, such as water. For example, it can be deposited under conditions where the deposition rate is sufficiently low, similar to insulating film 110a.

[0161] Since the insulating film 110c is deposited on the insulating film 110b, the effect on the semiconductor layer 108 during the deposition of insulating film 110c is smaller compared to that of insulating film 110a. Therefore, insulating film 110c can be deposited under higher power conditions than insulating film 110a. By reducing the flow rate ratio of the depositing gas and depositing the film at a relatively high power, a dense film with reduced surface defects can be obtained.

[0162] In other words, a laminated film deposited under conditions where the deposition rate is highest for insulating film 110b, followed by insulating film 110a and then insulating film 110c, can be used as the insulating layer 110. Furthermore, the etching rate of the insulating layer 110 under the same conditions in wet etching or dry etching is highest for insulating film 110b, followed by insulating film 110a and then insulating film 110c.

[0163] It is preferable to form the insulating film 110b thicker than insulating films 110a and 110c. By forming the insulating film 110b, which has the fastest deposition rate, thicker, the time required for the deposition process of the insulating layer 110 can be shortened.

[0164] Here, the boundaries between insulating film 110a and insulating film 110b, and between insulating film 110b and insulating film 110c, may be unclear; therefore, in Figure 12A and other figures, these boundaries are indicated by dashed lines. Note that because insulating film 110a and insulating film 110b have different film densities, these boundaries may be observed as differences in contrast in transmission electron microscope images of the cross-section of the insulating layer 110. Similarly, the boundary between insulating film 110b and insulating film 110c may also be observed as a difference in contrast.

[0165] In one embodiment of the present invention, it is preferable to apply a metal oxide film with a low gallium content or a gallium-free metal oxide film to the semiconductor layer 108 of the transistor 100B. Furthermore, it is preferable to use a film formed by a film deposition method that reduces damage to the semiconductor layer 108 as the insulating film 110a that is in contact with the upper surface of the semiconductor layer 108. This reduces the defect level density at the interface between the semiconductor layer 108 and the insulating layer 110, resulting in a transistor 100B with high reliability.

[0166] <Configuration Example 4> Figure 13A is a top view of transistor 100C, Figure 13B is a cross-sectional view of transistor 100C in the channel length direction, and Figure 13C is a cross-sectional view of transistor 100C in the channel length direction.

[0167] Transistor 100C differs from transistor 100 shown in Figure 1, etc., mainly in that it has a conductive layer 106 and an insulating layer 103 between the substrate 102 and the semiconductor layer 108. The conductive layer 106 has a region that overlaps with the conductive layer 112 via the semiconductor layer 108.

[0168] In transistor 100C, the conductive layer 112 functions as a second gate electrode (also called a top gate electrode), and the conductive layer 106 functions as a first gate electrode (also called a bottom gate electrode). In addition, a portion of the insulating layer 110 functions as a second gate insulating layer, and a portion of the insulating layer 103 functions as a first gate insulating layer.

[0169] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel-forming region. For the sake of simplicity, in the following explanation, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 may be referred to as the channel-forming region, but in reality, channels can also be formed in the portion that overlaps with the conductive layer 106 (the portion including the low-resistance region 108N) without overlapping with the conductive layer 112.

[0170] As shown in Figure 13C, the conductive layer 106 may be electrically connected to the conductive layer 112 through openings 142 provided in the insulating layer 110 and the insulating layer 103. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential. By giving the conductive layer 112 and the conductive layer 106 the same potential, the current that can flow when the transistor 100C is ON can be increased.

[0171] The conductive layer 106 can be made of the same material as conductive layer 112, conductive layer 120a, or conductive layer 120b. In particular, using a copper-containing material for conductive layer 106 is preferable because it can reduce wiring resistance.

[0172] As shown in Figures 13A and 13C, it is preferable that the conductive layer 112 and conductive layer 106 protrude outward from the edge of the semiconductor layer 108 in the channel width direction. In this case, as shown in Figure 13C, the entire channel width direction of the semiconductor layer 108 is covered by the conductive layer 112 and conductive layer 106 via the insulating layer 110 and insulating layer 103.

[0173] This configuration allows the semiconductor layer 108 to be electrically surrounded by the electric field generated by the pair of gate electrodes. In particular, it is preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. This effectively applies an electric field to induce a channel in the semiconductor layer 108, thereby increasing the on-current of the transistor 100C. As a result, it becomes possible to miniaturize the transistor 100C.

[0174] Alternatively, the conductive layer 112 and the conductive layer 106 may be configured without connection. In this case, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving transistor 100C may be applied to the other electrode. In this case, the threshold voltage when driving transistor 100C with the other gate electrode can be controlled by the potential applied to one gate electrode.

[0175] The conductive layer 106 may be electrically connected to the conductive layer 120a or the conductive layer 120b. In this case, the conductive layer 106 may be electrically connected to the conductive layer 120a or the conductive layer 120b through openings provided in the insulating layer 118, the insulating layer 110, and the insulating layer 103.

[0176] The insulating layer 103 can be formed using a method that can be used to form the insulating layer 118. In particular, it is preferable to form the insulating layer 103 by the PECVD method.

[0177] The insulating layer 103, which functions as a second gate insulating layer, preferably satisfies one or more of the following conditions: high breakdown voltage, low film stress, low hydrogen release, low water release, few defects in the film, and suppression of the diffusion of metal elements contained in the conductive layer 106. It is most preferable that it satisfies all of these conditions.

[0178] Figures 13B and 13C show an example in which the insulating layer 103 has a laminated structure of an insulating film 103a and an insulating film 103b on top of the insulating film 103a. For the insulating film 103a in contact with the conductive layer 106, it is preferable to use an insulating film that does not easily diffuse the metal elements contained in the conductive layer 106. For example, the insulating film 103a is preferably a silicon nitride film, a silicon oxide film, an aluminum oxide film, or a hafnium oxide film. For the insulating film 103b in contact with the semiconductor layer 108, it is preferable to use an insulating film containing oxygen. For example, the insulating film 103b is preferably a silicon oxide film or a silicon oxide nitride film.

[0179] Although Figures 13B and 13C show a two-layer structure of insulating film 103a and insulating film 103b as the insulating layer 103, the present invention is not limited to this. The insulating layer 103 may be a single-layer structure or a laminated structure of three or more layers. Furthermore, each of the insulating film 103a and insulating film 103b may have a laminated structure of two or more layers.

[0180] When the insulating layer 103 has a laminated structure, it is preferable that each insulating film of the insulating layer 103 be deposited continuously without coming into contact with the atmosphere. For example, it is preferable that each insulating film of the insulating layer 103 be deposited continuously without coming into contact with the atmosphere using a plasma CVD apparatus.

[0181] <Configuration Example 5> Figure 14A is a cross-sectional view of transistor 100D in the channel length direction, and Figure 14B is a cross-sectional view of transistor 100D in the channel length direction. A top view of transistor 100D can be found in Figure 13A.

[0182] Transistor 100D differs primarily from transistor 100C shown in Figure 13, etc., in that it has a metal oxide layer 114 between the insulating layer 110 and the conductive layer 112.

[0183] The conductive layer 112 and the metal oxide layer 114 are processed so that their upper surface shapes are substantially the same. The metal oxide layer 114 can be formed, for example, by processing it using a resist mask for processing the conductive layer 112.

[0184] The metal oxide layer 114 has the function of supplying oxygen to the insulating layer 110. Furthermore, if a conductive film containing an easily oxidizable metal or alloy is used as the conductive layer 112, the metal oxide layer 114 can also function as a barrier layer to prevent the conductive layer 112 from being oxidized by the oxygen in the insulating layer 110. Alternatively, the metal oxide layer 114 may be removed before the formation of the conductive layer 112, resulting in a configuration where the conductive layer 112 and the insulating layer 110 are in contact. The metal oxide layer 114 may also be omitted if it is not needed.

[0185] The metal oxide layer 114, located between the insulating layer 110 and the conductive layer 112, functions as a barrier film to prevent oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112. Furthermore, the metal oxide layer 114 also functions as a barrier film to prevent impurities containing hydrogen elements contained in the conductive layer 112 from diffusing to the insulating layer 110. Examples of hydrogen elements as impurities include hydrogen or water. It is preferable that the metal oxide layer 114 be made of a material that is less permeable to oxygen and hydrogen than at least the insulating layer 110.

[0186] The metal oxide layer 114 prevents oxygen from diffusing from the insulating layer 110 to the conductive layer 112, even when a metal material that easily attracts oxygen is used for the conductive layer 112. Furthermore, even when the conductive layer 112 contains hydrogen, it prevents hydrogen from diffusing from the conductive layer 112 to the semiconductor layer 108 via the insulating layer 110. As a result, the carrier concentration in the channel formation region of the semiconductor layer 108 can be kept extremely low. Examples of metal materials that easily attract oxygen include aluminum and copper.

[0187] The metal oxide layer 114 can be made of an insulating material or a conductive material. If the metal oxide layer 114 is insulating, it functions as part of the gate insulating layer. On the other hand, if the metal oxide layer 114 is conductive, it functions as part of the gate electrode.

[0188] It is preferable to use an insulating material with a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, using an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film is preferable because it can reduce the driving voltage.

[0189] As the metal oxide layer 114, conductive oxides such as indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can also be used. Conductive oxides containing indium are particularly preferred due to their high conductivity.

[0190] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the metal oxide layer 114. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. In this case, it is preferable to use a metal oxide film formed using the same sputtering target as the semiconductor layer 108 as the metal oxide layer 114, as this allows for the commonality of the apparatus.

[0191] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when forming an oxide film using a sputtering apparatus, forming it in an atmosphere containing oxygen gas allows for suitable addition of oxygen to one or both of the insulating layer 110 or the semiconductor layer 108.

[0192] Alternatively, a metal oxide film suitable for use in the metal oxide layer 114 may be formed, oxygen may be supplied to the insulating layer 110, and then the metal oxide film may be removed. Furthermore, the metal oxide layer 114 or the metal oxide film suitable for use in the metal oxide layer 114 may be omitted if they are not needed.

[0193] <Configuration Example 6> Figure 15A is a cross-sectional view of transistor 100E in the channel length direction, and Figure 15B is a cross-sectional view of transistor 100E in the channel length direction. A top view of transistor 100E can be found in Figure 13A.

[0194] Transistor 100E differs primarily from transistor 100C, shown in Figure 13, in the configuration of its insulating layer 110.

[0195] The insulating layer 110 is processed so that its upper surface shape substantially matches that of the conductive layer 112. The insulating layer 110 can be formed, for example, by processing it using a resist mask for processing the conductive layer 112.

[0196] The insulating layer 118 is in contact with the top and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 110, and the top and side surfaces of the conductive layer 112. The insulating layer 118 has openings 141a and 141b in the region that overlaps with the semiconductor layer 108.

[0197] The edges of the insulating layer 118 are preferably tapered. Regarding the corners of the edges of the insulating layer 118, please refer to the description of angle θ1 above; therefore, a detailed explanation is omitted.

[0198] For the insulating layer 130, the conductive layer 120a, and the conductive layer 120b, since the above description can be referred to, detailed explanations are omitted.

[0199] <Configuration Example 7> FIG. 16A is a top view of the transistor 100F, FIG. 16B is a cross-sectional view of the transistor 100F in the channel length direction, and FIG. 16C is a cross-sectional view of the transistor 100F in the channel length direction.

[0200] The transistor 100F is mainly different from the transistor 100E shown in FIG. 15 and the like in that the configuration of the insulating layer 110 is different.

[0201] The end of the conductive layer 112 is located inside the end of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the end of the conductive layer 112 at least on the semiconductor layer 108.

[0202] The semiconductor layer 108 has a pair of regions 108L sandwiching the channel formation region and a pair of low-resistance regions 108N outside thereof. The region 108L is a region of the semiconductor layer 108 that overlaps with the insulating layer 110 and does not overlap with the conductive layer 112.

[0203] The region 108L functions as a buffer region for relaxing the drain electric field. Since the region 108L does not overlap with the conductive layer 112, it is a region where almost no channel is formed even when a gate voltage is applied to the conductive layer 112. It is preferable that the carrier concentration in the region 108L is higher than that in the channel formation region. Thereby, the region 108L can function as a LDD (Lightly Doped Drain) region.

[0204] The region 108L can also be said to be a region having the same or lower resistance, the same or higher carrier concentration, the same or higher oxygen defect density, and the same or higher impurity concentration as compared with the channel formation region.

[0205] Region 10⁸L can also be described as a region with similar or higher resistance, similar or lower carrier concentration, similar or lower oxygen defect density, and similar or lower impurity concentration compared to the low-resistance region 10⁸N.

[0206] In this way, by providing a region 108L that functions as an LDD region between the channel formation region and the low-resistance region 108N that functions as a source region or drain region, it is possible to realize a highly reliable transistor that combines high drain breakdown voltage and high on-current.

[0207] The low-resistance region 108N functions as either a source or drain region and is the region with the lowest resistance compared to other regions of the semiconductor layer 108. Alternatively, the low-resistance region 108N can also be described as the region with the highest carrier concentration, the highest oxygen vacancy density, or the highest impurity concentration compared to other regions of the semiconductor layer 108.

[0208] The electrical resistance in the low-resistance region 10⁸N is preferably as low as possible. For example, the sheet resistance value in the low-resistance region 10⁸N should be 1Ω / □ or more, or 1 × 10⁻⁶. 3 Less than Ω / □, preferably 1Ω / □ or more, 8×10 2 It is preferable that the ratio be Ω / □ or less.

[0209] A higher electrical resistance in the channel-forming region when no channel is formed is preferable. For example, the sheet resistance value of the channel-forming region is 1 × 10⁻⁶. 9 Ω / □ or greater, preferably 5 × 10 9 Ω / □ or greater, comfortable 1 × 10 10 It is preferable that the ratio is Ω / □ or greater.

[0210] Since a higher electrical resistance in the channel-forming region is preferable when no channel is formed, there is no need to set an upper limit. However, if an upper limit is to be set, for example, the sheet resistance value of the channel-forming region should be 1 × 10⁻⁶. 9 Ω / □ or more 1×10 12 Ω / □ or less, preferably 5 × 109 Ω / □ or more 1×10 12 Ω / □ or less, more preferably 1 × 10 10 Ω / □ or more 1×10 12 It is preferable that the value is Ω / □ or less.

[0211] The sheet resistance value of region 108L is, for example, 1 × 10⁻⁶. 3 Ω / □ or more 1×10 9 Ω / □ or less, preferably 1 × 10 3 Ω / □ or more 1×10 8 Ω / □ or less, more preferably 1 × 10 3 Ω / □ or more 1×10 7 The resistance can be set to Ω / □. By setting the resistance to this range, a transistor with good electrical characteristics and high reliability can be made. The sheet resistance can be calculated from the resistance value. By providing such a region 108L between the low-resistance region 108N and the channel formation region, the source-drain breakdown voltage of transistor 100F can be increased.

[0212] The electrical resistance of the channel-forming region when no channel is formed is 1 × 10⁻⁶ of the electrical resistance of the low-resistance region of 10⁸N. 6 1×10 times more 12 Less than or equal to 1x10, preferably 1x10 6 1×10 times more 11 More preferably 1 × 10⁻⁶ times or less. 6 1×10 times more 10 It can be reduced to less than double.

[0213] The electrical resistance of the channel-forming region when no channel is formed is 1 × 10⁻⁶ of the electrical resistance of region 10⁸L. 0 1×10 times more 9 Less than or equal to 1x10, preferably 1x10 1 1×10 times more 8 More preferably 1 × 10⁻⁶ times or less. 2 1×10 times more 7 It can be reduced to less than double.

[0214] The electrical resistance of region 10⁸L is 1 × 10⁸ of the electrical resistance of the low-resistance region 10⁸N. 01×10 times more 9 Less than or equal to 1x10, preferably 1x10 1 1×10 times more 8 More preferably 1 × 10⁻⁶ times or less. 1 1×10 times more 7 It can be reduced to less than double.

[0215] Preferably, the carrier concentration in the semiconductor layer 108 has a distribution such that it is lowest in the channel formation region, and increases in the order of region 108L and then in the low-resistance region 108N. By providing region 108L between the channel formation region and the low-resistance region 108N, the carrier concentration in the channel formation region can be kept extremely low, even if impurities such as hydrogen diffuse from the low-resistance region 108N during the manufacturing process.

[0216] A lower carrier concentration is preferable in the channel-forming region, which functions as a channel-forming region, such as 1 × 10⁻⁶. 18 cm -3 The following is preferable: 1 × 10 17 cm -3 More preferably, 1 × 10 16 cm -3 It is even more preferable that the following conditions apply: 1 × 10 13 cm -3 It is even more preferable that the following conditions apply: 1 × 10 12 cm -3 The following is even more preferable. There are no particular limitations on the lower limit of the carrier concentration in the channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0217] On the other hand, the carrier concentration in the low-resistance region 10⁸N is, for example, 5 × 10⁻⁶. 18 cm -3 Preferably 1 × 10 19 cm -3 The above is more comfortable 5x10 19 cm -3 The above can be applied. There is no particular limit to the upper limit of the carrier concentration in the low-resistance region 10⁸N, but for example, 5 × 10⁻⁶ 21cm -3 , or 1 × 10 22 cm -3 It can be done in this way.

[0218] The carrier concentration in region 108L can be a value between the channel-forming region and the low-resistance region 108N. For example, 1 × 10⁻⁶ 14 cm -3 The above 1 x 10 20 cm -3 The value should be in the range less than or equal to.

[0219] Furthermore, the carrier concentration in region 108L does not necessarily have to be uniform; it may have a gradient such that the carrier concentration decreases from the low-resistance region 108N to the channel-forming region. For example, the hydrogen concentration or the oxygen vacancy concentration, or both, in region 108L may have a gradient such that the concentration decreases from the low-resistance region 108N to the channel-forming region.

[0220] A portion of the edge of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 has a region that overlaps with the conductive layer 112 and functions as a gate insulating layer, and a region that does not overlap with the conductive layer 112 (i.e., a region that overlaps with region 108L).

[0221] <Configuration Example 8> Figure 17A is a cross-sectional view of transistor 100G in the channel length direction, and Figure 17B is a cross-sectional view of transistor 100G in the channel length direction. A top view of transistor 100G can be found in Figure 13A.

[0222] Transistor 100G differs primarily from transistor 100E shown in Figure 15, etc., in that it has an insulating layer 116.

[0223] The insulating layer 116 is provided in contact with the upper and side surfaces of the semiconductor layer 108 that are not covered by the conductive layer 112 and the insulating layer 110. The insulating layer 116 covers the upper surface of the insulating layer 103, the side surfaces of the insulating layer 110, and the upper and side surfaces of the conductive layer 112.

[0224] The insulating layer 116 has a function of reducing the resistance of the low-resistance region 108N. As such an insulating layer 116, an insulating film capable of supplying impurities into the low-resistance region 108N can be used by heating during or after the film formation of the insulating layer 116. Alternatively, an insulating film capable of causing oxygen deficiency in the low-resistance region 108N can be used by heating during or after the film formation of the insulating layer 116.

[0225] For example, as the insulating layer 116, an insulating film that functions as a source for supplying impurities to the low-resistance region 108N can be used. At this time, the insulating layer 116 is preferably a film that releases hydrogen by heating. By forming such an insulating layer 116 in contact with the semiconductor layer 108, impurities such as hydrogen can be supplied to the low-resistance region 108N, and the resistance of the low-resistance region 108N can be reduced.

[0226] The insulating layer 116 is preferably a film formed using a film-forming gas containing impurity elements such as hydrogen element during film formation. Also, the lower the film formation temperature of the insulating layer 116, the more effectively a large amount of impurity elements can be supplied to the semiconductor layer 108. The film formation temperature of the insulating layer 116 is preferably, for example, 200°C or higher and 500°C or lower, more preferably 220°C or higher and 450°C or lower, and even more preferably 230°C or higher and 400°C or lower.

[0227] By performing the film formation of the insulating layer 116 under reduced pressure and with heating, the desorption of oxygen from the region that becomes the low-resistance region 108N in the semiconductor layer 108 can be promoted. By supplying impurities such as hydrogen to the semiconductor layer 108 in which a large amount of oxygen deficiency is formed, the carrier concentration in the low-resistance region 108N increases, and the resistance of the low-resistance region 108N can be reduced more effectively.

[0228] The insulating layer 116 can preferably be an insulating film containing a nitride, such as silicon nitride, silicon oxide nitride, silicon oxynitride, aluminum nitride, or aluminum oxide nitride. In particular, since silicon nitride has blocking properties for both hydrogen and oxygen, it can prevent both the diffusion of hydrogen from the outside into the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside, thereby realizing a highly reliable transistor.

[0229] The insulating layer 116 may be an insulating film that has the function of attracting oxygen from the semiconductor layer 108 and creating an oxygen vacancy. In particular, it is especially preferable to use a metal nitride such as aluminum nitride for the insulating layer 116.

[0230] When using a metal nitride for the insulating layer 116, it is preferable to use an aluminum, titanium, tantalum, tungsten, chromium, or ruthenium nitride. In particular, it is preferable to include aluminum or titanium. For example, an aluminum nitride film formed by a reaction sputtering method using aluminum as the sputtering target and a nitrogen-containing gas as the film-forming gas can be made into a film that combines extremely high insulating properties with extremely high blocking properties against both hydrogen and oxygen by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the film-forming gas. Therefore, by providing such an insulating film containing a metal nitride in contact with the semiconductor layer, it is possible not only to lower the resistance of the semiconductor layer but also to effectively prevent oxygen from detaching from the semiconductor layer and hydrogen from diffusing into the semiconductor layer.

[0231] When aluminum nitride is used as the metal nitride, it is preferable that the thickness of the insulating layer containing the aluminum nitride be 5 nm or more. Even with such a thin film, it is possible to achieve both high blocking properties against hydrogen and oxygen and the function of reducing the resistance of the semiconductor layer. The thickness of the insulating layer can be any thickness, but considering productivity, it is preferable to set it to 500 nm or less, preferably 200 nm or less, and more preferably 50 nm or less.

[0232] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x It is preferable to use a film that satisfies the condition (where x is a real number greater than 0 and less than or equal to 2, preferably a real number greater than 0.5 and less than or equal to 1.5). This makes it possible to create a film with excellent insulating properties and excellent thermal conductivity, thereby improving the heat dissipation of heat generated when the transistor 100B is driven.

[0233] Alternatively, an aluminum titanium nitride film, a titanium nitride film, or the like can be used as the insulating layer 116.

[0234] By providing such an insulating layer 116 in contact with the low-resistance region 108N, the insulating layer 116 can draw oxygen from the low-resistance region 108N, thereby forming oxygen vacancies in the low-resistance region 108N. Furthermore, by performing a heat treatment after forming such an insulating layer 116, more oxygen vacancies can be formed in the low-resistance region 108N, thereby promoting lower resistance. In addition, if a film containing a metal oxide is used for the insulating layer 116, as a result of the insulating layer 116 drawing oxygen from the semiconductor layer 108, a layer containing an oxide of the metal element (e.g., aluminum) contained in the insulating layer 116 may be formed between the insulating layer 116 and the low-resistance region 108N.

[0235] In this case, when a metal oxide film containing indium is used as the semiconductor layer 108, a region where indium oxide is deposited, or a region with a high indium concentration, may be formed near the interface of the low-resistance region 108N on the insulating layer 116 side. This makes it possible to form an extremely low-resistance region 108N. The existence of such a region can sometimes be observed by analytical methods such as X-ray photoelectron spectroscopy (XPS).

[0236] In this example, an insulating layer 116 is used as a film to reduce the resistance of a portion of the semiconductor layer 108. However, the resistance of a portion of the semiconductor layer 108 can also be reduced by providing the insulating layer 118 in contact with a portion of the semiconductor layer 108. In other words, a configuration without an insulating layer 116 is also possible. In this case, an insulating film containing an oxide, such as a silicon oxide film or a silicon oxynitride film, can be used as the insulating layer 118 that is in contact with a portion of the semiconductor layer 108.

[0237] <Configuration Example 9> Figure 18A is a top view of transistor 100H, Figure 18B is a cross-sectional view of transistor 100H in the channel length direction, and Figure 18C is a cross-sectional view of transistor 100H in the channel length direction. Figure 19 shows an enlarged view of the region T enclosed by the dashed line in Figure 18B.

[0238] Transistor 100H differs primarily from transistor 100C shown in Figure 13 in that it has an insulating layer 132.

[0239] The insulating layer 132 is provided covering the upper and side surfaces of the insulating layer 130. The insulating layer 132 has an opening 149a inside the opening 143a and an opening 149b inside the opening 143b. Furthermore, the insulating layer 132 may have a region in contact with the upper surface of the semiconductor layer 108.

[0240] The conductive layer 120a and the conductive layer 120b are electrically connected to the low-resistance region 108N via openings 149a or 149b provided in the insulating layer 132, respectively.

[0241] The insulating layer 132 can be made of the same material as the insulating layer 118. By providing the insulating layer 132 between the conductive layers 120a and 120b and the insulating layer 130, and configuring the conductive layers 120a and 120b to be in contact with the insulating layer 132, the adhesion between the conductive layers 120a and 120b can be improved. The insulating layer 132 can also be applied to other configuration examples.

[0242] Enlarged views of openings 149a, 143a, and 141a, and their vicinity, are shown in Figures 20A and 20B. Figure 20A is a top view, and Figure 20B corresponds to a cross-sectional view of the section along the dashed line D1-D2 shown in Figure 20A. Note that hatching has been omitted in Figure 20B to avoid making the drawing too complex.

[0243] In any straight line crossing openings 149a, 143a, and 141a, it is preferable that the width 143W at the bottom of opening 143a is smaller than the width 141W at the bottom of opening 141a. Furthermore, it is preferable that the width 149W at the bottom of opening 149a is smaller than the width 143W at the bottom of opening 143a.

[0244] Detailed explanations of angles θ1, θ2, and width 151 are omitted as they can be found in the previously mentioned description.

[0245] <Example of manufacturing method 1> The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. Here, we will use transistor 100C shown in Figure 13 as an example.

[0246] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, CVD, vacuum deposition, PLD, ALD, and other methods. CVD methods include PECVD and thermal CVD. MOCVD is one type of thermal CVD method.

[0247] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0248] When processing thin films that constitute semiconductor devices, photolithography or other methods can be used. Alternatively, thin films may be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films may be directly formed using a film deposition method that utilizes a shielding mask such as a metal mask.

[0249] There are two main methods of photolithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0250] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure may also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays may be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0251] For etching thin films, methods such as dry etching, wet etching, and sandblasting can be used.

[0252] Figures 21A to 24C show cross-sections in the channel length direction and channel width direction at each stage of the manufacturing process of transistor 100C.

[0253] [Formation of conductive layer 106] A conductive film is formed on the substrate 102, and this is processed by etching to form a conductive layer 106 that functions as a gate electrode (Figure 21A).

[0254] In this case, it is preferable to process the ends of the conductive layer 106 so that they are tapered, as shown in Figure 21A. This improves the stepped coverage of the insulating layer 103 that is formed next.

[0255] By using a conductive film containing copper as the conductive layer 106, the wiring resistance can be reduced. For example, when applied to large display devices or high-resolution display devices, it is preferable to use a conductive film containing copper. Furthermore, even when a conductive film containing copper is used for the conductive layer 106, the diffusion of copper to the semiconductor layer 108 is suppressed by the insulating layer 103, thus enabling the realization of a highly reliable transistor.

[0256] [Formation of insulating layer 103] Next, an insulating layer 103 is formed by covering the substrate 102 and the conductive layer 106 (Figure 21B). The insulating layer 103 can be formed using methods such as PECVD, ALD, or sputtering.

[0257] Here, the insulating layer 103 is formed by laminating an insulating film 103a and an insulating film 103b. In particular, it is preferable that each insulating film constituting the insulating layer 103 be formed by the PECVD method.

[0258] The insulating film 103a can be, for example, a nitrogen-containing insulating film such as a silicon nitride film, a silicon oxide nitride film, an aluminum nitride film, or a hafnium nitride film. In particular, it is preferable to use a dense silicon nitride film deposited using a PECVD apparatus as the insulating film 103a. By using such a nitrogen-containing insulating film, even when the thickness is thin, the diffusion of impurities from the surface to be formed can be effectively suppressed.

[0259] By using a nitrogen-containing insulating film as insulating film 103a, it is possible to suppress the diffusion of oxygen in insulating film 103b into the conductive layer 106, etc., thereby reducing the amount of oxygen contained in insulating film 103b and preventing oxidation of the conductive layer 106, etc.

[0260] The insulating film 103b in contact with the semiconductor layer 108 is preferably formed of an insulating film containing an oxide. In particular, it is preferable to use an oxide film for the insulating film 103b. It is preferable to use a dense insulating film for the insulating film 103b that does not easily adsorb impurities such as water on its surface. Furthermore, it is preferable to use an insulating film for the insulating film 103b that has as few defects as possible and has reduced impurities, including hydrogen.

[0261] The insulating film 103b can be an insulating film containing, for example, one or more silicon oxide films, silicon oxide nitride films, silicon oxide nitride films, aluminum oxide films, hafnium oxide films, yttrium oxide films, zirconium oxide films, gallium oxide films, tantalum oxide films, magnesium oxide films, lanthanum oxide films, cerium oxide films, and neodymium oxide films. In particular, it is preferable to use a silicon oxide film or a silicon oxide nitride film as the insulating film 103b.

[0262] It is more preferable that the insulating film 103b has a region containing an excess of oxygen compared to its stoichiometric composition. In other words, it is preferable that the insulating film 103b is an insulating film that can release oxygen upon heating. For example, oxygen can be supplied into the insulating film 103b by forming the insulating film 103b in an oxygen-containing atmosphere, performing heat treatment on the insulating film 103b after film formation in an oxygen-containing atmosphere, performing plasma treatment on the insulating film 103b after film formation in an oxygen-containing atmosphere, or forming an oxide film on the insulating film 103b in an oxygen-containing atmosphere. In each of the above oxygen supply processes, an oxidizing gas may be used instead of or in addition to oxygen. Alternatively, oxygen may be supplied from the insulating film to the insulating film 103b by forming an insulating film that can release oxygen upon heating on the insulating film 103b and then performing heat treatment. Alternatively, oxygen may be supplied to the insulating film 103b by plasma ion doping or ion implantation.

[0263] Here, it is preferable that the insulating film 103b is formed to be thicker than the insulating film 103a. This increases the amount of oxygen that can be released from the insulating film 103b upon heating, and reduces the amount of hydrogen released from the insulating film 103a. As a result, it is possible to supply a large amount of oxygen to the subsequent semiconductor layer 108 while suppressing the supply of hydrogen, thereby realizing a highly reliable transistor. The thickness of the insulating film 103b is preferably 2 to 50 times that of the insulating film 103a, preferably 3 to 30 times, more preferably 5 to 20 times, and even more preferably 7 to 15 times, and typically about 10 times thicker.

[0264] When forming the metal oxide film that will become the semiconductor layer 108 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 103b. Furthermore, after forming the metal oxide film that will become the semiconductor layer, a heat treatment may be performed. The heat treatment can more effectively supply oxygen from the insulating film 103b to the metal oxide film, thereby reducing oxygen deficiencies in the metal oxide film.

[0265] When forming the insulating layer 103 using a PECVD apparatus, after forming the insulating layer 103, a plasma treatment at a lower power than that used for forming the insulating layer 103 may be performed in the processing chamber to remove static electricity accumulated on the substrate 102. This plasma treatment can be called a static elimination treatment. The static elimination treatment can be performed using an atmosphere containing one or more of the following: nitrogen, nitrous oxide, nitrogen dioxide, hydrogen, ammonia, or a noble gas. For example, an argon gas atmosphere can be suitably used for the static elimination treatment. Alternatively, the static elimination treatment may use a mixed gas containing the aforementioned multiple gases.

[0266] After forming the insulating layer 103, the surface of the insulating layer 103 may be removed. Defects may occur on the surface of the insulating layer 103 due to the static discharge treatment described above. If defects exist in the insulating layer 103, which functions as the first gate insulating layer of transistor 100C, they may become carrier trapping sites, potentially degrading the reliability of transistor 100C. Therefore, the reliability of transistor 100C can be improved by removing the surface of the insulating layer 103 that has defects. For example, cleaning using a cleaning solution containing hydrofluoric acid can be used to remove the surface of the insulating layer 103.

[0267] After forming the insulating layer 103, a heat treatment may be performed. The heat treatment can reduce defects in the insulating layer 103. It can also remove impurities containing hydrogen elements from the insulating layer 103. Examples of hydrogen-containing impurities include hydrogen and water.

[0268] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 250°C to 450°C, and more preferably 300°C to 450°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA) may be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., the incorporation of hydrogen, water, etc. into the insulating layer 103 can be suppressed. The heat treatment can be carried out using an oven, a rapid thermal annealing (RTA) device, etc. Using an RTA device can shorten the heat treatment time.

[0269] This heat treatment may be performed after removing the surface of the insulating layer 103.

[0270] Next, a process to supply oxygen to the insulating layer 103 may be performed. The oxygen supply process involves supplying oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc., to the insulating layer 103 by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption may be formed on the insulating layer 103, and then oxygen may be added to the insulating layer 103 through the film. It is preferable to remove the film after adding oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0271] [Formation of semiconductor layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (Figure 21D).

[0272] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

[0273] The metal oxide film 108f is preferably a dense film with as few defects as possible. Further, the metal oxide film 108f is preferably a high-purity film in which impurities containing hydrogen elements are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0274] When forming the metal oxide film 108f, it is preferable to use oxygen gas. A schematic cross-sectional view inside the sputtering apparatus when forming the metal oxide film 108f on the insulating layer 103 is shown in FIG. 21C. In FIG. 21C, a target 193 installed inside the sputtering apparatus and a plasma 194 formed below the target 193 are schematically shown. By using oxygen gas when forming the metal oxide film 108f, oxygen can be suitably supplied into the insulating layer 103. For example, when an oxide is used for the insulating film 103a, oxygen can be suitably supplied into the insulating film 103a. In FIG. 21C, the oxygen supplied to the insulating layer 103 is represented by an arrow.

[0275] By supplying oxygen to the insulating layer 103, oxygen is supplied to the semiconductor layer 108 in a later process, and oxygen vacancies V O and V O H in the semiconductor layer 108 can be reduced.

[0276] When forming the metal oxide film, oxygen gas and an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed. Note that the higher the ratio of oxygen gas in the entire film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio), the higher the crystallinity of the metal oxide film can be increased, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and a transistor with an increased on-current can be obtained.

[0277] When forming a metal oxide film, higher substrate temperatures result in a more crystalline and dense metal oxide film. Conversely, lower substrate temperatures result in a less crystalline and more electrically conductive metal oxide film.

[0278] The conditions for forming a metal oxide film are such that the substrate temperature is between room temperature and 250°C, preferably between room temperature and 200°C, and more preferably between room temperature and 140°C. For example, setting the substrate temperature between room temperature and 140°C is preferable as it increases productivity. Furthermore, crystallinity can be reduced by forming the metal oxide film at room temperature or without heating the substrate.

[0279] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103, and a treatment to supply oxygen into the insulating layer 103. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment in an oxygen-containing atmosphere may be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). Plasma treatment containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 103 while supplying oxygen. After such treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 103 to the atmosphere.

[0280] Furthermore, when the semiconductor layer 108 is a laminated structure in which multiple semiconductor layers are stacked, it is preferable to deposit the next metal oxide film continuously after depositing the first metal oxide film without exposing its surface to the atmosphere.

[0281] Next, island-shaped semiconductor layers 108 are formed by etching a portion of the metal oxide film 108f (Figure 22A).

[0282] For processing the metal oxide film 108f, either a wet etching method, a dry etching method, or both may be used. In this case, a portion of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner. For example, the insulating film 103b of the insulating layer 103 may disappear due to etching, exposing the surface of the insulating film 103a.

[0283] Here, it is preferable to perform a heat treatment after the metal oxide film 108f has been formed, or after the metal oxide film 108f has been processed into a semiconductor layer 108. The heat treatment can remove hydrogen or water contained in the metal oxide film 108f or semiconductor layer 108, or adsorbed on the surface. In addition, the heat treatment may improve the film quality of the metal oxide film 108f or semiconductor layer 108 (for example, by reducing defects or improving crystallinity).

[0284] Heat treatment can also supply oxygen from the insulating layer 103 to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing the semiconductor layer 108.

[0285] The heat treatment temperature can typically be 150°C or higher but below the strain point of the substrate, or 200°C or higher but 500°C or lower, or 250°C or higher but 450°C or lower, or 300°C or higher but 450°C or lower.

[0286] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. Alternatively, heating may be performed in such an atmosphere followed by heating in an oxygen-containing atmosphere. Alternatively, heating may be performed in a dry air atmosphere. It is preferable that the atmosphere used for the heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment can be carried out using an electric furnace or an RTA (Restoration Time Adjustment) device. Using an RTA device can shorten the heat treatment time.

[0287] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0288] [Formation of insulating layer 110] Next, the insulating layer 110 is formed by covering the insulating layer 103 and the semiconductor layer 108 (Figure 22B).

[0289] Here, the insulating layer 110 is formed by laminating insulating film 110a, insulating film 110b, and insulating film 110c.

[0290] In particular, each insulating film constituting the insulating layer 110 is preferably formed by the PECVD method. The method for forming each layer constituting the insulating layer 110 can be described by reference to the description in Configuration Example 3 above.

[0291] It is preferable to perform plasma treatment on the surface of the semiconductor layer 108 before depositing the insulating layer 110. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, since impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced, a highly reliable transistor can be realized. This is particularly preferable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating layer 110. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating layer 110 are performed continuously without exposure to the atmosphere.

[0292] Here, it is preferable to perform a heat treatment after forming the insulating layer 110. The heat treatment can remove hydrogen or water contained in or adsorbed on the surface of the insulating layer 110. It can also reduce defects in the insulating layer 110.

[0293] The conditions for heat treatment can be applied as described above.

[0294] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0295] [Formation of opening 142] Next, an opening 142 reaching the conductive layer 106 is formed by etching a portion of the insulating layer 110 and the insulating layer 103 (Figure 22C). This allows the conductive layer 106 and the conductive layer 112, which will be formed later, to be electrically connected through the opening 142.

[0296] [Formation of conductive layer 112] Next, a conductive film 112f, which will become the conductive layer 112, is formed on the insulating layer 110 (Figure 22D).

[0297] It is preferable to use a low-resistance metal or alloy material for the conductive film 112f. Furthermore, it is preferable to use a material for the conductive film 112f that is less likely to release hydrogen and less likely to allow hydrogen to diffuse. Additionally, it is preferable to use a material for the conductive film 112f that is less prone to oxidation.

[0298] For example, the conductive film 112f is preferably deposited by a sputtering method using a sputtering target containing a metal or alloy.

[0299] For example, it is preferable that the conductive film 112f be a laminated film in which a conductive film that is resistant to oxidation and hydrogen diffusion is laminated with a conductive film with low resistance.

[0300] Next, a conductive layer 112 is formed by etching a portion of the conductive film 112f (Figure 23A). For processing the conductive film 112f, either a wet etching method, a dry etching method, or both may be used.

[0301] In this way, by creating a structure in which the upper and side surfaces of the semiconductor layer 108 and the insulating layer 103 are covered without etching the insulating layer 110, it is possible to prevent the semiconductor layer 108 and the insulating layer 103 from being etched and becoming thin when etching the conductive film 112f or the like.

[0302] [Processing of supplying impurity elements] Next, using the conductive layer 112 as a mask, a process is performed to supply (add or implant) impurity elements 140 to the semiconductor layer 108 via the insulating layer 110 (Figure 23B). This makes it possible to form a low-resistance region 108N in the region of the semiconductor layer 108 that is not covered by the conductive layer 112. At this time, it is preferable to determine the conditions for the supply process of impurity elements 140 by considering the material and thickness of the conductive layer 112 and other components that serve as a mask, so that as little as possible is supplied to the region of the semiconductor layer 108 that overlaps with the conductive layer 112. This makes it possible to form a channel-forming region with a sufficiently reduced impurity concentration in the region of the semiconductor layer 108 that overlaps with the conductive layer 112.

[0303] The supply of impurity element 140 can preferably be achieved using plasma ion doping or ion implantation. These methods allow for highly precise control of the depth-direction concentration profile by adjusting the ion acceleration voltage and dose. Plasma ion doping can increase productivity. Furthermore, ion implantation using mass separation can improve the purity of the supplied impurity element.

[0304] In the supply process of impurity element 140, it is preferable to control the processing conditions so that the highest concentration is achieved at the interface between the semiconductor layer 108 and the insulating layer 110, or in a portion of the semiconductor layer 108 close to the interface, or in a portion of the insulating layer 110 close to the interface. This allows for the supply of impurity element 140 at the optimal concentration to both the semiconductor layer 108 and the insulating layer 110 in a single process.

[0305] Examples of the impurity element 140 include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, or noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to use boron, phosphorus, aluminum, magnesium, or silicon.

[0306] As the source gas of the impurity element 140, a gas containing the above impurity element can be used. When supplying boron, typically one or more of B2H6 gas or BF3 gas can be used. When supplying phosphorus, typically PH3 gas can be used. Alternatively, a mixed gas obtained by diluting these source gases with a noble gas may be used.

[0307] In addition, as the source gas, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. The ion source is not limited to gases, and a solid or a liquid heated and vaporized may also be used.

[0308] The addition of the impurity element 140 can be controlled by setting conditions such as acceleration voltage and dose amount in consideration of the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108.

[0309] For example, when boron is added by ion implantation or plasma ion doping, the acceleration voltage can be in the range of, for example, 5 kV or more and 100 kV or less, preferably 7 kV or more and 70 kV or less, and more preferably 10 kV or more and 50 kV or less. The dose amount is, for example, 1×10 13 ions / cm 2 or more and 1×10 17 ions / cm 2 or less, preferably 1×10 14 ions / cm 2 or more and 5×10 16 ions / cm 2 or less, and more preferably 1×10 15 ions / cm 2The above is 3 x 10 16 ions / cm 2 The following range is possible.

[0310] When adding phosphorus ions by ion implantation or plasma ion doping, the acceleration voltage can be in the range of, for example, 10kV to 100kV, preferably 30kV to 90kV, and more preferably 40kV to 80kV. The dose can also be, for example, 1 × 10⁻⁶ 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 × 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 More preferably 1 × 10 15 ions / cm 2 The above 3 x 10 16 ions / cm 2 The following range is possible.

[0311] The method of supplying the impurity element 140 is not limited to this, and other methods such as plasma treatment or treatment utilizing thermal diffusion by heating may also be used. In the case of plasma treatment, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0312] For example, by performing plasma processing in an atmosphere containing hydrogen gas using a plasma CVD apparatus, hydrogen can be supplied as an impurity element 140 to the semiconductor layer 108 in a region that does not overlap with the conductive layer 112. Furthermore, by using a plasma CVD apparatus for both the supply of impurity elements 140 and the formation of the insulating layer 118, the supply of impurity elements 140 and the formation of the insulating layer 118 can be performed continuously within the apparatus, thereby increasing productivity.

[0313] In one aspect of the present invention, impurity elements 140 can be supplied to the semiconductor layer 108 via the insulating layer 110. Therefore, even if the semiconductor layer 108 is crystalline, the damage to the semiconductor layer 108 during the supply of impurity elements 140 is reduced, and the loss of crystallinity can be suppressed. This is therefore suitable in cases where a decrease in crystallinity would increase electrical resistance.

[0314] [Formation of insulating layer 118] Next, an insulating layer 118 is formed by covering the insulating layer 110 and the conductive layer 112 (Figure 23C).

[0315] If the deposition temperature of the insulating layer 118 is too high, impurities contained in the low-resistance region 108N may diffuse to the peripheral area including the channel formation region of the semiconductor layer 108, and the electrical resistance of the low-resistance region 108N may increase. Therefore, the deposition temperature of the insulating layer 118 should be determined taking these factors into consideration.

[0316] For example, the film deposition temperature for the insulating layer 118 is preferably between 150°C and 400°C, more preferably between 180°C and 360°C, and more preferably between 200°C and 250°C. By depositing the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to transistors with short channel lengths.

[0317] After the formation of the insulating layer 118, a heat treatment may be performed. This heat treatment may make the low-resistance region 108N more stable and low-resistance. For example, by performing the heat treatment, the impurity elements 140 may diffuse appropriately and become locally homogenized, and a low-resistance region 108N with an ideal concentration gradient of impurity elements may be formed. However, if the heat treatment temperature is too high (for example, above 500°C), the impurity elements 140 may diffuse into the channel formation region, which may lead to a deterioration of the electrical characteristics and reliability of the transistor.

[0318] The conditions for heat treatment can be applied as described above.

[0319] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, if there is a high-temperature treatment in a later step (e.g., a film deposition process), it may be possible to combine this heat treatment with that step.

[0320] [Formation of openings 141a and 141b] Next, by etching a portion of the insulating layer 118 and insulating layer 110, openings 141a and 141b that reach the low-resistance region 108N are formed (Figure 24A).

[0321] [Formation of insulating layer 130] Next, an insulating layer 130 is formed on the insulating layer 118 so as to cover openings 141a and 141b (Figure 24B).

[0322] The insulating layer 130 has openings 143a and 143b, and the insulating layer 130 is formed such that opening 143a is located inside opening 141a and opening 143b is located inside opening 141b.

[0323] For example, when a photosensitive organic material is used for the insulating layer 130, the insulating layer 130 can be formed by applying a composition containing the organic material by a spin coating method, followed by selective exposure and development. Other formation methods may include sputtering, vapor deposition, droplet ejection (inkjet method), screen printing, or offset printing, one or more of which may be used.

[0324] In this case, it is preferable to perform a heat treatment after the formation of the insulating layer 130. If an organic material is used for the insulating layer 130, the organic material can be cured by the heat treatment.

[0325] The heat treatment temperature is preferably below the heat resistance temperature of the organic material. For example, the heat treatment temperature is preferably 150°C to 350°C, more preferably 180°C to 300°C, more preferably 200°C to 270°C, more preferably 200°C to 250°C, and more preferably 220°C to 250°C.

[0326] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. Alternatively, it may be heated in a dry air atmosphere. It is preferable that the atmosphere used for the heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment can be carried out using an electric furnace or an RTA (Restoration Time Analysis) apparatus.

[0327] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is formed on the insulating layer 130 so as to cover the openings 143a and 143b, and the conductive film is processed into a desired shape to form the conductive layer 120a and conductive layer 120b (Figure 24C).

[0328] By following the above steps, transistor 100A can be manufactured. For example, if transistor 100C is to be applied to the pixels of a display device, a step of forming one or more of the following can be added: a protective insulating layer, a planarization layer, pixel electrodes, or wiring.

[0329] The above is an explanation of manufacturing method example 1.

[0330] Furthermore, when manufacturing the transistor 100 exemplified in Configuration Example 1, the steps for forming the conductive layer 106, the insulating layer 103, and the opening 142 in the above manufacturing method example 1 can be omitted. Also, transistor 100 and transistor 100C can be formed on the same substrate through the same process.

[0331] <Example of manufacturing method 2> The method for fabricating transistor 100D shown in Figures 14A and 14B will be explained. Note that explanations of parts that overlap with what has been previously described will be omitted, and only the differences will be explained.

[0332] Note that we will omit explanations of parts that overlap with Manufacturing Method Example 1, and will provide detailed explanations of the differences.

[0333] First, the insulating layer 110 is formed in the same manner as in example 1 of the manufacturing method (Figure 22B). Since the formation of the insulating layer 110 can be described in the previous section, a detailed explanation is omitted.

[0334] [Formation of metal oxide film 114f] Next, a metal oxide film 114f is formed on the insulating layer 110 (Figure 25B).

[0335] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to form it by sputtering in an atmosphere containing oxygen. Figure 25A shows a schematic cross-sectional view of the inside of a sputtering apparatus when forming the metal oxide film 114f on the insulating layer 110. Figure 25A schematically shows the target 195 installed inside the sputtering apparatus and the plasma 196 formed below the target 195. By using oxygen gas when forming the metal oxide film 114f, oxygen can be suitably supplied into the insulating layer 110. In Figure 25A, the oxygen supplied to the insulating layer 110 is indicated by an arrow.

[0336] By supplying oxygen to the insulating layer 110, oxygen is supplied to the semiconductor layer 108 in a later process, and oxygen deficiencies V in the semiconductor layer 108 are eliminated. O , and V O H can be reduced.

[0337] The above description can be applied when the metal oxide film 114f is formed by a sputtering method using an oxide target containing the same metal oxide as the semiconductor layer 108.

[0338] For example, as a deposition condition for the metal oxide film 114f, the metal oxide film may be formed by a reactive sputtering method using a metal target and oxygen as the deposition gas. If, for example, aluminum is used as the metal target, an aluminum oxide film can be deposited.

[0339] When forming the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more oxygen can be supplied into the insulating layer 110. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to bring the oxygen partial pressure in the deposition chamber as close to 100% as possible.

[0340] In this way, by forming the metal oxide film 114f by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating layer 110 during the deposition of the metal oxide film 114f, while preventing oxygen from escaping from the insulating layer 110. As a result, a large amount of oxygen can be trapped in the insulating layer 110.

[0341] It is preferable to perform a heat treatment after forming the metal oxide film 114f. The heat treatment allows oxygen contained in the insulating layer 110 to be supplied to the semiconductor layer 108. By heating with the metal oxide film 114f covering the insulating layer 110, oxygen is prevented from escaping from the insulating layer 110 to the outside, and a large amount of oxygen can be supplied to the semiconductor layer 108. As a result, oxygen deficiencies in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized.

[0342] The conditions for heat treatment can be applied as described above.

[0343] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0344] The metal oxide film 114f may be removed after the film formation or after the heat treatment.

[0345] [Formation of opening 142] Next, the metal oxide film 114f, the insulating layer 110, and a portion of the insulating layer 103 are etched to form an opening 142 that reaches the conductive layer 106 (Figure 25C).

[0346] [Formation of conductive layer 112] Next, a conductive film 112f, which will become the conductive layer 112, is deposited on the metal oxide film 114f (Figure 25D). A detailed explanation of the conductive film 112f is omitted as it can be found in the previous description.

[0347] Next, the conductive layer 112 and the metal oxide layer 114 are formed by etching a portion of the conductive film 112f and the metal oxide film 114f (Figure 26A). It is preferable to process the conductive film 112f and the metal oxide film 114f using the same resist mask. Alternatively, the etched conductive layer 112 may be used as a hard mask to etch the metal oxide film 114f.

[0348] For etching the conductive film 112f and the metal oxide film 114f, it is particularly preferable to use a wet etching method.

[0349] This makes it possible to form a conductive layer 112 and a metal oxide layer 114 with substantially matching upper surface shapes.

[0350] [Processing of supplying impurity elements] Next, using the conductive layer 112 as a mask, an impurity element 140 is supplied (also called added or implanted) to the semiconductor layer 108 via the insulating layer 110 (Figure 26B). This makes it possible to form a low-resistance region 108N in the region of the semiconductor layer 108 that is not covered by the conductive layer 112. A detailed explanation of the impurity element supply process is omitted as it can be found in the previous description.

[0351] [Formation of insulating layer 118] Next, an insulating layer 118 is formed by covering the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 (Figure 26C). Since the formation of the insulating layer 118 can be found in the previously mentioned description, a detailed explanation is omitted.

[0352] After the formation of the insulating layer 118, a heat treatment may be performed. Since the details of this heat treatment can be found in the previous description, a detailed explanation is omitted.

[0353] [Formation of openings 141a and 141b] Next, openings 141a and 141b, which reach the low-resistance region 108N, are formed by etching a portion of the insulating layer 118 and insulating layer 110 (Figure 27A).

[0354] [Formation of insulating layer 130] Next, an insulating layer 130 is formed on the insulating layer 118 so as to cover openings 141a and 141b (Figure 27B). A detailed explanation of the formation of the insulating layer 130 is omitted as it can be found in the previous description.

[0355] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is formed on the insulating layer 130 so as to cover the openings 143a and 143b, and the conductive film is processed into a desired shape to form the conductive layer 120a and conductive layer 120b (Figure 27C).

[0356] By following the above steps, transistor 100D can be manufactured.

[0357] <Example of manufacturing method 3> The method for fabricating transistor 100G shown in Figures 17A and 17B will be explained. Note that parts that overlap with what has been previously described will be omitted, and only the differences will be explained.

[0358] First, the conductive film 112f is formed, similar to the method in Example 1 (Figure 22D). Since the formation of the conductive film 112f can be described in the previous section, a detailed explanation is omitted.

[0359] Next, a portion of the conductive film 112f is etched to form a conductive layer 112, and then a portion of the insulating layer 110 is etched to expose a portion of the semiconductor layer 108 (Figure 28A). This makes it possible to form a conductive layer 112 and an insulating layer 110 with substantially matching top surface shapes.

[0360] Etching of the insulating layer 110 is preferably performed using a resist mask for etching the conductive film 112f. Alternatively, etching of the insulating layer 110 may be performed in the same process as etching the conductive film 112f, or it may be etched using a different etching method after etching the conductive film 112f.

[0361] For example, the conductive film 112f can be etched by a wet etching method, and then the insulating layer 110 can be etched by a dry etching method. In particular, if the conductive film 112f is processed by a dry etching method, reaction products containing metal may be generated, which may contaminate the semiconductor layer 108 or the insulating layer 110. Therefore, it is preferable to process the conductive film 112f by a wet etching method before etching the insulating layer 110.

[0362] Depending on the etching conditions, the edges of the conductive layer 112 and the insulating layer 110 may not coincide. For example, the edge of the conductive layer 112 may be located inward or outward from the edge of the insulating layer 110.

[0363] During etching of the insulating layer 110, a portion of the exposed semiconductor layer 108 may be etched and thinned. In this case, the semiconductor layer 108 may have a shape in which the thickness of the low-resistance region 108N is thinner than the thickness of the channel formation region.

[0364] During etching of the insulating layer 110, a portion of the insulating layer 103 not covered by the semiconductor layer 108 may be etched and become a thin film. For example, the insulating film 103b in the region not covered by the semiconductor layer 108 may disappear.

[0365] [Formation of insulating layer 116 and insulating layer 118] Next, an insulating layer 116 is formed in contact with the exposed portion of the semiconductor layer 108, followed by the formation of the insulating layer 118 (Figure 28B). The formation of the insulating layer 116 reduces the resistance of the exposed portion of the semiconductor layer 108, forming a low-resistance region 108N.

[0366] The insulating layer 116 can be an insulating film that releases impurity elements that have the function of reducing the resistance of the semiconductor layer 108. In particular, it is preferable to use an inorganic insulating film such as a silicon nitride film, silicon oxide nitride film, or silicon oxynitride film that can release hydrogen. In this case, it is preferable to use a plasma CVD method using a hydrogen-containing film-forming gas so that hydrogen can be supplied to the semiconductor layer 108 even when the insulating layer 116 is formed.

[0367] When silicon nitride is used for the insulating layer 116, it is preferable to form it by a PECVD method using a mixed gas containing silicon, such as silane, and a gas containing nitrogen as the film-forming gas. In this case, it is preferable that hydrogen is contained in the silicon nitride film being formed. This makes it easier to reduce the resistance of a portion of the semiconductor layer 108 by allowing hydrogen in the insulating layer 116 to diffuse into the semiconductor layer 108. Examples of gases containing nitrogen include ammonia or nitrous oxide.

[0368] The insulating layer 116 can also be an insulating film that has the function of creating oxygen vacancies in the semiconductor layer 108. In particular, it is preferable to use an insulating film containing a metal nitride. For example, it is preferable to form it by a reactive sputtering method using a sputtering target containing a metal and a mixed gas of nitrogen gas and a diluent gas such as a rare gas as the film formation gas. This makes it easy to control the film quality of the insulating layer 116 by controlling the flow rate ratio of the film formation gas.

[0369] When using an aluminum nitride film formed by reactive sputtering with an aluminum target for the insulating layer 116, it is preferable that the flow rate of nitrogen gas relative to the total flow rate of the film formation gas be 30% to 100%, preferably 40% to 100%, and more preferably 50% to 100%.

[0370] In this case, it is preferable that the insulating layer 116 and the insulating layer 118 be formed continuously without being exposed to the atmosphere.

[0371] Furthermore, if the insulating layer 118 is provided in contact with the semiconductor layer 108, the process of forming the insulating layer 116 can be omitted.

[0372] Heat treatment may be performed after the deposition of the insulating layer 116 or after the deposition of the insulating layer 118. Heat treatment can promote the reduction of resistance in the low-resistance region 108N.

[0373] The conditions for heat treatment can be applied as described above.

[0374] Note that this heat treatment may be omitted if it is not necessary. Alternatively, the heat treatment may be omitted here and combined with a heat treatment performed in a later step. Furthermore, in some cases, this heat treatment can be combined with a high-temperature treatment in a later step (for example, a film deposition process).

[0375] [Formation of openings 141a and 141b] Next, openings 141a and 141b reaching the low-resistance region 108N are formed in the insulating layer 118 and the insulating layer 116 (Figure 28C).

[0376] [Formation of insulating layer 130] Next, an insulating layer 130 is formed on the insulating layer 118 so as to cover openings 141a and 141b (Figure 29A). A detailed explanation of the formation of the insulating layer 130 is omitted as it can be found in the previous description.

[0377] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is formed on the insulating layer 130 so as to cover the openings 143a and 143b, and the conductive film is processed into a desired shape to form the conductive layer 120a and conductive layer 120b (Figure 29B).

[0378] By following the above steps, a 100G transistor can be manufactured.

[0379] Furthermore, by omitting the formation of the insulating layer 116, the transistor 100E shown in Figures 15A and 15B can be manufactured.

[0380] <Example of manufacturing method 4> The method for fabricating transistor 100F, shown in Figure 16, will be explained. Note that parts that overlap with what has been previously described will be omitted, and only the differences will be explained.

[0381] First, the conductive film 112f is formed, similar to the method in example 3 (Figure 22D). Since the formation of the conductive film 112f can be described in the previous section, a detailed explanation is omitted.

[0382] [Formation of insulating layer 110 and conductive layer 112] Next, a resist mask 115 is formed on the conductive film 112f (Figure 30A). Then, the conductive film 112f is removed in the areas not covered by the resist mask 115 to form a conductive layer 112 (Figure 30B).

[0383] When forming the conductive layer 112, the edges of the conductive layer 112 are processed so that they are located inside the contour of the resist mask 115. A wet etching method can be suitably used to form the conductive layer 112. For example, an etchant containing hydrogen peroxide can be used in the wet etching method. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid can be used. In particular, when using a copper-containing material for the conductive layer 112, an etchant containing phosphoric acid, acetic acid, and nitric acid can be suitably used. The width of region 108L can be controlled by adjusting the etching time.

[0384] To form the conductive layer 112, the conductive film 112f may be etched using an anisotropic etching method, and then the sides of the conductive film 112f may be etched using an isotropic etching method to recess the end faces (also called side etching). This makes it possible to form a conductive layer 112 that is located inside the insulating layer 110 in a plan view.

[0385] Next, the insulating layer 110 in the area not covered by the resist mask 115 is removed to form an insulating layer 110 (Figure 30C). Either a wet etching method or a dry etching method, or both, can be used to form the insulating layer 110. Although the insulating layer 110 may be formed after removing the resist mask 115, leaving the resist mask 115 in place can prevent the thickness of the conductive layer 112 from becoming too thin.

[0386] After the insulating layer 110 is formed, the resist mask 115 is removed.

[0387] [Plasma treatment] Next, plasma treatment may be performed. Plasma treatment creates oxygen vacancies in the semiconductor layer 108 in regions that do not overlap with the conductive layer 112. O It is possible to form this.

[0388] Plasma treatment can be performed using an atmosphere containing nitrogen, hydrogen, or one or more noble gases. For example, an argon gas atmosphere is preferably used for plasma treatment. Alternatively, plasma treatment may use a mixed gas containing the aforementioned multiple gases. For example, a mixed gas atmosphere of argon and nitrogen gas is preferably used for plasma treatment.

[0389] Oxygen vacancies V formed in semiconductor layer 108 O This is due to hydrogen in semiconductor layer 108. O As the value becomes H, the carrier concentration in the semiconductor layer 108 in the region that does not overlap with the conductive layer 112 increases. In other words, by performing plasma treatment, the resistance of region 108L and the low-resistance region 108N can be lowered (see Figure 16B).

[0390] Since region 108L is subjected to plasma treatment via the insulating layer 110, the oxygen deficiency V formed is different compared to the low-resistance region 108N. O The amount becomes similar or less. Therefore, region 108L has a carrier concentration that is similar to or lower than that of the low-resistance region 108N.

[0391] When forming the insulating layer 118 using a PECVD apparatus, the plasma treatment can be performed using the same apparatus. Furthermore, the plasma treatment and the formation of the insulating layer 118 can be performed continuously in the same processing chamber where the insulating layer 118 is formed.

[0392] Next, the insulating layer 118 is formed. Since the process from the formation of the insulating layer 118 onward can be described in the aforementioned example of the manufacturing method 3, a detailed explanation is omitted.

[0393] By following the above steps, transistor 100F can be manufactured.

[0394] <Example of manufacturing method 5> The method for fabricating transistor 100H, shown in Figures 18A to 18C, will be explained below. Note that explanations of parts that overlap with previous descriptions will be omitted, and only the differences will be explained.

[0395] First, the insulating layer 130 is formed in the same manner as in example 1 of the manufacturing method (Figure 24B). Since the formation of the insulating layer 130 can be described in the previous section, a detailed explanation is omitted.

[0396] [Formation of insulating layer 132] Next, an insulating layer 132 is formed on the insulating layer 118 so as to cover the openings 143a and 143b (Figure 31A).

[0397] The film formation temperature of the insulating layer 132 is preferably below the heat resistance temperature of the organic material. For example, the heat treatment temperature is preferably 150°C to 350°C, more preferably 180°C to 300°C, more preferably 200°C to 270°C, more preferably 200°C to 250°C, and more preferably 220°C to 250°C.

[0398] [Formation of openings 149a and 149b] Next, openings 149a and 149b reaching the low-resistance region 108N are formed in the insulating layer 132 (Figure 31B).

[0399] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is formed on the insulating layer 132 so as to cover the openings 149a and 149b, and the conductive film is processed into a desired shape to form the conductive layer 120a and conductive layer 120b (Figure 31C).

[0400] By following the above steps, transistor 100H can be manufactured.

[0401] <Components of a semiconductor device> The following describes the components included in the semiconductor device of this embodiment.

[0402] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., may be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is mounted may be used as the substrate 102.

[0403] A flexible substrate may be used as the substrate 102, and the semiconductor device may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer can be used to separate the semiconductor device from the substrate 102 after it has been partially or completely completed and to transfer it to another substrate. In this case, the semiconductor device can be transferred to a substrate with poor heat resistance or a flexible substrate.

[0404] [Conductive film] The conductive layers 112 and 106, which function as gate electrodes, and the conductive layer 120a, which functions as one of the source electrode or drain electrode, and the conductive layer 120b, which functions as the other, can each be formed using one or more metallic elements selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, alloys composed of the above metallic elements, or alloys combining the above metallic elements.

[0405] The conductive layers 112, 106, 120a, and 120b can also be made of oxide conductors or metal oxides such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide.

[0406] Here, we will explain oxide conductors (OC). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0407] The conductive layer 112, etc., may have a laminated structure of a conductive film containing the above-mentioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced. In this case, it is preferable to apply a conductive film containing an oxide conductor to the side that is in contact with the insulating layer that functions as a gate insulating layer.

[0408] The conductive layers 112, 106, 120a, and 120b preferably contain one or more of the above-mentioned metallic elements, particularly titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferred. This tantalum nitride film is conductive, has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself, making it suitable for use as a conductive film in contact with the semiconductor layer 108 or as a conductive film in the vicinity of the semiconductor layer 108.

[0409] [Semiconductor layer] When the semiconductor layer 108 is an In-M-Zn oxide, possible atomic ratios of metal elements in the sputtering target used to deposit the In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:8, etc. Furthermore, if element M includes two or more elements as described above, the proportion of M in the atomic ratio shall correspond to the sum of the atomic numbers of those two or more metallic elements.

[0410] Using a sputtering target containing a polycrystalline oxide is preferable because it facilitates the formation of a crystalline semiconductor layer 108. The atomic ratio of the deposited semiconductor layer 108 includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, if the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the deposited semiconductor layer 108 may be close to In:Ga:Zn=4:2:3 [atomic ratio].

[0411] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wider energy gap than silicon in this way, the off-current of the transistor can be reduced.

[0412] The semiconductor layer 108 is preferably a non-single-crystal structure. Non-single-crystal structures include, for example, the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described later. Among non-single-crystal structures, the amorphous structure has the highest defect level density, and the CAAC structure has the lowest defect level density.

[0413] The following section describes CAAC (c-axis aligned crystal). CAAC represents one example of a crystal structure.

[0414] CAAC structure is a type of crystalline structure found in thin films and other materials that have multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). In this structure, each nanocrystal has its c-axis oriented in a specific direction, while its a-axis and b-axis are not oriented, and the nanocrystals are continuously connected to each other without forming grain boundaries. In particular, thin films with a CAAC structure tend to have the c-axis of each nanocrystal oriented in the direction of the film's thickness, the direction normal to the surface it is formed on, or the direction normal to the surface of the film.

[0415] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. Furthermore, because clear grain boundaries cannot be observed in CAAC-OS, it is less susceptible to the reduction in electron mobility caused by grain boundaries. Also, since the crystallinity of oxide semiconductors can decrease due to impurities or defects, CAAC-OS can be considered an oxide semiconductor with fewer impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors containing CAAC-OS have stable physical properties. Consequently, oxide semiconductors containing CAAC-OS are highly heat-resistant and reliable.

[0416] In crystallography, it is common to define a unit cell with a specific axis designated as the c axis, among the three axes (crystal axes) a, b, and c that constitute the unit cell. In particular, in crystals with a layered structure, it is common to define the two axes parallel to the plane direction of the layer as the a and b axes, and the axis intersecting the layer as the c axis. A typical example of such a layered crystal is graphite, which is classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the cleavage planes, and the c axis is perpendicular to the cleavage planes. For example, the crystal of InGaZnO4, which has a layered YbFe2O4 type crystal structure, can be classified as a hexagonal crystal system, where the a and b axes of its unit cell are parallel to the plane direction of the layer, and the c axis is perpendicular to the layer (i.e., the a and b axes).

[0417] In oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films), the crystalline regions may not be clearly visible in TEM observation images. The crystalline regions in microcrystalline oxide semiconductor films are often between 1 nm and 100 nm in size, or between 1 nm and 10 nm. In particular, oxide semiconductor films containing nanocrystals (nc) that are microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm, are called nc-OS (nanocrystalline oxide semiconductor) films. Furthermore, in nc-OS films, the grain boundaries may not be clearly visible in TEM observation images, for example.

[0418] nc-OS films exhibit periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). Furthermore, nc-OS films show no regularity in crystal orientation between different crystalline regions. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. For example, when structural analysis of an nc-OS film is performed using an XRD instrument with an X-ray diameter larger than that of the crystalline region, out-of-plane analysis does not detect peaks indicating crystal planes. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the crystalline region (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the crystal region (for example, 1 nm to 30 nm), a ring-shaped region of high brightness is observed in a circular pattern, and multiple spots may be observed within this ring-shaped region.

[0419] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-OS films lack regularity in crystal orientation between different crystalline regions. Therefore, nc-OS films have a higher defect level density compared to CAAC-OS films. Consequently, nc-OS films may have a higher carrier concentration and higher electron mobility compared to CAAC-OS films. Therefore, transistors using nc-OS films may exhibit high field-effect mobility.

[0420] nc-OS films can be formed by reducing the oxygen flow rate ratio during deposition compared to CAAC-OS films. Furthermore, nc-OS films can also be formed by lowering the substrate temperature during deposition compared to CAAC-OS films. For example, nc-OS films can be deposited at relatively low substrate temperatures (e.g., below 130°C) or even without heating the substrate, making them suitable for use with large glass or resin substrates and increasing productivity.

[0421] An example of a metal oxide crystal structure is described below. Metal oxides formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) at a substrate temperature between 100°C and 130°C tend to adopt either an nc (nano crystal) structure or a CAAC structure, or a mixed structure of both. On the other hand, metal oxides formed at room temperature tend to adopt an nc crystal structure. Note that room temperature here includes the temperature when the substrate is not heated.

[0422] <Composition of metal oxides> The following describes the configuration of a CAC (Cloud-Aligned Composite)-OS that can be used in a transistor disclosed in one aspect of the present invention.

[0423] Note that CAAC (c-axis aligned crystal) represents an example of a crystal structure, while CAC (Cloud-Aligned Composite) represents an example of a function or material composition.

[0424] CAC-OS or CAC-metal oxide is a material that possesses conductive properties in some parts, insulating properties in others, and semiconductor properties as a whole. When CAC-OS or CAC-metal oxide is used as the active layer of a transistor, the conductive function is the function of allowing electrons (or holes) to flow, and the insulating function is the function of preventing electrons from flowing. By making the conductive and insulating functions work complementaryly, a switching function (on / off function) can be given to CAC-OS or CAC-metal oxide. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

[0425] CAC-OS or CAC-metal oxide has conductive regions and insulating regions. The conductive regions have the conductive function described above, and the insulating regions have the insulating function described above. Furthermore, the conductive regions and insulating regions may be separated at the nanoparticle level within the material. Also, the conductive regions and insulating regions may be unevenly distributed within the material. In addition, the conductive regions may be observed as blurred around the edges and connected in a cloud-like manner.

[0426] In CAC-OS or CAC-metal oxide, conductive regions and insulating regions may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0427] CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide band gap due to an insulating region and a component with a narrow band gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component with the narrow band gap. Furthermore, the component with the narrow band gap acts complementaryly to the component with the wide band gap, and carriers also flow in the component with the wide band gap in conjunction with the component with the narrow band gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, i.e., a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0428] In other words, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0429] The above is an explanation of the composition of metal oxides.

[0430] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0431] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0432] (Embodiment 2) This embodiment describes an example of a display device having the transistors illustrated in the previous embodiment.

[0433] <Example Configuration> Figure 32A shows a top view of the display device 700. The display device 700 has a first substrate 701 and a second substrate 705 bonded together by a sealing material 712. In the region sealed by the first substrate 701, the second substrate 705, and the sealing material 712, a pixel section 702, a source driver circuit section 704, and a gate driver circuit section 706 are provided on the first substrate 701. Multiple display elements are provided on the pixel section 702.

[0434] An FPC terminal section 708 is provided on the first substrate 701 in a portion that does not overlap with the second substrate 705, to which an FPC 716 (FPC: Flexible printed circuit) is connected. Various signals are supplied to the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706, respectively, via the FPC terminal section 708 and the signal line 710.

[0435] Multiple gate driver circuits 706 may be provided. Furthermore, the gate driver circuit 706 and the source driver circuit 704 may each be formed separately on a semiconductor substrate or the like and packaged as an IC chip. This IC chip can be mounted on the first substrate 701 or on the FPC 716.

[0436] A transistor that is a semiconductor device according to one aspect of the present invention can be applied to the transistors in the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706.

[0437] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. Liquid crystal elements can include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. Examples of light-emitting elements include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), QLEDs (Quantum-dot LEDs), and semiconductor lasers. Furthermore, display elements employing shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used.

[0438] The display device 700A shown in Figure 32B is an example of a display device that can be used as a flexible display, in which a flexible resin layer 743 is applied in place of the first substrate 701.

[0439] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. Also, as shown in region P1 in Figure 32B, the pixel section 702 and a portion of the resin layer 743 have notches. A pair of gate driver circuit sections 706 are provided on both sides of the pixel section 702. The gate driver circuit sections 706 are also provided along the arc-shaped contour at the corners of the pixel section 702.

[0440] The resin layer 743 has a protruding shape in which the FPC terminal portion 708 is provided. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, can be folded back to the other side in area P2 in Figure 32B. By folding back a portion of the resin layer 743, the display device 700A can be mounted on the electronic device with the FPC 716 overlapping the back side of the pixel portion 702, thereby saving space in the electronic device.

[0441] The FPC716 connected to the display device 700A has an IC717 mounted on it. The IC717 functions, for example, as a source driver circuit. In this case, the source driver circuit section 704 in the display device 700A can be configured to include at least one of the following: a protection circuit, a buffer circuit, a demultiplexer circuit, etc.

[0442] The display device 700B shown in Figure 32C is a display device that can be suitably used in electronic devices having a large screen. For example, it can be suitably used in television equipment, monitor equipment, personal computers (including notebook or desktop types), tablet terminals, digital signage, and the like.

[0443] The display device 700B has multiple source driver ICs 721 and a pair of gate driver circuit sections 722.

[0444] Multiple source driver ICs 721 are each mounted on an FPC 723. Furthermore, one terminal of each FPC 723 is connected to the first board 701, and the other terminal is connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be positioned on the back of the pixel section 702, allowing it to be mounted in an electronic device and thus saving space in the electronic device.

[0445] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to realize electronic devices with a narrow bezel.

[0446] This configuration makes it possible to realize large and high-resolution display devices. For example, it is possible to create display devices with screen sizes of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. Furthermore, it is possible to create display devices with extremely high resolutions such as 4K2K or 8K4K.

[0447] <Example of cross-sectional configuration> In the following, configurations using liquid crystal elements and EL elements as display elements will be explained with reference to Figures 33 to 36. Figures 33 to 35 are cross-sectional views of the display device 700 shown in Figure 32A along the dashed line QR, respectively. Figure 36 is a cross-sectional view of the display device 700A shown in Figure 32B along the dashed line ST. Figures 33 and 34 show configurations using liquid crystal elements as display elements, and Figures 35 and 36 show configurations using EL elements.

[0448] [Explanation of common parts of display devices] The display device shown in Figures 33 to 36 includes a wiring section 711, a pixel section 702, a source driver circuit section 704, and an FPC terminal section 708. The wiring section 711 has signal lines 710. The pixel section 702 has a transistor 750 and a capacitive element 790. The source driver circuit section 704 has a transistor 752. Figure 34 shows the case where the capacitive element 790 is absent.

[0449] Transistors 750 and 752 can be the transistors exemplified in Embodiment 1.

[0450] The transistor used in this embodiment has an oxide semiconductor film that has been purified to suppress the formation of oxygen vacancies. This transistor can reduce the off-current. Therefore, the holding time of electrical signals such as image signals can be extended, and the writing interval of image signals can also be set to a longer interval. As a result, the frequency of refresh operations can be reduced, which has the effect of reducing power consumption.

[0451] The transistors used in this embodiment can achieve relatively high field-effect mobility, enabling high-speed driving. For example, by using such high-speed driving transistors in a display device, the switching transistors in the pixel section and the driver transistors used in the driving circuit section can be formed on the same substrate. In other words, a configuration that does not require a driving circuit formed from a silicon wafer or the like is possible, reducing the number of components in the display device. Furthermore, by using high-speed driving transistors in the pixel section, high-quality images can be provided.

[0452] The capacitive element 790 shown in Figures 33, 35, and 36 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has low resistance, similar to the source and drain regions of the transistor 750. Furthermore, a portion of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. In other words, the capacitive element 790 has a laminated structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. In addition, wiring obtained by processing the same film as the source and drain electrodes of the transistor is connected to the upper electrode.

[0453] A planarizing insulating film 770 is provided on transistors 750, 752, and capacitive element 790.

[0454] The transistor 750 in the pixel section 702 and the transistor 752 in the source driver circuit section 704 may be transistors with different structures. For example, one may be a top-gate type transistor and the other a bottom-gate type transistor. Similarly to the source driver circuit section 704, the gate driver circuit section 706 may use a transistor with the same structure as transistor 750, or it may use a transistor with a different structure.

[0455] The signal line 710 is formed of the same conductive film as the source and drain electrodes of transistor 750 or transistor 752. In this case, using a low-resistance material such as a material containing copper is preferable because it reduces signal delays caused by wiring resistance, enabling display on a large screen.

[0456] The FPC terminal section 708 includes wiring 760, an anisotropic conductive film 780, and the FPC 716, some of which function as connecting electrodes. The wiring 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source and drain electrodes of transistor 750 or transistor 752.

[0457] The first substrate 701 and the second substrate 705 can be flexible substrates such as glass substrates or plastic substrates. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer between the first substrate 701 and the transistor 750, etc., which has barrier properties against impurities containing hydrogen.

[0458] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0459] [Example configuration of a display device using liquid crystal elements] The display device 700 shown in Figure 33 has a liquid crystal element 775. The liquid crystal element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planarizing insulating film 770 and functions as a pixel electrode.

[0460] The conductive layer 772 can be made of a material that is transparent to visible light or a material that is reflective to visible light. For the transparent material, for example, an oxide material containing indium, zinc, tin, etc., is suitable. For the reflective material, for example, a material containing aluminum, silver, etc., is suitable.

[0461] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, if a translucent material is used for the conductive layer 772, it becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich the liquid crystal elements.

[0462] A structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may also be used as the structure 778.

[0463] The display device 700 shown in Figure 34 is an example that uses a transverse electric field type (e.g., FFS mode) liquid crystal element 775. A conductive layer 774, which functions as a common electrode, is provided on the conductive layer 772 via an insulating layer 773. The orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive layer 772 and the conductive layer 774.

[0464] In Figure 34, the retaining capacitance can be configured by a laminated structure of conductive layer 774, insulating layer 773, and conductive layer 772. Therefore, there is no need to provide a separate capacitive element, and the aperture ratio can be increased.

[0465] Although not shown in Figures 33 and 34, a configuration in which an alignment film in contact with the liquid crystal layer 776 is provided is also possible. Furthermore, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, as well as light sources such as backlights and sidelights, can be provided as appropriate.

[0466] The liquid crystal layer 776 can be made of thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. Furthermore, when employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0467] The liquid crystal element can utilize modes such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, and guest host mode.

[0468] A scattering-type liquid crystal, such as a polymer-dispersed liquid crystal or a polymer-network liquid crystal, can also be used for the liquid crystal layer 776. In this case, the configuration may be one that displays in black and white without a colored film 736, or one that displays in color using a colored film 736.

[0469] As a driving method for the liquid crystal elements, a time-division display method (also called a field sequential driving method) that performs color display based on a time-additive color mixing method may be applied. In that case, a configuration without a colored film 736 can be used. When using a time-division display method, there is no need to provide subpixels that exhibit each of the colors, such as R (red), G (green), and B (blue), which has advantages such as improving the aperture ratio of the pixels or increasing the resolution.

[0470] [Display devices using light-emitting elements] The display device 700 shown in Figure 35 has a light-emitting element 782. The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 has a light-emitting material such as an organic compound or an inorganic compound.

[0471] The light-emitting material can be fluorescent material, phosphorescent material, thermally activated delayed fluorescence (TADF) material, or inorganic compound (such as quantum dot material).

[0472] The display device 700 shown in Figure 35 is provided with an insulating film 730 covering a portion of the conductive layer 772 on a planar insulating film 770. Here, the light-emitting element 782 has a translucent conductive film 788 and is a top-emission type light-emitting element. The light-emitting element 782 may have a bottom-emission structure that emits light towards the conductive layer 772, or a dual-emission structure that emits light towards both the conductive layer 772 and the conductive film 788.

[0473] The colored film 736 is provided in a position that overlaps with the light-emitting element 782. The light-shielding film 738 is provided in a position that overlaps with the insulating film 730, in the routing wiring section 711, and in the source driver circuit section 704. The colored film 736 and the light-shielding film 738 are covered with the insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that when the EL layer 786 is formed in an island-like manner for each pixel or in a striped manner for each row of pixels, i.e., formed by color separation, the colored film 736 may be omitted.

[0474] Figure 36 shows a configuration of a display device that can be suitably applied to a flexible display. Figure 36 is a cross-sectional view of the display device 700A shown in Figure 32B along the dashed line ST.

[0475] The display device 700A shown in Figure 36 has a configuration in which a support substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated, instead of the first substrate 701 shown in Figure 35. The transistor 750 and capacitive elements 790, etc., are provided on the insulating layer 744 which is provided on the resin layer 743.

[0476] The support substrate 745 is a substrate containing an organic resin or glass, and is thin enough to be flexible. The resin layer 743 is a layer containing an organic resin such as polyimide resin or acrylic resin. The insulating layer 744 contains an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. It is preferable that the resin layer 743 is thinner than the support substrate 745.

[0477] The display device 700A shown in Figure 36 has a protective layer 740 instead of the second substrate 705 shown in Figure 35. The protective layer 740 is bonded to the sealing film 732. The protective layer 740 can be made of a glass substrate or a resin film, etc. Alternatively, the protective layer 740 may be made of optical elements such as polarizing plates or scattering plates, input devices such as touch sensor panels, or a configuration in which two or more of these are laminated together.

[0478] The EL layer 786 of the light-emitting element 782 is provided in an island-like manner on the insulating film 730 and the conductive layer 772. By making the EL layer 786 emit different colors for each sub-pixel, color display can be achieved without using a colored film 736. In addition, a protective layer 741 is provided covering the light-emitting element 782. The protective layer 741 has the function of preventing impurities such as water from diffusing into the light-emitting element 782. It is preferable to use an inorganic insulating film for the protective layer 741. It is even more preferable to have a laminated structure containing one or more inorganic insulating films and one or more organic insulating films.

[0479] Figure 36 shows the bendable region P2. Region P2 includes areas where no inorganic insulating film is provided, in addition to the support substrate 745 and adhesive layer 742, such as the insulating layer 744. Furthermore, a resin layer 746 is provided in region P2, covering the wiring 760. By minimizing the amount of inorganic insulating film in the bendable region P2 and by laminating only a conductive layer containing metal or alloy and a layer containing organic material, it is possible to prevent cracks from occurring when bent. In addition, by not providing the support substrate 745 in region P2, a portion of the display device 700A can be bent with an extremely small radius of curvature.

[0480] An input device may be provided with the display device 700 or display device 700A shown in Figures 33 to 36. Examples of such input devices include touch sensors.

[0481] For example, various sensor types can be used, such as capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive types. Alternatively, two or more of these may be used in combination.

[0482] The configuration of the touch panel may include an in-cell type touch panel in which the input device is formed between a pair of circuit boards, an on-cell type touch panel in which the input device is formed on the display device 700, or an out-cell type touch panel in which the input device is attached to the display device 700.

[0483] [Variation] The following describes a modified version of the display device that differs in some configurations from the one described above.

[0484] Figure 37A is a schematic cross-sectional view of the display device 800. The display device 800 has light-emitting elements 820R, 820G, and 820B on a substrate 801. Light-emitting element 820R is a red-emitting element, light-emitting element 820G is a green-emitting element, and light-emitting element 820B is a blue-emitting element. Note that light-emitting elements 820R, 820G, and 820B are sometimes collectively referred to as light-emitting element 820.

[0485] The substrate 801 can be a circuit board having transistors or wiring. For example, the semiconductor device shown in Embodiment 1 can be suitably used. When a passive matrix method or a segment method can be applied, an insulating substrate such as a glass substrate can be used as the substrate 801. Furthermore, the substrate 801 is a substrate on which semiconductor circuits that function as circuits for driving each light-emitting element (also called pixel circuits), or drive circuits for driving said pixel circuits, are provided.

[0486] The light-emitting element 820R has a conductive layer 811, a reflective layer 812, an insulating layer 813, a conductive layer 814R, an EL layer 815, and a conductive layer 816. The light-emitting element 820G has a conductive layer 811, a reflective layer 812, an insulating layer 813, a conductive layer 814G, an EL layer 815, and a conductive layer 816. The light-emitting element 820B has a conductive layer 811, a reflective layer 812, an insulating layer 813, a conductive layer 814B, an EL layer 815, and a conductive layer 816. Note that the conductive layers 814R, 814G, and 814B may be collectively referred to as the conductive layer 814.

[0487] The conductive layer 811 functions as the lower electrode, and the conductive layer 816 functions as the upper electrode. The reflective layer 812 provided on the conductive layer 811 has the function of reflecting visible light. The insulating layer 813 and the conductive layer 814 have the function of transmitting visible light, and the conductive layer 816 has both transmittance and reflectivity to visible light. The EL layer 815 contains a light-emitting compound.

[0488] The conductive layer 814 on each light-emitting element 820 has a different thickness for each light-emitting element. Of the three conductive layers 814, conductive layer 814B is the thinnest, and conductive layer 814R is the thickest. Here, as shown in Figure 37A, the distance between the upper surface of the reflective layer 812 and the lower surface of the conductive layer 816 (i.e., the interface between the conductive layer 816 and the EL layer 815) in each light-emitting element is defined as distance D. R Distance D G Distance D B In this case, the distance D R The largest, distance DB This is the smallest. Distance D R Distance D G Distance D B The difference corresponds to the difference in optical distance (optical path length) in each light-emitting element.

[0489] Of the three light-emitting elements, element 820R has the longest optical path length, and therefore emits light R, in which the longest wavelength light is most strongly concentrated. On the other hand, element 820B has the shortest optical path length, and therefore emits light B, in which the shortest wavelength light is most strongly concentrated. Element 820G emits light G, in which light of intermediate wavelengths is most strongly concentrated. For example, light R can be light in which red light is strongly concentrated, light G can be light in which green light is strongly concentrated, and light B can be light in which blue light is strongly concentrated.

[0490] This configuration eliminates the need to create separate EL layers for each different colored light-emitting element (EL) of the EL-emitting element 820, allowing for highly color-reproducible color displays using elements with the same configuration. Furthermore, it enables the arrangement of the EL-emitting elements 820 at extremely high density. For example, it can realize a display device with a resolution exceeding 5000 ppi.

[0491] The substrate 801 and the conductive layer 811 of the light-emitting element 820 are electrically connected via a plug 831. The plug 831 is formed to be embedded in an opening provided in the insulating layer 821. The conductive layer 811 is provided in contact with the upper surface of the plug 831.

[0492] In the display device 800, the EL layer 815 and the conductive layer 816 are separated between adjacent light-emitting elements of different colors. This prevents leakage current from flowing through the EL layer 815 between adjacent light-emitting elements of different colors. Therefore, the light emission caused by such leakage current can be suppressed, enabling a display with high contrast. Furthermore, even when increasing the resolution, a highly conductive material can be used for the EL layer 815, thus broadening the range of material choices and making it easier to improve efficiency, reduce power consumption, and improve reliability.

[0493] The EL layer 815 and the conductive layer 816 may be formed into island-like patterns by deposition using a shadow mask such as a metal mask, but it is particularly preferable to use a processing method that does not use a metal mask. This makes it possible to form extremely fine patterns, and thus improves the fineness and aperture ratio compared to the formation method using a metal mask. Typical processing methods that can be used for this purpose include photolithography. Other formation methods such as nanoimprint lithography and sandblasting can also be used.

[0494] In this specification, devices using a metal mask or an FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as an MM (metal mask) structure. Furthermore, in this specification, devices that do not use a metal mask or an FMM may be referred to as an MML (metal maskless) structure.

[0495] The method for manufacturing the display device 800 involves first depositing the EL layer 815 and the conductive layer 816 without using a metal mask, and then forming a resist mask on the conductive layer 816. Subsequently, the parts of the EL layer 815 and conductive layer 816 not covered by the resist mask are removed by etching, and then the resist mask is removed. Finally, an insulating layer 118 is formed. This allows the display device 800 to be manufactured.

[0496] In the display device 800, an insulating layer 818 is provided covering the light-emitting elements 820B, 820G, and 820R. Between adjacent light-emitting elements, a portion of the insulating layer 818 is in contact with the upper surface of the insulating layer 817. The insulating layer 818 functions as a protective layer to prevent impurities such as water from diffusing into the light-emitting elements. It is preferable to use an inorganic insulating film with low moisture permeability, such as a silicon oxide film, a silicon nitride film, or an aluminum oxide film, for the insulating layer 818.

[0497] The display device 800A shown in Figure 37B differs from the display device 800 in that it has a plug 830 and the configuration of the conductive layers 814R, 814G, and 814B are different.

[0498] The display device 800A has a reflective layer 812, an insulating layer 813, and a conductive layer 814 stacked in that order on a conductive layer 811 formed at a distance from each other. The thickness of the conductive layer 814 differs for each light-emitting element. Since the conductive layer 814 is electrically connected to the conductive layer 811 via a plug 830, it is not necessary to make the conductive layer 814 larger than the conductive layer 811. With this configuration, the conductive layer 811, which functions as a pixel electrode, can be made larger, and furthermore, since there is no need to provide contact between the conductive layer 814 and the conductive layer 811, the aperture ratio of the pixels can be increased.

[0499] Figure 37B shows a configuration in which the plug 830 is embedded in the insulating layer 813 and the reflective layer 812, but the present invention is not limited to this. The plug 830 may be embedded in the insulating layer 813 and in contact with the reflective layer 812. In this case, the reflective layer 812 and the plug 830 may be in contact without providing the conductive layer 811, but if the reflective layer 812 is thin, the reflective layer 812 may be penetrated when forming an opening in the insulating layer 813 to form the plug 830, so it is preferable to provide the conductive layer 811.

[0500] In the display device 800 and the display device 800A, it is preferable that the EL layer 815 and the conductive layer 816 are processed so that they are continuous without being interrupted between pixels of the same color. For example, the EL layer 815 and the conductive layer 816 can be processed in a stripe pattern. This allows the conductive layer 816 of all light-emitting elements to be given a predetermined potential without being in a floating state.

[0501] Figures 37A and 37B illustrate a structure in which the EL layer 815 emits different colors for each R, G, and B pixel (also known as a Side By Side (SBS) structure), but the present invention is not limited to this. For example, each of the R, G, and B pixels may have a white-emitting EL layer, and a colored layer (so-called a color filter) may be provided on the side from which light is emitted from the white-emitting EL layer. Furthermore, a structure in which multiple light-emitting units are connected in series via an intermediate layer (charge generation layer) (also known as a tandem structure) may be used as the white-emitting EL layer. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made. In this specification, a light-emitting element having a white-emitting EL layer may be referred to as a white light-emitting element.

[0502] When comparing the aforementioned white light-emitting elements (single or tandem structure) with SBS structure light-emitting elements, SBS structure light-emitting elements can consume less power than white light-emitting elements. Therefore, SBS structure light-emitting elements are preferable when minimizing power consumption. On the other hand, white light-emitting elements are preferable because their manufacturing process is simpler than that of SBS structure light-emitting elements, resulting in lower manufacturing costs or higher manufacturing yields.

[0503] The above is an explanation of the variations.

[0504] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0505] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0506] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention will be described with reference to Figures 38A to 38C.

[0507] The display device shown in Figure 38A includes a pixel section 502, a drive circuit section 504, a protection circuit 506, and a terminal section 507. The protection circuit 506 may be omitted.

[0508] A transistor according to one aspect of the present invention can be applied to the transistors in the pixel section 502 and the transistors in the drive circuit section 504. Furthermore, a transistor according to one aspect of the present invention may also be applied to the protection circuit 506.

[0509] The pixel unit 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (where X and Y are independent natural numbers of 2 or more). Each pixel circuit 501 has a circuit for driving a display element.

[0510] The drive circuit section 504 includes drive circuits such as a gate driver 504a that outputs a scan signal to gate lines GL_1 to GL_X, and a source driver 504b that supplies data signals to data lines DL_1 to DL_Y. The gate driver 504a may be configured to include at least a shift register. The source driver 504b may be configured using, for example, multiple analog switches. Alternatively, the source driver 504b may be configured using a shift register or the like.

[0511] The terminal section 507 refers to the part of the device that is equipped with terminals for inputting power, control signals, and image signals from an external circuit to the display device.

[0512] The protection circuit 506 is a circuit that makes a wire it is connected to conduct when a potential outside a certain range is applied to that wire. The protection circuit 506 shown in Figure 38A is connected to various wires, such as the gate line GL, which is the wire between the gate driver 504a and the pixel circuit 501, or the data line DL, which is the wire between the source driver 504b and the pixel circuit 501. In Figure 38A, the protection circuit 506 is hatched to distinguish it from the pixel circuit 501.

[0513] The gate driver 504a and the source driver 504b may each be provided on the same substrate as the pixel unit 502, or a separate substrate (for example, a drive circuit substrate made of a single-crystal semiconductor or polycrystalline semiconductor) on which the gate driver circuit or source driver circuit is formed may be mounted on the substrate on which the pixel unit 502 is provided by COG or TAB (Tape Automated Bonding).

[0514] The multiple pixel circuits 501 shown in Figure 38A can be configured as shown in Figure 38B or Figure 38C, for example.

[0515] The pixel circuit 501 shown in Figure 38B includes a liquid crystal element 570, a transistor 550, and a capacitive element 560. Data lines DL_n, gate lines GL_m, potential supply lines VL, etc., are also connected to the pixel circuit 501.

[0516] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by the data being written. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 in each of the multiple pixel circuits 501. Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in each row of the pixel circuit 501.

[0517] The pixel circuit 501 shown in Figure 38C includes transistors 552 and 554, a capacitive element 562, and a light-emitting element 572. Data lines DL_n, gate line GL_m, potential supply line VL_a, and potential supply line VL_b are also connected to the pixel circuit 501.

[0518] A high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is supplied to the other. The current flowing through the light-emitting element 572 is controlled according to the potential supplied to the gate of transistor 554, thereby controlling the luminescence brightness from the light-emitting element 572.

[0519] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., can be implemented by appropriately combining at least a part of them with other configuration examples or drawings, etc.

[0520] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0521] (Embodiment 4) The following describes a pixel circuit equipped with memory for correcting the gradation displayed on a pixel, and a display device having the same. The transistor exemplified in Embodiment 1 can be applied to the transistor used in the pixel circuit exemplified below.

[0522] <Circuit Configuration> Figure 39A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 includes transistor M1, transistor M2, capacitor C1, and circuit 401. Wiring S1, S2, G1, and G2 are connected to the pixel circuit 400.

[0523] Transistor M1 has its gate connected to wiring G1, one of its source and drain connected to wiring S1, and the other connected to one electrode of capacitor C1. Transistor M2 has its gate connected to wiring G2, one of its source and drain connected to wiring S2, the other connected to the other electrode of capacitor C1, and circuit 401.

[0524] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element, but typically, light-emitting elements such as organic EL elements and LED elements, liquid crystal elements, or MEMS (Micro Electro Mechanical Systems) elements can be applied.

[0525] Let node N1 be the node connecting transistor M1 and capacitor C1, and node N2 be the node connecting transistor M2 and circuit 401.

[0526] The pixel circuit 400 can maintain the potential of node N1 by turning off transistor M1. Similarly, it can maintain the potential of node N2 by turning off transistor M2. Furthermore, with transistor M2 in the off state, by writing a predetermined potential to node N1 via transistor M1, the potential of node N2 can be changed in accordance with the displacement of the potential of node N1 through capacitive coupling via capacitor C1.

[0527] Here, one or both of transistors M1 and M2 can be replaced with transistors that utilize an oxide semiconductor, as exemplified in Embodiment 1. Therefore, the potential of node N1 or node N2 can be maintained for a long period of time with an extremely low off-current. Note that if the period for maintaining the potential of each node is short (specifically, when the frame frequency is 30 Hz or higher, for example), transistors using semiconductors such as silicon may be used.

[0528] <Example of driving method> Next, an example of how the pixel circuit 400 operates will be explained using Figure 39B. Figure 39B is a timing chart related to the operation of the pixel circuit 400. For the sake of simplicity, the effects of various resistors such as wiring resistance, parasitic capacitance of transistors or wiring, and the threshold voltage of transistors will not be considered here.

[0529] In the operation shown in Figure 39B, one frame period is divided into period T1 and period T2. Period T1 is the period during which the potential is written to node N2, and period T2 is the period during which the potential is written to node N1.

[0530] [Period T1] During period T1, a potential is applied to both wires G1 and G2 to turn the transistor ON. Additionally, a fixed potential V is applied to wire S1. ref The first data potential V is supplied to wiring S2. w To supply.

[0531] Node N1 receives a potential V from wiring S1 via transistor M1. ref The following is given. Also, node N2 has a first data potential V from wiring S2 via transistor M2. w Therefore, the potential difference V is given to capacitor C1. w -V ref This state is maintained.

[0532] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and a potential is applied to wiring G2 to turn off transistor M2. In addition, a second data potential V is applied to wiring S1. data The following is supplied: A predetermined constant potential may be applied to the wiring S2, or it may be left in a floating state.

[0533] Node N1 receives a second data potential V from wiring S1 via transistor M1. data The following is given. At this time, due to capacitive coupling by capacitance C1, the second data potential V data Accordingly, the potential of node N2 changes by a potential dV. That is, circuit 401 has a first data potential V w The input potential will be the sum of the potential dV and the second data potential V. Note that although Figure 39B shows the potential dV as a positive value, it can also be a negative value. That is, the second data potential V data The potential is V ref It can be lower.

[0534] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second data potential V data The potential will be close to that.

[0535] In this way, the pixel circuit 400 can combine two types of data signals to generate a potential that is supplied to the circuit 401, which includes a display element, making it possible to perform grayscale correction within the pixel circuit 400.

[0536] The pixel circuit 400 can also generate a potential exceeding the maximum potential that can be supplied by the source drivers connected to wiring S1 and S2. For example, when using light-emitting elements, high dynamic range (HDR) display can be performed. When using liquid crystal elements, overdrive driving can be realized.

[0537] <Examples of application> [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 39C has circuit 401LC. Circuit 401LC has a liquid crystal element LC and a capacitor C2.

[0538] In a liquid crystal element (LC), one electrode is at node N2 and capacitance C2, while the other electrode is at potential V com2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Connect to the provided wiring.

[0539] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed.

[0540] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, enabling features such as high-speed display through overdrive driving and the application of liquid crystal materials with high drive voltages. Furthermore, by supplying a correction signal to wiring S1 or S2, the gradation can be corrected according to the operating temperature or the degradation state of the liquid crystal element LC.

[0541] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 39D has circuit 401EL. Circuit 401EL has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0542] Transistor M3 has its gate connected to one electrode of node N2 and capacitance C2, and one of its source and drain connected to potential V. H One end of the wiring is connected to one electrode of the light-emitting element EL. Capacitor C2 is connected to the other electrode at potential V comConnect to the wiring provided. The light-emitting element EL has the other electrode at potential V L Connect to the provided wiring.

[0543] Transistor M3 controls the current supplied to the light-emitting element EL. Capacitor C2 functions as a retaining capacitor. Capacitor C2 can be omitted if not needed.

[0544] Note that although the configuration shown here connects the anode side of the light-emitting element EL to transistor M3, transistor M3 may also be connected to the cathode side. In that case, the potential V H and potential V L The value can be changed as needed.

[0545] The pixel circuit 400EL can supply a large current to the light-emitting element EL by applying a high potential to the gate of transistor M3, thereby enabling features such as HDR display. Furthermore, variations in the electrical characteristics of transistor M3 and the light-emitting element EL can be corrected by supplying a correction signal to wiring S1 or S2.

[0546] Note that the circuits are not limited to those exemplified in Figures 39C and 39D; configurations with additional transistors or capacitors may also be used.

[0547] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0548] (Embodiment 5) This embodiment describes a display module that can be manufactured using one aspect of the present invention.

[0549] The display module 6000 shown in Figure 40A has a display device 6006 with an FPC 6005 connected between an upper cover 6001 and a lower cover 6002, a frame 6009, a printed circuit board 6010, and a battery 6011.

[0550] For example, a display device manufactured using one aspect of the present invention can be used as the display device 6006. The display device 6006 makes it possible to realize a display module with extremely low power consumption.

[0551] The upper cover 6001 and the lower cover 6002 can be appropriately modified in shape or dimensions to match the size of the display device 6006.

[0552] The display device 6006 may also have the functionality of a touch panel.

[0553] Frame 6009 may have functions such as protecting the display device 6006, blocking electromagnetic waves generated by the operation of the printed circuit board 6010, and acting as a heat sink.

[0554] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, and the like.

[0555] Figure 40B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor.

[0556] The display module 6000 has a light-emitting section 6015 and a light-receiving section 6016 provided on the printed circuit board 6010. It also has a pair of light guides (light guide section 6017a, light guide section 6017b) in the area enclosed by the upper cover 6001 and the lower cover 6002.

[0557] The display device 6006 is mounted on top of the printed circuit board 6010 and the battery 6011 with a frame 6009 in between. The display device 6006 and the frame 6009 are fixed to the light guide section 6017a and the light guide section 6017b.

[0558] Light 6018 emitted from the light-emitting unit 6015 passes over the top of the display device 6006 via the light guide unit 6017a, and then through the light guide unit 6017b to reach the light-receiving unit 6016. For example, touch operation can be detected when the light 6018 is blocked by an object to be detected, such as a finger or stylus.

[0559] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite the light-emitting units 6015. This makes it possible to acquire information about the location where a touch operation was performed.

[0560] The light-emitting unit 6015 can use a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared rays. The light-receiving unit 6016 can use a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode capable of receiving infrared rays can be used.

[0561] The light guides 6017a and 6017b, which transmit light 6018, allow the light-emitting unit 6015 and the light-receiving unit 6016 to be positioned below the display device 6006, thereby suppressing external light from reaching the light-receiving unit 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively suppress touch sensor malfunctions.

[0562] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0563] (Embodiment 6) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied.

[0564] The electronic device 6500 shown in Figure 41A is a portable information terminal that can be used as a smartphone.

[0565] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0566] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0567] Figure 41B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0568] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0569] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0570] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back. The FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to terminals provided on the printed circuit board 6517.

[0571] A flexible display panel according to one embodiment of the present invention can be applied to the display panel 6511. This makes it possible to realize an extremely lightweight electronic device. Furthermore, because the display panel 6511 is extremely thin, it is possible to incorporate a large-capacity battery 6518 while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel area, a narrow-bezel electronic device can be realized.

[0572] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0573] (Embodiment 7) This embodiment describes an electronic device equipped with a display device manufactured using one aspect of the present invention.

[0574] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Furthermore, it is possible to create an electronic device that achieves both high resolution and a large screen.

[0575] The display unit of an electronic device according to one aspect of the present invention can display video having a resolution of, for example, Full HD, 4K2K, 8K4K, 16K8K, or higher.

[0576] Examples of electronic devices include those with relatively large screens, such as television sets, notebook computers, monitors, digital signage, pachinko machines, and game consoles, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0577] An electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of the interior or exterior walls of a house or building, the interior or exterior of an automobile, etc.

[0578] Figure 42A shows the external appearance of the camera 8000 with the viewfinder 8100 attached.

[0579] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached.

[0580] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0581] Camera 8000 can take an image by pressing the shutter button 8004 or by touching the display unit 8002, which functions as a touch panel.

[0582] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, a strobe device and the like can be connected to it.

[0583] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0584] The housing 8101 is attached to the camera 8000 by a mount that engages with the camera's mount. The viewfinder 8100 can display images and other data received from the camera 8000 on the display unit 8102.

[0585] Button 8103 functions as a power button, etc.

[0586] A display device according to one embodiment of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. The camera 8000 may also have a built-in viewfinder.

[0587] Figure 42B shows the external appearance of the head-mounted display 8200.

[0588] The head-mounted display 8200 includes a mounting section 8201, lenses 8202, a main unit 8203, a display unit 8204, a cable 8205, etc. The mounting section 8201 also contains a built-in battery 8206.

[0589] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 8203 is equipped with a wireless receiver and can display received video information on display unit 8204. In addition, main unit 8203 is equipped with a camera and can use information about the user's eyeball or eyelid movements as an input means.

[0590] The attachment unit 8201 may have a function to recognize gaze, provided with multiple electrodes at a position that touches the user and capable of detecting the current flowing in accordance with the user's eye movements. It may also have a function to monitor the user's pulse based on the current flowing through the electrodes. Furthermore, the attachment unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have one or more functions to display the user's biometric information on the display unit 8204, or to change the image displayed on the display unit 8204 in accordance with the user's head movements.

[0591] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0592] Figures 42C, 42D, and 42E show the external appearance of the head-mounted display 8300. The head-mounted display 8300 comprises a housing 8301, a display unit 8302, a band-shaped fixing device 8304, and a pair of lenses 8305.

[0593] The user can view the display on the display unit 8302 through the lens 8305. It is preferable to position the display unit 8302 in a curved shape, as this allows the user to experience a greater sense of presence. Furthermore, by viewing different images displayed in different areas of the display unit 8302 through the lens 8305, three-dimensional display using parallax can be performed. Note that the configuration is not limited to a single display unit 8302; two display units 8302 may be provided, with one display unit for each of the user's eyes.

[0594] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. Because the display device having the semiconductor device according to one embodiment of the present invention has extremely high resolution, even when magnified using the lens 8305 as shown in Figure 42E, the user cannot see the pixels, and a more realistic image can be displayed.

[0595] The electronic equipment shown in Figures 43A to 43G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, sensors 9007 (including functions for measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0596] The electronic devices shown in Figures 43A to 43G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0597] Details of the electronic equipment shown in Figures 43A to 43G will be explained below.

[0598] Figure 43A is a perspective view showing the television system 9100. The television system 9100 can incorporate a large screen, for example, a display unit 9001 of 50 inches or more, or 100 inches or more.

[0599] Figure 43B is a perspective view showing a personal digital assistant (PDA) 9101. The PDA 9101 can be used, for example, as a smartphone. The PDA 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDA 9101 can also display one or more characters or image information on multiple surfaces. Figure 43B shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the subject of an email or SNS message, the sender's name, date and time, time, battery level, and antenna signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0600] Figure 43C is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0601] Figure 43D is a perspective view showing a wristwatch-type personal information terminal 9200. The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals or be charged via the connection terminal 9006. Charging may be performed by wireless power supply.

[0602] Figures 43E, 43F, and 43G are perspective views showing a foldable personal information terminal 9201. Figure 43E shows the personal information terminal 9201 in an unfolded state, Figure 43G shows it in a folded state, and Figure 43F shows a state in between the transition from Figure 43E or Figure 43G to the other. The personal information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the personal information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm to 150 mm.

[0603] Figure 44A shows an example of a television system. The television system 7100 has a display unit 7500 incorporated into a housing 7101. Here, the housing 7101 is shown supported by a stand 7103.

[0604] The television device 7100 shown in Figure 44A can be operated using the operation switches on the housing 7101 or a separate remote control unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television device 7100 may be operated by touching it. The remote control unit 7111 may have a display unit in addition to operation buttons.

[0605] The television equipment 7100 may also include a television broadcast receiver or a communication device for network connection.

[0606] Figure 44B shows the notebook personal computer 7200. The notebook personal computer 7200 has a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is incorporated into the casing 7211.

[0607] Figures 44C and 44D show examples of digital signage.

[0608] The digital signage 7300 shown in Figure 44C comprises a housing 7301, a display unit 7500, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0609] Figure 44D shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7500 that is provided along the curved surface of the column 7401.

[0610] The larger the display area 7500, the more information can be provided at once, and because it is more eye-catching, it can have the effect of enhancing the promotional effect of advertisements, for example.

[0611] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This allows it to be used not only for advertising purposes, but also for providing information that the user needs, such as route information, traffic information, or information about commercial facilities.

[0612] As shown in Figures 44C and 44D, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 such as a smartphone owned by the user. For example, the information of advertisements displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311. For example, the display on the display unit 7500 can be switched by operating the information terminal 7311.

[0613] The digital signage 7300 or digital signage 7400 can also be used to run games using the information terminal 7311 as the control device (controller). This allows a large number of users to participate in and enjoy the game simultaneously.

[0614] A display device according to one embodiment of the present invention can be applied to the display unit 7500 in Figures 44A to 44D.

[0615] Although the electronic device in this embodiment has a display unit, one aspect of the present invention can also be applied to electronic devices that do not have a display unit.

[0616] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part. [Examples]

[0617] In this example, the effect of ultraviolet light on a metal oxide film was evaluated. Three types of samples (sample 1A, sample 1B, and sample 1C) having a metal oxide film were prepared. Schematic cross-sectional diagrams of sample 1A are shown in Figure 45A, sample 1B in Figure 45B, and sample 1C in Figure 45C.

[0618] <Sample preparation> First, a first metal oxide film 908 with a thickness of 30 nm was deposited on substrate 902. The first metal oxide film 908 was deposited by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The deposition pressure was 0.6 Pa, the power supply was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen and argon was used as the deposition gas, with an oxygen flow rate ratio of 10%. A glass substrate was used as the substrate 902.

[0619] Next, the samples were heat-treated at 370°C for 1 hour in a nitrogen gas atmosphere, followed by another heat-treatment at 370°C for 1 hour in a mixed atmosphere of nitrogen and oxygen gases. The nitrogen and oxygen gas mixture was composed of nitrogen gas:oxygen gas = 4:1 (by volume). An oven was used for the heat treatment.

[0620] Next, a silicon oxide-nitride film 910 with a thickness of 140 nm was deposited on the first metal oxide film 908.

[0621] Next, the samples were heat-treated at 370°C for 1 hour in a nitrogen gas atmosphere. An oven was used for the heat treatment.

[0622] Next, a second metal oxide film with a thickness of 20 nm was deposited on the silicon oxidizride film 910. The second metal oxide film was deposited by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The deposition pressure was 0.8 Pa, the power supply was 3.5 kW, and the substrate temperature was room temperature. Oxygen gas was used as the deposition gas (oxygen flow rate ratio 100%).

[0623] Next, the samples were heat-treated at 370°C for 1 hour in a mixed atmosphere of nitrogen and oxygen gas. The nitrogen and oxygen gas mixture was nitrogen:oxygen = 4:1 (by volume). An oven was used for the heat treatment.

[0624] Next, the second metal oxide film was removed.

[0625] Next, the samples were heat-treated at 370°C for 1 hour in a nitrogen gas atmosphere. An oven was used for the heat treatment.

[0626] Next, samples 1B and 1C were subjected to plasma treatment using a dry etching apparatus. The plasma treatment used carbon tetrachloride gas, with an ICP power supply of 6000W, a bias power of 500W, and a pressure of 0.67Pa. During plasma treatment, masks were placed on samples 1B and 1C to prevent them from being exposed to the plasma. For sample 1B, a quartz substrate 920 was used as the mask. For sample 1C, a mask with a light-shielding film 930 on a quartz substrate 920 was used to prevent exposure to ultraviolet light. A 200nm thick aluminum film was used as the light-shielding film 930.

[0627] Figure 45B shows a schematic cross-sectional view of sample 1B during plasma treatment, and Figure 45C shows a schematic cross-sectional view of sample 1C during plasma treatment. Figures 45B and 45C schematically show ultraviolet light 940 generated by the plasma.

[0628] Sample 1A was not subjected to plasma treatment.

[0629] Next, the silicon oxidizride film 910 was removed, exposing the first metal oxide film 908.

[0630] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the first metal oxide film 908.

[0631] Figure 46 shows the sheet resistance values ​​of the first metal oxide film 908 for each sample. In Figure 46, the horizontal axis represents the sample name, whether or not plasma treatment was performed, and the conditions of the mask used during plasma treatment, while the vertical axis represents the sheet resistance (Rs) of the first metal oxide film 908.

[0632] As shown in Figure 46, the resistance of sample 1B, which was exposed to ultraviolet light by plasma treatment, was lower than that of sample 1A, which was not subjected to plasma treatment and was not exposed to ultraviolet light. On the other hand, the resistance of sample 1C, which was not exposed to ultraviolet light by plasma treatment, was equivalent to that of sample 1A.

[0633] From these results, it was found that ultraviolet light generated during plasma treatment reduces the resistance of metal oxide films. Furthermore, it was found that the decrease in the resistance of metal oxide films can be suppressed by preventing exposure to ultraviolet light during plasma treatment. [Examples]

[0634] In this example, the transmittance of an organic material that can be used in one aspect of the present invention was evaluated. In this example, eight different samples (Sample 2A to Sample 2H) were prepared using different organic materials.

[0635] <Sample preparation> Sample 2A consisted of an organic material A with a thickness of 1.5 μm formed on a glass substrate. Acrylic resin (JEM-549, manufactured by JSR Corporation) was used as the organic material A.

[0636] Sample 2B consisted of a 1.5 μm thick layer of organic material B formed on a glass substrate. Polyimide resin (DL-1603, manufactured by Toray Industries, Inc.) was used as organic material B.

[0637] Sample 2C consisted of an organic material C with a thickness of 1.5 μm formed on a glass substrate. Novolac resin (Merck RG-300) was used as the organic material C. Organic material C can also be used, for example, as a resist in photolithography processes.

[0638] Sample 2D consisted of an organic material D with a thickness of 1.2 μm formed on a glass substrate. Novolac resin (TELR-P003PM, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as the organic material D. The organic material D exhibited a brown color.

[0639] Sample 2E consisted of an organic material E with a thickness of 0.6 μm formed on a glass substrate. Acrylic resin (BK-4611, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was used as the organic material E. The organic material E is black in color and can be used, for example, as a light-shielding layer.

[0640] Sample 2F consisted of an organic material F with a thickness of 1.5 μm formed on a glass substrate. Acrylic resin (CR-7001W, manufactured by Fujifilm Electronic Materials Corporation) was used as the organic material F. The organic material F exhibits a red color and can be used, for example, as a red colored layer.

[0641] Sample 2G consisted of an organic material G with a thickness of 1.5 μm formed on a glass substrate. Acrylic resin (CG-7001W, manufactured by Fujifilm Electronic Materials Corporation) was used as the organic material G. The organic material G exhibits a green color and can be used, for example, as a green colored layer.

[0642] Sample 2H consisted of an organic material H with a thickness of 1.5 μm formed on a glass substrate. Acrylic resin (CB-7001W, manufactured by Fujifilm Electronic Materials Corporation) was used as the organic material H. The organic material H exhibits a blue color and can be used, for example, as a blue colored layer.

[0643] Next, samples 2A through 2H were heat-treated at 250°C. An oven was used for the heat treatment. Samples 2A through 2C and samples 2F through 2H were treated in a nitrogen gas atmosphere for 1 hour. Sample 2D was treated in an air atmosphere for 1 hour. Sample 2E was treated in a nitrogen gas atmosphere for 30 minutes. An oven was used for the heat treatment of all samples.

[0644] Samples 2I and 2J were prepared as comparative samples. Sample 2I was on a glass substrate, and Sample 2J was on a quartz substrate.

[0645] <Transmittance measurement> Next, the transmittance of the sample prepared as described above was measured.

[0646] The transmittance measurement results for each sample are shown in Figures 47 and 48. In Figures 47 and 48, the horizontal axis represents wavelength λ, and the vertical axis represents transmittance T.

[0647] As shown in Figures 47 and 48, it was confirmed that samples 2A to 2H had low transmittance in the ultraviolet wavelength region. [Examples]

[0648] In this example, a transistor was fabricated and its electrical characteristics were evaluated.

[0649] In this example, sample 3A, which is a transistor according to one aspect of the present invention, and samples 3B and 3C, which are comparative transistors, were fabricated. The configuration of sample 3A can be found by referring to the description of transistor 100 shown in Embodiment 1, Figures 1A to 1C.

[0650] Figure 49A shows a schematic cross-sectional view of sample 3B in the channel direction, which is a comparative example. Sample 3B differs from sample 3A in that the openings 143a and 143b of the insulating layer 130 are located outside the openings 141a and 141b of the insulating layer 110 and insulating layer 118, and the conductive layers 120a and 120b are in contact with the side surfaces of the insulating layer 110 and the insulating layer 118.

[0651] Figure 49B shows a schematic cross-sectional view of the channel direction of sample 3C, which is a comparative example. Sample 3C does not have an insulating layer 130, and differs from sample 3A in that the conductive layers 120a and 120b are in contact with the side surfaces of the insulating layer 110 and the insulating layer 118.

[0652] <Sample preparation> First, a metal oxide film with a thickness of approximately 30 nm was deposited on substrate 102. The metal oxide film was deposited by sputtering using a sputtering target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1. A glass substrate was used for substrate 102.

[0653] Next, the samples were heat-treated at 340°C for 2 hours in a dry air atmosphere. An oven was used for the heat treatment.

[0654] Next, a metal oxide film was formed and processed to obtain the semiconductor layer 108.

[0655] Next, a silicon oxidizride film with a thickness of approximately 140 nm was deposited as an insulating layer 110, which functions as a gate insulating layer, by plasma CVD.

[0656] Next, the samples were heat-treated at 340°C for 1 hour in a dry air atmosphere. An oven was used for the heat treatment.

[0657] Next, a titanium film with a thickness of approximately 50 nm, an aluminum film with a thickness of approximately 200 nm, and another titanium film with a thickness of approximately 50 nm were deposited by sputtering. Subsequently, each conductive film was processed to obtain a conductive layer 112 that functions as a gate electrode.

[0658] Next, after plasma treatment in a hydrogen atmosphere, a silicon nitride film with a thickness of approximately 300 nm was formed as an insulating layer 118. The plasma treatment and the formation of the silicon nitride film were carried out continuously using a plasma CVD apparatus. The plasma treatment formed a low-resistance region 108N in the region of the semiconductor layer 108 that did not overlap with the conductive layer 112.

[0659] Next, a portion of the insulating layer 110 and the insulating layer 118 was removed by etching to form openings 141a and 141b.

[0660] Next, an insulating layer 130 was formed on samples 3A and 3B. A polyimide resin with a thickness of 1.5 μm was used as the insulating layer 130. In this case, sample 3A, which is a transistor according to one embodiment of the present invention, had the insulating layer 130 formed such that the opening 143a of the insulating layer 130 was located inside the opening 141a, and the opening 143b of the insulating layer 130 was located inside the opening 141b, as shown in Figure 1B. In this way, the sides of the insulating layer 110 and the sides of the insulating layer 118 were covered with the insulating layer 130 on the low-resistance region 108N.

[0661] As shown in Figure 49A, in comparative example sample 3B, the insulating layer 130 was formed such that the opening 143a of the insulating layer 130 was located outside the opening 141a, and the opening 143b of the insulating layer 130 was located outside the opening 141b. In this way, the sides of the insulating layer 110 and the insulating layer 118 were not covered by the insulating layer 130 on the low-resistance region 108N. As shown in Figure 49B, sample 3C did not have an insulating layer 130 formed.

[0662] Next, the samples were heat-treated at 250°C for 1 hour in a nitrogen gas atmosphere. An oven was used for the heat treatment.

[0663] Next, a titanium film with a thickness of approximately 50 nm, an aluminum film with a thickness of approximately 300 nm, and another titanium film with a thickness of approximately 50 nm were deposited by sputtering. Subsequently, each conductive film was processed to obtain conductive layers 120a and 120b, which function as source and drain electrodes.

[0664] Samples 3A to 3C were obtained through the above process.

[0665] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistors were measured for samples 3A through 3C prepared as described above.

[0666] The Id-Vg characteristics of the transistor were measured by applying a voltage to the gate electrode (hereinafter also called gate voltage (VG)) in 0.25V increments from -15V to +15V. The voltage applied to the source electrode (hereinafter also called source voltage (VS)) was set to 0V (comm), and the voltage applied to the drain electrode (hereinafter also called drain voltage (VD)) was set to 0.1V and 10V.

[0667] Here, transistors with a design specification of a channel length of 6 μm and a channel width of 100 μm were measured. Twenty measurements were taken for each sample.

[0668] Figure 50 shows the threshold voltage Vth of the transistors for samples 3A to 3C. In Figure 50, the horizontal axis represents the sample name, and the vertical axis represents the threshold voltage Vth.

[0669] As shown in Figure 50, compared to sample 3C without the insulating layer 130, sample 3B with the insulating layer 130 showed a more positive threshold voltage Vth. Furthermore, compared to sample 3B, sample 3A, which has a transistor according to one embodiment of the present invention, showed an even more positive threshold voltage Vth, confirming good normally-off electrical characteristics. [Examples]

[0670] In this example, a transistor was fabricated and its electrical characteristics were evaluated.

[0671] In this embodiment, samples 4A and 4B, which are transistors according to one aspect of the present invention, and sample 4C, which is a comparative example transistor, were fabricated. The configurations of samples 4A and 4B can be found by referring to the description of transistor 100C shown in Embodiment 1, Figures 13A to 13C.

[0672] Figure 49C shows a schematic cross-sectional view of sample 4C in the channel direction, which is a comparative example. Sample 4C differs from samples 4A and 4B in that the openings 143a and 143b of the insulating layer 130 are located outside the openings 141a and 141b of the insulating layers 110 and 118, and the points where the conductive layers 120a and 120b contact the side surfaces of the insulating layer 110 and the insulating layer 118.

[0673] <Sample preparation> First, a tungsten film with a thickness of approximately 100 nm was formed on a glass substrate by sputtering, and this was processed to obtain a conductive layer 106 that functions as the first gate electrode.

[0674] Next, an insulating layer 103, which functions as the first gate insulating layer, was formed. The insulating layer 103 had a laminated structure of insulating film 103a and insulating film 103b. Insulating film 103a used a laminated structure of a silicon nitride film with a thickness of approximately 30 nm and a silicon oxide nitride film with a thickness of approximately 280 nm. Insulating film 103b used a silicon oxide nitride film with a thickness of approximately 20 nm.

[0675] Next, a metal oxide film with a thickness of approximately 30 nm was deposited. The metal oxide film was deposited by sputtering using a sputtering target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1.

[0676] Next, the samples were heat-treated at 340°C for 2 hours in a dry air atmosphere. An oven was used for the heat treatment.

[0677] Next, a metal oxide film was formed and processed to obtain the semiconductor layer 108.

[0678] Next, a silicon oxidizride film with a thickness of approximately 140 nm was deposited as an insulating layer 110, which functions as a second gate insulating layer, by plasma CVD.

[0679] Next, the samples were heat-treated at 340°C for 1 hour in a dry air atmosphere. An oven was used for the heat treatment.

[0680] Next, a titanium film with a thickness of approximately 50 nm, an aluminum film with a thickness of approximately 200 nm, and another titanium film with a thickness of approximately 50 nm were deposited by sputtering. Subsequently, each conductive film was processed to obtain a conductive layer 112 that functions as a second gate electrode.

[0681] Next, after plasma treatment in a hydrogen atmosphere, a silicon nitride film with a thickness of approximately 300 nm was formed as an insulating layer 118. The plasma treatment and the formation of the silicon nitride film were carried out continuously using a plasma CVD apparatus. The plasma treatment formed a low-resistance region 108N in the region of the semiconductor layer 108 that did not overlap with the conductive layer 112.

[0682] Next, a portion of the insulating layer 110 and the insulating layer 118 was removed by etching to form openings 141a and 141b.

[0683] Next, an insulating layer 130 was formed. For samples 4A and 4C, a polyimide resin with a thickness of 2.0 μm was used as the insulating layer 130. For sample 4B, an acrylic resin with a thickness of 2.0 μm was used as the insulating layer 130. In this case, for samples 4A and 4B, which are transistors according to one embodiment of the present invention, the insulating layer 130 was formed such that the opening 143a of the insulating layer 130 is located inside the opening 141a, and the opening 143b of the insulating layer 130 is located inside the opening 141b, as shown in Figure 13B. In this way, the sides of the insulating layer 110 and the sides of the insulating layer 118 are covered with the insulating layer 130 on the low-resistance region 108N.

[0684] As shown in Figure 49C, in the comparative example sample 4C, the insulating layer 130 was formed such that the opening 143a of the insulating layer 130 was located outside the opening 141a, and the opening 143b of the insulating layer 130 was located outside the opening 141b. In this way, the sides of the insulating layer 110 and the insulating layer 118 were not covered by the insulating layer 130 in the low-resistance region 108N.

[0685] Next, the samples were heat-treated at 250°C for 1 hour in a nitrogen gas atmosphere. An oven was used for the heat treatment.

[0686] Next, a titanium film with a thickness of approximately 50 nm, an aluminum film with a thickness of approximately 300 nm, and another titanium film with a thickness of approximately 50 nm were deposited by sputtering. Subsequently, each conductive film was processed to obtain conductive layers 120a and 120b, which function as source and drain electrodes.

[0687] Samples 4A to 4C were obtained through the above process.

[0688] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistors were measured for samples 4A through 4C prepared as described above.

[0689] The Id-Vg characteristics of the transistor were measured by applying a voltage to the gate electrode (hereinafter also called gate voltage (VG)) in 0.25V increments from -15V to +15V. The voltage applied to the source electrode (hereinafter also called source voltage (VS)) was set to 0V (comm), and the voltage applied to the drain electrode (hereinafter also called drain voltage (VD)) was set to 0.1V and 10V. The Id-Vg characteristics were measured by applying the same gate voltage to both the first and second gate electrodes.

[0690] Here, we measured transistors with a design specification of a channel length of 3 μm and a channel width of 50 μm. We performed 20 measurements for each sample.

[0691] Figure 51 shows the Id-Vg characteristics of samples 4A to 4C. In Figure 51, the Id-Vg characteristics of 20 transistors are superimposed. Figure 51 also shows the average value (ave.) and standard deviation (3σ) of the threshold voltage Vth for each sample.

[0692] As shown in Figure 51, compared with comparative example sample 4C, it was confirmed that samples 4A and 4B, which represent one embodiment of the present invention, have a positive threshold voltage Vth. Furthermore, compared with sample 4B, sample 4A has an even more positive threshold voltage Vth, confirming good normally-off electrical characteristics.

[0693] <Cross-sectional observation> Next, the sample was thinned using a focused ion beam (FIB), and the cross-section was observed using a scanning transmission electron microscope (STEM).

[0694] STEM images of the cross-section of sample 4A are shown in Figures 52A and 52B. STEM images of the cross-section of sample 4B are shown in Figures 53A and 53B. STEM images of the cross-section of sample 4C are shown in Figures 54A and 54B. Figures 52A, 53A, and 54A are transmitted electron (TE) images at a magnification of 8,000x. Figures 52B, 53B, and 54B are transmitted electron (TE) images at a magnification of 25,000x, showing a magnified view of aperture 143a and its vicinity.

[0695] As shown in Figures 52A to 54B, it was confirmed that each sample had a good shape. Furthermore, the width 151 of the region of the insulating layer 130 that is in contact with the semiconductor layer 108 (low-resistance region 108N) was approximately 490 nm (left side of Figure 52B) and approximately 460 nm (right side of Figure 52B) for sample 4A, and approximately 630 nm (left side of Figure 53B) and approximately 650 nm (right side of Figure 53B) for sample 4B. [Examples]

[0696] In this example, the transmittance of a conductive film that can be used in one embodiment of the present invention was evaluated.

[0697] <Sample preparation> A titanium film was deposited on a quartz substrate by sputtering. In this example, a titanium film was used as the conductive film, and six different samples were prepared with varying titanium film thicknesses (20 nm, 35 nm, 50 nm, 70 nm, 100 nm, and 200 nm).

[0698] <Transmittance measurement> Next, the transmittance of the sample prepared as described above was measured.

[0699] The transmittance measurement results for each sample are shown in Figure 55A. A magnified graph of the vertical axis in Figure 55A is shown in Figure 55B. In Figures 55A and 55B, the horizontal axis represents wavelength λ, and the vertical axis represents transmittance T.

[0700] As shown in Figures 55A and 55B, it was found that the thicker the titanium film, the lower the transmittance of ultraviolet light. [Examples]

[0701] In this example, the effect of ultraviolet light on the deposition of a conductive film on a metal oxide film was evaluated. In this example, six types of samples with different thicknesses of conductive films formed on the metal oxide film were prepared. In addition, one sample without a conductive film was prepared as a reference sample.

[0702] <Sample preparation> First, a silicon nitride film with a thickness of 120 nm was deposited on a glass substrate.

[0703] Next, a first silicon oxidoxide-nitride film with a thickness of 150 nm was deposited.

[0704] Next, a 30 nm thick metal oxide film was deposited. The metal oxide film was deposited by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 5:1:3 [atomic ratio]). The deposition pressure was 0.4 Pa, the power supply was 1.0 kW, and the substrate temperature was room temperature. A mixed gas of oxygen and argon was used as the deposition gas, with an oxygen flow rate ratio of 50%.

[0705] Next, the samples were heat-treated in a dry air (CDA) atmosphere at 320°C for 1 hour, followed by another heat-treatment at 340°C for 1 hour. An oven was used for the heat treatment.

[0706] Next, a second silicon oxide-nitride film with a thickness of 140 nm was deposited.

[0707] Next, the samples were heat-treated at 340°C for 1 hour in a dry air (CDA) atmosphere. An oven was used for the heat treatment.

[0708] Next, a conductive film was deposited on the second silicon oxide-nitride film by sputtering. This conductive film had a laminated structure consisting of the first titanium film, an aluminum film on the first titanium film, and the second titanium film on the aluminum film. Six different samples were prepared by varying the thickness of the first titanium film (20 nm, 35 nm, 50 nm, 70 nm, 100 nm, and 200 nm). The aluminum film was 200 nm thick, and the second titanium film was 50 nm thick. One sample did not have a conductive film deposited.

[0709] Next, the conductive film was removed. The conductive film was removed using the wet etching method.

[0710] Next, the second silicon oxide nitride film was removed, exposing the metal oxide film. The second silicon oxide nitride film was removed using a dry etching method.

[0711] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the metal oxide film.

[0712] Figure 56 shows the sheet resistance values ​​of the metal oxide film for each sample. In Figure 56, the horizontal axis represents the thickness of the first titanium film, and the vertical axis represents the sheet resistance (Rs) of the metal oxide film. Samples for which no conductive film was deposited are marked "None" on the horizontal axis of Figure 56.

[0713] As shown in Figure 56, it was found that the resistance of the metal oxide film decreased by depositing a conductive film. Furthermore, the resistance of the metal oxide film decreased as the thickness of the first titanium film increased, and no difference in the resistance of the metal oxide film was observed when the thickness of the first titanium film was 70 nm or more. In the deposition of the conductive film, the resistance of the metal oxide film decreases in the initial stages of deposition because ultraviolet light reaches the metal oxide film, but as the thickness of the conductive film increases, the ultraviolet light is blocked by the conductive film, and it is thought that no difference in the resistance of the metal oxide film is observed. [Examples]

[0714] In this example, the effect of ultraviolet light on the deposition of a conductive film on a metal oxide film was evaluated. Nine different samples were prepared with varying deposition conditions for the conductive film formed on the metal oxide film. Additionally, one sample without a conductive film was prepared as a reference sample.

[0715] <Sample preparation> First, a silicon nitride film with a thickness of 120 nm was deposited on a glass substrate.

[0716] Next, a first silicon oxidoxide-nitride film with a thickness of 150 nm was deposited.

[0717] Next, a 30 nm thick metal oxide film was deposited. The metal oxide film was deposited by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 5:1:3 [atomic ratio]). The deposition pressure was 0.4 Pa, the power supply was 1.0 kW, and the substrate temperature was room temperature. A mixed gas of oxygen and argon was used as the deposition gas, with an oxygen flow rate ratio of 50%.

[0718] Next, the samples were heat-treated in a dry air (CDA) atmosphere at 320°C for 1 hour, followed by another heat-treatment at 340°C for 1 hour. An oven was used for the heat treatment.

[0719] Next, a second silicon oxide-nitride film with a thickness of 140 nm was deposited.

[0720] Next, the samples were heat-treated at 340°C for 1 hour in a dry air (CDA) atmosphere. An oven was used for the heat treatment.

[0721] Next, a conductive film was deposited on the second silicon oxide-nitride film by sputtering. This conductive film had a laminated structure consisting of the first titanium film, an aluminum film on the first titanium film, and the second titanium film on the aluminum film. The thickness of the first titanium film was 50 nm, the thickness of the aluminum film was 200 nm, and the thickness of the second titanium film was 50 nm. Nine different samples were prepared by varying the deposition conditions for the first titanium film. The deposition conditions for the first titanium film were three pressure conditions (0.3 Pa, 0.6 Pa, and 0.85 Pa) and three power conditions (8 kW, 29 kW, and 58 kW). In addition, one sample did not have a conductive film deposited.

[0722] Next, the conductive film was removed. The conductive film was removed using the wet etching method.

[0723] Next, the second silicon oxide nitride film was removed, exposing the metal oxide film. The second silicon oxide nitride film was removed using a dry etching method.

[0724] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the metal oxide film.

[0725] Figure 57 shows the sheet resistance values ​​of the metal oxide films for each sample. In Figure 57, the horizontal axis represents the deposition conditions for the first titanium film, and the vertical axis represents the sheet resistance (Rs) of the metal oxide film. Samples for which no conductive film was deposited are marked "None" on the horizontal axis of Figure 57.

[0726] As shown in Figure 57, it was found that the resistance of the metal oxide film decreased by depositing a conductive film. Furthermore, it was found that increasing the power during the deposition of the first titanium film increased the resistance of the metal oxide film. It is thought that a higher power during deposition of the first titanium film resulted in a faster deposition rate, shortening the time that ultraviolet light reached the metal oxide film. As a result, the amount of ultraviolet light reaching the metal oxide film decreased, suppressing the decrease in the metal oxide film's resistance. No difference in the resistance of the metal oxide film was observed with respect to the pressure during deposition of the first titanium film. [Examples]

[0727] In this example, the effect of ultraviolet light on the deposition of a conductive film on a metal oxide film was evaluated. Nine different samples were prepared with varying deposition conditions for the conductive film formed on the metal oxide film. Additionally, one sample without a conductive film was prepared as a reference sample.

[0728] <Sample preparation> First, a silicon nitride film with a thickness of 120 nm was deposited on a glass substrate.

[0729] Next, a first silicon oxidoxide-nitride film with a thickness of 150 nm was deposited.

[0730] Next, a 30 nm thick metal oxide film was deposited. The metal oxide film was deposited by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 5:1:3 [atomic ratio]). The deposition pressure was 0.4 Pa, the power supply was 1.0 kW, and the substrate temperature was room temperature. A mixed gas of oxygen and argon was used as the deposition gas, with an oxygen flow rate ratio of 50%.

[0731] Next, the samples were heat-treated in a dry air (CDA) atmosphere at 320°C for 1 hour, followed by another heat-treatment at 340°C for 1 hour. An oven was used for the heat treatment.

[0732] Next, a second silicon oxide-nitride film with a thickness of 140 nm was deposited.

[0733] Next, the samples were heat-treated at 340°C for 1 hour in a dry air (CDA) atmosphere. An oven was used for the heat treatment.

[0734] Next, a conductive film was deposited on the second silicon oxidizrind film by sputtering. This conductive film had a laminated structure consisting of a first titanium film, an aluminum film on the first titanium film, and a second titanium film on the aluminum film. The thickness of the first titanium film was 50 nm, the thickness of the aluminum film was 200 nm, and the thickness of the second titanium film was 50 nm. Nine different samples were prepared with different aluminum film deposition conditions. The aluminum film deposition conditions were three pressure conditions (0.3 Pa, 0.6 Pa, and 0.85 Pa) and three power conditions (10 kW, 36 kW, and 78 kW). In addition, one sample did not have a conductive film deposited.

[0735] Next, the conductive film was removed. The conductive film was removed using the wet etching method.

[0736] Next, the second silicon oxide nitride film was removed, exposing the metal oxide film. The second silicon oxide nitride film was removed using a dry etching method.

[0737] <Sheet resistance measurement> Next, the sheet resistance of the sample prepared above was measured to evaluate the resistance of the metal oxide film.

[0738] Figure 58 shows the sheet resistance values ​​of the metal oxide films for each sample. In Figure 58, the horizontal axis represents the deposition conditions for the aluminum film, and the vertical axis represents the sheet resistance (Rs) of the metal oxide film. Samples for which no conductive film was deposited are marked "None" on the horizontal axis of Figure 58.

[0739] As shown in Figure 58, it was found that the resistance of the metal oxide film decreased by depositing a conductive film. Furthermore, it was found that increasing the power during aluminum film deposition increased the resistance of the metal oxide film. This is thought to be because a higher power during aluminum film deposition leads to a faster deposition rate, shortening the time ultraviolet light reaches the metal oxide film. As a result, the amount of ultraviolet light reaching the metal oxide film decreases, suppressing the decrease in the metal oxide film's resistance. No difference in the resistance of the metal oxide film was observed with respect to the pressure during aluminum film deposition. [Explanation of symbols]

[0740] DL_1: data line, DL_n: data line, DL_Y: data line, DL: data line, GL_1: gate line, GL_m: gate line, GL_X: gate line, GL: gate line, LC: liquid crystal element, VL_a: potential supply line, VL_b: potential supply line, 100A: transistor, 100B: transistor, 100C: transistor, 100D: transistor, 100E: transistor, 100F: transistor, 100G: transistor, 100H: transistor, 100: transistor, 102: substrate, 103a: insulating film, 103b: insulating film, 103: insulating layer, 106 : Conductive layer, 108f: Metal oxide film, 108L: Region, 108N: Low resistance region, 108: Semiconductor layer, 110a: Insulating film, 110b: Insulating film, 110c: Insulating film, 110: Insulating layer, 112f: Conductive film, 112: Conductive layer, 112m: Conductive film, 114f: Metal oxide film, 114: Metal oxide layer, 116: Insulating layer, 118: Insulating layer, 120a: Conductive layer, 120b: Conductive layer, 130: Insulating layer, 132: Insulating layer, 140: Impurity element, 141a: Aperture, 141b: Aperture, 141W: Width, 142: Aperture, 143a: Aperture, 143b: Aperture, 143W: Width, 145a: Aperture ,145b: Aperture, 145W: Width, 147a: Aperture, 147b: Aperture, 147W: Width, 149a: Aperture, 149b: Aperture, 149W: Width, 151: Width, 193: Target, 194: Plasma, 195: Target, 196: Plasma, 400EL: Pixel circuit, 400LC: Pixel circuit, 400: Pixel circuit, 401EL: Circuit, 401LC: Circuit, 401: Circuit, 501: Pixel circuit, 502: Pixel section, 504a: Gate driver, 504b: Source driver, 504: Drive circuit section, 506: Protection circuit, 507: Terminal section, 550: Transistor, 552: Transistor Transistor, 554: Transistor, 560: Capacitive element, 562: Capacitive element, 570: Liquid crystal element, 572: Light-emitting element, 700A: Display device, 700B: Display device, 700: Display device, 701: First substrate, 702: Pixel section, 704: Source driver circuit section, 705: Second substrate, 706: Gate driver circuit section, 708: FPC terminal section, 710: Signal line, 711: Wiring section, 712: Sealing material, 716: FPC, 717: IC, 721: Source driver IC, 722: Gate driver circuit section, 723: FPC, 724: Printed circuit board, 730: Insulating film,732: Encapsulation film, 734: Insulating film, 736: Colored film, 738: Light-shielding film, 740: Protective layer, 741: Protective layer, 742: Adhesive layer, 743: Resin layer, 744: Insulating layer, 745: Support substrate, 746: Resin layer, 750: Transistor, 752: Transistor, 760: Wiring, 770: Planarizing insulating film, 772: Conductive layer, 773: Insulating layer, 774: Conductive layer, 775: Liquid crystal element, 776: Liquid crystal layer, 778: Structure, 780: Anisotropic conductive film, 782: Light-emitting element, 786: EL layer, 788: Conductive film, 790: Capacitive element, 800A: Display device, 800: Display device, 801: Base Plate, 811: conductive layer, 812: reflective layer, 813: insulating layer, 814B: conductive layer, 814G: conductive layer, 814R: conductive layer, 814: conductive layer, 815: EL layer, 816: conductive layer, 817: insulating layer, 818: insulating layer, 820B: light-emitting element, 820G: light-emitting element, 820R: light-emitting element, 820: light-emitting element, 821: insulating layer, 830: plug, 831: plug, 902: substrate, 908: first metal oxide film, 910: silicon oxide nitride film, 920: quartz substrate, 930: light-shielding film, 940: ultraviolet light, 6000: display module, 6001: upper cover, 6002: lower cover Bar, 6005: FPC, 6006: Display device, 6009: Frame, 6010: Printed circuit board, 6011: Battery, 6015: Light-emitting part, 6016: Light-receiving part, 6017a: Light guide part, 6017b: Light guide part, 6018: Light, 6500: Electronic equipment, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 65 17: Printed circuit board, 6518: Battery, 7100: Television equipment, 7101: Enclosure, 7103: Stand, 7111: Remote control, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7500: Display unit, 8000: Camera, 8001: Enclosure, 8002: Display unit, 8003: Operation buttons8004: Shutter button, 8006: Lens, 8100: Viewfinder, 8101: Housing, 8102: Display unit, 8103: Button, 8200: Head-mounted display, 8201: Mounting part, 8202: Lens, 8203: Main unit, 8204: Display unit, 8205: Cable, 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8302: Display unit, 8304: Fixing device, 8305: Lens, 9000: Housing, 9001: Display unit, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television device, 9101: Personal digital assistant, 9102: Personal digital assistant, 9200: Personal digital assistant, 9201: Personal digital assistant,

Claims

1. It comprises a semiconductor layer, a gate insulating layer, a gate electrode, a first insulating layer, a second insulating layer, and a conductive layer. The gate insulating layer is in contact with the upper and side surfaces of the semiconductor layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer, The first insulating layer has an inorganic material, The first insulating layer is in contact with the upper surface of the gate insulating layer, and the upper and side surfaces of the gate electrode. The gate insulating layer and the first insulating layer have a first opening in the region overlapping with the semiconductor layer. The second insulating layer has an organic material, The second insulating layer has a second opening inside the first opening, The second insulating layer is in contact with the upper surface and side surface of the first insulating layer, and the side surface of the gate insulating layer. A semiconductor device wherein the conductive layer is electrically connected to the semiconductor layer through the second opening.

2. It comprises a semiconductor layer, a gate insulating layer, a gate electrode, a first insulating layer, a second insulating layer, and a conductive layer. The gate insulating layer is in contact with the upper surface of the semiconductor layer. The gate electrode has a region that overlaps with the semiconductor layer via the gate insulating layer, The first insulating layer has an inorganic material, The first insulating layer is in contact with the upper and side surfaces of the semiconductor layer, the side surfaces of the gate insulating layer, and the upper and side surfaces of the gate electrode. The first insulating layer has a first opening in the region overlapping with the semiconductor layer, The second insulating layer has an organic material, The second insulating layer has a second opening inside the first opening, The second insulating layer is in contact with the upper and side surfaces of the first insulating layer. A semiconductor device wherein the conductive layer is electrically connected to the semiconductor layer through the second opening.

3. In claim 1 or claim 2, A semiconductor device in which the angle formed by the side surface of the second insulating layer and the upper surface of the semiconductor layer is 45 degrees or more and less than 90 degrees.

4. In any one of claims 1 to 3, The second insulating layer has a region that is in contact with the upper surface of the semiconductor layer, A semiconductor device having a region width of 50 nm or more and 3000 nm or less.

5. In any one of claims 1 to 4, A semiconductor device having a transmittance of 0.01% to 70% in the wavelength range of 200 nm to 350 nm of the second insulating layer.

6. In any one of claims 1 to 5, A semiconductor device having a transmittance of 0.01% to 70% of the organic material in the wavelength range of 200 nm to 350 nm.

7. In any one of claims 1 to 6, The aforementioned organic material comprises one or more acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimidoamide resins, siloxane resins, benzocyclobutene resins, phenolic resins, novolac resins, and precursors of these resins, in a semiconductor device.

8. In any one of claims 1 to 7, Having a third insulating layer, The third insulating layer described above has an inorganic material, The third insulating layer has a third opening inside the second opening, The third insulating layer is in contact with the upper and side surfaces of the second insulating layer, and is a semiconductor device.

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