Chalcogenide material sealing layer

Abstract

The present invention provides a sealing layer for semiconductor devices, particularly semiconductor devices containing chalcogenide materials, and a method for manufacturing the same. [Solution] The method for manufacturing a semiconductor device includes providing a substrate 18 having an exposed surface containing a chalcogenide material, and forming low-χ metal oxide layers 46A and 52A on the chalcogenide material by periodically exposing the substrate to an oxygen precursor containing a low-electronegativity (low-χ) metal precursor and O2. The electronegativity of the low-χ metal of the metal precursor is 1.6 or less.

Description

[Technical Field]

[0001] The disclosed technology generally relates to semiconductor devices, and more specifically, to a encapsulation layer for semiconductor devices containing a chalcogenide material and a method for manufacturing the same. [Background technology]

[0002] Non-volatile memory or storage devices can switch between memory states, for example, between logical 1 and 0, by changing the physical state of the storage element. For example, some non-volatile memory devices, such as flash memory devices, can switch memory states by transferring charge to and from a floating gate configured as a storage element. Some other non-volatile or storage devices can switch between memory states by changing the resistance in the storage element. The latter type of non-volatile memory device includes phase-change memory (PCM) devices, which contain a phase-change material within the storage element. PCM devices can switch by performing a phase change, including crystallization and amorphous phase change, in the phase-change material of the storage element. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] The ongoing dimensional scaling, performance improvements, low-temperature integration, variable resistors, voltage / current scaling, and / or the need for three-dimensional (3D) integration in PCM devices, among many other trends, are driving the corresponding need for improved integration schemes in PCM devices. [Means for solving the problem]

[0004] In one embodiment, a method for manufacturing a semiconductor device includes providing a substrate having an exposed surface containing a chalcogenide material. The method further includes forming a low electronegativity (low χ) metal oxide layer on the chalcogenide material by periodically exposing the substrate to a low electronegativity (low χ) metal precursor and an oxygen precursor containing O2. In this case, the electronegativity of the low χ metal of the metal precursor is 1.6 or less.

[0005] In another embodiment, a method for manufacturing a semiconductor device includes providing a substrate on which a chalcogenide layer is formed. The method further includes patterning the chalcogenide layer to expose the sidewalls of the chalcogenide layer. The method further includes forming a low electronegativity (low χ) metal oxide layer on the sidewalls of the chalcogenide layer by periodically exposing the substrate to a low χ metal precursor and an oxygen precursor at a temperature of 300°C or less without the assistance of plasma. The electronegativity of the low χ metal of the metal oxide is 1.6 or less.

[0006] In another embodiment, a method for manufacturing a semiconductor device includes providing a substrate on which a chalcogenide material is formed, wherein the chalcogenide material has a chalcogenide oxide material formed on its surface region. The method further includes at least partially chemically reducing the chalcogenide oxide material by exposing it to a low electronegativity (low χ) metal precursor. The electronegativity of the low χ metal precursor is 1.6 or less, so that the oxygen content of the surface region is reduced compared to the surface region before the chalcogenide oxide material is exposed to the low χ metal precursor.

[0007] In another embodiment, the phase-change memory device includes a memory cell arranged longitudinally between a first conductive wire extending in a first direction and a second conductive wire extending in a second transverse direction intersecting the first transverse direction, wherein the memory cell includes a phase-change memory element and a selector element. The memory device further includes a low electronegativity (low χ) metal oxide layer formed on the sidewall of the memory cell, in which case the electronegativity of the low χ metal in the low χ metal oxide layer is 1.6 or less. [Brief explanation of the drawing]

[0008] Hereinafter, embodiments of the present disclosure will be described as non-limiting examples with reference to the accompanying drawings. [Figure 1] Figure 1 shows an exemplary phase-change memory cell configured to be protected by a sealing layer according to an embodiment. [Figure 2] Figure 2 schematically shows an example of an access operation that can be performed on a phase-change memory device. [Figure 3A] Figure 3A shows an exemplary crosspoint memory array according to an embodiment, comprising a plurality of memory cells having sidewalls covered with a sealing layer, viewed from the y-direction and the x-direction, respectively. [Figure 3B] Figure 3B shows an exemplary crosspoint memory array according to an embodiment, comprising a plurality of memory cells having sidewalls covered with a sealing layer, viewed from the y-direction and the x-direction, respectively. [Figure 4] Figure 4 schematically shows an example of a precursor delivery sequence for forming a sealing layer according to an embodiment. [Figure 5A] Figure 5A schematically shows a method for encapsulating a phase-change memory cell according to an embodiment. [Figure 5B] Figure 5B schematically shows a method for forming a sealing layer as part of the encapsulation method shown in Figure 5A. [Figure 6A] Figure 6A shows intermediate structures at various stages in manufacturing a crosspoint array having encapsulated phase-change memory cells according to an embodiment. [Figure 6B] Figure 6B shows intermediate structures at various stages in manufacturing a crosspoint array having encapsulated phase-change memory cells according to an embodiment. [Figure 6C] Figure 6C shows intermediate structures at various stages in manufacturing a crosspoint array having encapsulated phase-change memory cells according to an embodiment. [Figure 6D]FIG. 6D shows intermediate structures at various stages of manufacturing a cross-point array having encapsulated phase change memory cells according to an embodiment. [Figure 6E] FIG. 6E shows intermediate structures at various stages of manufacturing a cross-point array having encapsulated phase change memory cells according to an embodiment. [Figure 6F] FIG. 6F shows intermediate structures at various stages of manufacturing a cross-point array having encapsulated phase change memory cells according to an embodiment. [Figure 6G] FIG. 6G shows intermediate structures at various stages of manufacturing a cross-point array having encapsulated phase change memory cells according to an embodiment. [Figure 6H] FIG. 6H shows intermediate structures at various stages of manufacturing a cross-point array having encapsulated phase change memory cells according to an embodiment. [Figure 7A] FIG. 7A is a graph showing experimentally measured changes in the thickness of a lanthanum oxide layer over time as a function of the thickness of a hafnium oxide capping layer formed thereon. [Figure 7B] FIG. 7B is a graph showing experimentally measured changes in the thickness of a lanthanum oxide layer over time as a function of the thickness of an aluminum oxide capping layer formed thereon. [Figure 8A] FIG. 8A shows a wafer map indicating locations where an experimental adhesion strength test of a sealing layer according to an embodiment was performed. [Figure 8B] FIG. 8B shows a scanning electron microscope photograph (SEM) of the location shown in FIG. 8A where the adhesion strength test was performed. [Figure 8C] FIG. 8C shows an energy-dispersive X-ray spectrum (EDS) obtained from one of the locations shown in FIG. 8A where the adhesion strength test was performed. [Figure 9A] FIG. 9A shows a cross-sectional transmission electron microscope photograph (XTEM) of a sealing layer including a LaOx layer and a HfOx layer according to an embodiment. [Figure 9B] FIG. 9B shows an element map obtained from the cross-sectional region shown in FIG. 9A according to an embodiment. [Figure 9C] FIG. 9C shows a depth profile of the composition of the sealing layer shown in FIG. 9A.

MODE FOR CARRYING OUT THE INVENTION

[0009] As described above, the need for continuous dimensional scaling, performance improvement, voltage / current scaling, and / or 3D integration among many trends in PCM devices has driven corresponding needs for improvement in their process integration schemes. Process integration schemes that require improvement include the passivation schemes of memory cells of PCM devices. To understand the need for such improvements, FIGS. 1 and 2 show an exemplary phase change memory cell and an exemplary access operation executable thereon, respectively.

[0010] FIG. 1 shows an example of a phase change memory (PCM) device 100 including a PCM cell that can enjoy the benefits of improved passivation according to an embodiment. The PCM device 100 has a memory cell 30 including a phase change memory element 34, and the element 34 has an intermediate electrode 36 formed on its lower surface and an upper electrode 32 formed on its upper surface. The cell stack 30 may further include a selector element 38 that can have a lower electrode 40 formed on its lower surface and separated from the phase change memory element 34 by the intermediate electrode 36. The selector element 38 can be, for example, a two-terminal selection device. The cell stack 30 including the phase change memory element 34 and the selector element 38 can be connected at one end to an upper metal line 20, such as one of a word line and a bit line, via the upper electrode 32, and at the other end to a lower metal line 22, such as the other of the word line and the bit line, via the lower electrode 40.

[0011] In the PCM device 100, one or both of the phase-change memory element 34 and the selector element 38 may include a chalcogenide material. The phase-change memory element 34 is configured to store a plurality of memory states that can be non-volatile or persistent memory states. The selector element 38 is electrically connected in series with the phase-change memory element 34. The selector element 38 is configured as a switch for controlling the voltage and / or current that may be supplied to the phase-change memory element 34 by a voltage source and / or current source in order to switch the phase-change memory element 34 between or within a plurality of memory states.

[0012] Figure 2 schematically shows an exemplary access operation that can be performed on the PCM device 100 described above with respect to Figure 1. The operation to induce the transition from crystalline to amorphous in the phase-change memory element 34 (Figure 1), i.e., the reset operation, is performed by applying a reset pulse 210, for example, a pulse of current or voltage, to the phase-change memory element 34 (Figure 1) in a low-resistance state or set state that substantially corresponds to the crystalline state of the phase-change material. The pulse can be applied using a selector element 38 to control its duration and / or magnitude. The reset pulse 210 causes the phase-change material of the phase-change memory element 34 (Figure 1) to melt at least partially at the melting temperature (Tmelt) of the phase-change material. After reaching the peak of the reset pulse 210, the phase-change memory element is rapidly quenched within a sufficiently short time to prevent substantial recrystallization of the phase-change material.

[0013] Referring further to Figure 2, the operation that induces the transition of the phase change material from amorphous to crystalline, i.e., the set operation, is performed by applying a set pulse 220, for example, a current or voltage pulse, to the phase change memory element 34 (Figure 1) in a high-resistance reset state corresponding to a substantially amorphous state of the phase change material. The pulse can be applied by a selector element 38 to control its duration and / or magnitude. The set pulse 220 causes the phase change material of the phase change memory element 34 (Figure 1) to recrystallize at least partially at the crystallization temperature (Tcrys).

[0014] The operation to determine the state of the phase-change memory element 34 (Figure 1), i.e., the reading operation, can be performed by applying a reading pulse 230, for example, a pulse of current or voltage, and detecting the resulting electrical signal using a sensor amplifier. The pulse can be applied using a selector element to control its duration and / or magnitude.

[0015] In the example shown in Figure 1, the memory cell 30 is arranged as a pillar structure formed from a corresponding multilayer stack. As described below, each sidewall of the phase-change memory element 34 and / or selector element 38 may be exposed during manufacturing. These sidewalls may be exposed to a variety of process environments, such as air and moisture and other process gases and / or liquids. As a result, undesirably, one or more sidewalls of the phase-change memory element 34 and / or selector element 38 may absorb or chemically react with those gases and / or liquids from the process environment, thereby degrading the device characteristics of the PCM device 100. In addition, as described above with respect to Figure 2, after manufacturing, the various operations of the non-volatile memory device as described herein may expose the areas of the phase-change memory element 34 and / or selector element 38 to relatively high electric fields and / or high temperatures exceeding the melting temperature of the phase-change material, which can exceed several hundred degrees. Furthermore, such operating conditions may cause chemical reactions between the phase-change memory element 34 and / or selector element 38 and elements from the surrounding material, such as oxygen and moisture. Because the PCM device 100 may be periodically exposed to such conditions tens of thousands or hundreds of thousands of times or more, one or more of the set, reset, or read voltages or currents may degrade over time, leading to reliability failures. Some of these failures may be due to post-manufacturing contamination in various areas of the PCM device, including the phase-change memory element 34 and / or selector element 38.

[0016] [Phase-change memory cell lined with a sealing layer] To address the need to prevent degradation of the PCM device 100 described above, the inventors found it necessary to protect one or both of the phase-change memory element 34 and the selector element 38 with a sealing layer to protect them from moisture, air, or other impurities during manufacturing and / or operation. Figures 3A and 3B show an exemplary crosspoint memory array 300 formed on a semiconductor substrate 18, viewed from the y and x directions, respectively. The crosspoint array 300 has a plurality of memory cells 30 having sidewalls lined by sealing, according to the embodiment. Each memory cell 30 is longitudinally positioned between a first conductive line 20, which is, for example, one of the word lines or bit lines and extends in a first direction, and a second conductive line 22, which is, for example, the other of the word line or bit line and extends in a second transverse direction intersecting the first transverse direction. Each memory cell 30 has sealing layers 46, 52 formed on one or both of its sidewalls. The sealing layers 46 and 52 according to the embodiment include low electronegativity (low χ) metal oxide layers 46A and 52A, and the metals in the low χ metal oxide layers 46A and 52A have an electronegativity of 1.6 or less.

[0017] Refer further to Figures 3A and 3B. Each memory cell 30 is a phase-change memory cell, positioned between an upper conductive wire 20 extending in the y-direction and a lower conductive wire 22 extending in the x-direction. The upper conductive wire 20 and the lower conductive wire 22 are conductors configured to transmit electrical signals, such as voltage or current pulses, between the memory cell 30 and peripheral circuits (not shown), such as drive circuits and sensor circuits. The memory cell 30 includes a selector element 38 and a memory element 34 separated by an intermediate electrode 36. The illustrated memory cell 30 further includes a lower electrode 40 between the selector element 38 and the lower conductive wire 22, and an upper electrode 32 between the upper conductive wire 20 and the phase-change memory element 34. In some embodiments, it will be understood that the positions of the phase-change memory element 34 and the selector element 38 are interchangeable. Furthermore, in some embodiments, one or more of the upper electrode 32, the intermediate electrode 36, and the lower electrode 40 may be omitted.

[0018] Although not shown for clarity and simplification of illustration, it will be understood that the semiconductor substrate 18 may include a variety of structures processed through the front end of line, and may also include a variety of peripheral and / or support devices, such as CMOS transistors that form part of the word line and bit line drive circuits or sensor amplification circuits. Furthermore, the semiconductor substrate 18 may include one or more pre-formed structures thereon, such as diffusion regions, insulating regions, electrodes, and metallization structures such as contacts and metal wires, on which the array 300 can be placed. Some of these devices and structures may limit the thermal budget of the process steps used to manufacture the array 300, as will be discussed later.

[0019] The elements of the memory cell 30 according to embodiments of the present invention will now be described in detail. Referring further to Figures 3A and 3B, the phase change material of the phase change memory element 34 may include, in particular among many chalcogenide alloy systems, a chalcogenide alloy composition containing at least two elements from the GeSbTe(GST) alloy system, such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, etc., or a chalcogenide alloy composition containing at least two elements from the InSbTe(IST) alloy system, such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc. The chalcogenide alloy system may further contain certain elements, such as doped Si. Other chalcogenide alloy systems can be used that contain one or more chalcogenide elements and can undergo a phase change directly or indirectly in response to an electrical signal. Appropriate deposition techniques can be used to form a thin film layer capable of forming a phase-change memory element. For example, a thin film layer of the phase-change material can be deposited using, for example, physical vapor deposition, chemical vapor deposition, and atomic layer deposition, from which a phase-change memory element 34 can be formed by a combination of appropriate patterning techniques.

[0020] Referring to Figures 3A and 3B, the upper conductive wire 20 and / or the lower conductive wire 22 may contain metals. Examples of metals include elemental metals such as Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides such as TiN, TaN, WN, and TaCN; conductive metal silicides such as tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; and conductive metal oxides such as RuO2.

[0021] The selector element 38 includes a suitable two-terminal or three-terminal device that can be used to switch the memory state of the phase-change memory element. In some embodiments, the selector element includes a semiconductor device, such as a metallic silicon oxide (MOS) transistor, a bipolar junction transistor (BJT), a silicon-controlled rectifier (thyristor), a DIAC, a PN junction diode, or a Schottky diode. In some embodiments, the selector element 38 may include an ovonic threshold switch (OTS), which is a bidirectional symmetric two-terminal switch. Some OTSs include a chalcogenide composition. However, unlike the phase-change material of the phase-change memory element 34, the chalcogenide material of the OTS does not crystallize and does not undergo a phase change. Instead, when a voltage or electric field exceeding a threshold is applied to it, the OTS can be turned on to conduct current through it, and when the voltage or electric field is removed, the OTS can be turned off to block the current conducting through it. The OTS may include a chalcogenide composition comprising any of the chalcogenide alloy systems described above with respect to the phase change memory element 34, and may also include elements that can suppress crystallization, such as arsenic (As), nitrogen (N), and carbon (C). Examples of OTS material systems include, in particular, Te-As-Ge-Si, Ge-Te-Pb, Ge-Se-Te, Al-As-Te, Se-As-Ge-Si, Se-As-Ge-C, Se-Te-Ge-Si, Ge-Sb-Te-Se, Ge-Bi-Te-Se, Ge-As-Sb-Se, Ge-As-Bi-Te, and Ge-As-Bi-Se systems. Examples of chalcogenide alloy systems that can form OTS, though not limited to these, include TeAsGeSi, GeTePb, GeSeTe, AlAsTe, SeAsGeSi, SeAsGeC, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe alloy systems. An appropriate combination of process technologies can be used to form a thin film layer capable of forming an OTS. For example, a thin film layer of OTS material can be deposited using methods such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition, thereby enabling the formation of a selector element through an appropriate combination of patterning techniques.

[0022] Referring further to Figures 3A and 3B, the upper electrode 32, the intermediate electrode 36, and the lower electrode 40 may include materials that electrically connect the operating elements of the memory cell but are intended to prevent interaction and / or interdiffusion between adjacent materials. For example, depending on the adjacent materials, a suitable electrode material may include one or more conductive and semiconducting materials, such as carbon (C); n-doped polysilicon and p-doped polysilicon; metals including Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides including tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; and conductive metal oxides including RuO2.

[0023] Referring further to Figures 3A and 3B, in some embodiments, each layer of the memory cell 30 and the upper conductive wires 20 and lower conductive wires 22 may have lateral dimensions selected for a particular lithography technology node, for example, widths in the x and y directions, and may be in the range of about 3 nm to 60 nm, about 5 nm to 40 nm, or about 5 nm to 30 nm, depending on the technology node for integrated circuit design. Smaller or larger dimensions are also possible and are limited only by the lithography capabilities employed by those skilled in the art. The upper conductive wires 20 and lower conductive wires 22 may have lengths in the y and x directions, respectively, and may be selected to be much larger than their widths, for example, at least 100 times or 1000 times larger than their widths.

[0024] Referring to Figure 3A, the opposite sidewalls (in the x-direction) of the upper conductive wire 20 and the first opposite sidewalls (in the x-direction) of the memory cell 20 are lined with a first sealing layer 46, and the spaces between adjacent upper conductive wires 20 and adjacent memory cells 30 are filled with a first insulating material 50. Referring to Figure 3B, the opposite sidewalls (in the y-direction) of the lower conductive wire 22 and the second opposite sidewalls (in the y-direction) of the memory cell 30 are lined with a second sealing layer 52, and the spaces between adjacent lower conductive wires 22 and adjacent memory cells 30 are filled with a second insulating material 48.

[0025] The first sealing layer 46 and the second sealing layer 52 may be advantageous in protecting one or both of the phase-change memory element 34 and the selector element 38 from moisture, air, or other impurities during their manufacture. The first sealing layer 46 and the second sealing layer 52 may further function in minimizing cross-contamination and / or material interdiffusion between the various elements of the memory cell 30 and surrounding materials, such as adjacent memory cells and insulating materials, during their manufacture.

[0026] [Sealing layer of phase-change memory cell] As described above, the memory cell according to the embodiment has a sealing layer formed on its sidewall to protect one or both of the phase-change memory element and the selector element from the environment during its manufacture and / or operation. The physical and chemical properties of the sealing layer will be described below.

[0027] Returning to Figures 3A and 3B, one or both of the first and second sealing layers 46 and 52 have an oxide of a low electronegativity metal, i.e., a low electronegativity (low χ) metal oxide layer 46A, 52A. As described herein, a low χ metal is a metal having an electronegativity lower than the electronegativity of the elements of the phase-change memory element and / or selector element that are in contact with the low χ metal oxide layer 46A, 52A. For the various phase-change materials described herein, a low χ metal has an electronegativity value of about 1.6 or less. According to the embodiment, the electronegativity of the low χ metal is less than a value within the range defined by about 1.6, 1.5, 1.4, 1.3, 1.2, 1.1, 1.0, 0.9, 0.8, 0.7 or any of these values.

[0028] According to various embodiments, the low-χ metal oxide layers 46A and 52A can be oxides of one metal (M) having an electronegativity of less than 1.6, and being one of rare earth metals, transition metals, alkaline earth metals, or alkali metals. Therefore, the low-χ metal oxides 46A and 52A are MO x It can be written as follows, where M is a low χ metal, and MO x This indicates that the oxide may be stoichiometric or non-stoichiometric. For example, when M is La, the low χ metal oxide layers 46A and 52A are LaO x This can be done, in which case x is greater than zero and less than or equal to 1.5, and the stoichiometric lanthanum oxide is La2O3.

[0029] In some embodiments, the low-χ metal can be a rare earth metal. The rare earth metal can be one or more of the lanthanide and actinide elements. The lanthanide elements can be selected from the group consisting of La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. The actinide elements can be selected from the group consisting of Ac, Th, Pu, Am, Cm, Bk, Cf, Es, Fm, Md, and No.

[0030] In some other embodiments, the low electronegativity metal can be an alkaline earth metal selected from the group consisting of Mg, Ca, Sr, Ba, and Ra.

[0031] In some other embodiments, the low electronegativity metal can be an alkali metal selected from the group consisting of Li, Na, K, Rb, Cs, and Fr.

[0032] In some other embodiments, the low electronegativity metal can be a transition metal selected from the group consisting of Sc, Ti, V, Mn, Zn, Y, Zr, Nb, Hf, Ta, and Tl.

[0033] Referring further to Figures 3A and 3B, the inventors found that when the low-χ metals in the low-χ metal oxide layers 46A and 52A, which are part of the sealing layers 46 and 52, have an electronegativity sufficiently lower than that of oxygen, which has an electronegativity of 3.44, the sealing layers 46 and 52 not only function as a diffusion barrier protecting the memory cell 30 during manufacturing and operation, but can also chemically reduce any existing oxides in the chalcogenide material that may already be formed. The inventors found that this is due to at least some of the phase-change memory elements 34 and / or selector elements 38 having an electronegativity substantially higher than that of the low-χ metals. The inventors found that, at least in part, the low-χ metals of the low-χ metal oxides can attract oxygen from the chalcogenide oxide material because the difference in electronegativity between the low-χ metals and oxygen is relatively large compared to the difference in electronegativity between the phase-change elements 34 / selector elements 38 and oxygen. Therefore, according to the embodiment, when a chalcogenide oxide material is exposed to a low-χ metal precursor, the low-χ metal of the low-χ metal oxides 46A and 52A chemically reduces the chalcogenide oxide material at least partially, thereby reducing its oxygen content. The inventors have found that in order to efficiently bring about this process, it may be important that the low-χ metal of the low-χ metal oxide layers 46A and 52A has an electronegativity of about 1.6 or less.

[0034] According to several embodiments, the low-χ metal oxide layers 46A, 52A, comprising a metal oxide of a low electronegativity metal, have a thickness effective for functioning as a barrier and / or for chemically reducing the oxide of the chalcogenide material. On the one hand, the thickness must be sufficiently thick to conformally and continuously cover the desired sidewall of the memory cell 30. On the other hand, the thickness must be less than half the space between adjacent memory cells 30 in each direction, as shown in Figures 3A and 3B. The inventors have found that the thickness of the low-χ metal oxide layers 46A, 52A can be greater than 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or a value within the range defined by any of these values.

[0035] The inventors discovered that some low-χ metal oxide layers, being hygroscopic under given conditions, may undesirably absorb or react with moisture over time. This absorption and / or reaction can increase the thickness of some of the low-χ metal oxide layers. The inventors further discovered that under these conditions, it may be advantageous to form a capping layer as part of one or both of the first and second sealing layers 46, 52 to suppress the absorption and / or reaction of the low-χ metal oxide with moisture. Thus, returning to Figures 3A and 3B, in some embodiments, one or both of the first and second sealing layers 46, 52 include corresponding capping layers 46B, 52B formed on the low-χ metal oxide layers 46A, 52A, respectively. The inventors discovered that a certain high-K dielectric is particularly effective in achieving this objective.

[0036] According to these embodiments, one or both of the first and second sealing layers 46, 52 further include corresponding capping layers 46B, 52B, the capping layers having a high-K dielectric material including an oxide of Al, Zr, or Hf. For example, the capping layer may include one or more of Al2O3, ZrO2, and HfO2. x , ZrO x , and HfO x It may also be a quasi-stoichiometric oxide layer represented as follows.

[0037] If a capping layer is present, it will be understood that the capping layers 46B and 52B have sufficient thickness to conformally and continuously cover the corresponding low-χ metal oxide layers 46A and 52A. On the other hand, as shown in Figures 3A and 3B, their thickness must be small enough that the total thickness of the first and second sealing layers 46 and 52 is less than half the space between adjacent memory cells 30 in each direction. The inventors have determined that, if a capping layer is present, the thickness of the capping layer should not exceed a value within the range defined by 0.5 nm, 1 nm, 2 nm, 4 nm, 5 nm, or any of these values.

[0038] [Periodic deposition method for the sealing layer of phase-change memory cells] As described above, the memory cell according to the embodiment has a sealing layer formed on its sidewall to protect one or both of the phase-change memory element and the selector element from the environment during the process and / or operation. Returning to Figures 3A and 3B, in addition to the various characteristics described above, it is advantageous that one or both of the first and second sealing layers 46, 52 are deposited using the periodic deposition method described herein.

[0039] Periodic deposition processes such as atomic layer deposition (ALD) can provide relatively conformable thin films with relatively high thickness uniformity and precision on structures with relatively high aspect ratios (e.g., 2:1). Generally, thin films deposited using continuous deposition processes such as chemical vapor deposition (CVD) offer higher productivity and lower costs, although they are less conformable and uniform than ALD. According to the embodiment, first and second sealing layers 46, 52 are formed in the spaces formed between the lines or pillars of the memory cell 30 (Figures 3A and 3B), and these spaces have a relatively small width and / or a high aspect ratio. For example, these spaces may have a width smaller than 20 nm, 15 nm, 10 nm, 5 nm, or a value within the range defined by any of these values. Therefore, according to the embodiment, it is advantageous that the first and second sealing layers 46, 52 are formed using a periodic deposition process, such as ALD, as described herein. In particular, the periodic deposition process according to the embodiment is a thermal cycle deposition process that relies on chemical reactions between thermally activated precursors without the assistance of plasma.

[0040] A periodic deposition process, including atomic layer deposition (ALD) according to the embodiment, involves alternately exposing a substrate to multiple precursors to form a thin film in a layer-by-layer manner, and precisely controlling the properties of the thin film, such as conformality, uniformity, stress, and barrier properties against oxygen, moisture, and various other impurities. The reactants, i.e., precursors, may include oxidizing and reducing reactants that are alternately introduced into a reaction chamber in which the substrate is placed. The introduction of one or more reactants or precursors may be alternated with a purging and / or pumping process to remove excess reactants or precursors from the reaction chamber. The precursors or reactants may be introduced into the reaction chamber for a suitable period of time under conditions such that the surface on which the sealing layer is deposited is at least partially saturated with the precursors or reactants and / or reaction products of the reactants, e.g., substantially entirely saturated. Excess or residual precursors or reactants may then be purged and / or pumped out of the reaction chamber. The pumping process can be carried out by a suitable suction pumping process, and the purging step can be carried out by introducing an unreactive or inert gas, such as nitrogen or a noble gas, into the reaction chamber. Figure 4 shows an example of a precursor delivery sequence for forming a sealing layer according to an embodiment. Referring to Figure 4, the periodic deposition cycle or ALD cycle includes a first subcycle 400A, i.e., a vapor phase deposition step, and a second subcycle 400B, i.e., a vapor phase deposition step. The first subcycle 400A includes exposure of the substrate to a first precursor 404, and the second subcycle 400B includes exposure of the substrate to a second precursor 416. The first subcycle 400A is executable through a first ALD precursor delivery line including a first ALD valve, and the second subcycle 400B is executable through a second ALD precursor delivery line including a second ALD valve.

[0041] In some embodiments, one or both of the first subcycle 400A and the second subcycle 400B include a continuous purge 412, 424, each using an inert gas, such as Ar or N2. In some embodiments, one or both of the first subcycle 400A and the second subcycle 400B include a rapid purge 408, 420, each using an inert gas, following exposure to one or both of the first and second precursors. The rapid purges 408, 420 can be performed at a higher flow rate than the continuous purges 412, 424. In some embodiments, one or both of the continuous purge and the rapid purge can be omitted from one or both of the first and second subcycles 400A and 400B. In these embodiments, the precursor can be pumped out without a purge gas instead of rapid purging. It will be understood that the illustrated precursor delivery sequence may be a schematic representation of the sequence for forming one or both of the low-χ metal oxide layers 46A, 52A (Figures 3A, 3B) and the capping layers 46B, 52B (Figures 3A, 3B) described above. Below, the deposition method for forming the low-χ metal oxide layers 46A, 52A of the sealing layers 46, 52 will be described first, followed by the deposition method for forming the capping layers 46B, 52B.

[0042] Figure 5A schematically shows a method for manufacturing a phase-change memory cell according to an embodiment. Method 500 includes providing a substrate and forming a sealing layer. Figure 5B schematically shows a method for forming a sealing layer as part of the method shown in Figure 5A.

[0043] Referring to Figure 5A, the method 500 for manufacturing a phase-change memory cell includes providing a substrate having an exposed surface including a chalcogenide layer 510. The method 500 further includes forming a sealing layer including a low-χ oxide layer on the chalcogenide layer by periodically exposing the substrate to a low-χ metal precursor and an oxygen precursor, such as O2 520. In this case, the electronegativity of the low-χ metal in the low-χ metal oxide layer is 1.6 or less. Referring to Figure 5B, forming the sealing layer 520 includes exposing the substrate to one or more first subcycles, i.e., gas phase deposition stages 400A (Figure 4), which include exposure to a low χ metal precursor each time, and exposing the substrate to one or more second subcycles, i.e., gas phase deposition stages 400B (Figure 4), which include exposure to an oxygen precursor each time, 530.

[0044] Referring to Figure 5A, providing the substrate 510 includes providing a semiconductor substrate 18 (Figures 3A and 3B) having a surface containing a chalcogenide material. For example, providing the substrate may include lithographically patterning a layer stack to expose the sidewalls of the memory cells 30 (Figures 3A and 3B) before forming one or both of the one or more first and second sealing layers 46, 52. The exposed sidewalls may expose one or both of the phase-change memory elements 34 and the selector elements 38. Forming the sealing layer 520 may include forming at least a low-χ metal oxide layer, which will be described later.

[0045] Referring to Figure 5B, in various embodiments, exposure of the substrate in each of the one or more first deposition stages 525 includes exposure of the substrate to a low-χ metal precursor and exposure of the substrate to an oxygen precursor. Each exposure to the low-χ metal precursor is such that the substrate surface may be substantially or partially saturated with the metal precursor after the exposure. After the substrate is exposed to the low-χ metal precursor, any excess or residual metal precursor and / or reaction products that are adsorbed or chemically adsorbed and do not remain on the substrate surface can be removed from the substrate surface, for example, by pumping and / or purging from the process chamber. Each exposure to the oxygen precursor is such that the substrate surface may be substantially or partially saturated with the oxygen precursor after exposure. After the substrate is exposed to the oxygen precursor, any excess or residual oxygen precursor and / or reaction products that are adsorbed or chemically adsorbed onto the substrate surface can be removed from the substrate surface, for example, by pumping and / or purging from the process chamber. By subjecting the substrate to one or more first and second deposition steps, one or more monolayers or regions substantially formed from low χ metal oxides can be formed.

[0046] In some embodiments, exposure to a low-χ metal precursor in a given first deposition stage may be performed sequentially multiple times. Similarly, exposure to an oxygen precursor in a given second deposition stage may be performed sequentially multiple times. An advantage is that, under certain circumstances, exposure of the substrate to low-χ metal and / or oxygen precursors one or more times may result in higher surface saturation, for example, by exposing more reactive sites for the adsorption of each precursor when substantial steric hindrance effects are present.

[0047] In various embodiments, it will be understood that the number of cycles, each including one or both of the first and second deposition stages, the frequency and number of repetitions of the first deposition stage, the frequency and number of repetitions of the second deposition stage, the frequency and number of repetitions of substrate exposure to the low-χ metal precursor during the first deposition stage, and the frequency and number of repetitions of substrate exposure to the oxygen precursor during the second deposition stage, as described herein, can be modified based on various considerations, including the sensitivity of the precursor to steric hindrance effects, in order to obtain the desired thickness, stoichiometric composition, and other properties of the resulting low-χ metal oxide layer and the resulting encapsulation layer.

[0048] As described above, the inventors have found that low-χ metals can be effective in chemically reducing chalcogenide oxide materials or reducing their oxygen content. In these embodiments, the inventors have found that it may be particularly advantageous to begin the deposition of one or both of the first and second low-χ metal oxides 46A, 52A from a low-χ metal precursor. In these embodiments, referring to Figure 5B, exposure of the substrate to one or more first gas-phase deposition steps 525, each including exposure to a low-χ metal precursor, precedes any exposure of the substrate to one or more second gas-phase deposition steps 530, each including exposure to an oxygen precursor. By exposing the substrate to a low-χ metal precursor as a first precursor, low-χ metal atoms can be effectively provided in the vicinity of the underlying chalcogenide oxide material to chemically react with the oxygen atoms of the chalcogenide oxide material.

[0049] Alternatively, in some embodiments, a similar effect can be achieved by forming low-χ metal oxide layers 46A and 52A as quasi-stoichiometric oxide layers, thereby chemically reducing the chalcogenide oxide material and thereby reducing its oxygen content. In these embodiments, the low-χ metal oxide layers 46A and 52A of the first and second sealing layers 46 and 52 may have an oxygen content deficit of at least 10%, 20%, 30%, and 50%, respectively, compared to the stoichiometric oxide, or may have a deficit within the range defined by any of these values.

[0050] To deposit the low-χ metal oxide layers 46A and 52A according to the embodiment (Figures 3A and 3B), the following metal precursors and oxygen precursors can be used as non-limiting examples.

[0051] Non-limiting examples of Sr precursors include bis(2,2,6,6-tetramethyl-3,5-heptanedione)strontium ("Sr(tmhd)2").

[0052] Non-limiting examples of La precursors include tris-isopropylcyclopentadienyllanthane ("La(iPrCp)3"), tris-formamidinatelanthane ("La(fAMD)3"), and tris(2,2,6,6-tetramethyl-3,5-heptanedionate)lanthane ("La(tmhd)3").

[0053] Non-limiting examples of Ti precursors include TiCl4, StarTi, tetrakis-dimethylaminotitanium ("TDMAT"), tetrakis-diethylaminotitanium ("TDEAT"), tetrakis-ethylmethylaminotitanium ("TEMAT"), titanium tetrakis-isopropoxide ("TTIP"), titanium methoxide, titanium ethoxide, titanium t-butoxide, chlorotriisopropoxytitanium, titanium 2-ethylhexyloxide, and titanium oxyacetylacetonate.

[0054] Non-limiting examples of Nb precursors include tert(butylimide)tris(diethylamide)niobium(V) ("TBTDENb").

[0055] Non-limiting examples of Ta precursors include tertiary butyrimide trisdiethyltantalum ("TBTDETa") and tertiary butylimido trisethylmethylaminotantalum ("TBITEMATa").

[0056] Non-limiting examples of Mg precursors include bis-ethylcyclopentadienylmagnesium ("Mg(CpEt)2"), tetra(2,2,6,6-tetramethyl-3,5-heptanedionate)magnesium ("Mg2(tmhd)4"), and Mg(tmhd)2(EtOH)2, where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedionate.

[0057] Non-limiting examples of Ce precursors include Ce(iPrCp)3, Ce(tmhd)4, and Ce(tmhd)3phen, where iPrCp is isopropylcyclopentadienyl, tmhd is 2,2,6,6-tetramethyl-3,5-heptanedione, and phen is 1,10-phenanthroline.

[0058] Non-limiting examples of Gd precursors include tris(2,2,6,6-tetramethyl-3,5-heptanedione)gadolinium ("Gd(tmhd)3"), trisisopropylcyclopentadienylgadolinium ("Gd(iPrCp)3"), (tris(2,3-dimethyl-2-butoxy)gadolinium(III)) ("Gd[OC(CH3)2CH(CH3)2]3"), and Gd(CpCH3)3, where Cp is cyclopentadienyl (C5H5).

[0059] A non-limiting example of a Dy precursor is Dy(tmhd)3, where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedione.

[0060] A non-limiting example of an Er precursor is Er(tmhd)3, where tmhd is 2,2,6,6-tetramethyl-3,5-heptanedione.

[0061] Non-limiting examples of Y precursors include yttrium tris(N,N'-diisopropylacetamidinate) ("Y(iPr2amd)3"), (CpCH3)3Y, where Cp is cyclopentadienyl, and further, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)yttrium ("Y(tmhd)3").

[0062] Non-limiting examples of Sc precursors include tris(2,2,6,6-tetramethyl-3,5-heptanedione)scandium (Sc(tmhd)3), Sc(MeCp)3, and Sc(MeCp)2 (Me2pz) (where 1,MeCp is methylcyclopentadienyl and Me2pz is 3,5-dimethylpyrazolate).

[0063] According to various embodiments, non-limiting examples of oxygen precursors for forming the first and second low-χ metal oxide layers 46A, 52A include O2, O3, and H2O. The inventors have found that, depending on the situation, one oxygen precursor may be preferable to another. For example, the inventors have found that while O3 can generally provide relatively high growth rates and high film density, it can unduly cause further oxidation of one or both of the chalcogenide materials in the phase-change memory element and the selector element. As a result, in preferred embodiments, O2 may be employed to limit the undesirable oxidation of one or both of the chalcogenide materials in the phase-change memory element and the selector element. Limiting undesirable oxidation can be important, for example, when the lateral dimensions of the memory cell are on a scale of less than 20 nm. At such dimensions, the effective amount of chalcogenide material available for either memory or threshold switching can be greatly reduced by oxidation of the chalcogenide material. On the other hand, if the memory cell is relatively large, for example, >20 nm, further oxidation is not a major problem, and O3 can be employed for high film quality and productivity.

[0064] To deposit the capping layers 56B and 52B according to the embodiment (Figures 3A and 3B), the following metal precursors and oxygen precursors can be used as non-limiting examples.

[0065] Non-restrictive examples of Al precursors include Al(CH3)3 ("TMA").

[0066] Non-restrictive examples of Hf precursors include Hf[N(CH3)(C2H5)]4 ("TEMAH") and Hf[N(CH3)2]4.

[0067] Non-restrictive examples of Zr precursors include Zr[N(CH3)(C2H5)]4 ("TEMAZ"), Zr[N(CH3)(C2H5)]4 ("TEMAZ"), and Zr[N(CH3)2]4, and Zr[N(CH3)2]4.

[0068] Non-limiting examples of oxygen precursors for forming the capping layer include O2, O3, and H2O. The inventors found that since the capping layers 46B and 52B (Figures 3A and 3B) are formed on the low-χ metal oxide layers 46A and 52A (Figures 3A and 3B) already formed on the chalcogenide material, using O3 may not cause substantial further oxidation of the chalcogenide material. Therefore, O3 may be suitable for depositing the capping layer at a higher growth rate and higher film density under certain circumstances, for example, when the thickness of the low-χ metal oxide layers 46A and 52A exceeds 2 nm. However, if the first and second low-χ metal oxide layers 46A and 52A are relatively thin, for example, thinner than 2 nm, then O2 can be used to cause further oxidation of the chalcogenide material of one or both of the phase-change memory element and the selector element, even in the presence of the low-χ metal oxide layers 46A and 52A.

[0069] The low-χ metal oxide layers 46A, 52A (Figures 3A, 3B) and the capping layers 46B, 52B (Figures 3A, 3B) can be formed at relatively low temperatures. Low-temperature deposition can be important for several reasons in order to protect the chalcogenide material as described herein. For example, the sealing layers 46, 52 (Figures 3A, 3B) are advantageous in that they can be deposited at temperatures that do not exceed the thermal budget in most back-end-of-line (BEOL) portions of the process flow for manufacturing PCM memory devices. In some PCM devices, as described above, the thermal budget can be lowered to 400°C or less to prevent degradation of the metallization structure and / or to change the properties of the diffuse semiconductor region formed on the substrate or the device. Furthermore, when formed after the formation of the phase-change memory element, the sealing layers 42, 56 are advantageous in that they can be formed at deposition temperatures that significantly change the nanostructure or microstructure, such as crystallization of the phase-change memory element. When it is advantageous for the phase-change memory element to maintain an amorphous phase throughout the manufacturing process flow, the low deposition temperature of the sealing layers 46, 52 can suppress substantial crystallization of the phase-change memory element. In these embodiments, the deposition temperature can be lower than the crystallization temperature of the phase-change memory element. Maintaining the amorphous phase of the phase-change memory element throughout the manufacturing flow can be advantageous in several situations, for example, when reliability testing of the phase-change memory element is performed after manufacturing without passing a huge test current. According to the embodiments, in order to realize these and other advantages, the low-χ metal oxide layers 46A, 52A and the capping layers 46B, 52B can be formed at a substrate temperature within the range defined by 200°C to 250°C, 250°C to 300°C, 300°C to 350°C, 350°C to 390°C, 350°C to 400°C, or any of these values, for example, 285°C.

[0070] [Method for lining the sidewalls of a phase-change memory cell with a sealing layer] In the following, as an example, an integration scheme for manufacturing a phase-change memory device including sealed memory cells according to an embodiment is described. Figures 6A to 6H show intermediate structures at various stages in manufacturing a crosspoint array having sealed phase-change memory cells according to an embodiment to reach array 300 (Figures 3A, 3B). Figures 6A, 6C, 6E, and 6G are cross-sectional views of the intermediate structures of the crosspoint memory array at various stages of manufacturing, viewed from the y-direction (e.g., bit line direction), and Figures 6B, 6D, 6F, and 6H are cross-sectional views of the intermediate structures of the crosspoint array viewed from the x-direction (e.g., word line direction).

[0071] Referring to the intermediate structures shown in Figures 6A and 6B, the method for manufacturing a memory array includes forming a memory cell material stack on a substrate 18. The illustrated stack includes a lower conductive material 22a formed on the substrate 18 and a memory cell material stack formed on top of it, which includes a lower electrode material 40a on the lower conductive material 22a, a selector element material 38a on the lower electrode material 40a, an intermediate electrode material 36a on the selector element material 38a, a phase change memory element material 34a on the intermediate electrode material 36a, and an upper electrode material 32a on the phase change memory element material 34a. The above features of the lower conductive material 22a and the memory cell material stack can be formed, for example, by deposition techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0072] Referring to the intermediate array structure 100b in Figures 6C and 6D, the method for manufacturing the memory array further includes reducing the amount of material stacking of the memory cell material stack and the lower conductive material 22a (Figures 6A and 6B) by patterning them using a first photomask and a first etching process to form a memory cell line stack on the lower conductive line 22, both extending in the x direction. The memory cell line stack includes a lower electrode line 40b on the lower conductive line 22, a first active element line 38b (e.g., a memory element line) on the lower electrode line 40b, an intermediate electrode line 36b on the first active element line, a second active element line 34b (e.g., a memory element line) on the intermediate electrode line 36b, and an upper electrode line 32b on the second active element line 34b.

[0073] Referring further to the intermediate array structures in Figures 6C and 6D, after the formation of the memory cell line stack, a sealing layer 52a, including its sidewalls, is formed on the line stack extending in the x direction, as shown in Figure 6D. The first sealing layer 52a may include one or both of the low-χ metal oxide layer and the capping oxide layer, respectively, formed using the thermal cycle deposition method described above. For example, at advanced technology nodes of 20 nm or more, it will be understood that thermal cycle deposition processes such as thermal ALD can be particularly advantageous in applying the sealing layer 52a inside high aspect ratio trenches between memory cell line stacks.

[0074] Referring further to the intermediate array structure 100b in Figures 6C and 6D, the inter-line spaces between adjacent memory cell line stacks are filled with dielectric material to form insulating dielectric regions 48a. Suitable dielectric materials for filling these spaces may include, for example, silicon oxides and silicon nitrides, which can be deposited by known suitable gap-filling processes. Once the inter-line spaces between adjacent memory cell line stacks are filled, the intermediate array structure 100b may be chemically and mechanically polished (not shown) to form alternating memory cell line stacks and insulating dielectric regions 48a in the y-direction.

[0075] Referring to the intermediate array structure 100c in Figures 6E and 6F, the manufacturing method of the memory array further includes depositing an upper conductive material and reducing its patterning using a second photomask to form a plurality of upper conductive wires 20 extending in the y direction. The upper conductive material may include a material similar to or the same as that of the lower conductive wires 22 and may be formed using substantially similar or the same process as described above for forming the lower conductive wires 22. Once formed, the plurality of upper conductive wires 20 are positioned above the alternating memory cell line stack and the insulating dielectric region 48b. The upper conductive wires 20 extend in the y direction and intersect the memory cell line stack extending in the x direction. By forming the upper conductive wires 20, as shown in Figure 6E, a portion of the upper electrode wires 32b of the alternating line stack is exposed, as well as a portion of the starting insulating dielectric region 48b between adjacent upper conductive wires 20.

[0076] Referring to the intermediate structure 100d in Figures 6G and 6H, the method for forming the memory array further includes forming a pillar of memory cells at the intersection of the lower conductive wire 22 and the upper conductive wire 20 by removing at least the upper part of the exposed portion of the memory cell line stack in Figures 6E and 6F. In the illustrated embodiment, the entire exposed portion (upper and lower parts) of the memory cell line stack is removed by stopping etching at the lower conductive wire 22 (or at the etching stop layer above it), and the resulting pillar includes an upper electrode 32, a phase change memory element 34, an intermediate electrode 36, a selector element 38, and a lower electrode 40. In other embodiments, etching can be stopped after etching any of the layers above the lower conductive wire 22, thereby allowing one of the cell stack component layers, for example, the lower electrode 40 or the first active element 38, to form a line similar to the lower electrode wire 22. The intermediate structure 100d thus formed includes a pillar of memory cells formed at the intersection of the lower conductive wire 22 and the upper conductive wire 20, separated by a space 50 in the x-direction.

[0077] After forming a pillar of memory cells between the lower conductive wire 22 and the upper conductive wire 20, the method for forming the memory array includes forming a second sealing layer 46 on the side wall of the pillar shown in Figure 6G, and then filling the gap formed between the pillars with insulating material 50 to reach the intermediate structure 300 described in relation to Figures 3A and 3B. Similar to the first sealing layer 52, the second sealing layer 46 may also include one or both of the low-χ metal oxide layer 46A and the capping oxide layer 46B formed using the thermal cycle deposition process described above. For example, a thermal cycle deposition process such as ALD may be particularly advantageous for applying the sealing layer 46 inside high aspect ratio trenches between memory cell pillars. In a subsequent process, the intermediate structure 300 may be chemically and mechanically polished to remove the insulating material 50 on the upper surface of the upper conductive wires 20 before forming a BEOL metallization structure to electrically connect the memory cell 30. Once formed in this way, the combination of sealing layers 46 and 52 can surround the memory cell 30 to completely seal it in all directions.

[0078] [Examples] Figure 7A is a graph showing the experimentally measured change in the thickness of the lanthanum oxide layer over time in the embodiment, as a function of the thickness of the hafnium oxide capping layer formed on top of it. As described above, the increasing thickness over time can serve as an indicator of the absorption of moisture from the environment into the low-χ oxide layer and / or its reaction with it. Figure 7B is a graph showing the experimentally measured change in the thickness of the lanthanum oxide layer over time in the embodiment, as a function of the thickness of the aluminum oxide capping layer formed on top of it. In Figures 7A and 7B, the x-axis represents the thickness of the capping layer, and the y-axis represents the thickness of the underlying low-χ metal oxide layer. In each of the experimental measurements shown in Figures 7A and 7B, the lanthanum oxide layer was deposited as a low-χ metal oxide layer of the sealing layer by varying the amount of the capping layer, and the measured change in the thickness of the lanthanum layer was determined by the inventors to be phase-related to the absorption and / or reaction with moisture. The arrows indicate the magnitude of the change in the thickness of the lanthanum oxide layer. The lanthanum oxide layer was deposited using the Eugenus QXP-8300® ALD system with 1 M tris(isopropylcyclopentadienyl)lanthanum (La(iPrCp)3) in decalin as a low-χ precursor and oxygen as an oxygen precursor. To protect the underlying lanthanum oxide layer from moisture in the air, for samples containing hafnium oxide and aluminum oxide layers, the hafnium oxide and aluminum oxide layers were deposited in situ at 285°C at 6 Å and 10 Å, respectively, using the same QXP-8300(registered trademark) ALD system with TEMAH and TMA as metal precursors. As shown in the figure, the lanthanum oxide layer without a capping layer increased in thickness by more than 50% compared to its original thickness. In contrast, the 6 Å hafnium oxide and aluminum oxide capping layer significantly suppressed the increase in thickness. The 10 Å hafnium oxide and aluminum oxide capping substantially maintained the thickness of the lanthanum oxide layer within the experimental error range.

[0079] Figures 8A-8C show experimental evaluations of the adhesion strength of the sealing layer formed according to the embodiment. Figure 8A shows a wafer map in which experimental adhesion strength tests of the sealing layer were performed. The sealing layer needs to have high adhesion strength to the underlying layer, for example, the sidewall of the phase change memory cell described herein. Therefore, the adhesion strength of the lanthanum oxide layer formed on the Si substrate was performed using a tape test. Adhesive tape was applied to the lanthanum oxide layer and peeled off, and the lanthanum oxide layer was visually observed to determine whether or not it had separated. The central, intermediate, and edge regions of the wafer, as indicated in the substrate map shown on the left side of Figure 8A, were tested for uniformity of adhesion strength within the wafer. To statistically quantify adhesion defects, each square region shown in Figure 8A was marked with a diamond pencil to create a 10x10 matrix containing 100 squares, as shown on the right side of Figure 8A, before applying the tape. Then, the tape was applied to the square regions on the encapsulation layer and removed by pulling it perpendicularly away from the wafer surface. Adhesion strength was qualitatively evaluated after removing the tape by counting the number of missing squares in the deposited encapsulation layer within the 10x10 matrix of 100 marked squares.

[0080] Figure 8B shows a scanning electron microscope (SEM) image of one of the marked squares within a 10 × 10 matrix that underwent an adhesion strength test. The SEM image shows residual adhesive from the tape across the entire forward direction of the markings, indicating that the encapsulating layer was not peeled off. Analysis showed that no encapsulating layer was lost within any of the square regions. This indicates excellent adhesion strength of the encapsulating layer on the Si substrate.

[0081] FIG. 8C shows an energy-dispersive X-ray spectrum (EDS) obtained from one of the square regions where the adhesion strength test was performed. This spectrum was obtained from 5 out of the 100 grid-drawn squares of the 10×10 matrix shown in FIG. 8B. The EDS peak analysis shows peaks of La and Al on the film, which are LaO x film and AlO x The sealing layer including the capping layer remains after the adhesion test, indicating that it remains.

[0082] FIG. 9A shows a cross-sectional transmission electron micrograph (XTEM) of a sealing layer including a LaO x layer and a HfO x layer formed on a Si substrate according to an embodiment. FIG. 9B shows an elemental map obtained from an electron energy loss spectrum (EELS) obtained from the XTEM shown in FIG. 9A according to an embodiment. FIG. 9C shows a depth profile of the composition of the sealing layer imaged in FIG. 9A. This result shows the presence of an interfacial oxide layer between the lanthanum oxide layer and the Si substrate, which shows a strong affinity between La atoms and oxygen atoms. In addition, this result shows that La and Hf do not diffuse into other layers, and that the LaO x layer and the HfO x layer remain as separate layers.

[0083] Although the present invention has been described herein with reference to specific embodiments, these embodiments are not intended to limit the present invention but are described for purposes of illustration. It will be apparent to those skilled in the art that changes and improvements can be made without departing from the spirit and scope of the present invention.

[0084] Such simple changes and improvements to the various embodiments disclosed herein are within the scope of the disclosed technology, and the specific scope of the disclosed technology will be further defined by the appended claims.

[0085] It will be understood from the above that any one feature of an embodiment can be combined with or substituted for any other feature of an embodiment.

[0086] Unless the context clearly requires otherwise, throughout this specification and the claims, words such as “comprise,” “consisting,” “include,” and “including” shall be interpreted in a comprehensive sense, that is, “including but not limited to,” as opposed to an exclusive or exhaustive sense. The term “coupled” as commonly used herein refers to two or more elements that are directly connected or connected via one or more intermediate elements. Similarly, the term “connected” as commonly used herein refers to two or more elements that are directly connected or connected via one or more intermediate elements. Furthermore, in this specification, “herein,” “above,” “below,” and similar terms shall refer to this specification as a whole, not to any particular part thereof. In addition, in the above description of modes for carrying out the invention, words used singular or plural may include plural or singular, respectively, where the context permits. The word "or" when referring to a list of two or more items encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0087] Furthermore, conditional words used herein, particularly “can,” “could,” “might,” “may,” “eg,” “for example,” and “such as,” are generally intended to convey that a particular embodiment includes certain features, elements, and / or states, while other embodiments do not, unless otherwise specified or understood within the context in which they are used. Therefore, such conditional words are generally not intended to suggest that features, elements, and / or states are required in any way in one or more embodiments, or that these features, elements, and / or states are included in or performed in any particular embodiment.

[0088] While specific embodiments have been described, these embodiments are presented for illustrative purposes only and are not intended to limit the scope of the disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications to the forms of methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while a function is shown in a given mechanism, in an alternative embodiment, a similar function may be performed with different components and / or sensor topologies, and some functions may be deleted, moved, added, subdivided, combined, and / or modified. Each of these functions can be performed in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. The various functions and processes described above may be performed independently of each other or combined in a variety of ways. All possible combinations and subcombinations of the features of the disclosure are intended to fall within the scope of the disclosure.

Claims

1. A method for manufacturing semiconductor devices, A substrate having an exposed surface containing a chalcogenide material is provided, and Low electronegativity (low χ) metal precursors and oxygen O ２ This includes forming a low-χ metal oxide layer on the chalcogenide material by periodically exposing the substrate to an oxygen precursor containing the following: A method wherein the electronegativity of the low χ metal of the metal precursor is 1.6 or less.

2. The method according to claim 1, wherein the electronegativity of the low-χ metal of the metal precursor is less than the electron mark accuracy of the element of the chalcogenide material.

3. The method of claim 2, wherein the elements of the chalcogenide material are one or more of Ge, Sb, Te, Si, Se, and As.

4. The method of claim 1, wherein forming the low-χ metal oxide includes periodically exposing the substrate to the low-χ metal precursor and the oxygen precursor at a temperature of 300°C or less without the assistance of plasma.

5. The method of claim 4, wherein the low-χ metal is a rare earth metal.

6. The rare earth metal is La and the low χ metal oxide layer is LaO ２ The method of claim 5, comprising a layer.

7. The method of claim 6, wherein periodic exposure includes exposing the chalcogenide material to a La precursor as a first precursor.

8. The method of claim 7, wherein the La precursor comprises tris(isopropylcyclopentadienyl)lanthanum.

9. The method of claim 5, wherein providing a substrate includes providing a chalcogenide material having a surface region containing a chalcogenide oxide material, and forming a low-χ metal oxide includes chemically reducing the chalcogenide oxide material with the rare earth metal.

10. The method of claim 5, wherein the low-χ metal oxide includes a quasi-stoichiometric rare-earth metal oxide.

11. The method of claim 1, further comprising forming a capping metal oxide layer on the low-χ metal oxide layer by periodically exposing the substrate to a second metal precursor and a second oxygen precursor.

12. The capping metal oxide layer is HfO ｘ Or AlO ｘ The method of claim 11, including the method of claim 11.

13. The second oxygen precursor is O ２ The method of claim 12, or comprising ozone.

14. The method of claim 1, wherein the substrate includes an intermediate structure of a crosspoint array comprising a plurality of memory cells arranged between bit lines and word lines, the intermediate structure comprising the chalcogenide material as part of a phase-change memory element, and the formation of the low-χ metal oxide layer includes forming it directly on the exposed sidewall of the phase-change memory element.

15. The method of claim 14, wherein forming the low-χ metal oxide layer prevents the phase-change memory element from crystallizing.

16. A method for manufacturing semiconductor devices, A substrate is provided on which a chalcogenide layer is formed. Patterning the chalcogenide layer in order to expose the sidewalls of the chalcogenide layer, This includes forming a low-χ metal oxide layer on the sidewall of the chalcogenide layer by periodically exposing the substrate to a low-electronegativity (low-χ) metal precursor and an oxygen precursor at a temperature of 300°C or below without the support of plasma, A method wherein the electronegativity of the low χ metal of the metal oxide is 1.6 or less.

17. The method of claim 16, wherein the substrate includes an intermediate structure of a crosspoint array including a plurality of memory cells arranged between bit lines and word lines, the intermediate structure includes the chalcogenide layer as part of a phase-change memory element, and the low-χ metal oxide is formed directly on the exposed sidewall of the phase-change memory element.

18. The method of claim 17, wherein the exposed sidewall of the phase-change memory element contains a chalcogenide oxide material, and the formation of the low-χ metal oxide layer includes chemically reducing the chalcogenide oxide material with the low-χ metal.

19. The method of claim 17, wherein the elements of the chalcogenide layer include one or more of Ge, Sb, Te, Si, Se, and As.

20. The method of claim 19, wherein the electronegativity of the low χ metal is smaller than the electronegativity of the elements in the chalcogenide layer.

21. The method of claim 16, wherein the low χ metal is a lanthanide element.

22. The oxygen precursor is O ２ The method of claim 21, including the method of claim 21.

23. The method of claim 16, wherein periodic exposure includes exposing the chalcogenide layer to a rare earth metal precursor as a first precursor.

24. The method of claim 23, wherein the rare earth metal precursor includes a La precursor.

25. The method of claim 16, further comprising forming a capping metal oxide layer on the low-χ metal oxide layer by periodically exposing the substrate to a first metal precursor and a second oxygen precursor.

26. The capping metal oxide layer is HfO ｘ Or AlO ｘ The method of claim 25, including the method of claim 25.

27. A method for manufacturing semiconductor devices, The method includes providing a substrate on which a chalcogenide material is formed, wherein the chalcogenide material has a chalcogenide oxide material formed on its surface region, and This includes at least partially chemically reducing the chalcogenide oxide material by exposing it to a low electronegativity (low χ) metal precursor. A method wherein the electronegativity of the low-χ metal of the metal precursor is 1.6 or less, thereby reducing the oxygen content of the surface region compared to the surface region before the chalcogenide oxide material is exposed to the low-χ metal precursor.

28. The method of claim 27, wherein the electronegativity of the low χ metal is smaller than the electronegativity of the element of the chalcogenide material.

29. The method of claim 28, wherein the elements of the chalcogenide material include one or more of Ge, Sb, Te, Si, Se, and As.

30. The method of claim 29, wherein the low-χ metal is a rare earth metal.

31. The method of claim 30, wherein exposure to the low electronegativity (low χ) metal precursor includes directly exposing the chalcogenide oxide material to the La precursor.

32. The method of claim 31, wherein the La precursor comprises tris(isopropylcyclopentadienyl)lanthanum.

33. The method of claim 27, comprising periodically exposing the substrate to the low-χ metal precursor and the oxygen precursor in order to form a low-χ metal oxide layer.

34. Forming the low-χ metal oxide layer includes exposing the substrate to the low-χ metal precursor and O without plasma assistance at 300 °C or lower. ２ The method of claim 33, further comprising periodically exposing the substrate to ２ .

35. A phase-change memory device, The device has a memory cell arranged vertically between a first conductive wire extending in a first transverse direction and a second conductive wire extending in a second transverse direction that intersects the first transverse direction. The memory cell includes a phase-change memory element and a selector element, A phase-change memory device having a low electronegativity (low χ) metal oxide layer formed on the side wall of the memory cell, wherein the electronegativity of the low χ metal in the low χ metal oxide layer is 1.6 or less.

36. The phase-change memory device according to claim 35, wherein a low-χ metal oxide layer surrounds each of the phase-change memory elements and the selector element.

37. The phase-change memory device according to claim 35, wherein each of the phase-change memory element and the selector element comprises a chalcogenide material, and the electronegativity of the low-χ metal is less than the electronegativity of each element of the phase-change memory element and the selector element.

38. The phase change memory device according to claim 35, wherein the low-χ metal is a rare earth metal.

39. The rare earth metal is La, and the low χ metal oxide layer is LaO ｘ A phase-change memory device according to claim 38, including a layer.

40. The phase change memory device according to claim 35, further comprising a capping metal oxide layer on the low-χ metal oxide layer.

41. The capping metal oxide layer is HfO ｘ Or AlO ｘ A phase-change memory device according to claim 40, including the above.

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