Data storage device and method for dynamic bit error rate estimation scan (BES).

Abstract

The present invention provides a data storage device, storage system, and method for performing a Dynamic Bit Error Rate Estimation Scan (BES), comprising memory and one or more processors. [Solution] After BES5 is started 910, the controller of the data storage device determines whether the page being read is in a special offset pool 920. If so, proceed to BES5 with the updated offset 930; otherwise, proceed to BES5 with the default offset 940. Next, the controller determines whether the shift is greater than a predefined read level (RL) threshold 950. If so, terminate 960; otherwise, update the page information to place the page in the special offset pool 970, and then terminate 980.

Description

Technical Field

[0001] A data storage device includes a memory for storing data. To increase the storage density, multi-level cells (MLCs) can be used to store two or more bits per memory cell in the memory. During operation, after determining the sequence of bits to be stored in a particular memory cell, the memory cell is programmed to a state by setting a threshold voltage corresponding to the sequence of bits. To read the memory cell, the memory cell is sensed and its threshold voltage is compared with one or more read voltages. However, the sensed threshold voltage can sometimes vary from the written threshold voltage due to one or more factors such as process variations, data retention issues, and program disturb conditions.

Brief Description of the Drawings

[0002] [Figure 1A] It is a block diagram of a data storage device according to an embodiment. [Figure 1B] It is a block diagram illustrating a memory module according to an embodiment. [Figure 1C] It is a block diagram illustrating a hierarchical memory system according to an embodiment. [Figure 2A] It is a block diagram illustrating the components of a controller of a data storage device illustrated in FIG. 1A according to an embodiment. [Figure 2B] It is a block diagram illustrating the components of a data storage device illustrated in FIG. 1A according to an embodiment. [Figure 3] It is a block diagram of a host and a data storage device according to an embodiment. [Figure 4] It is a graph of an embodiment in which the bit error rate (BER) estimation scan (BES) delta is extended. [Figure 5] It is a graph of an embodiment in which the BES offset is adjusted. [Figure 6]This is a graph of the BES range for one embodiment. [Figure 7] This is a graph of one embodiment in which the high-temperature data retention BES range is limited. [Figure 8] This is a graph of one embodiment in which the high-temperature data retention BES range has a dynamic BES offset. [Figure 9] This is a flowchart of a dynamic BES offset method according to one embodiment. [Modes for carrying out the invention]

[0003] The following embodiments generally relate to data storage devices and methods for dynamic bit error rate estimation scans (BES). In one embodiment, a data storage device is provided comprising memory and one or more processors. The one or more processors are configured to individually or in combination to perform a first bit error rate estimation scan (BES) on a scan range in memory, wherein the BES is performed using a first offset to determine whether a page in the scan range contains a digital-to-analog conversion (DAC) shift below a threshold, and, in response to determining that a page in the scan range contains a DAC shift below a threshold, to perform a second BES on the page, wherein the second BES is performed using a second offset.

[0004] Another embodiment provides a method to be performed in a data storage device having memory. This method includes: initiating a bit error rate estimation scan of a page in memory; determining whether the page is associated with an offset pool; and, depending on whether the page is associated with an offset pool, proceeding with the bit error rate estimation scan of the page using the updated offset.

[0005] In yet another embodiment, a data storage device is provided, comprising: a memory; and means for performing a first bit error rate estimation scan (BES) on a scan range in the memory, wherein the BES is performed using a first offset to identify whether a page in the scan range contains a digital-to-analog (DAC) shift below a criterion; and for performing a second BES on the page, wherein the second BES is performed using a second offset.

[0006] Other embodiments are also possible, and each embodiment can be used individually or in combination. Accordingly, various embodiments are described herein with reference to the accompanying drawings.

[0007] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, and hybrid drives. Illustrative details of DSDs are provided below.

[0008] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in Figures 1A and 1C. Note that these are examples only, and other implementations may be used. Figure 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to Figure 1A, the data storage device 100 in this example includes a controller 102 coupled to a non-volatile memory which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells and associated circuits for managing the physical operation of those non-volatile memory cells, formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory dies 104. Also as used herein, the phrases “communicate with” or “coupled with” may mean directly communicating / coupled, or indirectly communicating / coupled through one or more components, which may or may not be illustrated or described herein. The communication / coupled may be wired or wireless.

[0009] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include, individually or in combination, one or more components configured to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, as shown in Figure 2A, the controller 102 may include one or more processors 138 configured individually or in combination to perform functions, including but not limited to those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-temporary memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) inside and / or outside the controller 102. As another example, one or more components may include, but are not limited to, circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0010] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device having any suitable operating system. In addition to the specific functions described herein, the non-volatile memory controller 102 may have a variety of other functions. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory is functioning properly, map out faulty non-volatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells may be used to operate the non-volatile memory controller and hold firmware (and / or other metadata used for housekeeping and tracking) to implement other features. While operating, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address from which data is read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address in the non-volatile memory. Non-volatile memory controllers can also perform a variety of memory management functions, including, but are not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to new blocks after a block is full, so that full blocks can be erased and reused).

[0011] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be once programmable, multiple times programmable, or many times programmable. The memory cells may also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or other memory cell level technologies currently known or to be developed may be used. Furthermore, the memory cells may be manufactured in two-dimensional or three-dimensional manner.

[0012] The interface between the controller 102 and the non-volatile memory die 104 may be any preferred flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system such as a Secure Digital (SD) or Micro Secure Digital (microSD) card. In another embodiment, the data storage device 100 may be part of an embedded data storage device.

[0013] In the example illustrated in Figure 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in Figures 1B and 1C), depending on the capabilities of the controller, two, four, eight or more memory channels may exist between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the drawings, two or more channels may exist between the controller and the memory die.

[0014] Figure 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. Thus, the storage module 200 may include a host and a storage controller 202 that interfaces with a data storage device 204 containing the plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, double-data-rate (DDR) interface, or serial attached small-scale compute interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptop computers and tablet computers.

[0015] Figure 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each controlling its own data storage device 204. A host system 252 can access the memory in the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0016] Referring again to Figure 2A, the controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, including, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls internal bus arbitration of the controller 102. The modules may include one or more processors or components, as considered above. ROM 118 can store system boot code. Although illustrated separately in Figure 2A, in other embodiments, one or both of RAM 116 and ROM 118 may be located within the controller 102. In yet another embodiment, parts of RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0017] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with the host or a next-level storage controller. The choice of host interface 120 may depend on the type of memory being used. Examples of host interface 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0018] The backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, to be sent to the non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for the data written to the memory device 104. In some cases, the RAID module 128 can be part of the ECC engine 124. A memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 can be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110.

[0019] The data storage device 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not required for the controller 102.

[0020] Figure 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuits 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells may be any suitable non-volatile memory cells, including two-dimensional and / or three-dimensional ReRAM, MRAM, PCM, NAND flash memory cells and / or NOR flash memory cells. The non-volatile memory die 104 further includes a data cache 156 that caches data and address decoders 148, 150. In this example, the peripheral circuits 141 include a state machine 152 that provides status information to the controller 102. The peripheral circuits 141 may also comprise one or more components configured to perform certain functions, individually or in combination, including but not limited to the functions described herein and illustrated in the flowcharts. For example, as shown in Figure 2B, the memory die 104 may comprise one or more processors 168 configured individually or in combination to execute computer-readable program code stored in one or more non-temporary memories 169, stored in a memory array 142, or stored outside the memory die 104. As another example, one or more components may include, but are not limited to, circuitry such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0021] In addition to, or instead of, one or more processors 138 (or, more generally, components) within controller 102 and one or more processors 168 (or, more generally, components) within memory die 104, data storage device 100 can include another set of one or more processors (or, more generally, components). In general, one or more processors (or, more generally, components) within data storage device 100, regardless of where they are located and regardless of how many there are, can be configured to perform various functions, including but not limited to the functions described herein and illustrated in the flowcharts, individually or in combination. For example, one or more processors (or components) can be located within controller 102, memory device 104, and / or other locations within data storage device 100. Also, different functions can be performed using different processors (or components), or combinations of processors (or components). Further, the means for performing functions can be implemented using a controller that includes one or more components (e.g., the processors or other components described above).

[0022] Returning again to FIG. 2A, flash control layer 132 (referred to herein as flash translation layer (FTL)) processes flash errors and interfaces with the host. In particular, the FTL, which can be an algorithm within the firmware, takes care of the internal memory management and converts writes from the host into writes to memory 104. The FTL can be needed because memory 104 can have limited endurance, can only be written to a plurality of pages, and / or can only be written until it is erased as a block. The FTL understands these potential limitations of memory 104 that may not be visible to the host. Thus, the FTL attempts to convert writes from the host into writes to memory 104.

[0023] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses ("logical block addresses, LBAs") from the host to physical addresses in memory 104. The FTL may include, but is not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear on some blocks, which would lead to a greater likelihood of failure).

[0024] Referring again to the drawings, Figure 3 is a block diagram of a host 300 and a data storage device 100 according to one embodiment. The host 300 can take any preferred form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 in this embodiment (here, a computing device) comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform operations described herein as being executed by the host 300. Thus, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0025] As mentioned above, multilevel cells (MLCs) can be used to store two or more bits per memory cell in memory 104. During operation, after determining the sequence of bits to be stored in a particular memory cell, the memory cell is programmed to a state by setting a threshold voltage corresponding to the sequence of bits. To read a memory cell, the memory cell is sensed and its threshold voltage is compared to one or more read voltages. However, the sensed threshold voltage may occasionally fluctuate from the written threshold voltage due to one or more factors such as data retention problems and program disturb conditions. Therefore, the default read threshold used to read from memory (e.g., flash) in a new device may not be suitable for devices that maintain such conditions.

[0026] There are several methods that can be used to help recalibrate the readout threshold. For example, valley search (VS) is an algorithm that can be used to optimize the readout threshold by finding the minimum value on the cell voltage distribution (CVD) histogram between any two adjacent states. It is typically implemented inside the NAND die, but a controller-based version of valley search can be used. Bit Error Rate (BER) Estimation Scan (BES) is another method for calibrating and optimizing the readout threshold. BES relies on optimizing the readout threshold so that a syndrome weight (SW), which is a substitute for the bit error rate, is minimized. Optimizing the syndrome weight / bit error rate has advantages over optimizing the minimum value on the CVD histogram because it directly reduces the objective function, although the minimum value on the CVD histogram does not necessarily translate to the minimum bit error rate.

[0027] BES-based CVD ("BES-CVD") is a method for obtaining an optimal read level shift. During operation, firmware within controller 102 can perform five or seven NAND senses (in BES5 or BES7 respectively) and transfer data from one flash management unit (FMU) (e.g., 4K) to hardware (e.g., within controller 102) to calculate the optimal read level that provides the smallest syndrome weight or failure bit count. Thus, BES-CVD is a hardware-managed operation for generating an updated, optimized voltage read threshold. This operation is based on the actual syndrome weight (equivalent to BER) in a relatively low-resolution read operation. BES-CVD is relatively fast and simple to use. In one example, the BES5 comb center is at the default read plus offset, and the BES7 comb center is at the optimal read level from BES5.

[0028] As more word lines are introduced into memory dies such as three-dimensional NAND bit column stacked (BiCS) memory, the BES5 scan range may become insufficient. For example, even if the bit error rate (BER) of those pages is still relatively low, there may be pages that are not covered by the BES5 scan range and exhibit high shifts. Several approaches can be used to solve this problem. For example, the BES5 delta can be extended. However, as shown in Figure 4, extending the BES5 delta can worsen the BER / SW because this approach may result in lower precision and higher syndrome weights. Another approach is to adjust the initial BES5 offset. As shown in Figure 5, this approach can provide a short-term improvement, but coverage may still be limited by the BES5 delta. Yet another approach is to dynamically adjust the BES5 offset for pages exhibiting high BES shifts, even when the BER is low, which can help solve this problem.

[0029] In one example, device benchmark data shows an optimal shift of approximately -50 digital-to-analog conversion (DAC) (approximately 600mV) for a given data retention condition. In this case, the BES shift scan range is 400mV for BES5 and 300mV for BES7 (BES5 delta = 200mV, BES7 delta = 100mV). In this case, BES5 may select the best of the five worst levels if it cannot find the optimal read level. This could mean selecting a level with an insufficient shift. For example, when selecting the best-worst level, if BES5 considers right comb 1 to be the best level, even BES7 may not be able to scan and find the optimal read level which is at -50DAC from the reference read level. Thus, the data storage device will see failures where the BES shift is smaller and more negative as the data storage device data passes through it. Referring to Figure 6, the dashed line Vt dist represents DR Vt at Ea = 1.0eV for 495 hours at 95°C. The device data for this distribution shows an optimal BES shift of 50 DAC (-600 mV), which is outside the BES range. Therefore, the failure is observed at the system level.

[0030] To solve this problem, in one embodiment, a dynamic BES5 offset approach can be used. In this approach, the controller 102 of the data storage device 100 identifies pages in memory 104 that have a DAC shift below a certain threshold (e.g., TLC pages with a worse offset based on drive-level statistics) and applies a second BES5 offset. This can be done by monitoring syndrome weights versus BES5 shifts. For example, if the BES shift is very high, even if the BER / SW is not too high, the controller 102 can be contrived to use an additional BES5 offset. Figure 7 shows a plot of DAC shift versus BER observed during high-temperature data retention conditions. It can be seen that as the time interval increases, the DAC shift becomes increasingly negative and falls outside the BES range. Thus, the BES range for high-temperature data retention is limited. Figure 8 shows how the updated dynamic BES5 offset can provide more scan coverage and reduce BES7 triggers.

[0031] Figure 9 is a flowchart 900 of a dynamic BES offset method according to one embodiment. As shown in Figure 9, after BES5 is started (910), the controller 102 of the data storage device 100 determines whether the page being read is in a special offset pool (920). If so, the controller 102 proceeds to BES5 with the updated offset (930). Otherwise, the controller 102 proceeds to BES5 with the default offset (940). Next, the controller 102 determines whether the shift is greater than a predefined read level (RL) threshold (950). If so, the method terminates (960). Otherwise, the controller 102 updates the page information to place the page in the special offset pool (970), and then the method terminates (980).

[0032] In this method, for new data storage devices, the special offset pool list is empty because this pool contains a list of pages that use non-default BES5 offsets. This list can be based on word lines, strings, or page identifiers. In this method, if BES5 results in a BES shift greater than a predefined threshold, the page is added to the special offset pool. Whenever BES is triggered on a page, it is checked whether it is already part of the special offset pool. If so, the BES5 operation uses the non-default (updated) BES offset. There are several advantages associated with these embodiments. For example, these embodiments can reduce the BES7 trigger rate and provide more reliable read error handling. This can provide a better quality of service (QoS) with improved reliability.

[0033] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0034] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching memory elements such as antifuses and phase-change materials, and optionally steering elements such as diodes. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0035] Multiple memory elements can be configured so that they are connected in series, or so that each element is individually accessible. As a non-limiting example, a flash memory device with a NAND configuration (NAND memory) typically includes memory elements connected in series. A NAND memory array can be configured so that the array consists of multiple strings of memory, each string consisting of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0036] Semiconductor memory elements located within and / or on the substrate may be arranged in two or three dimensions, such as in a two-dimensional memory structure or a three-dimensional memory structure.

[0037] In a two-dimensional memory structure, semiconductor memory elements are arranged on a single plane or at the level of a single memory device. Typically, in a two-dimensional memory structure, memory elements are arranged on a plane (e.g., the xz plane) that extends substantially parallel to the main plane of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed or within it, or a carrier substrate to which memory elements are attached after they have been formed. In non-limiting examples, the substrate may include semiconductors such as silicon.

[0038] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0039] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0040] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction) where each column has multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in the xz plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0041] As a non-restrictive example, in a three-dimensional NAND memory array, memory elements may be joined together to form a NAND string within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be joined together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0042] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. In a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0043] In this case as well, the two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0044] Associated circuitry is typically required for the operation of memory elements and for communication with them. In a non-limiting example, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This associated circuitry may be on the same board as the memory elements and / or on a separate board. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same board as the memory elements.

[0045] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described herein, but encompasses all relevant memory structures within the spirit and scope of the invention as described herein and as understood by those skilled in the art.

[0046] The above detailed description is intended to be understood not as a definition of the present invention, but as an illustrative example of selected forms that the invention may take. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of the embodiments described herein may be used individually or in combination with others.

Claims

1. A data storage device, Memory and A system comprising one or more processors, wherein the one or more processors can be operated individually or in combination. A first bit error rate estimation scan (BES) is performed on the scan range in the memory, wherein the BES is performed using a first offset. Determine whether the pages within the scan range contain a DAC shift below a certain threshold. A data storage device configured to perform a second BES on the page, in response to determining that the page within the scan range contains a DAC shift below the criterion, the second BES being performed using a second offset.

2. The data storage device according to claim 1, wherein one or more processors are further configured to determine whether the pages within the scan range contain a DAC shift below a certain criterion by individually or in combination monitoring syndrome weight versus BES shift.

3. The data storage device according to claim 1, wherein one or more processors are further configured to determine whether the pages within the scan range contain a DAC shift below a criterion by determining individually or in combination whether the DAC shift is becoming increasingly negative and out of range.

4. The data storage device according to claim 1, wherein one or more processors are further configured to determine whether the pages within the scan range include a DAC shift below a criterion by determining, individually or in combination, whether the pages include an offset based on data storage device-level statistics.

5. The data storage device according to claim 1, wherein the BES includes a BES5 that performs five memory sensing operations.

6. The data storage device according to claim 5, wherein performing the second BES using the second offset avoids performing the BES7 which performs seven memory senses.

7. The data storage device according to claim 1, wherein the pages within the scan range include a DAC shift below the standard depending on the high-temperature data retention conditions.

8. The data storage device according to claim 1, wherein the memory comprises a multilevel memory cell.

9. The data storage device according to claim 1, wherein the memory comprises a three-dimensional memory.

10. The data storage device according to claim 1, wherein the memory comprises a two-dimensional memory.

11. A method for a data storage device equipped with memory, The process involves initiating a scan to estimate the bit error rate of the memory pages, To determine whether the aforementioned page is associated with the offset pool, A method comprising determining that the page is associated with the offset pool, and then using the updated offset to proceed with the bit error rate estimation scan of the page.

12. The method according to claim 11, further comprising, in response to determining that the page is not associated with the offset pool, proceeding with the bit error rate estimation scan of the page using a default offset.

13. The bit error rate estimation scan on the aforementioned page determines whether the read voltage level shift is greater than the threshold, The method of claim 11, further comprising associating the page with the offset pool in response to determining that the bit error rate estimation scan of the page indicates that the read voltage level shift is greater than the threshold.

14. The method according to claim 13, wherein the bit error rate estimation scan on the aforementioned page indicates that the read voltage level shift is greater than the threshold depending on the high-temperature data retention conditions.

15. The method according to claim 11, wherein the pages in the offset pool are identified by word line identifiers.

16. The method according to claim 11, wherein the pages in the offset pool are identified by string identifiers.

17. The method according to claim 11, wherein the pages in the offset pool are identified by a page identifier.

18. The method according to claim 11, wherein the memory comprises a three-dimensional memory.

19. The method according to claim 11, wherein the memory comprises a two-dimensional memory.

20. It is a memory system, Memory and A first bit error rate estimation scan (BES) is performed on the scan range in the memory, wherein the BES is performed using a first offset. Identify whether the pages within the scan range contain a DAC shift below a certain threshold. A storage system comprising, with respect to the aforementioned page, a second BES, the second BES being performed using a second offset, and means for performing the second BES.

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