Information processing system and information processing method

Abstract

The goal is to provide a unified view of memory access status by both the CPU and the FPGA during the processing of application functions. [Solution] The CPU repeatedly collects first memory access information related to memory accesses performed on the first memory when processing the second subfunction at predetermined intervals, and the FPGA repeatedly collects second memory access information related to memory accesses performed on the second memory when processing the first subfunction at predetermined intervals, and combines the first memory access information and the second memory access information acquired during the same time period for each function.

Description

Technical Field

[0001] The present invention relates to an information processing system and an information processing method.

Background Art

[0002] For example, in an IA (Intel (registered trademark) Architecture) processor or the like, a performance counter for acquiring processing event information of a CPU (Central Processing Unit) or memory inside the processor is implemented. The processing event information is, for example, the number of issued instructions. It is known to perform performance analysis of an application operating on a CPU using such processing event information.

[0003] For example, by setting an event to be monitored for the performance counter, acquiring and collecting processing event information in real time, and performing a performance trace that associates the execution contents of the Kernel and the application, performance analysis of the application is performed.

[0004] In recent years, devices equipped with processors such as FPGAs (Field Programmable Gate Arrays) have been implemented on accelerator cards such as PCI (Peripheral Component Interconnect) cards. For example, the processing speed is increased by causing a program executed by a CPU to be executed by another processor (for example, Patent Document 1).

[0005] Also, for example, a configuration in which an application operating on a CPU causes processing to be executed on an FPGA in units of functions such as C language, and operates in close conjunction with the CPU has been increasing.

[0006] In heterogeneous computing configurations with CPUs and FPGAs, applications where devices operate in coordination do not have performance counters on the device side. Therefore, it is common practice to collect performance information separately from the CPU and FPGA using different methods and mechanisms, and then perform performance analysis. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2016-212667 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] However, in a heterogeneous computing configuration that implements an accelerator card equipped with an FPGA, computing resources and memory resources are distributed between the CPU and the FPGA. Therefore, performance counters implemented on the primary CPU cannot collect information about the accelerator card's behavior.

[0009] This is because the CPU, which is the primary execution device for the application, cannot manage FPGA operation information in a way that links it to the same time point as the CPU.

[0010] Specifically, the CPU's performance counters are counters that do not have a time concept, and similarly, the FPGA does not have time information synchronized with the primary CPU. Therefore, when the CPU aggregates the information, it is not possible to link the CPU's performance counters with the FPGA's information.

[0011] Furthermore, the CPU, which issues execution instructions for the application, cannot manage the memory information accessed by the FPGA, which executes the functions, and link it to the CPU's memory access.

[0012] Consequently, in conventional performance analysis methods for heterogeneous computing configurations, for example, when trying to calculate the memory hit rate to DRAM (Dynamic Random Access Memory) in performance analysis, it is possible to determine the memory hit rate accessed from the CPU, but it is not possible to calculate the memory hit rate for the entire shared memory, including access from the FPGA. Therefore, the analysis becomes biased towards CPU-side performance information.

[0013] In one aspect, the present invention aims to provide a unified view of the memory access status by the CPU and the memory access status by the FPGA when processing application functions. [Means for solving the problem]

[0014] Therefore, this information processing system includes a CPU (Central Processing Unit) that executes an application having a function that includes a first subfunction and a second subfunction, a first memory accessible by the CPU, an FPGA (Field Programmable Gate Array) that processes the first subfunction according to execution instructions from the CPU, and a second memory accessible by the FPGA, wherein the CPU repeatedly collects first memory access information relating to memory accesses performed on the first memory when processing the second subfunction at predetermined intervals, the FPGA repeatedly collects second memory access information relating to memory accesses performed on the second memory when processing the first subfunction at predetermined intervals, and performs a process to combine the first memory access information and the second memory access information acquired in the same time period with respect to the function. [Effects of the Invention]

[0015] According to one embodiment, when processing application functions, the status of memory access by the CPU and the status of memory access by the FPGA can be grasped in a unified manner.

Brief Description of the Drawings

[0016] [Figure 1] It is a diagram schematically showing the hardware configuration of an information processing system according to an embodiment. [Figure 2] It is a diagram illustrating the functional configuration of an information processing system according to an embodiment. [Figure 3] It is a diagram illustrating the information stored in the storage unit of an information processing system according to an embodiment. [Figure 4] It is a diagram illustrating the information stored in the DDR memory of an information processing system according to an embodiment. [Figure 5] It is a diagram for explaining the processing of an application executed in an information processing system according to an embodiment. [Figure 6] It is a diagram for explaining the relationship between an in-application function and memory access in an information processing system according to an embodiment. [Figure 7] It is a diagram illustrating the information aggregated in the FPGA in an information processing system according to an embodiment. [Figure 8] It is a diagram illustrating the performance counter information in an information processing system according to an embodiment. [Figure 9] It is a diagram illustrating the CPU memory access - program counter aggregation table of an information processing system according to an embodiment. [Figure 10] It is a diagram illustrating the CPU memory hit - program counter aggregation table of an information processing system according to an embodiment. [Figure 11] It is a diagram illustrating the CPU execution function conversion table of an information processing system according to an embodiment. [Figure 12] It is a diagram illustrating the CPU per - function memory access aggregation table of an information processing system according to an embodiment. [Figure 13] It is a diagram illustrating the CPU per - function memory hit aggregation table of an information processing system according to an embodiment. [Figure 14]It is a diagram illustrating the memory access number DB of an information processing system according to an embodiment. [Figure 15] It is a diagram for explaining the generation process of the memory access number DB in an information processing system according to an embodiment. [Figure 16] It is a diagram for explaining the merging method of the memory access number in the FPGA to the memory access number DB in an information processing system according to an embodiment. [Figure 17] It is a diagram illustrating the memory hit number DB of an information processing system according to an embodiment. [Figure 18] It is a diagram for explaining the generation process of the memory hit number DB in an information processing system according to an embodiment. [Figure 19] It is a diagram for explaining the merging method of the memory hit number in the FPGA to the memory hit number DB in an information processing system according to an embodiment. [Figure 20] It is a flowchart for explaining the processing of the event notification unit of an information processing system according to an embodiment. [Figure 21] It is a flowchart for explaining the processing of the statistics unit of an information processing system according to an embodiment. [Figure 22] It is a flowchart for explaining the processing of the reception unit of an information processing system according to an embodiment. [Figure 23] It is a flowchart for explaining the processing of the counter unit of the FPGA of an information processing system according to an embodiment. [Figure 24] It is a flowchart for explaining the processing of the sampling unit of the FPGA of an information processing system according to an embodiment. [Figure 25] It is a flowchart for explaining the processing of the notification unit of the FPGA of an information processing system according to an embodiment. [Figure 26] It is a diagram for explaining a modification example of the merging method of the memory access number in the FPGA to the memory access number in an information processing system according to an embodiment.

Mode for Carrying Out the Invention

[0017] Embodiments of this information processing system and information processing method will be described below with reference to the drawings. However, the embodiments shown below are merely illustrative, and there is no intention to exclude various modifications or applications of technologies not explicitly shown in the embodiments. In other words, these embodiments can be implemented in various ways (such as by combining embodiments and their respective modifications) without departing from their spirit. Furthermore, each figure is not intended to represent only the components shown in the figure, but may include other functions, etc.

[0018] (A) Configuration Figure 1 is a schematic diagram showing the hardware configuration of an information processing system 1 according to one embodiment, and Figure 2 is a diagram illustrating the functional configuration of an information processing system 1 according to one embodiment.

[0019] (A-1) Example hardware configuration The information processing system 1 illustrated in Figure 1 has one or more (one in the example shown in Figure 1) CPUs 2, DDR (Double Data Rate) memory 3, and an accelerator card 4. The accelerator card 4 also has an FPGA 5 and DDR memory 6.

[0020] CPU2 is an example of an arithmetic processing unit that performs various control and calculations, and is a control unit that executes various processes. CPU2 is connected to DDR memory 3 and accelerator card 4 so as to be able to communicate with each other, for example, via a bus (not shown). The bus connecting CPU2 and accelerator card 4 may be, for example, a PCI bus. Note that CPU2 may be a multiprocessor including multiple processors, a multicore processor having multiple processor cores, or a configuration having multiple multicore processors.

[0021] For example, CPU2 implements the functions of the management unit 13 and the event notification unit 16 by loading the program (monitoring program) stored in the memory unit 7 into the DDR memory 3 and executing it. Alternatively, multiple CPUs, including CPU2, may be provided, and a CPU other than CPU2 may execute the monitoring program to implement the functions of the management unit 13 and the event notification unit 16.

[0022] DDR memory 3 is an example of hardware that stores various data and program information. Alternatively, instead of DDR memory 3, the system may be equipped with one or both of the following: volatile memory such as DRAM (Dynamic Random Access Memory) and non-volatile memory such as PM (Persistent Memory).

[0023] Furthermore, the information processing system 1 has a storage unit 7. The storage unit 7 is an example of hardware that stores various data, programs, and other information. Examples of storage units 7 include magnetic disk devices such as HDDs (Hard Disk Drives), semiconductor drive devices such as SSDs (Solid State Drives), and various storage devices such as non-volatile memory. Examples of non-volatile memory include flash memory, SCM (Storage Class Memory), and ROM (Read Only Memory).

[0024] The storage unit 7 may store programs that implement all or part of the various functions of the information processing system 1. For example, the storage unit 7 may store a monitoring program and an FPGA-side counter program. The FPGA-side counter program may be stored in the storage unit 7 as part of the monitoring program.

[0025] The CPU 2 implements the monitoring function described later by loading the monitoring program stored in the memory unit 7 into the DDR memory 3 and executing it.

[0026] Figure 3 is a diagram illustrating information stored in the storage unit 7 of an information processing system 1 according to one embodiment. In the example shown in Figure 3, the storage unit 7 stores information that constitutes performance counter information 20, CPU memory access-program counter summary table 21, CPU memory hit-program counter summary table 22, CPU execution function conversion table 23, CPU function-specific memory access summary table 24, CPU function-specific memory hit summary table 25, memory access count DB 26, memory hit count DB 27, counter summary table 28, FPGA execution function conversion table 29, FPGA address-specific access count summary table 33, and FPGA address-specific hit count summary table 34. Note that the information that constitutes these tables may be stored in the DDR memory 3 described above.

[0027] The accelerator card 4 has an FPGA 5 and DDR memory 6. The FPGA 5 is a device that allows for the electrical modification of the circuit design of a digital circuit. The FPGA 5 is an LSI (Large Scale Integration circuit) with a large number of logic gates. The FPGA 5 functions as a predetermined logic circuit by writing configuration data describing the logic relationships and connection relationships between logic gates to the configuration RAM (not shown) provided in the FPGA 5.

[0028] FPGA5 loads the program file (bitstream data) sent from CPU2 and loads it into the static RAM (SRAM) within FPGA5 (not shown). Each bit of the bitstream data loaded into SRAM becomes the source of information for the user circuit implemented on FPGA5, and the predetermined circuit is realized by customizing the resources equipped on FPGA5.

[0029] As shown in Figure 2, FPGA 5 implements the functions of a counter unit 17, a sampling unit 18, and a notification unit 19.

[0030] DDR memory 6 is an example of hardware that stores various data and program information. Alternatively, instead of DDR memory 6, the system may be equipped with one or both of the following: volatile memory such as DRAM, and non-volatile memory such as PM.

[0031] DDR memory 3 and DDR memory 6 are managed as shared memory and treated as a common memory space.

[0032] Figure 4 is a diagram illustrating the information stored in the DDR memory 6 of an information processing system 1 according to one embodiment. In the example shown in Figure 4, the DDR memory 6 stores the FPGA memory access-address summary table 31 and the FPGA memory hit-address summary table 32.

[0033] (A-2) Example of Functional Configuration In the information processing system 1 according to this embodiment, an application running on the CPU 2 causes the FPGA 5 to execute processing in function units such as C language, thereby realizing heterogeneous computing in which the CPU 2 and FPGA 5 operate in a tightly coupled manner.

[0034] Therefore, in the information processing system 1, some of the multiple functions included in the application executed on CPU 2 are executed on CPU 2, while other parts are executed on FPGA 5.

[0035] Figure 5 is a diagram illustrating the processing of an application executed in an information processing system 1 according to one embodiment.

[0036] In the example shown in Figure 5, the application executed on CPU2 has function A and function B. Function A includes subfunctions A-1 and A-2, and function B includes subfunction B-1. In function A, subfunction A-2 is an example of the first subfunction, and subfunction A-1 is an example of the second subfunction.

[0037] This indicates that functions A-1, A-2, and B-1 are executed in the application, with function A-1 being executed by CPU2, and functions A-2 and B-1 being loaded and executed by FPGA5.

[0038] Furthermore, a monitoring program is executed on CPU2, and the monitoring function realized by the execution of this monitoring program receives aggregated information regarding memory access notified from FPGA5 and centrally manages it together with the aggregated information regarding memory access on CPU2.

[0039] The aggregated information regarding memory access may include, for example, the number of memory accesses, the number of memory hits, and the hit rate. The number of memory accesses is the number of read instructions issued when searching for table information in DDR memory. The number of memory hits is the number of times an entry referenced during memory access exists in the table information and that entry was successfully read. If the entry does not exist in the table information, it is considered a miss. The determination of whether an entry is a hit can be implemented using known circuits and functions, and their explanation is omitted here.

[0040] The initial table information on DDR memory 6, which FPGA 5 accesses, is stored (updated) on DDR memory 6 by CPU 2 when the application starts. If a mis-hit occurs in DDR memory 6, the table information is retrieved from DDR memory 3 on CPU 2.

[0041] The hit rate represents the percentage of memory accesses that resulted in a memory hit. The hit rate is calculated by dividing the number of memory hits by the total number of memory accesses.

[0042] Figure 6 is a diagram illustrating the relationship between application functions and memory access in an information processing system 1 according to one embodiment.

[0043] Figure 6 shows the relationship between the execution entity and memory access destination of each function within an application executed primarily by CPU2.

[0044] In the example shown in Figure 6, the main application runs on CPU2, and function A is called within this application. Function A also contains subfunctions A-1 and A-2. Function A, which includes these subfunctions A-1 and A-2, can be referred to as the main function.

[0045] Function A-1 is executed by CPU2, which accesses DDR memory 3 during the execution of function A-1. DDR memory 3 is an example of the first memory. Meanwhile, function A-2 is loaded into FPGA5, which accesses DDR memory 6 during the execution of function A-2. DDR memory 6 is an example of the second memory.

[0046] In this information processing system 1, the monitoring function realizes that the number of counts recorded by the performance counter 12 when the CPU 2 accesses the DDR memory 3 in conjunction with the execution of function A-1, and the number of counts recorded by the counter unit 17 when the FPGA 5 accesses the DDR memory 6 in conjunction with the execution of function A-2, are aggregated as the total for function A at the same time.

[0047] The counter unit 17 receives the sampling period and a monitoring start instruction from the event notification unit 16 of the CPU 2 (monitoring program). Based on the notified sampling period and monitoring start instruction, the counter unit 17 generates sampling triggers using a period generation circuit (not shown) formed in the FPGA 5. For example, if the sampling period is 100 μS (microseconds), the counter unit 17 generates a sampling trigger every 100 μS elapsed since the monitoring start instruction.

[0048] The program for forming the periodic generation circuit on FPGA5 may be included in the FPGA counter program.

[0049] The counter unit 17 monitors and aggregates memory access to the DDR memory 6 by the FPGA 5 for each sampling trigger. Memory access to the DDR memory 6 by the FPGA 5 can be called FPGA memory access. Memory access may be based on read instructions.

[0050] The counter unit 17 counts the number of memory accesses and memory hits for FPGA memory access. The number of memory accesses and memory hits can be referred to as memory access information.

[0051] The counter unit 17 collects memory access information about FPGA memory access for each generated sampling trigger.

[0052] The counter unit 17, triggered by a monitoring start instruction sent from the CPU 2, counts the number of memory accesses and memory hits for each read instruction issued from the FPGA 5 to the DDR memory 6 after a sampling period has elapsed (each sampling trigger).

[0053] The counter unit 17 may obtain the number of memory accesses by counting the read instructions issued on the bus between FPGA 5 and DDR memory 6. In addition, when FPGA 5 accesses DDR memory 6, the counter unit 17 counts the number of times the entry to be referenced exists in the table information of DDR memory 6 and that the entry was successfully read as the number of memory accesses.

[0054] Figure 7 illustrates the information aggregated by FPGA5 in an information processing system 1 according to one embodiment.

[0055] In Figure 7, code A illustrates memory access information aggregated by the counter unit 17, code B illustrates the FPGA memory access-address aggregation table 31, and code C illustrates the FPGA memory hit-address aggregation table 32.

[0056] The information aggregated in FPGA5, as shown by symbols A to C in Figure 7, may be stored, for example, in registers of FPGA5 (not shown).

[0057] In Figure 7, the memory access information indicated by symbol A shows the number of memory accesses and memory hits for each sampling time interval.

[0058] The sampling elapsed time represents the time elapsed since CPU2 started executing the application for each of the multiple samples that are repeatedly performed in the sampling period.

[0059] In Figure 7, etc., N+100, N+200, N+300, etc. are shown as sampling elapsed times (unit: [μS (microseconds)], the same as in the following explanation).

[0060] The sampling period is a fixed length of time (e.g., 100 μS), and one sample is taken at each sampling period, during which memory access information (number of memory accesses, number of memory hits) is aggregated. The sampling period is the standard or unit of time used to monitor memory access.

[0061] In the example shown in Figure 7, the sampling period is 100 μS, indicating that multiple samples are repeatedly taken at this sampling period.

[0062] N is the elapsed time from when CPU2 executes the application until it notifies FPGA5 of the instruction to start monitoring. Hereafter, N may be referred to as elapsed time N. The sampling elapsed time can be said to be corrected using elapsed time N to represent the elapsed time from when CPU2 started the application. N is notified by CPU2, and for example, the counter unit 17 may calculate the sampling elapsed time.

[0063] The number of memory accesses performed during the sampling time can be referred to as the "number of memory accesses per sampling time unit" or the "number of memory accesses per sampling time unit." Similarly, the number of memory hits performed during the sampling time can be referred to as the "number of memory hits per sampling time unit" or the "number of memory hits per sampling time unit."

[0064] The memory access information in FPGA5, aggregated by the counter unit 17 as shown by symbol A in Figure 7, can be referred to as the FPGA5 performance counter.

[0065] Similar to the counter unit 17, the sampling unit 18 is notified of the sampling period and a monitoring start instruction from the CPU 2 (monitoring program). Based on the notified sampling period and monitoring start instruction, the sampling unit 18 generates sampling triggers using a period generation circuit formed in the FPGA 5. For example, if the sampling period is 100 μS, the sampling unit 18 generates a sampling trigger every 100 μS elapsed since the monitoring start instruction.

[0066] The sampling unit 18 performs sampling at each sampling period and obtains the address information of the access destination for memory access to the DDR memory 6 by the FPGA 5.

[0067] The sampling unit 18 collects address information of the access destination in FPGA memory access (access based on read instructions) at each sampling period.

[0068] The sampling unit 18 starts sampling when it receives a monitoring start instruction from the CPU 2, and performs sampling each time a sampling cycle has elapsed (each sampling trigger) to collect the number of memory accesses and memory hits for FPGA memory access, as well as address information of the access destination in FPGA memory access (access based on read instructions).

[0069] The sampling unit 18 updates (creates) the FPGA memory access-address summary table 31, as shown by symbol B in Figure 7, using the collected access destination address information and the number of memory accesses obtained from the performance counter on the FPGA 5 side.

[0070] The FPGA memory access-address summary table 31, indicated by symbol B in Figure 7, associates the number of memory accesses with the target address for each individual sample (sampling elapsed time).

[0071] Furthermore, the sampling unit 18 uses the collected access destination address information and the number of memory hits obtained from the performance counter on the FPGA 5 side to update (create) the FPGA memory hit-address summary table 32, as shown by symbol C in Figure 7.

[0072] The FPGA memory hit-address summary table 32, indicated by the symbol C in Figure 7, associates the number of memory hits with the accessed address in relation to the sampling (sampling elapsed time).

[0073] In the example shown in Figure 6, the sampling unit 18 repeatedly collects (samples) second memory access information (number of memory accesses, number of memory hits) related to memory access performed on the DDR memory 6 (second memory) when processing subfunction A-2 (first subfunction) in FPGA 5, at a sampling period (predetermined period).

[0074] The notification unit 19 notifies (sends to) the CPU 2 the information that constitutes the FPGA memory access-address summary table 31 and the FPGA memory hit-address summary table 32, which have been generated (updated) by the sampling unit 18.

[0075] The notification unit 19 notifies the CPU 2 of the information constituting the FPGA memory access-address summary table 31 and the information constituting the FPGA memory hit-address summary table 32 at each notification interval. The notification interval may be pre-set in the FPGA 5, or it may be notified to the FPGA 5 by the CPU 2. The notification period may be, for example, 300 μS.

[0076] In FPGA5, when the notification unit 19 receives a monitoring start instruction from CPU2, it starts notifying information that constitutes the FPGA memory access-address summary table 31 and information that constitutes the FPGA memory hit-address summary table 32.

[0077] As shown in Figure 2, CPU2 has functions as a program counter 11 and a performance counter 12, as well as a management unit 13 and an event notification unit 16.

[0078] The program counter 11 is a type of register (memory device) installed in, for example, an IA (Intel® Architecture) processor, and it has the function of holding the address on the memory (DDR memory 3) where the next instruction to be executed by the application is stored. The program counter 11 may be a function installed as hardware in, for example, the CPU 2, and the value of the program counter 11 can be said to indicate the number of lines that the CPU 2 is currently executing. The value of the program counter 11 can be called program counter information. Note that the function of the program counter 11 is already known, so its explanation will be omitted.

[0079] The performance counter 12 is a type of register (memory device) installed in, for example, an IA processor, and implements a counter function to acquire processing event information (number of instructions issued) from the CPU 2 and memory (DDR memory 3) inside the processor.

[0080] The performance counter 12 monitors and aggregates memory accesses to DDR memory 3 by CPU 2 for each sampling trigger. Memory accesses to DDR memory 3 by CPU 2 can be called CPU memory accesses. Memory accesses may be based on read instructions.

[0081] The performance counter 12 counts the number of memory accesses and memory hits at each sampling period, triggered by the setting of the event type and the instruction to start monitoring.

[0082] Performance counter 12 counts memory access information (number of memory accesses and number of memory hits) for CPU memory access. The function of performance counter 12 is already known, so its explanation is omitted.

[0083] In the example shown in Figure 6, the performance counter 12 repeatedly collects first memory access information (number of memory accesses, number of memory hits) related to memory accesses performed on the DDR memory 3 when processing function A-1 (second subfunction) at a sampling period (predetermined period).

[0084] The event notification unit 16, upon application startup, notifies the statistics unit 14 of the management unit 13 of a command to start monitoring the sampling period and memory access information (number of memory accesses and number of memory hits). The event notification unit 16 also stores (retains) a timestamp of the time it notified the statistics unit 14 of the command to start monitoring in a predetermined storage area such as the DDR memory 3 or the storage unit 7.

[0085] Furthermore, when the application starts up, the event notification unit 16 notifies the FPGA 5 of an instruction to start monitoring memory access information (number of memory accesses and number of memory hits), and also notifies it of the sampling period and notification interval. The event notification unit 16 also stores (retains) a timestamp of the time when it notified the FPGA 5 of the instruction to start monitoring in a predetermined storage area such as the DDR memory 3 or the storage unit 7.

[0086] Furthermore, the event notification unit 16 calculates the elapsed time N from the time the CPU 2 starts executing the application until it notifies the FPGA 5 of a monitoring start command. The event notification unit 16 stores (retains) the calculated elapsed time N in a predetermined storage area such as the storage unit 7 or the DDR memory 3.

[0087] The management unit 13 manages the monitoring of memory access in the information processing system 1 and has the functions of a receiving unit 15 and a statistics unit 14.

[0088] The receiving unit 15 receives information constituting the FPGA memory access-address summary table 31 and information constituting the FPGA memory hit-address summary table 32, respectively, which are notified from the notification unit 19 of the FPGA 5.

[0089] The receiving unit 15 stores the received information constituting the FPGA memory access-address summary table 31 and the information constituting the FPGA memory hit-address summary table 32 in predetermined storage areas such as the DDR memory 3 and the storage unit 7.

[0090] Furthermore, the receiving unit 15 notifies the statistics unit 14 when it receives information from FPGA 5 (notification unit 19) that constitutes the FPGA memory access-address summary table 31, or when it receives information that constitutes the FPGA memory hit-address summary table 32.

[0091] The statistics unit 14 updates (generates) the performance counter information 20 using the memory access information (number of memory accesses and number of memory hits) counted by the performance counter 12.

[0092] Figure 8 is a diagram illustrating performance counter information 20 in an information processing system 1 according to one embodiment.

[0093] The performance counter information 20 shown in Figure 8 indicates the number of memory accesses and memory hits for each sampling time interval.

[0094] Furthermore, the statistics unit 14 constantly polls the count value of the performance counter 12, and when the memory access count increases, that is, when the number of memory accesses increases, it obtains the program counter information at that time.

[0095] The statistics unit 14 updates (generates) the performance counter information 20 using the memory access information (number of memory accesses and number of memory hits) counted by the performance counter 12.

[0096] Furthermore, the statistics unit 14 updates (creates) the CPU memory access-program counter summary table 21 using the number of memory accesses and program counter information obtained from the performance counter information 20.

[0097] Figure 9 is a diagram illustrating the CPU memory access-program counter summary table 21 of an information processing system 1 according to one embodiment.

[0098] The CPU memory access-program counter summary table 21 illustrated in Figure 9 associates the number of memory accesses and the program counter with each of the multiple sampling elapsed times included in the sampling elapsed time.

[0099] Furthermore, the statistics unit 14 updates (creates) the CPU memory hit-program counter summary table 22 using the memory hit count and program counter information obtained from the performance counter information 20.

[0100] Figure 10 illustrates a CPU memory hit-program counter summary table 22 of an information processing system 1 according to one embodiment.

[0101] The CPU memory hit-program counter summary table 22 illustrated in Figure 10 associates the number of memory hits and the program counter with multiple sampling elapsed times included in the sampling elapsed time.

[0102] Now, when an application is executed, the memory regions of DDR memory 3 and 6 that a function accesses are predetermined and fixed. Therefore, based on the value of the program counter information, it is possible to identify the function that uses the memory region indicated by that value.

[0103] Figure 11 illustrates a CPU execution function conversion table 23 of an information processing system 1 according to one embodiment.

[0104] In the CPU execution function conversion table 23 illustrated in Figure 11, the program counter value is associated with the name of the smallest unit of function that CPU2 executes. In this embodiment, since CPU2 executes function processing in units of subfunctions, the function name may be the name of the subfunction (function A-1, function B-1, etc.).

[0105] The information that constitutes the CPU execution function conversion table 23 may be set in advance; for example, this CPU execution function conversion table 23 may be generated when the application is loaded.

[0106] The statistics unit 14 can identify the function name (sub-function name) that uses the memory area indicated by the value of the program counter information by referring to the CPU execution function conversion table 23 based on the program counter information.

[0107] The statistics unit 14 obtains program counter information from the CPU memory access-program counter summary table 21 at each sampling period, and retrieves the function name corresponding to the program counter information by searching the CPU execution function conversion table 23 based on the obtained program counter information.

[0108] The statistics unit 14 then generates a CPU function-specific memory access summary table 24 by distributing and re-aggregating the number of memory accesses for each function (subfunction) executed by the CPU 2 in units of sampling period.

[0109] Figure 12 illustrates a memory access summary table 24 for each CPU function in an information processing system 1 according to one embodiment.

[0110] The CPU function-specific memory access summary table 24 illustrated in Figure 12 associates the number of memory accesses per sampling elapsed time with the function name. The CPU function-specific memory access summary table 24 shows the number of memory accesses per sampling elapsed time for each function (sub-function) executed by CPU2.

[0111] Furthermore, the statistics unit 14 redistributes and aggregates the number of memory hits for each function (subfunction) executed by the CPU 2 in units of sampling period, thereby obtaining the number of memory hits for each subfunction per sampling elapsed time. The statistics unit 14 updates (generates) the CPU function memory hit aggregation table 25 using the obtained number of memory hits per subfunction per sampling elapsed time.

[0112] Figure 13 illustrates a memory hit aggregation table 25 for each CPU function in an information processing system 1 according to one embodiment.

[0113] The CPU function memory hit summary table 25 illustrated in Figure 13 associates the number of memory hits for each sampling elapsed time with the function name, and shows the number of memory hits for multiple sampling elapsed times for each function (e.g., subfunction) executed by CPU2.

[0114] The statistics unit 14 manages the number of memory accesses for each function (main function) using the memory access count DB 26.

[0115] Figure 14 is a diagram illustrating the number of memory accesses DB26 in an information processing system 1 according to one embodiment.

[0116] The memory access count DB26 shown in Figure 14 associates the number of memory accesses with each function name for each sampling elapsed time.

[0117] The statistics unit 14 calculates the number of memory accesses for each main function by summing the number of memory accesses for subfunctions included in the same main function, based on the CPU function memory access summary table 24, which registers the number of memory accesses for each smallest unit function (subfunction) executed by the CPU 2, and registers this information in the memory access count DB 26.

[0118] The DB26 memory access count essentially manages the number of memory accesses for each main function, based on the elapsed sampling time.

[0119] Figure 15 is a diagram illustrating the process of generating the memory access count DB26 in an information processing system 1 according to one embodiment.

[0120] In the example below, the prerequisites are that the sampling period is 100 μS, the notification interval is 300 μS, and the elapsed time N = 200 μS. Furthermore, function A is assumed to include access to FPGA5's 0x1000.

[0121] The statistics unit 14 updates the CPU memory access-program counter summary table 21 using the number of memory accesses and program counter information obtained from the performance counter information 20 (see symbol P1 in Figure 15).

[0122] The statistics unit 14 stores the number of memory accesses and program counters in association with each sampling time in the CPU memory access-program counter summary table 21. The statistics unit 14 may generate the CPU memory access-program counter summary table 21 by combining the number of memory accesses for each sampling time obtained from the performance counter information 20 with the program counter value corresponding to the memory access that occurred at each sampling time.

[0123] Next, the statistics unit 14 obtains the function name corresponding to the program counter value by referring to the CPU execution function conversion table 23 based on the program counter value in the CPU memory access-program counter summary table 21 (see symbol P2 in Figure 15).

[0124] The statistics unit 14 updates (generates) the CPU function-specific memory access summary table 24 by aggregating the number of memory accesses per sampling period for each function, based on the number of memory accesses per sampling elapsed time in the CPU memory access-program counter summary table 21 and the function name corresponding to the program counter (see symbol P3 in Figure 15).

[0125] The statistics unit 14 calculates the number of memory accesses for each main function by summing the number of memory accesses of sub-functions included in the same main function in units of sampling period, based on the CPU function memory access summary table 24, and updates (generates) the memory access count DB 26 (see symbol P4 in Figure 15).

[0126] The statistics unit 14 manages the memory access count DB 26 by merging the memory access counts from CPU 2 and FPGA 5.

[0127] Figure 16 is a diagram illustrating a method for merging the number of memory accesses in FPGA 5 with the number of memory accesses in DB 26 in an information processing system 1 according to one embodiment.

[0128] Figure 16 shows an example in which the statistics unit 14 updates the memory access count DB 26, as illustrated in Figure 14, based on the information in the FPGA memory access-address summary table 31, as illustrated by symbol B in Figure 7.

[0129] As described above, in the FPGA memory access-address summary table 31, multiple sampling elapsed times are corrected by adding the elapsed time N to each so that they represent the elapsed time since the application was started in CPU2. In other words, the sampling elapsed time in FPGA memory access-address summary table 31 is corrected so that it is the sampling elapsed time based on CPU2. In this embodiment, an example with elapsed time N = 200 μS is shown.

[0130] The statistics unit 14 may perform this process each time information constituting the FPGA memory access-address summary table 31 is notified from the FPGA 5, that is, at each notification interval.

[0131] The statistics unit 14 generates an FPGA address-per-address access count summary table 33 by aggregating the number of memory accesses for each predetermined address range in units of sampling elapsed time, based on the FPGA memory access-address summary table 31 periodically received from FPGA 5 (see arrow P1 in Figure 16). It is desirable that the address ranges in the FPGA address-per-address access count summary table 33 be set to match the address ranges in the FPGA execution function conversion table 29, which will be described later.

[0132] The FPGA memory access-address summary table 31 illustrated in Figure 16 includes, for example, memory access information corresponding to the address range 0x1000-0x1FFF, including all (5) memory accesses with a sampling time of 300 μS, all (4) memory accesses with a sampling time of 500 μS, and 3 of the 6 memory accesses with a sampling time of 400 μS.

[0133] The statistics unit 14 calculates the number of accesses for each sampling time interval for these memory accesses in the FPGA memory access-address summary table 31, corresponding them to the address range 0x1000-0x1FFF in the FPGA address-per-address access count summary table 33, and registers them accordingly.

[0134] In the example shown in Figure 16, the statistics unit 14 registers the following memory access counts for the address range 0x1000-0x1FFF of the FPGA address access count summary table 33: 5 memory access counts at a sampling time of 300 μS, 3 memory access counts at a sampling time of 400 μS, and 4 memory access counts at a sampling time of 500 μS.

[0135] Similarly, the statistics unit 14 registers a memory access count of 3 for the address range 0x2000-0x2FFF of the FPGA address access count summary table 33 at a sampling elapsed time of 400 μS.

[0136] In the FPGA address-based access count summary table 33 illustrated in Figure 16, the number of memory accesses for each sampling elapsed time is associated with the address range (address) of the DDR memory 6.

[0137] Furthermore, in FPGA5, when loading a function from a CPU2 application, the memory region accessed by each function is fixedly determined. Therefore, based on the memory access address, it is possible to identify the function that uses the memory region indicated by that address.

[0138] In the FPGA execution function conversion table 29 illustrated in Figure 16, the function names of functions (e.g., subfunctions) executed by FPGA 5 are associated with the address ranges of DDR memory 6 accessed by FPGA 5. The information constituting this FPGA execution function conversion table 29 may be pre-configured; for example, FPGA execution function conversion table 29 may be generated when the application is loaded.

[0139] The statistics unit 14 can identify the function (sub-function) that uses the memory region indicated by the address range by referring to the FPGA execution function conversion table 29 based on the address range. In the FPGA execution function conversion table 29 illustrated in Figure 16, for example, it can be seen that the address range 0x1000-0x1FFF is used for the execution of sub-function A-2. It can be said that the statistics unit 14 identifies the memory space accessed by FPGA 5 for each function by referring to the FPGA execution function conversion table 29.

[0140] Next, the statistics unit 14 sums the number of memory accesses per sampling time unit for each address range in the FPGA address access count summary table 33 with the number of memory accesses per sampling time unit for the function corresponding to the address range in the memory access count DB 26. In this way, the statistics unit 14 reflects the number of memory accesses in the FPGA address access count summary table 33 in the memory access count DB 26 (see symbol P2 in Figure 16).

[0141] In the example shown in Figure 16, in the memory access count DB26 before the memory access count is reflected in the FPGA address access count summary table 33, the memory access information by CPU2 is registered for function A as follows: for example, 2 at a sampling elapsed time of 300 μS, 0 at a sampling elapsed time of 400 μS, and 0 at a sampling elapsed time of 500 μS.

[0142] On the other hand, in the FPGA address access count summary table 33, for the address range 0x1000-0x1FFF corresponding to function A-2, 5 is registered as the number of memory accesses at a sampling time of 300 μS, 3 at a sampling time of 400 μS, and 4 at a sampling time of 500 μS.

[0143] The statistics unit 14 retrieves the memory access counts 5, 3, and 4 registered for sampling elapsed times of 300μS, 400μS, and 500μS for the address range 0x1000-0x1FFF corresponding to function A-2 in the FPGA address access count summary table 33, and adds these to the memory access counts of 2, 0, and 0 for sampling elapsed times of 300μS, 400μS, and 500μS for function A in the memory access count DB26, respectively.

[0144] As a result, the number of accesses for function A in DB26 at sampling times of 300μS, 400μS, and 500μS will be 7 (=2+5), 3 (=0+3), and 4 (=0+4).

[0145] Thus, the memory access count DB26 manages the number of memory accesses to DDR memory 3 by CPU2 and the number of memory accesses to DDR memory 6 by FPGA5.

[0146] The statistics unit 14 combines (adds) the number of memory accesses by CPU 2 (first memory access information) and the number of memory accesses by FPGA 5 (second memory access information), which were obtained by CPU 2 during the same sampling elapsed time (same time period) for each function. Furthermore, the statistics unit 14 manages the number of memory hits for each function (main function) using the memory hit count DB 27.

[0147] Figure 17 illustrates the memory hit count DB27 of an information processing system 1 according to one embodiment.

[0148] The memory hit count DB27 illustrated in Figure 17 associates the number of memory hits per sampling elapsed time unit with the function name.

[0149] The statistics unit 14 calculates the number of memory hits for each main function by summing the number of memory hits for subfunctions included in the same main function, based on the CPU function memory hit summary table 25, which registers the number of memory hits for each smallest unit function (subfunction) executed by the CPU 2, and registers this in the memory hit count DB 27.

[0150] The DB27 memory hit count essentially manages the memory hit count for each main function in units of sampling time.

[0151] Figure 18 is a diagram illustrating the process of generating the memory hit count DB27 in an information processing system 1 according to one embodiment.

[0152] In the example below, the prerequisites are that the sampling period is 100 μS, the notification interval is 300 μS, and the elapsed time N = 200 μS. Furthermore, function A is assumed to include access to FPGA5's 0x1000.

[0153] The statistics unit 14 updates the CPU memory hit-program counter summary table 22 using the memory hit count and program counter information obtained from the performance counter information 20 (see symbol P1 in Figure 18).

[0154] The statistics unit 14 stores the number of memory hits and the program counter in association with each sampling time in the CPU memory hit-program counter summary table 22. The statistics unit 14 may generate the CPU memory hit-program counter summary table 22 by combining the number of memory hits for each sampling time obtained from the performance counter information 20 with the program counter value corresponding to the memory access that occurred at each sampling time.

[0155] Next, the statistics unit 14 obtains the function name corresponding to the program counter value by referring to the CPU execution function conversion table 23 based on the program counter value in the CPU memory hit-program counter summary table 22 (see symbol P2 in Figure 18).

[0156] The statistics unit 14 generates a CPU function-specific memory hit summary table 25 by aggregating the number of memory hits per sampling time unit for each function, based on the number of memory hits per sampling time unit in the CPU memory hit-program counter summary table 22 and the function name corresponding to the program counter (see symbol P3 in Figure 18).

[0157] The statistics unit 14 calculates the number of memory hits for each main function by summing the number of memory hits of sub-functions included in the same main function in units of sampling elapsed time, based on the CPU function memory hit aggregation table 25, and generates the memory hit count DB 27 (see symbol P4 in Figure 18).

[0158] The statistics unit 14 manages the memory hit count by merging the memory hit count from CPU2 and the memory hit count from FPGA5 in the memory hit count DB27.

[0159] Figure 19 is a diagram illustrating the merging method of the memory hit count in FPGA 5 with the memory hit count DB27 in an information processing system 1 according to one embodiment. Note that in the figure, the same symbols as those described above indicate the same parts, so their explanation is omitted.

[0160] Figure 19 shows an example of the process by which the statistics unit 14 updates the memory hit count DB27 shown in Figure 17 based on the information in the FPGA memory hit-address summary table 32, indicated by the symbol C in Figure 7.

[0161] As described above, in the FPGA memory hit-address summary table 32, multiple sampling elapsed times are corrected by adding the elapsed time N to each so that they represent the elapsed time since the application was started in CPU2. In other words, the sampling elapsed time in FPGA memory hit-address summary table 32 is corrected to the sampling elapsed time based on CPU2. In this embodiment, an example with elapsed time N = 200 μS is shown.

[0162] The statistics unit 14 may perform this process each time information constituting the FPGA memory hit-address summary table 32 is notified from the FPGA 5, that is, at each notification interval.

[0163] The statistics unit 14 generates an FPGA address-specific hit count summary table 34 by aggregating the number of memory hits for each predetermined address range in units of sampling elapsed time, based on the FPGA memory hit-address summary table 32 that is periodically received from FPGA 5 (see arrow P1 in Figure 19). It is desirable that the address ranges in the FPGA address-specific hit count summary table 34 be set to match the address ranges in the FPGA execution function conversion table 29.

[0164] The FPGA address hit count summary table 34 illustrated in Figure 19 includes, for example, memory access information corresponding to the address range 0x1000-0x1FFF, such as all (1) memory accesses with a sampling elapsed time of 300 μS and all (2) memory accesses with a sampling elapsed time of 400 μS in the FPGA memory hit-address summary table 32.

[0165] The statistics unit 14 registers the number of hits for each sampling time, corresponding to these memory accesses in the FPGA memory hit-address summary table 32 to the address range 0x1000-0x1FFF in the FPGA address hit count summary table 34.

[0166] In other words, the statistics unit 14 registers memory hit count 1 at a sampling elapsed time of 300 μS and memory hit count 2 at a sampling elapsed time of 400 μS for the address range 0x1000-0x1FFF of the FPGA address hit count summary table 34.

[0167] Similarly, the statistics unit 14 registers a memory hit count of 1 for the address range 0x2000-0x2FFF of the FPGA address hit count summary table 34 at a sampling elapsed time of 500 μS.

[0168] In the FPGA address-specific hit count summary table 34 illustrated in Figure 19, the number of memory hits for each sampling elapsed time is associated with the address range (address) of the DDR memory 6.

[0169] The statistics unit 14 identifies the function (sub-function) that uses the memory region indicated by the address range by referring to the FPGA execution function conversion table 29 based on the address range. In the FPGA execution function conversion table 29 illustrated in Figure 19, for example, it can be seen that the address range 0x1000-0x1FFF is used for the execution of sub-function A-2, and the address range 0x2000-0x2FFF is used for the execution of sub-function B-2.

[0170] Next, the statistics unit 14 sums the number of memory hits per sampling time unit for each address range in the FPGA address hit count summary table 34 with the number of memory hits per sampling time unit for the function corresponding to the address range in the memory hit count DB 27. In this way, the statistics unit 14 reflects the number of memory hits in the FPGA memory hit-address summary table 32 in the memory hit count DB 27 (see symbol P2 in Figure 19).

[0171] In the example shown in Figure 19, in the memory hit count DB27 before the memory hit count is reflected in the FPGA address hit count summary table 34, the memory access information by CPU2 is registered as follows for function A: for example, 0 for sampling elapsed times of 300 μS and 400 μS, and 2 for sampling elapsed time of 500 μS. Also, for function B, for example, 1 for sampling elapsed time of 400 μS, and 0 for sampling elapsed times of 300 μS and 500 μS.

[0172] On the other hand, in the FPGA address-specific hit count summary table 34, for the address range 0x1000-0x1FFF corresponding to function A-2, 1 is registered as the memory hit count at a sampling time of 300 μS, and 2 is registered at a sampling time of 400 μS. Also, for the address range 0x2000-0x2FFF corresponding to function B-2, 1 is registered as the memory hit count at a sampling time of 500 μS.

[0173] The statistics unit 14 retrieves memory hit counts 1 and 2 registered at sampling elapsed times of 300 μS and 400 μS for the address range 0x1000-0x1FFF corresponding to function A-2 in the FPGA address hit count summary table 34, and adds them to the memory hit counts of 0 and 0 for function A at sampling elapsed times of 300 μS and 400 μS, respectively, in the memory hit count DB27.

[0174] As a result, the number of hits for function A in memory access DB26 at sampling times of 300 μS and 400 μS will be 1 (= 0 + 1) and 2 (= 0 + 2), respectively.

[0175] Furthermore, the statistics unit 14 retrieves the memory hit count of 1 registered at a sampling time of 500 μS for the address range 0x2000-0x2FFF corresponding to function B-2 in the FPGA address hit count summary table 34, and adds it to the memory hit count of 0 at a sampling time of 500 μS for function B in the memory hit count DB 27.

[0176] As a result, the number of hits for function B with memory access count DB26 at a sampling elapsed time of 500 μS is 1 (= 0 + 1).

[0177] Thus, the memory hit count DB27 manages the number of memory hits for memory access to DDR memory 3 by CPU2 and the number of memory hits for memory access to DDR memory 6 by FPGA5.

[0178] The statistics unit 14 combines (adds) the number of memory hits related to memory access by CPU 2 (first memory access information) and the number of memory hits related to memory access by FPGA 5 (second memory access information), both obtained by CPU 2 during the same sampling elapsed time (same time period) for the function.

[0179] (B) Operation First, the processing of the event notification unit 16 of the information processing system 1 according to one embodiment configured as described above will be explained according to the flowchart (steps A1 to A5) shown in Figure 20.

[0180] The following process may be performed, for example, when CPU2 starts executing an application in information processing system 1 (when the application is launched).

[0181] In step A1, the event notification unit 16 notifies the statistics unit 14 of the instruction to start monitoring the sampling period and memory access information (number of memory accesses and number of memory hits).

[0182] In step A2, the event notification unit 16 stores (retains) the timestamp of the time it notified the statistics unit 14 of the instruction to start monitoring in a predetermined storage area such as the DDR memory 3 or the storage unit 7.

[0183] In step A3, the event notification unit 16 notifies the counter unit 17 of FPGA 5 of an instruction to start monitoring memory access information (number of memory accesses and number of memory hits), and also notifies it of the sampling period and notification interval.

[0184] In step A4, the event notification unit 16 stores (retains) a timestamp of the time it notified the FPGA 5 of the start of monitoring in a predetermined storage area such as the DDR memory 3 or the storage unit 7.

[0185] In step A5, the event notification unit 16 calculates the elapsed time N and stores (retains) the calculated elapsed time N in a predetermined storage area such as the storage unit 7 or DDR memory 3. After that, the process ends.

[0186] Next, the processing of the statistics unit 14 of the information processing system 1 according to one embodiment will be explained according to the flowchart (steps B1 to B10) shown in Figure 21.

[0187] In step B1, the statistics unit 14 checks if there is an instruction to start sampling of memory access information (number of memory accesses and number of memory hits). If there is no instruction to start sampling (see the No route in step B1), step B1 is repeated. If there is an instruction to start sampling (see the Yes route in step B1), the process proceeds to step B2.

[0188] In step B2, the statistics unit 14 obtains memory access information (number of memory accesses and number of memory hits) counted by the performance counter 12.

[0189] In step B3, the statistics unit 14 updates the CPU memory access-program counter summary table 21 based on the acquired number of memory accesses. The statistics unit 14 also updates the CPU memory hit-program counter summary table 22 based on the acquired number of memory hits.

[0190] Note that the CPU memory access-program counter summary table 21 and the CPU memory hit-program counter summary table 22 are sometimes collectively referred to as the CPU memory access / hit-program counter summary table. The statistics unit 14 updates the CPU memory access / hit-program counter summary table.

[0191] In step B4, the statistics unit 14 retrieves data from the CPU memory access-program counter summary table 21 and the CPU memory hit-program counter summary table 22, respectively.

[0192] Specifically, the statistics unit 14 obtains the number of memory accesses and the program counter for each sampling elapsed time from the CPU memory access-program counter summary table 21. In addition, the statistics unit 14 obtains the number of memory hits and the program counter for each sampling elapsed time from the CPU memory hit-program counter summary table 22.

[0193] In step B5, the statistics unit 14 obtains the corresponding function name by referring to the CPU execution function conversion table 23 based on the value of the program counter. This allows the statistics unit 14 to convert the program counter into a function name.

[0194] In step B6, the statistics unit 14 recalculates the number of memory accesses for each function name in units of sampling elapsed time and updates the CPU function memory access summary table 24. The statistics unit 14 also recalculates the number of memory hits for each function name in units of sampling elapsed time and updates the CPU function memory hit summary table 25. Note that the CPU function memory access summary table 24 and the CPU function memory hit summary table 25 are sometimes collectively referred to as the CPU function memory access / hit summary table. The statistics unit 14 updates the CPU function memory access / hit summary table.

[0195] In step B7, the statistics unit 14 checks whether it has received a notification from the receiving unit 15 indicating that it has received information that constitutes the FPGA memory access-address summary table 31 or information that constitutes the FPGA memory hit-address summary table 32.

[0196] If, upon confirmation, there is a notification from the receiving unit 15 (see the Yes route in step B7), the process proceeds to step B8. In step B8, the statistics unit 14 updates the FPGA address-per-access count summary table 33 using the information from the FPGA memory access-address summary table 31. The statistics unit 14 also updates the FPGA address-per-hit count summary table 34 using the information from the FPGA memory hit-address summary table 32. The FPGA address-per-access count summary table 33 and the FPGA address-per-hit count summary table 34 are sometimes collectively referred to as the FPGA address-per-access / hit count summary table. The statistics unit 14 updates the FPGA address-per-access / hit count summary table.

[0197] In step B9, the statistics unit 14 sums the number of memory accesses per sampling time unit for each address range in the FPGA address access count summary table 33 with the number of memory accesses per sampling time unit for the function corresponding to the address range in the memory access count DB 26. That is, the statistics unit 14 updates the number of memory accesses by CPU2 in the memory access count DB 26 by adding the information from the FPGA address access count summary table 33. In this way, the statistics unit 14 reflects (merges) the number of memory accesses in the FPGA address access count summary table 33 into the memory access count DB 26.

[0198] Furthermore, the statistics unit 14 sums the number of memory hits for each sampling time in the FPGA address-specific hit count summary table 34 with the number of memory hits for each sampling time in the memory hit count DB 27 for the function corresponding to the address range. In other words, the statistics unit 14 updates the memory hit count in the memory hit count DB 27 by adding the information from the FPGA address-specific hit count summary table 34 to the number of memory hits by the CPU2. As a result, the statistics unit 14 reflects (merges) the number of memory hits in the FPGA memory hit-address summary table 32 into the memory hit count DB 27.

[0199] Note that the number of memory accesses (DB26) and the number of memory hits (DB27) may be combined and expressed as number of memory accesses / hits (DB). Also, the number of memory accesses and the number of memory hits may be combined and expressed as number of memory accesses / hits. Then, return to step B1.

[0200] Furthermore, if, as a result of the check in step B7, there is no notification from the receiving unit 15 (see No. route in step B7), the process proceeds to step B10.

[0201] In step B10, the statistics unit 14 calculates the number of memory accesses for each main function by summing the number of memory accesses for subfunctions included in the same main function in units of sampling elapsed time, based on the CPU function memory access summary table 24, and updates (generates) the memory access count DB 26.

[0202] Furthermore, the statistics unit 14 calculates the number of memory hits for each main function by summing the number of memory hits of sub-functions included in the same main function in units of sampling elapsed time, based on the CPU function memory hit aggregation table 25, and updates (generates) the memory hit count DB 27. After that, it returns to step B10.

[0203] Next, the processing of the receiving unit 15 of the information processing system 1 according to one embodiment will be explained according to the flowchart (steps C1 to C2) shown in Figure 22.

[0204] In step C1, the receiving unit 15 checks whether it has received notifications from the FPGA 5's notification unit 19 regarding information constituting the FPGA memory access-address summary table 31 and information constituting the FPGA memory hit-address summary table 32. If no such notifications are received (see No. route in step C1), the process returns to step C1.

[0205] Furthermore, if there are notifications from FPGA5's notification unit 19 (see the Yes route in step C1), in step C2, the receiving unit 15 notifies the statistics unit 14 (CPU2). Then, the process returns to step C1.

[0206] Next, the processing of the counter unit 17 of the FPGA 5 in the information processing system 1 according to one embodiment will be explained according to the flowchart (steps D1 to D3) shown in Figure 23.

[0207] In step D1, the counter unit 17 checks if there is a notification from the event notification unit 16. If there is no notification from the event notification unit 16 (see No. route in step D1), step D1 is repeated.

[0208] If there is a notification from the event notification unit 16 (see the Yes route in step D1), in step D2, the counter unit 17 generates a sampling trigger using a period generation circuit (not shown).

[0209] In step D3, the counter unit 17 counts the number of memory accesses and memory hits for memory accesses performed between the FPGA 5 and the DDR memory 6. After that, the process returns to step D1.

[0210] Next, the processing of the sampling unit 18 of the FPGA 5 in the information processing system 1 according to one embodiment will be explained according to the flowchart (steps E1 to E3) shown in Figure 24.

[0211] In step E1, the sampling unit 18 checks if there is a notification from the event notification unit 16. If there is no notification from the event notification unit 16 (see No. route in step E1), the process returns to step E1.

[0212] Furthermore, if there is a notification from the event notification unit 16 (see the Yes route in step E1), in step E2, the sampling unit 18 checks whether it is the timing of the sampling cycle, that is, whether the sampling trigger has been reached. If it is not the sampling cycle (see the No route in step E2), the process returns to step E1.

[0213] If it is the sampling period (see the Yes route in step E2), proceed to step E3. In step E3, the sampling unit 18 updates the FPGA memory access-address summary table 31 and the FPGA memory hit-address summary table 32. Note that the FPGA memory access-address summary table 31 and the FPGA memory hit-address summary table 32 are sometimes collectively referred to as the FPGA memory access / hit-address summary table. After that, return to step E1.

[0214] Next, the processing of the notification unit 19 of the FPGA 5 in the information processing system 1 according to one embodiment will be explained according to the flowchart (steps F1 to F2) shown in Figure 25.

[0215] In step F1, the notification unit 19 checks if it is the transmission interval cycle timing. If it is not the transmission interval cycle (see the No route in step F1), it returns to step F1. If it is the transmission interval cycle (see the Yes route in step F1), it proceeds to step F2.

[0216] In step F2, the notification unit 19 notifies (sends) the CPU 2 the information that constitutes the FPGA memory access-address summary table 31 and the information that constitutes the FPGA memory hit-address summary table 32, respectively. Then, the process returns to step F1.

[0217] (C) Effects As described above, according to the information processing system 1 of one embodiment, the statistics unit 14 updates the memory access count DB 26 by adding the information from the FPGA address-specific access count summary table 33 to the memory access count of CPU 2 that has been updated. As a result, the statistics unit 14 reflects (merges) the memory access count counted in FPGA 5 into the memory access count DB 26 managed by CPU 2.

[0218] Furthermore, the statistics unit 14 updates the memory hit count DB 27 by adding the information from the FPGA address-specific hit count summary table 34 to the memory hit count of CPU 2 that has been updated. In this way, the statistics unit 14 reflects (merges) the memory hit count counted in FPGA 5 into the memory hit count DB 27 managed by CPU 2.

[0219] Therefore, in CPU2, the total number of memory hits for the shared memory over the period to be analyzed can be calculated based on the number of memory accesses (DB26) and the number of memory hits (DB27). Furthermore, performance analysis can be performed using the memory hit rate for the entire memory, including both DDR memory 3 and DDR memory 6, without bias towards either CPU2 or FPGA5, thereby improving the accuracy of the performance analysis.

[0220] In FPGA5, the sampling elapsed time, which is measured when a monitoring start command is received from CPU2, is corrected to represent the elapsed time since the application started by adding the elapsed time N from when CPU2 executes the application until it notifies FPGA5 of the monitoring start command.

[0221] This allows for the synchronized management of memory access information (number of memory accesses, number of memory hits) obtained by CPU2 and memory access information (number of memory accesses, number of memory hits) obtained by FPGA5. CPU2 can manage the memory access information from FPGA5 in conjunction with the memory access information from CPU2 at the same time point relative to the CPU, offering high convenience.

[0222] When processing application functions, it is possible to unify the memory access status of DDR memory 3 by CPU2 and the memory access status of DDR memory 6 by FPGA5.

[0223] The statistics unit 14 updates the access count information per function by converting the address range in the FPGA address-specific access count summary table 33 to function names by referring to the FPGA execution function conversion table 29. This allows the memory access information obtained in FPGA 5 to be easily linked and managed in CPU 2 to the memory access information in CPU 2.

[0224] (D) Other Each component and process of this embodiment can be selected or omitted as needed, or combined as appropriate.

[0225] Furthermore, the disclosed technology is not limited to the embodiments described above, and can be implemented in various modified forms without departing from the spirit of this embodiment.

[0226] For example, in the embodiment described above, in the method for merging (combining) the number of memory accesses in FPGA5 with the number of memory accesses DB26 shown in Figure 16, the statistics unit 14 simply adds the number of memory accesses counted in FPGA5 to the number of memory accesses counted in CPU2, but it is not limited to this.

[0227] For example, when the statistics unit 14 combines the number of memory accesses (memory access information) in FPGA 5 with the memory access count DB 26 on the CPU 2 side, it may calculate the average number of memory accesses per sampling period of FPGA 5 and add this calculated average number of memory accesses (average memory access information) to the number of memory accesses counted by CPU 2.

[0228] Figure 26 illustrates a modified example of the merging method for the number of memory accesses in FPGA 5 to the number of memory accesses in DB 26 in an information processing system 1 according to one embodiment.

[0229] Figure 26 shows an example where the sampling period is 5 μS and the notification interval is 15 μS.

[0230] In this modified example, the statistics unit 14 calculates the average value (average number of memory accesses) of memory access counts 5, 3, and 4 for sampling elapsed times of 205 μS, 210 μS, and 215 μS in the address range 0x1000-0x1FFF in the FPGA address access count summary table 33. This average number of memory accesses may be calculated, for example, by the following formula.

[0231] Average number of memory accesses =sum(number of memory accesses per FPGA address) / (notification interval / sampling period) =(5+3+4) / (15 / 5) =4 The statistics unit 14 sums the calculated average number of memory accesses with the number of memory accesses per sampling time unit for the function corresponding to the address range in the memory access count DB 26.

[0232] In the example shown in Figure 26, in the memory access count DB26 before the memory access count is reflected in the FPGA address access count summary table 33, the memory access information by CPU2 is registered for function A as follows: 2 at a sampling time of 205 μS, 0 at a sampling time of 210 μS, and 0 at a sampling time of 215 μS.

[0233] The statistics unit 14 retrieves the memory access counts 5, 3, and 4 registered at sampling elapsed times of 300 μS, 400 μS, and 500 μS for the address range 0x1000-0x1FFF corresponding to function A-2 in the FPGA address access count summary table 33, and calculates the average memory access count of 4.

[0234] The statistics unit 14 adds the calculated average memory access count of 4 to the memory access counts of 2, 0, and 0 for function A at sampling times of 205 μS, 210 μS, and 215 μS in the memory access count DB 26.

[0235] As a result, the number of accesses for function A in memory access count DB26 at sampling elapsed times of 205μS, 210μS, and 215μS will be 6 (=2+4), 4 (=0+4), and 4 (=0+4).

[0236] In this way, for example, when the sampling period is short, the average number of memory accesses per sampling period of FPGA5 can be added to the number of memory accesses for the corresponding sampling elapsed time in the memory access count DB26, thereby suppressing the occurrence of bias (fluctuations) in the number of accesses.

[0237] In this modified example, the statistics unit 14 combines (adds) the average value of multiple memory access counts (second memory access information) obtained by FPGA5 during the same sampling elapsed time (same time period) with the number of memory accesses (first memory access information) related to memory access by CPU2.

[0238] In the modified example shown in Figure 26, the statistics unit 14 also manages the number of memory hits using a similar method.

[0239] Furthermore, in the above-described embodiment, the elapsed time N is reflected in the information constituting the FPGA memory access-address summary table 31 and the FPGA memory hit-address summary table 32 that the notification unit 19 of FPGA 5 notifies the CPU 2 of, but is not limited to this. The CPU 2 may also reflect the elapsed time N in the FPGA memory access-address summary table 31 and FPGA memory hit-address summary table 32 notified by FPGA 5.

[0240] Furthermore, in the embodiments described above, the program counter 11 and performance counter 12 are shown as being implemented by functions installed in an IA processor, and therefore, the example shows CPU2 as an IA processor, but it is not limited to this. CPU2 may be a processor other than an IA processor, and the program counter 11 and performance counter 12 may be implemented by functions installed in a processor other than an IA processor, and can be implemented in various modified forms.

[0241] Furthermore, the above disclosure makes it possible for those skilled in the art to implement and manufacture this embodiment.

[0242] (E) Note The following additional information is disclosed regarding the embodiments described above.

[0243] (Note 1) A CPU (Central Processing Unit) that executes an application having a function that includes a first subfunction and a second subfunction, The first memory accessible by the CPU, An FPGA (Field Programmable Gate Array) processes the first subfunction according to the execution instructions from the CPU, The FPGA has access to a second memory and An information processing system having, The CPU repeatedly collects first memory access information relating to memory accesses performed on the first memory when processing the second subfunction at predetermined intervals. The FPGA repeatedly collects second memory access information relating to memory accesses performed on the second memory when processing the first subfunction at predetermined intervals. The CPU combines the first memory access information and the second memory access information obtained during the same time period with respect to the function. An information processing system characterized by the following:

[0244] (Note 2) The time elapsed from when the CPU starts executing the application until when the FPGA starts collecting the second memory access information is added to the collection time information for the second memory access information. The information processing system described in Appendix 1, characterized by the features described herein.

[0245] (Note 3) The synthesis process includes adding the second memory access information, which has the same collection time information as the first memory access information, to the first memory access information. The information processing system described in Appendix 2, characterized by the features described herein.

[0246] (Note 4) The synthesis process includes adding to the first memory access information the average value of a plurality of second memory access pieces having the same collection time information as the first memory access information. The information processing system described in Appendix 2, characterized by the features described herein.

[0247] (Note 5) A CPU (Central Processing Unit) that executes an application having a function that includes a first subfunction and a second subfunction, The first memory accessible by the CPU, An FPGA (Field Programmable Gate Array) processes the first subfunction according to the execution instructions from the CPU, The FPGA has access to a second memory and In an information processing system having, The CPU repeatedly collects first memory access information relating to memory accesses performed on the first memory when processing the second subfunction at predetermined intervals. The FPGA repeatedly collects second memory access information relating to memory accesses performed on the second memory when processing the first subfunction at predetermined intervals. With respect to the aforementioned function, the first memory access information and the second memory access information obtained during the same time period are combined. An information processing method characterized by performing a process.

[0248] (Note 6) The time elapsed from when the CPU starts executing the application until when the FPGA starts collecting the second memory access information is added to the collection time information for the second memory access information. The information processing method described in Appendix 5, characterized by the features described herein.

[0249] (Note 7) The synthesis process includes adding the second memory access information, which has the same collection time information as the first memory access information, to the first memory access information. The information processing method described in Appendix 6, characterized by the features described herein.

[0250] (Note 8) The synthesis process includes adding to the first memory access information the average value of a plurality of second memory access pieces having the same collection time information as the first memory access information. The information processing method described in Appendix 6, characterized by the features described herein. [Explanation of symbols]

[0251] 1. Information Processing System 2 CPU 3.6 DDR memory 4. Accelerator Card 5 FPGA 11 Program Counter 12 Performance Counters 13 Management Department 14 Statistics Department 15 Receiving Unit 16 Event Notification Section 17 Counter section 18 Sampling section 19 Notification Department 20 Performance Counter Information 21. CPU Memory Access - Program Counter Summary Table 22 CPU Memory Hits - Program Counter Summary Table 23 CPU Execution Function Conversion Table 24 CPU Function-Specific Memory Access Summary Table 25 CPU Function-Specific Memory Hit Summary Table 26. Number of memory accesses in the database 27 Memory hit count DB 28 Counter Summary Table 29 FPGA Execution Function Conversion Table 31 FPGA Memory Access - Address Summary Table 32 FPGA Memory Hit-Address Summary Table 33 FPGA Address Access Count Summary Table 34. Table summarizing the number of hits per FPGA address

Claims

1. A CPU (Central Processing Unit) that executes an application having a function that includes a first subfunction and a second subfunction, The first memory accessible by the CPU, An FPGA (Field Programmable Gate Array) processes the first subfunction according to the execution instructions from the CPU, The FPGA has access to a second memory and An information processing system having, The CPU repeatedly collects first memory access information relating to memory accesses performed on the first memory when processing the second subfunction at predetermined intervals. The FPGA repeatedly collects second memory access information relating to memory accesses performed on the second memory when processing the first subfunction at predetermined intervals. The CPU combines the first memory access information and the second memory access information obtained during the same time period with respect to the function. An information processing system characterized by the following:

2. The time elapsed from when the CPU starts executing the application until when the FPGA starts collecting the second memory access information is added to the collection time information for the second memory access information. The information processing system according to feature 1.

3. The synthesis process includes adding the second memory access information, which has the same collection time information as the first memory access information, to the first memory access information. The information processing system according to feature 2.

4. The synthesis process includes adding to the first memory access information the average value of a plurality of second memory access pieces having the same collection time information as the first memory access information. The information processing system according to feature 2.

5. A CPU (Central Processing Unit) that executes an application having a function that includes a first subfunction and a second subfunction, The first memory accessible by the CPU, An FPGA (Field Programmable Gate Array) processes the first subfunction according to the execution instructions from the CPU, The FPGA has access to a second memory and In an information processing system having, The CPU repeatedly collects first memory access information relating to memory accesses performed on the first memory when processing the second subfunction at predetermined intervals. The FPGA repeatedly collects second memory access information relating to memory accesses performed on the second memory when processing the first subfunction at predetermined intervals. With respect to the aforementioned function, the first memory access information and the second memory access information obtained during the same time period are combined. An information processing method characterized by performing a process.

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