Method for manufacturing semiconductor devices

Abstract

To provide a semiconductor device with good electrical characteristics. [Solution] In a semiconductor device, a first insulating layer 103 covers the top and sides of the semiconductor layer, and a conductive layer 112 is located on the first insulating layer. A metal oxide layer 114 is located between the first insulating layer and the conductive layer, and the edges of the metal oxide layer are located inward from the edges of the conductive layer. An insulating region 150 is adjacent to the metal oxide layer and located between the first insulating layer and the conductive layer. The semiconductor layer has a first region 108C, a pair of second regions 108L, and a pair of third regions 108N. The first region overlaps with the metal oxide layer and the conductive layer. The second region sandwiches the first region and overlaps with the insulating region and the conductive layer. The third region sandwiches the first region and the pair of second regions and does not overlap with the conductive layer. Preferably, the third region includes a portion with lower resistance than the first region. The second region preferably includes a portion with higher resistance than the third region.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As the technical field of one aspect of the present invention disclosed in this specification and the like, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices , electronic devices, lighting devices, input devices, input / output devices, their driving methods, or their manufacturing methods, can be cited as an example. A semiconductor device generally refers to any device that can function by utilizing semiconductor characteristics.

[0003]

Background Art

[0004] Since the metal oxide that can be used for the semiconductor layer can be formed by using a sputtering method or the like, it can be used for the semiconductor layer of a transistor constituting a large display device. Also, since it is possible to improve and utilize a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon, capital investment can be suppressed. In addition, since a transistor using a metal oxide has a higher field-effect mobility than when using amorphous silicon, a drive circuit

[0005] This enables the creation of high-performance display devices. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2014-7399 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. One aspect of the invention aims to provide a highly reliable semiconductor device. One aspect of this invention aims to provide a semiconductor device with stable electrical characteristics. One objective of this invention is to provide a novel semiconductor device. One aspect of this invention is to provide a reliable semiconductor device. One objective is to provide a high-performance display device. One aspect of the present invention provides a novel display device. One of the objectives is to provide it.

[0007] Furthermore, the description of these problems does not preclude the existence of other problems. One approach does not require that all of these issues be resolved. The title can be extracted from descriptions such as the specification, drawings, and claims. [Means for solving the problem]

[0008] One aspect of the present invention comprises a semiconductor layer, a first insulating layer, a metal oxide layer, a conductive layer, and an insulating region. A semiconductor device having a region and a first insulating layer covering the top and sides of the semiconductor layer and The conductive layer is located on the first insulating layer. The metal oxide layer is located between the first insulating layer and the conductive layer. The edges of the metal oxide layer are located inside the edges of the conductive layer. The insulating region is the metal oxide layer. It is adjacent to the oxide layer and located between the first insulating layer and the conductive layer. The semiconductor layer is the first It has a region, a pair of second regions, and a pair of third regions. The first region is a metallic acid The second region overlaps with the oxide layer and the conductive layer. The second region sandwiches the first region and also overlaps with the insulating region and the conductive layer. It overlaps with the first region and the pair of second regions, and overlaps with the conductive layer. No. The third region preferably includes a portion with lower resistance than the first region. Preferably, the region includes a portion with higher resistance than the third region.

[0009] In the aforementioned semiconductor device, the dielectric constant of the insulating region and the first insulating layer are different. preferable.

[0010] In the aforementioned semiconductor device, it is preferable that the insulating region has a gap.

[0011] The semiconductor device described above further has a second insulating layer, the second insulating layer being the first insulating layer Preferably, the insulating region, which is in contact with the upper surface of the layer, includes a second insulating layer.

[0012] In the aforementioned semiconductor device, the first insulating layer comprises an oxide or nitride, and the second insulating layer It is preferable that it contains an oxide or nitride.

[0013] In the aforementioned semiconductor device, the first insulating layer contains silicon and oxygen, and the second insulating layer It is preferable that it contains silicon and oxygen.

[0014] In the aforementioned semiconductor device, the first insulating layer contains silicon and oxygen, and the second insulating layer It is preferable that it contains silicon and nitrogen.

[0015] The aforementioned semiconductor device further has a third insulating layer, the third insulating layer is the second insulating layer The third insulating layer, which is in contact with the upper surface of the layer, preferably contains a nitride.

[0016] In the aforementioned semiconductor device, the third insulating layer preferably contains silicon and nitrogen. .

[0017] In the aforementioned semiconductor device, the third region contains the first element, and the first element is boron. Preferably, it is one or more selected from phosphorus, aluminum, and magnesium.

[0018] In the aforementioned semiconductor device, the semiconductor layer and the metal oxide layer each contain indium. Preferably, the semiconductor layer and the metal oxide layer have approximately equal indium content. [Effects of the Invention]

[0019] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, reliability We can provide semiconductor devices with high performance, or semiconductor devices with stable electrical characteristics. Alternatively, we can provide a novel semiconductor device. Or, we can provide a highly reliable display device. Alternatively, a new display device can be provided.

[0020] Furthermore, the description of these effects does not preclude the existence of other effects. One embodiment does not necessarily have to possess all of these effects. Furthermore, other effects may be considered. This information can be extracted from descriptions such as specifications, drawings, and claims. [Brief explanation of the drawing]

[0021] [Figure 1]Figure 1A is a top view showing an example of a transistor configuration. Figures 1B and 1C are cross-sectional views showing an example of a transistor configuration. [Figure 2] Figures 2A and 2B are cross-sectional views showing examples of transistor configurations. [Figure 3] Figures 3A and 3B are cross-sectional views showing examples of transistor configurations. [Figure 4] Figures 4A and 4B are cross-sectional views showing examples of transistor configurations. [Figure 5] Figure 5A is a top view showing an example of transistor configuration. Figures 5B and 5C are cross-sectional views showing an example of transistor configuration. [Figure 6] Figures 6A and 6B are cross-sectional views showing examples of transistor configurations. [Figure 7] Figures 7A and 7B are cross-sectional views showing examples of transistor configurations. [Figure 8] Figures 8A, 8B, 8C, 8D, and 8E are cross-sectional views illustrating the method for fabricating a transistor. [Figure 9] Figures 9A, 9B, and 9C are cross-sectional views illustrating the method for fabricating a transistor. [Figure 10] Figures 10A, 10B, and 10C are cross-sectional views illustrating the method for fabricating a transistor. [Figure 11] Figures 11A, 11B, and 11C are cross-sectional views illustrating the method for fabricating a transistor. [Figure 12] Figures 12A, 12B, and 12C are top views of the display device. [Figure 13] Figure 13 is a cross-sectional view of the display device. [Figure 14] Figure 14 is a cross-sectional view of the display device. [Figure 15] Figure 15 is a cross-sectional view of the display device. [Figure 16] Figure 16 is a cross-sectional view of the display device. [Figure 17] Figure 17A is a block diagram of the display device. Figures 17B and 17C are circuit diagrams of the display device. [Figure 18]Figures 18A, 18C, and 18D are circuit diagrams of the display device. Figure 18B is a timing chart of the display device. [Figure 19] Figures 19A and 19B show examples of display module configurations. [Figure 20] Figures 20A and 20B show examples of electronic device configurations. [Figure 21] Figures 21A, 21B, 21C, 21D, and 21E show examples of electronic device configurations. [Figure 22] Figures 22A, 22B, 22C, 22D, 22E, 22F, and 22G show examples of electronic device configurations. [Figure 23] Figures 23A, 23B, 23C, and 23D show examples of electronic device configurations. [Figure 24] Figure 24 is a cross-sectional STEM image. [Figure 25] Figure 25 shows the Id-Vg characteristics of the transistor, as well as a STEM image of its cross-section. [Figure 26] Figure 26 shows the Id-Vg characteristics of the transistor, as well as a STEM image of its cross-section. [Figure 27] Figure 27 shows the Id-Vg characteristics of the transistor, as well as a STEM image of its cross-section. [Figure 28] Figure 28 shows the results of a transistor reliability test. [Figure 29] Figure 29 shows the cross-sectional structure of the sample. [Figure 30] Figure 30 shows the sheet resistance of the sample. [Figure 31] Figure 31 is a cross-sectional STEM image. [Modes for carrying out the invention]

[0022] The embodiments will be described below with reference to the drawings. However, many embodiments are described. It can be implemented in different ways, without deviating from its purpose and scope. Those skilled in the art will readily understand that the form and details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents described in the following embodiments.

[0023] In each figure described herein, the size, layer thickness, or area of ​​each component is clearly defined. It may be exaggerated for that reason.

[0024] The ordinal numbers "1st," "2nd," and "3rd" used in this specification, etc., are intended to avoid confusion of constituent elements. This was added to avoid the issue of a numerical limitation.

[0025] In this specification, phrases indicating placement such as "above" and "below" refer to the positional relationship between components. The terms are used for convenience when explaining with reference to the diagrams. Also, the positional relationships between the components are as follows: The terminology used in the specification changes appropriately depending on the direction in which each component is described. It's not limited to phrases; it can be appropriately rephrased depending on the situation.

[0026] In this specification and elsewhere, the source and drain functions of a transistor are defined as follows: The polarity may change, or the direction of the current may change during circuit operation. Therefore, the terms source and drain may be used interchangeably.

[0027] In this specification, the channel length direction of a transistor refers to the source region and the drain region. This refers to one of the directions parallel to the straight line connecting two regions by the shortest distance. In other words, channel length. The direction is one of the directions in which current flows through the semiconductor layer when the transistor is ON. It corresponds to. Furthermore, the channel width direction refers to the direction perpendicular to the channel length direction. Note that, Depending on the structure and shape of the transistor, the channel length and channel width directions may be uniquely determined. It may not always be the case.

[0028] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where they are connected via. Here, "something that has some kind of electrical effect" is There are no particular restrictions as long as it enables the exchange of electrical signals between connected objects. For example, "things that have some kind of electrical effect" include electrodes, wiring, transistors, etc. Switching elements, resistive elements, inductors, capacitors, and other elements with various functions This includes children, etc.

[0029] In this specification, the terms "membrane" and "layer" are interchangeable. It is possible. For example, the terms "conductive layer" and "insulating layer" are similar to "conductive film" and "insulating layer". In some cases, the term "membrane" can be used interchangeably.

[0030] In this specification, "approximately matching top surface shape" means that there is a small difference between the stacked layers. This refers to the overlapping of parts of the outlines. For example, the upper layer and the lower layer may have the same mask pattern. , or including cases where part of it is processed with the same mask pattern. However, strictly speaking, ring The walls do not overlap, and the upper layer is located inside the lower layer, or the upper layer is located outside the lower layer. In this case as well, it is said that "the top surface shape is roughly the same."

[0031] In this specification, unless otherwise specified, off-current refers to the state in which the transistor is in the off state. This refers to the drain current when the device is in a non-conductive state or interrupted state. The off state is a special state. Unless otherwise specified, in an n-channel transistor, the voltage between the gate and source Vgs but Threshold voltage V th Lower than (in p-channel transistors, V th (Higher than) To describe a state or attitude.

[0032] In this specification, a display panel, which is one form of a display device, displays an image or the like on its display surface. It has the function of (powering). Therefore, the display panel is one form of an output device.

[0033] In this specification, the substrate of the display panel is, for example, FPC (Flexible Printed Circuit). ed Circuit) or TCP (Tape Carrier Package) Connectors such as those mentioned above are attached, or COG (Chip On Glare) is attached to the circuit board. A display panel module, display module, etc., is a device on which an IC is mounted using the ss) method, etc. Alternatively, it may simply be called a display panel.

[0034] In this specification, a touch panel, which is one form of a display device, displays images, etc. on its display surface. The display function detects when an object such as a finger or stylus touches, presses, or comes near the display surface. It has the function of a touch sensor that detects things like touching. Therefore, touch panel This is one form of an input / output device.

[0035] A touch panel is, for example, a display panel (or display device) with a touch sensor. It can also be called a display panel (or display device) with a touch function. It can also be configured to have a panel and a touch sensor panel. Alternatively, the display panel The configuration can also include a touch sensor function either internally or on the surface.

[0036] In this specification, a touch panel circuit board with connectors and ICs mounted on it is referred to as a touch panel. It may be called a touch panel module, display module, or simply a touch panel.

[0037] (Embodiment 1) This embodiment describes a semiconductor device according to one aspect of the present invention and a method for manufacturing the same. In particular, in this embodiment, as an example of a semiconductor device, the semiconductor layer in which the channel is formed This section describes transistors that use oxide semiconductors.

[0038] One aspect of the present invention is a semiconductor layer on which a channel is formed on a surface to be formed, and an insulating layer on the semiconductor layer. This is a transistor having a marginal layer, a metal oxide layer on an insulating layer, and a conductive layer. A transistor according to one aspect of the invention preferably has an insulating region adjacent to the metal oxide layer. It is so. The insulating region is located between the gate insulating layer and the conductive layer. The semiconductor layer has semiconductor properties. It is preferable that the material is composed of a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits the following properties.

[0039] The edges of the metal oxide layer are positioned inward from the edges of the conductive layer. This is preferable. In other words, the conductive layer has a portion that protrudes outward beyond the edge of the metal oxide layer. It is preferable to have this. A portion of the metal oxide layer and the conductive layer functions as a gate electrode.

[0040] It is preferable that the insulating region has a different dielectric constant from the insulating layer. For example, the insulating region has air gaps. It may include. Furthermore, the insulating layer is preferably provided covering the top and sides of the semiconductor layer. The insulating layer and a portion of the insulating region function as a gate insulating layer.

[0041] The semiconductor layer comprises a first region overlapping with the metal oxide layer and the conductive layer, and an insulating region overlapping with the conductive layer. It has a second region and a third region that does not overlap with the conductive layer. The first region is channel-shaped This is a region that functions as a building region. The third region is a region with lower resistance than the first region. This is an area that functions as either a source area or a drain area. The second area is the third area. It is preferable that the region has higher resistance than the region.

[0042] The second region overlaps with the conductive layer that functions as the gate electrode, separated by an insulating region, therefore, It can also be called the burlap region (Lov region). The second region is the gate's electric field. It functions as a buffer region where no boundary is applied, or where the boundary is less likely to be applied than in the first region. A transistor according to one aspect of the invention comprises a first region which is a channel formation region in a semiconductor layer and ...having a second region between it and a third region that functions as a source region or drain region. By having a second region, the source-drain breakdown voltage of the transistor is improved. This allows for the creation of highly reliable transistors, even when driven at high voltages.

[0043] Below, we will explain more specific examples with reference to the diagrams.

[0044] <Configuration Example 1> Figure 1A is a top view of transistor 100, and Figure 1B shows the dashed line A1 shown in Figure 1A. -This corresponds to a cross-sectional view of the cross-section in A2, and Figure 1C is shown along the dashed line B1-B2 in Figure 1A. This corresponds to a cross-sectional view of the cut surface. Note that in Figure 1A, the components of transistor 100 are shown. Some of the elements (such as the gate insulating layer) are omitted in the diagram. Also, the dashed line A1-A2 direction The channel length direction corresponds to the channel width direction, and the dashed line B1-B2 direction corresponds to the channel width direction. Also, transition Regarding the top view of the sta, some of the components will be omitted in subsequent drawings, similar to Figure 1A. This shall be illustrated in the diagram.

[0045] The transistor 100 is provided on the substrate 102 and has an insulating layer 103, a semiconductor layer 108, and an insulating layer 103. It has an edge layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 118, etc. Island-shaped semiconductor The body layer 108 is provided on the insulating layer 103. The insulating layer 110 is on the upper surface, half of the insulating layer 103. The metal oxide layer 114 and conductive layer 112 are provided in contact with the upper and side surfaces of the conductive layer 108. These are arranged in this order on the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108. The insulating layer 118 covers the upper surface of the insulating layer 110, and the upper and side surfaces of the conductive layer 112. It is provided. Figure 2A shows an enlarged view of the region P enclosed by the dashed line in Figure 1B.

[0046] As shown in Figure 2A, transistor 100 is adjacent to the metal oxide layer 114 and insulating region 1 It has 50. The insulating region 150 is located between the insulating layer 110 and the conductive layer 112.

[0047] A conductive material can be used as the metal oxide layer 114. Conductive layer 112 and metal acid A portion of the oxide layer 114 functions as a gate electrode. The insulating layer 110 and insulating region 150 A portion of it functions as a gate insulating layer. Transistor 100 has a gate on semiconductor layer 108. This is a so-called top-gate type transistor, which has a top electrode.

[0048] The edges of the metal oxide layer 114 are located further inward on the insulating layer 110 than the edges of the conductive layer 112. It is located on the side. In other words, the conductive layer 112 is on the insulating layer 110, the metal oxide layer It has a portion that protrudes outward from the end of 114.

[0049] The semiconductor layer 108 contains a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor properties. It is composed of [something]. The semiconductor layer 108 preferably contains at least indium and oxygen. The semiconductor layer 108 contains indium oxide, which increases carrier mobility. For example, a transistor that can conduct a larger current than amorphous silicon can be created. This can be achieved. Furthermore, the semiconductor layer 108 may also contain zinc in addition to these. The semiconductor layer 108 may contain gallium.

[0050] Typical semiconductor layers 108 include indium oxide and indium zinc oxide (In- Zn oxide, indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO) You can also use terms such as (to be written as). In addition, indium tin oxide (In-Sn oxide) can be used. ), or indium tin oxide containing silicon can also be used. Details of the materials that can be used for layer 108 will be described later.

[0051] Here, the composition of the semiconductor layer 108 greatly affects the electrical characteristics and reliability of the transistor 100. It has a significant impact. For example, by increasing the indium content in semiconductor layer 108, the carrier This improves mobility and enables the realization of transistors with high field-effect mobility.

[0052] The semiconductor layer 108 consists of region 108C, a pair of regions 108L flanking region 108C, and It has a pair of regions 108N on the outside.

[0053] Region 108C overlaps with the conductive layer 112 and the metal oxide layer 114, and is a channel-forming region. It functions in this way.

[0054] Region 108L overlaps with the conductive layer 112 and the insulating region 150. Also, region 108L is It can also be said that it overlaps with the conductive layer 112, but does not overlap with the metal oxide layer 114. Region 108 L is the region where a channel can be formed when a gate voltage is applied to the conductive layer 112. However, since region 108L is superimposed on the conductive layer 112 via the insulating region 150, The electric field applied to region 10⁸L is weaker than the electric field applied to region 10⁸C. As a result, region 108L becomes a region with higher resistance than region 108C, thus mitigating the drain electric field. It functions as a buffer region for that purpose. Furthermore, for example, if the carrier concentration in region 108L is polar Even when the temperature is low and similar to that of region 108C, the electric field of the conductive layer 112 causes the temperature to rise. A channel can be formed.

[0055] Thus, there is a channel-forming region 108C and a source region or drain region. By providing region 108L between region 108N and region 108N, a high drain withstand pressure is achieved. This allows for the creation of highly reliable transistors that also possess high on-current capabilities.

[0056] Region 108N does not overlap with either the conductive layer 112 or the metal oxide layer 114, source It functions as a region or drain region.

[0057] In Figure 2A, the width of the conductive layer 112 in the channel length direction of transistor 100 is, The width of regions 108C and 108L is indicated by L1. Also, the width of transistor 100 The width of the insulating region in the channel length direction, i.e., the width of region 108L, is indicated by L2.

[0058] The low-resistance region 108N is a region with a higher carrier concentration than region 108C, and the source It functions as a region and a drain region. Region 108N has lower resistance than region 108C. Regions with high carrier concentrations, regions with high oxygen deficiencies, regions with high hydrogen concentrations, or This can also be described as a region with a high concentration of impurities.

[0059] The electrical resistance in region 10⁸N should be as low as possible. For example, the sheet resistance in region 10⁸N should be... 1Ω / □ or more 1×10 3 Less than Ω / □, preferably 1Ω / □ or more, 8×10 2 Ω / □ or less It is preferable to do so. Also, the electrical state of region 108C when no channel is formed. A higher resistance is preferable; for example, the sheet resistance of region 108C is 1 × 10⁻⁶. 9 Ω / □ or more, Preferably 5 × 10 9 Ω / □ or greater, comfortable 1 × 10 10 The condition is Ω / □ or greater. preferable.

[0060] Region 108L is a region with similar or lower resistance compared to region 108C, and has a higher carrier concentration. Regions with similar or higher degrees, regions with similar or higher oxygen defect densities, and regions with similar impurity concentrations. Alternatively, it could be described as a high-level area.

[0061] Region 108L is a region with similar or higher resistance compared to region 108N, and has a higher carrier concentration. Regions with similar or lower degrees, regions with similar or lower oxygen defect densities, and regions with similar impurity concentrations. Alternatively, it could be called a low-level area.

[0062] The sheet resistance of region 108L is 1×10 3 Ω / sq or more and 1×10 9 Ω / sq or less, preferably , more preferably 1×10 3 Ω / sq or more and 1×10 8 Ω / sq or less, and even more preferably 1×10 3 Ω / sq or more and 1×10 7 Ω / sq or less. By setting the resistance within the above range, a transistor with good electrical characteristics and high reliability can be obtained. Note that the sheet resistance can be calculated from the resistance value. By providing such a region 108L between region 108N and region 108C, the source-drain breakdown voltage of transistor 100 can be increased.

[0063] Note that the carrier concentration in region 108L does not have to be uniform, and there may be a gradient in which the carrier concentration decreases from the region 108N side to the region 108C side. For example, either one or both of the hydrogen concentration or the oxygen vacancy concentration in region 108L may have a gradient in which the concentration decreases from the region 108N side to the region 108C side.

[0064] As will be described later, since region 108L can be formed self-alignedly, a photomask for forming region 1 08L is not required, and the manufacturing cost can be reduced. Also, by forming region 108L self-alignedly, there is no relative positional shift between region 108L and conductive layer 112, so the width of region 108L in semiconductor layer 108 can be made to substantially coincide.

[0065] Between region 108C and region 108N in semiconductor layer 108, no gate electric field is applied, ​​Alternatively, region 108L can function as an offset region that is less likely to be affected than region 108C. It can be formed stably and without wobbling. As a result, the source-drain breakdown voltage of the transistor is improved. This allows for the creation of highly reliable transistors.

[0066] The width L2 of region 108L is preferably 5 nm or more and 2 μm or less, and more preferably 10 nm or more. A size of μm or less is preferred, and more preferably 15 nm to 500 nm. Region 108L is provided. This reduces the concentration of the electric field near the drain, especially when the drain voltage is high. This can suppress transistor degradation in certain conditions. In particular, by increasing the width L2 of region 108L By doing so, the concentration of the electric field near the drain can be effectively suppressed. On the other hand, width L If the length of 2 is longer than 500nm, the source-drain resistance increases, and the transistor's drive speed increases. It may be slower. By setting the width L2 to the aforementioned range, reliability is high and the drive speed This can be used to create fast transistors and semiconductor devices. Note that the width L2 of region 108L is half Thickness of conductor layer 108, thickness of insulating layer 110, source when driving transistor 100 - This can be determined according to the magnitude of the voltage applied between the drains.

[0067] By providing region 108L between region 108C and region 108N, region 108C and The current density at the boundary of region 10⁸N can be reduced, and at the boundary between the channel and the source or drain... This suppresses heat generation, resulting in highly reliable transistors and semiconductor devices.

[0068] The transistor 100 may have an insulating region 150 that includes a gap 130. Alternatively, the insulating region Region 150 may include one or more of the air gap 130 and the insulating layer 118. Figure 2A shows the insulating layer This example shows a case where the edge region 150 includes a void 130 and does not include the insulating layer 118. Figure 2A shows an example in which the insulating layer 118 is provided without contacting the side surface of the metal oxide layer 114. Figure 2B shows an example in which the insulating region 150 includes the void 130 and the insulating layer 118. Furthermore, Figure 2B shows that the insulating layer 118 is provided in contact with a part of the side surface of the metal oxide layer 114. An example is shown. Figure 3A shows an insulating region 150 that includes an insulating layer 118 and a gap 130. This shows an example where this does not happen. Also, Figure 3A shows an example where the insulating layer 118 is in contact with the side surface of the metal oxide layer 114. This shows an example of something that can be installed by touch.

[0069] Furthermore, as shown in Figure 2A, the insulating region 150 includes the void 130 and also includes the insulating layer 118. If not present, the insulating region 150 contains air, and the relative permittivity εr of the insulating region 150 is the same as that of air. It is approximately 1. In contrast, for example, silica oxide can be used as the insulating layer 110. The relative permittivity εr of n is approximately 4.0 to 4.5, while the relative permittivity εr of silicon nitride is approximately 7.0. Yes, the relative permittivity εr of the insulating layer 110 is greater than 1. Also, as shown in Figure 2B, the insulating region If 150 includes a void 130 and an insulating layer 118, the void 130 and insulating layer 1 in cross-section The relative permittivity εr of the insulating region 150 can be calculated from the area ratio of 18, and the relative permittivity of the insulating region 150 εr becomes greater than 1. Therefore, if the insulating region 150 includes the gap 130, the insulating region The relative permittivity of region 150 and the insulating layer 110 are different.

[0070] In this specification, "different relative permittivity" means that of the two relative permittivitys, the one with the smaller relative permittivity is... The ratio of the relative permittivity of one material to the relative permittivity of the other material, where the relative permittivity is larger, is 2.0 or greater. This refers to the matter.

[0071] As shown in Figures 1A and 1B, the transistor 100 has a conductive layer 12 on an insulating layer 118. It may have conductive layer 0a and conductive layer 120b. Conductive layer 120a and conductive layer 120b are It functions as a drain electrode or a drain electrode. Conductive layers 120a and 120b are The openings 141a or 141 provided in the insulating layer 118 and the insulating layer 110 respectively It is electrically connected to region 108N via b.

[0072] If a conductive film containing a metal or alloy is used as the conductive layer 112, electrical resistance can be suppressed. Therefore, it is preferable. Furthermore, an oxide conductive film may be used for the conductive layer 112.

[0073] The metal oxide layer 114 has the function of supplying oxygen to the insulating layer 110. The metal oxide layer 114 located between 110 and the conductive layer 112 is included in the insulating layer 110. It functions as a barrier film that prevents oxygen from diffusing to the conductive layer 112. Furthermore, it contains metal oxides. Layer 114 prevents hydrogen and water contained in the conductive layer 112 from diffusing to the insulating layer 110. It also functions as a rear film. The metal oxide layer 114 is, for example, at least more so than the insulating layer 110. It is preferable to use a material that is impermeable to oxygen and hydrogen.

[0074] The metal oxide layer 114 makes it easier for the conductive layer 112 to attract oxygen such as aluminum and copper. Even when using a metallic material, oxygen will diffuse from the insulating layer 110 to the conductive layer 112. This can prevent the conductive layer 112 from containing hydrogen. This prevents hydrogen from diffusing from the insulating layer 110 to the semiconductor layer 108. As a result, the carrier density in the channel formation region of the semiconductor layer 108 is made extremely low. It is possible.

[0075] A metal oxide can be used as the metal oxide layer 114. For example, indioxide Indium zinc oxide, indium tin oxide (ITO), silicon-containing Indium-containing oxides such as tincture tin oxide (ITSO) can be used. Conductive oxides containing cinnabar are preferred due to their high conductivity. Also, ITSO is silicon Because it contains [a specific compound], it is less likely to crystallize and has high flatness, and therefore it forms on ITSO. Adhesion to the film is improved. Furthermore, the metal oxide layer 114 contains zinc oxide and gallium. Metal oxides such as zinc oxide can be used as the metal oxide layer 114. A layered structure may also be used.

[0076] As the metal oxide layer 114, an oxide material containing one or more of the same elements as the semiconductor layer 108 is used. It is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. Preferably, the metal oxide layer 114 is made using the same sputtering process as the semiconductor layer 108. By applying a metal oxide film formed using a ring target, the equipment can be standardized. This is preferable because it allows for this.

[0077] The metal oxide layer 114 is preferably formed using a sputtering apparatus. When forming an oxide film using a sputtering apparatus, the film is formed in an atmosphere containing oxygen gas. This allows for the appropriate addition of oxygen to the insulating layer 110 and the semiconductor layer 108.

[0078] Region 108N of the semiconductor layer 108 is a region containing impurity elements. For example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and Examples of noble gases include helium, neon, argon, and chlorite. Examples include lipton and xenon. In particular, it is preferable that it contains boron or phosphorus. These impurity elements may contain two or more of each other.

[0079] As will be described later, the process of adding impurities to region 108N is performed using the conductive layer 112 as a mask. This can be done via the insulating layer 110.

[0080] In region 10⁸N, the impurity concentration is 1 × 10⁻⁶. 19 atoms / cm 3 The above is 1 x 10 23 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The above 5 x 10 2 2 atoms / cm 3 More preferably 1 × 10 20 atoms / cm 3 The above is 1× 10 22 atoms / cm 3 Preferably, the region includes the following:

[0081] The concentration of impurities in region 10⁸N can be determined, for example, by secondary ion mass spectrometry (SIMS:S (Econdatory Ion Mass Spectrometry) and X-ray photoelectron spectroscopy (XPS:X-ray Photoelectron Spectroscopy) etc. This can be analyzed using the following analytical methods. When using XPS analysis, the front or back side can be analyzed. By combining ion sputtering from the side with XPS analysis, the concentration distribution in the depth direction can be determined. You can learn about it.

[0082] In region 10⁸N, it is preferable that impurity elements exist in an oxidized state. Example For example, impurity elements such as boron, phosphorus, magnesium, aluminum, and silicon are oxidized. It is preferable to use elements that are easily oxidized. Such easily oxidized elements are found in semiconductor layer 108. Because it can exist stably in an oxidized state by combining with oxygen inside, it can withstand high temperatures in subsequent processes (for example) Even when subjected to temperatures above 400°C, 600°C, or 800°C, it will not detach. This is suppressed. Also, impurity elements remove oxygen from semiconductor layer 108, thus reducing region 1 Many oxygen vacancies are generated in O8N. These oxygen vacancies combine with hydrogen in the membrane. Because it acts as a carrier source, region 108N becomes extremely low-resistance.

[0083] For example, if boron is used as an impurity element, the boron contained in region 10⁸N is oxygen It can exist in a bound state. This is due to the B2O3 binding in XPS analysis. This can be confirmed by observing a spectral peak. In addition, in XPS analysis, boron Spectral peaks resulting from the element existing in its elemental form are not observed, or the detection limit is reached. The peak intensity is extremely low, to the point where it is buried in the background noise observed nearby. It will get worse.

[0084] Furthermore, due to the effects of heat during the manufacturing process, the above impurities contained in region 108N may be affected. Some of the elements may diffuse into regions 108L and 108C. The concentrations of impurity elements in region 10⁸C are 10 times the concentrations of impurity elements in region 10⁸N. It is preferable that it be 1 / 100 or less, and more preferably 1 / 100 or less.

[0085] The insulating layer 103 and insulating layer 110 that are in contact with the channel formation region of the semiconductor layer 108 contain oxide It is preferable to use a film. For example, a silicon oxide film, a silicon oxide nitride film, or aluminum oxide. Oxide films such as nium films can be used. This allows for the fabrication of transistor 100. During the process, oxygen detached from the insulating layer 103 and insulating layer 110 is removed from the semiconductor layer 1 It can be supplied to the channel formation region of 08, reducing oxygen vacancies in the semiconductor layer 108.

[0086] In this specification, an oxidized nitride is defined as a compound in which the oxygen content is greater than the nitrogen content. It refers to substances that are abundant in oxygen, and oxidized nitrides are included in oxides. Nitrided oxides are substances whose composition is such that oxygen is abundant in them. It refers to substances with a high nitrogen content, and nitride oxides are included in nitrides.

[0087] The insulating layer 110 in contact with the semiconductor layer 108 contains an excess of oxygen compared to its stoichiometric composition. It is more preferable that the region has an area. In other words, the insulating layer 110 releases oxygen. It has a possible insulating film. For example, the insulating layer 110 is formed in an oxygen atmosphere, and after film formation... The insulating layer 110 may be subjected to heat treatment, plasma treatment, etc., in an oxygen atmosphere, or By forming an oxide film on the insulating layer 110 under an oxygen atmosphere, etc., the insulating layer 110 contains It can also supply oxygen.

[0088] For example, the insulating layer 110 is made by sputtering, chemical vapor deposition (CVD). (Vapor Deposition) method, vacuum deposition method, pulsed laser deposition (PLD) :Pulsed Laser Deposition) method, atomic layer deposition (ALD: Ato It can be formed using methods such as the mic Layer Deposition method. As for CVD methods, there is Plasma Chemical Vapor Deposition (PECVD). Examples include the ED CVD method and the thermal CVD method.

[0089] In particular, the insulating layer 110 is preferably formed by plasma CVD.

[0090] Since the insulating layer 110 is formed on the semiconductor layer 108, it is important to avoid damaging the semiconductor layer 108 as much as possible. It is preferable that the film is deposited under conditions that do not cause damage. For example, the deposition rate (deposition rate) The film can be formed under conditions where the (also called) pressure is sufficiently low.

[0091] The deposition gas used for forming silicon oxide nitride films includes, for example, silanes and disilanes. Depositing gases containing condensate, and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. , can be used as a raw material gas. In addition to the raw material gas, argon and helium, It may contain diluent gases such as nitrogen.

[0092] The insulating layer 110 is in contact with the region 108C of the semiconductor layer 108, i.e., the conductive layer 112 and has a region that overlaps with the metal oxide layer 114. In addition, the insulating layer 110 has a semiconductor layer 10 It has a region that is in contact with region 8 108L and does not overlap with the metal oxide layer 114. The margin layer 110 is in contact with region 108N of the semiconductor layer 108 and does not overlap with the conductive layer 112. It has a region.

[0093] The region 110i of the insulating layer 110 that overlaps with region 108N contains the aforementioned impurity elements. In some cases, this occurs. At this time, similar to region 108N, the impurity elements in the insulating layer 110 become acidic. It is preferable that such easily oxidized elements exist in a bonded state with the element. Because it can exist stably in an oxidized state by combining with oxygen in 10, high temperatures are applied in subsequent processes. Even if this occurs, desorption is suppressed. In particular, desorption into the insulating layer 110 due to heating is suppressed. If excess oxygen (also called excess oxygen) is present, the excess oxygen will combine with the impurity element. To stabilize the region, the supply of oxygen from the insulating layer 110 to region 108N is suppressed. It is possible. In addition, a portion of the insulating layer 110 containing impurity elements in an oxidized state is oxygen Because it becomes difficult for the substance to diffuse, it enters from above the insulating layer 110 through the insulating layer 110. The supply of oxygen to region 108N is suppressed, and the resistance of region 108N increases. It can be suppressed.

[0094] As shown in Figures 1B and 1C, the insulating layer 103 has an interface or so that it is in contact with the insulating layer 110. In the vicinity of , there is a region 103i containing the aforementioned impurity elements. Also, as shown in Figure 2A Furthermore, region 103i may also be provided at or near the interface with region 108N. Good. At this time, the impurity concentration in the part overlapping with region 108N is the same as the part in contact with the insulating layer 110. The concentration will be lower than that.

[0095] The insulating layer 110 and the insulating layer 103 may each have a laminated structure. Figure 3B shows an example in which the insulating layer 103 each has a laminated structure. The insulating layer 110 is a semiconductor The insulating layer 110a, insulating layer 110b, and insulating layer 110c are stacked from the body layer 108 side. It has a layered structure. The insulating layer 103 is made up of insulating layer 103a and insulating layer 10 from the substrate 102 side. It has a laminated structure in which 3b, insulating layer 103c, and insulating layer 103d are laminated. In 3B, for clarity, regions 110i and 103i are omitted from the diagram.

[0096] An example of an insulating layer 110 having a laminated structure will be described.

[0097] The insulating layer 110a has a region that is in contact with the semiconductor layer 108. The insulating layer 110c is made of a metallic acid It has a region in contact with the oxide layer 114. The insulating layer 110b has an insulating layer 110a and an insulating layer 110 It is located between c.

[0098] Insulating layer 110a, insulating layer 110b, and insulating layer 110c each contain an oxide insulating It is preferable that it be a film. In this case, insulating layer 110a, insulating layer 110b and insulating layer 110 It is preferable that each of c is deposited continuously using the same deposition apparatus.

[0099] For example, the insulating layer 110a, insulating layer 110b, and insulating layer 110c are made of silicone oxide. silicon oxide film, silicon nitride film, silicon nitride film, aluminum oxide film, hafnium oxide Film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, oxide Contains one or more magnesium films, lanthanum oxide films, cerium oxide films, and neodymium oxide films. An insulating layer can be used.

[0100] The insulating layer 110 in contact with the semiconductor layer 108 preferably has a laminated structure of oxide insulating films. Furthermore, it is more preferable to have a region containing an excess of oxygen compared to the stoichiometric composition. In other words, the insulating layer 110 has an insulating film that is capable of releasing oxygen. For example, oxygen Forming the insulating layer 110 under an atmosphere, and then applying an oxygen atmosphere to the insulating layer 110 after film formation. Performing heat treatment, plasma treatment, etc., on the insulating layer 110 in an oxygen atmosphere Oxygen can also be supplied into the insulating layer 110 by forming a physical film.

[0101] For example, insulating layer 110a, insulating layer 110b and insulating layer 110c are formed by sputtering. Chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition It can be formed using methods such as the (ALD) method. Furthermore, CVD methods include plasma chemistry. Examples include vapor deposition (PECVD) and thermal CVD.

[0102] In particular, insulating layers 110a, 110b, and 110c are formed by plasma CVD. It is preferable to form it in this way.

[0103] Since the insulating layer 110a is formed on the semiconductor layer 108, it is important to keep it as close to the semiconductor layer 108 as possible. It is preferable that the film is deposited under conditions that do not cause damage. For example, the deposition rate (film deposition The film can be deposited under conditions where the rate (also called the film rate) is sufficiently low.

[0104] For example, a silicon oxidizride film is formed as the insulating layer 110a by plasma CVD. In this case, forming it under low power conditions minimizes damage to the semiconductor layer 108. It can be made smaller. Transistor 100 in one aspect of the present invention has a semiconductor layer 108 on A film deposition method that reduces damage to the semiconductor layer 108 as an insulating layer 110a in contact with the surface. A film formed by this method is used. Therefore, at the interface between the semiconductor layer 108 and the insulating layer 110 The defect level density is reduced, resulting in a transistor 100 with high reliability. ru.

[0105] The deposition gas used for forming silicon oxide nitride films includes, for example, silanes and disilanes. Depositing gases containing condensate, and oxidizing gases such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. , can be used as a raw material gas. In addition to the raw material gas, argon and helium, It may contain diluent gases such as nitrogen.

[0106] For example, the ratio of the flow rate of the deposition gas to the total flow rate of the film-forming gas (hereinafter also simply referred to as the flow rate ratio) By reducing (u), the deposition rate can be lowered, resulting in the deposition of a dense film with fewer defects. can.

[0107] The insulating layer 110b is a film that was deposited under conditions with a higher deposition rate than the insulating layer 110a. This is preferable. This can improve productivity.

[0108] For example, the insulating layer 110b is subjected to conditions where the flow rate ratio of the depositing gas is increased compared to the insulating layer 110a. This allows for film deposition under conditions that increase the deposition rate.

[0109] The insulating layer 110c has reduced surface defects and absorbs impurities contained in the atmosphere, such as water. It is preferable that the film be extremely dense and difficult to adhere to. For example, similar to the insulating layer 110a, The film can be deposited under conditions where the deposition rate is sufficiently low.

[0110] Since the insulating layer 110c is formed on the insulating layer 110b, it is different from the insulating layer 110a. The effect on the semiconductor layer 108 during the deposition of 110c is small. Therefore, the insulating layer 110c The film can be formed under higher power conditions than those for the insulating layer 110a. The flow rate ratio of the depositing gas is By reducing the power and depositing the film at a relatively high power level, a dense film with reduced surface defects can be created. It is possible.

[0111] In other words, from the layer with the highest deposition rate, they are insulating layer 110b, insulating layer 110a, and insulating layer 110c. A laminated film formed under conditions such that the order is as described above can be used as the insulating layer 110. The insulating layer 110 consists of insulating layer 110b, insulating layer 110a, and insulating layer 110c, in that order, wet It offers a higher etching rate under the same conditions as etching or dry etching.

[0112] It is preferable that the insulating layer 110b be formed to be thicker than the insulating layers 110a and 110c. It is difficult. By forming a thicker insulating layer 110b, which has the fastest film deposition rate, the film deposition process of the insulating layer 110 is improved. The time required for the process can be reduced.

[0113] Here, the boundary between insulating layer 110a and insulating layer 110b, and the boundary between insulating layer 110b and insulating layer 110 Because the boundaries of c can be unclear, these boundaries are clearly indicated with dashed lines in Figure 3B. Furthermore, since insulating layer 110a and insulating layer 110b have different film densities, the insulating layer 110 will break down. Transmission electron microscopy (TEM) in a plane These boundaries are observed as differences in contrast in images such as microscopy. In some cases, this may be possible. Similarly, the boundary between insulating layer 110b and insulating layer 110c can also be observed. It may be possible in some cases.

[0114] An example of an insulating layer 103 having a laminated structure will be described.

[0115] The insulating layer 103 consists of insulating layer 103a, insulating layer 103b, and insulating layer 103 from the substrate 102 side. It has a laminated structure in which c and an insulating layer 103d are laminated. The insulating layer 103a is connected to the substrate 102 They are in contact. Also, the insulating layer 103d is in contact with the semiconductor layer 108.

[0116] The insulating layer 103, which functions as a second gate insulating layer, has high breakdown voltage and low film stress. being difficult to release hydrogen and water, having few defects in the film, inhibiting the diffusion of impurities contained in the substrate 102, among which, it is preferable to satisfy one or more of them, and most preferably to satisfy all of them. Among them, it is preferable to satisfy one or more of the following: being difficult to release hydrogen and water, having few defects in the film, and inhibiting the diffusion of impurities contained in the substrate 102, and most preferably to satisfy all of them. It is most preferable to satisfy all of them.

[0117] Among the four insulating films of the insulating layer 103, it is preferable to use an insulating film containing nitrogen for the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c located on the substrate 102 side. On the other hand, for the insulating layer 103d in contact with the semiconductor layer 108, it is preferable to use an insulating film containing oxygen. Moreover, for the four insulating films of the insulating layer 103, it is preferable to continuously form films without exposure to the atmosphere using a plasma CVD apparatus. It is preferable to continuously form films without exposure to the atmosphere using a plasma CVD apparatus.

[0118] As the insulating layer 103a, the insulating layer 103b, and the insulating layer 103c, for example, insulating films containing nitrogen such as silicon nitride films, silicon oxynitride films, aluminum nitride films, hafnium nitride films, etc. can be used. Also, as the insulating layer 103c, the insulating film that can be used for the insulating layer 110 can be adopted. Also, as the insulating layer 103c, the insulating film that can be used for the insulating layer 110 can be adopted. The insulating layer 103a and the insulating layer 103c are preferably dense films that can prevent the diffusion of impurities from below. The insulating layer 103a can block the impurities contained in the substrate 102,

[0119] and the insulating layer 103c is preferably a film that can block hydrogen and water contained in the insulating layer 103b respectively. Therefore, for the insulating layer 103a and the insulating layer 103c, an insulating film formed under conditions with a lower film formation rate than that of the insulating layer 103b can be applied. The insulating layer 103a can block the impurities contained in the substrate 102, and the insulating layer 103c is preferably a film that can block hydrogen and water contained in the insulating layer 103b respectively. Therefore, for the insulating layer 103a and the insulating layer 103c, an insulating film formed under conditions with a lower film formation rate than that of the insulating layer 103b can be applied. Therefore, for the insulating layer 103a and the insulating layer 103c, an insulating film formed under conditions with a lower film formation rate than that of the insulating layer 103b can be applied.

[0120] On the other hand, the insulating layer 103b uses an insulating film formed under conditions with low stress and high film formation rate. It is preferable that the insulating layer 103b is more insulating than insulating layer 103a and insulating layer 103c. It is preferable that it is formed to be thick.

[0121] For example, plasma Even when using a silicon nitride film deposited by the CVD method, the insulating layer 103b is the other 2 The film density is lower than that of the insulating film. Therefore, the permeability in the cross-section of the insulating layer 103 is lower. In hypermorphic electron microscope images, this can sometimes be observed as a difference in contrast. Yes. Note that the boundary between insulating layer 103a and insulating layer 103b, and the boundary between insulating layer 103b and insulating layer 10 Because the boundaries of 3c may be unclear, these boundaries are indicated with dashed lines in Figure 3B. Yes, they are.

[0122] The insulating layer 103d, which is in contact with the semiconductor layer 108, is less prone to adsorption of impurities such as water onto its surface. It is preferable to have a dense insulating film. Furthermore, it should have as few defects as possible, and should contain water and hydrogen. It is preferable to use an insulating film with reduced impurities. For example, as the insulating layer 103d, An insulating film similar to the insulating layer 110c of the insulating layer 110 can be used.

[0123] The insulating layer 103 having such a layered structure provides an extremely reliable transistor. It can be achieved.

[0124] The insulating layer 118 functions as a protective layer to protect the transistor 100. Insulating layer 110 For example, inorganic insulating materials such as oxides or nitrides can be used. More specifically Typical examples include silicon oxide, silicon oxide nitride, silicon nitride, silicon oxide nitride, Aluminum oxide, aluminum oxide nitride, aluminum nitride, hafnium oxide, hafnium Inorganic insulating materials such as aluminum aluminate can be used.

[0125] It is preferable to use a material with high step coverage for the insulating layer 118. Alternatively, insulating layer 11 8 is preferably formed using a film formation method that provides high step coverage. Formation of insulating layer 118 For example, the PECVD method can be suitably used. Due to the step difference with 110, the coverage of the insulating layer 118 provided on top of the layer is reduced, and the insulating layer 1 Steps or low-density regions (also called porosity) may form in 18 layers of the insulating layer 118. When cracks or low-density regions (also called porosity) are formed, impurities such as water and hydrogen can invade from the outside. This could lead to a decrease in the reliability of the transistor. Highly insulating layer 11 By using 8, a highly reliable transistor can be created.

[0126] When forming the conductive layer 112 and the metal oxide layer 114, the film thickness of a portion of the insulating layer 110 becomes thin. In some cases, the thickness of the insulating layer 110 in the region that does not overlap with the metal oxide layer 114 may be reduced. Figure 4A shows an example where the thickness of the insulating layer 110 in the region overlapping with the oxide layer 114 is thinner than the thickness of the insulating layer 110. The thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112 is greater than the thickness of the insulating layer 110 in the region that overlaps with the conductive layer 112. An example where the thickness is thinner than the edge layer 110 is shown in Figure 4B. Note that, as shown in Figure 3B, the insulating layer 1 If 10 is a laminated structure, the insulating layer 110c is in a region that does not overlap with the metal oxide layer 114. It is preferable that it remains. By configuring it so that the insulating layer 110c remains in the non-overlapping regions, This effectively suppresses the adsorption of water onto the insulating layer 110. The thickness of the insulating layer 110c is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, more preferably 3 nm or more and 30 nm or less.

[0127] <Configuration Example 2> FIG. 5A is a top view of the transistor 100A, and FIG. 5B is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 5C is a cross-sectional view of the transistor 100A in the channel width direction. It is.

[0128] The transistor 100A mainly differs from Configuration Example 1 in that it has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the semiconductor layer 108 and the conductive layer 112. It has.

[0129] In the transistor 100A, the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode), and the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode). Also, a part of the insulating layer 110 functions as a second gate insulating layer, and a part of the insulating layer 103 functions as a first gate insulating layer.

[0130]

[0131] A portion of the semiconductor layer 108 that overlaps at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. For ease of explanation below, a portion of the semiconductor layer 108 that overlaps with the conductive layer 112 may be referred to as the channel formation region, but actually, a channel can also be formed in a portion (including the region 108N) that overlaps with the conductive layer 106 without overlapping with the conductive layer 112.

[0132] As shown in FIG. 5C, the conductive layer 106 includes a metal oxide layer 114, an insulating layer 110, and an insulating Even though it is electrically connected to the conductive layer 112 through the opening 142 provided in layer 103 Good. This allows the conductive layer 106 and the conductive layer 112 to be given the same potential.

[0132] The conductive layer 106 is made of the same material as conductive layer 112, conductive layer 120a, or conductive layer 120b. This can be used. In particular, if a material containing copper is used for the conductive layer 106, the wiring resistance can be reduced. It is preferable for this reason.

[0133] As shown in Figures 5A and 5C, in the channel width direction, conductive layer 112 and conductive layer 1 It is preferable that 06 protrudes outward beyond the edge of the semiconductor layer 108. In this case, Figure As shown in 5C, the entire channel width direction of the semiconductor layer 108 is connected to the insulating layer 110 and the insulating layer 1 The structure is covered by conductive layer 112 and conductive layer 106 via 03.

[0134] With this configuration, the semiconductor layer 108 is protected from the electric field generated by the pair of gate electrodes. And it can be electrically surrounded. In particular, the conductive layer 106 and the conductive layer 112 are the same It is preferable to apply an electric potential. This induces a channel in the semiconductor layer 108. Because the electric field can be effectively applied, the on-current of the 100A transistor can be increased. Yes, it is possible. Therefore, it becomes possible to miniaturize the 100A transistor.

[0135] Furthermore, the conductive layer 112 and the conductive layer 106 may not be connected. In this case, one pair A constant potential is applied to one of the gate electrodes, and a signal to drive transistor 100A is applied to the other. This may be applied. In this case, the potential applied to one gate electrode will affect transistor 100. The threshold voltage when driving A with the other gate electrode can also be controlled.

[0136] The insulating layer 103 preferably has a laminated structure. For example, the insulating layer 103 may have a conductive layer From the 106 side, insulating layer 103a, insulating layer 103b, insulating layer 103c, and insulating layer 103d A laminated structure can be formed by stacking these (see Figure 3B). Insulating layer in contact with conductive layer 106 Preferably, 103a is a film that can block the metal elements contained in the conductive layer 106. Regarding insulating layers 103a, 103b, 103c, and 103d, see the previous Since the above information can be found, a detailed explanation will be omitted.

[0137] Furthermore, a metal film or alloy film that does not easily diffuse into the insulating layer 103 is used as the conductive layer 106. In some cases, the insulating layer 103a is omitted, and the insulating layer 103b, insulating layer 103c, and insulating layer 103a are omitted. A configuration in which three insulating films of layer 103d are stacked may also be used.

[0138] The insulating layer 103 having such a layered structure provides an extremely reliable transistor. It can be achieved.

[0139] <Configuration Example 3> Figure 6A is a cross-sectional view of transistor 100B in the channel length direction, and Figure 6B is a cross-sectional view of transistor 100B This is a cross-sectional view of transistor 100B in the channel width direction. Figure 5A shows a top view of transistor 100B. Since it can be referenced, the description is omitted.

[0140] Compared to transistor 100A exemplified in Configuration Example 2, transistor 100B has better isolation. The main difference is that it has an insulating layer 116 on top of layer 118.

[0141] The insulating layer 116 is provided covering the upper surface of the insulating layer 110. The insulating layer 116 is insulating It has the function of suppressing the diffusion of impurities from above layer 116 into semiconductor layer 108. Conductive layer 120a and conductive layer 120b are insulating layer 116, insulating layer 118 and insulating layer, respectively. Electricity is supplied to region 108N through the opening 141a or opening 141b provided in 110. It connects to the target.

[0142] Examples of insulating layer 116 include silicon nitride, silicon nitride oxide, and silicon oxide nitride. Preferably, an insulating film containing nitrides, such as aluminum nitride or aluminum oxide nitride, is used. This is possible. In particular, silicon nitride has blocking properties for hydrogen and oxygen, To prevent both the diffusion of hydrogen from the outside into the semiconductor layer and the desorption of oxygen from the semiconductor layer to the outside. This makes it possible to create highly reliable transistors.

[0143] When using metal nitrides as the insulating layer 116, aluminum, titanium, tantalum, and tan are used. It is preferable to use gusten, chromium, or ruthenium nitrides. In particular, aluminum It is particularly preferable to include aluminum or titanium. For example, aluminum is sputtered. It is used as a GET, and the shape is formed by a reaction sputtering method using a gas containing nitrogen as the film deposition gas. The resulting aluminum nitride film is formed by appropriately controlling the flow rate of nitrogen gas relative to the total flow rate of the deposition gas. This provides extremely high insulation properties and extremely high blocking properties against hydrogen and oxygen. A film containing such metal nitride can be formed. By providing it in contact with 108, the resistance of the semiconductor layer 108 is reduced, and the semiconductor layer 10 To effectively prevent oxygen from detaching from 8 and hydrogen from diffusing into the semiconductor layer 108. It is possible.

[0144] When aluminum nitride is used as the metal nitride, the insulating material containing the aluminum nitride It is preferable that the layer thickness be 5 nm or more. Even with such a thin film, hydrogen and acid It is possible to achieve both high blocking properties against the element and the function of lowering the resistance of the semiconductor layer. The thickness of the insulating layer can be any thickness, but considering productivity, 500 nm is recommended. The following is preferably 200 nm or less, and more preferably 50 nm or less.

[0145] When an aluminum nitride film is used for the insulating layer 116, the composition formula is AlN x (x is greater than 0) A film is used that satisfies the condition x is a real number less than or equal to 2, preferably a real number greater than 0.5 and less than or equal to 1.5. It is preferable to have this. This makes it possible to create a film with excellent insulating properties and excellent thermal conductivity. Therefore, it is possible to improve the heat dissipation of the heat generated when driving the transistor 100B. Cut.

[0146] As the insulating layer 116, an aluminum titanium nitride film, a titanium nitride film, etc. can be used. Cut.

[0147] By providing an insulating layer 116 on top of the insulating layer 118, the transistors with high on-current It can be made into a transistor capable of controlling the threshold voltage. It is possible to do this. Furthermore, it can be made into a highly reliable transistor.

[0148] <Configuration Example 4> Figure 7A is a cross-sectional view of transistor 100C in the channel length direction, and Figure 7B is a cross-sectional view of transistor 100C. This is a cross-sectional view of transistor 100C in the channel width direction. Figure 5A shows a top view of transistor 100C. Since it can be referenced, the description is omitted.

[0149] Compared to transistor 100A exemplified in Configuration Example 2, transistor 100C has better insulation. The main difference is that it has an insulating layer 116 between layer 118 and insulating layer 110.

[0150] The insulating layer 116 is provided so as to cover the upper surface of the insulating layer 118, as well as the upper and side surfaces of the conductive layer. Furthermore, the insulating layer 116 may be provided in contact with the side surface of the metal oxide layer 114. Furthermore, the insulating layer 116 may be provided in contact with a portion of the side surface of the metal oxide layer 114. The edge layer 116 suppresses the diffusion of impurities from above the insulating layer 116 into the semiconductor layer 108. It has the function of doing so.

[0151] By providing an insulating layer 116 between the insulating layer 118 and the insulating layer 110, ON-electric It can be made into a transistor with high current. Also, it can control the threshold voltage. It can be made into a transistor. Furthermore, it can be made into a highly reliable transistor. .

[0152] <Example of manufacturing method> The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. Let's explain using transistor 100A, which was illustrated in Configuration Example 2, as an example.

[0153] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are produced by sputtering. Methods include chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition. It can be formed using deposition (ALD) methods, etc. CVD methods include plasma chemical vapor deposition (CVD). These include phase deposition (PECVD) and thermal CVD. Furthermore, one type of thermal CVD involves organic One method is Metal Organic CVD (MOCVD).

[0154] Thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices are coated using spin coating, DIT coating, etc. Printing methods: spray coating, inkjet, dispensing, screen printing, offset printing. Doctor's knife coat, slit coat, roll coat, curtain coat, knife coat, etc. It can be formed by law.

[0155] When processing thin films that make up semiconductor devices, methods such as photolithography are used. It is possible to do this using other methods such as nanoimprint lithography, sandblasting, and lift-off lithography. The thin film may be processed by any method. Alternatively, a film deposition method using a shielding mask such as a metal mask may be used. This may be used to directly form island-like thin films.

[0156] There are two main methods of photolithography. One is to process the image... A resist mask is formed on a thin film, and the thin film is processed by etching or the like, and the resist This is a method for removing the mask. Another method is to deposit a photosensitive thin film and then expose it to light. This method involves developing the film and then processing it into a desired shape.

[0157] In photolithography, the light used for exposure is, for example, the i-line (wavelength 365 nm). Using g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof This can be done by using ultraviolet light, KrF laser light, or ArF laser light, etc. It is also possible to perform exposure using immersion lithography. Furthermore, the light used for exposure and Then, using extreme ultraviolet (EUV) light and X-rays... It is also possible to use an electron beam instead of light for exposure. Extreme ultraviolet Using light, X-rays, or electron beams is preferable because it allows for extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, the photomask is It is unnecessary.

[0158] Thin film etching methods include dry etching, wet etching, and sandblasting. Laws and other regulations can be used.

[0159] Figures 8A to 11C show the channel length at each stage of the manufacturing process of transistor 100A. Cross-sectional views in the direction and channel width are shown side by side.

[0160] [Formation of conductive layer 106] A conductive film is formed on the substrate 102, and this is processed by etching to form a gate electrode. A functional conductive layer 106 is formed (Figure 8A).

[0161] At this time, as shown in Figure 8A, the end of the conductive layer 106 is processed to have a tapered shape. It is preferable to do so. This improves the step coverage of the insulating layer 103 to be formed next. can.

[0162] By using a conductive film containing copper as the conductive film that forms the conductive layer 106, the wiring resistance can be reduced. It is possible to do so, for example, when applying it to large display devices or high-resolution display devices. In such cases, it is preferable to use a conductive film containing copper. Even when an electrolytic film is used, the insulating layer 103 causes copper to diffuse towards the semiconductor layer 108. Because this is suppressed, highly reliable transistors can be realized.

[0163] [Formation of insulating layer 103] Next, the substrate 102 and the conductive layer 106 are covered to form an insulating layer 103. 3 can be formed using methods such as PECVD, ALD, and sputtering.

[0164] Here, the insulating layer 103 consists of insulating layer 103a, insulating layer 103b, insulating layer 103c, And an insulating layer 103d is laminated to form it.

[0165] In particular, each insulating layer constituting the insulating layer 103 is preferably formed by the PECVD method. The method for forming the insulating layer 103 can be described by referring to the above example configuration 1.

[0166] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment can be performed in an oxygen atmosphere. Alternatively, oxygen can be supplied to the insulating layer 103 by plasma ion doping or ion implantation. That's fine.

[0167] [Formation of semiconductor layer 108] Next, a metal oxide film 108f is formed on the insulating layer 103 (Figure 8B).

[0168] The metal oxide film 108f is formed by a sputtering method using a metal oxide target. It is preferable to do so.

[0169] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f has impurities such as hydrogen and water reduced as much as possible, resulting in a high-purity film. It is preferable that the metal oxide film 108f is a crystalline metal oxide. It is preferable to use a membrane.

[0170] When forming the metal oxide film 108f, oxygen gas and an inert gas (for example, helium gas) are used. It may be mixed with (such as argon gas or xenon gas). Note that the metal oxide film 1 The proportion of oxygen gas in the total deposition gas when depositing 08f (hereinafter also referred to as the oxygen flow rate ratio) The higher the value, the higher the crystallinity of the metal oxide film 108f, and the more reliable the transistor. This can be achieved. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film 108f. This allows for the creation of a transistor with increased on-current.

[0171] When depositing the metal oxide film 108f, the higher the substrate temperature, the higher the crystallinity and density of the metal. It can be formed as an oxide film. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity. A high-quality metal oxide film can be formed.

[0172] The conditions for forming the metal oxide film 108f are to set the substrate temperature to room temperature or higher and 250°C or lower, preferably room temperature. The substrate temperature should be between 10°C and 200°C, more preferably between 140°C and 200°C. For example, it is preferable to keep the substrate temperature above room temperature but below 140°C, as this increases productivity. The metal oxide film 108f is deposited with the plate temperature at room temperature or without heating the substrate. This allows for a reduction in crystallinity.

[0173] Before forming the metal oxide film 108f, water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 103 are removed. Either a process to remove material, etc., or a process to supply oxygen into the insulating layer 103. It is preferable to perform the above. For example, in a reduced pressure atmosphere at a temperature of 70°C to 200°C Heat treatment can be performed. Alternatively, plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, plastics in an atmosphere containing oxidizing gases such as nitrous oxide (N2O) Oxygen may be supplied to the insulating layer 103 by Zuma treatment. Plasma containing nitrous oxide gas The treatment involves suitably removing organic matter from the surface of the insulating layer 103 while supplying oxygen. This can be done. After this process, the surface of the insulating layer 103 can be continuously treated without being exposed to the atmosphere. It is preferable to form a metal oxide film 108f.

[0174] Furthermore, if the semiconductor layer 108 is a stacked structure in which multiple semiconductor layers are stacked, After forming the metal oxide film, the surface is continuously exposed to the atmosphere and then the next It is preferable to form a metal oxide film.

[0175] Next, by etching a portion of the metal oxide film 108f, an island-shaped semiconductor layer 1 Forms O8 (Figure 8C).

[0176] The metal oxide film 108f can be processed using either a wet etching method or a dry etching method. Either one or both may be used. In this case, insulation that does not overlap with the semiconductor layer 108 is required. In some cases, a portion of layer 103 may be etched and become thinner. For example, of the insulating layer 103, In some cases, the insulating layer 103d may disappear due to etching, exposing the surface of the insulating layer 103c. .

[0177] Here, after the metal oxide film 108f is formed, or after the semiconductor layer 108 is processed, heating It is preferable to perform the treatment. By heat treatment, the metal oxide film 108f or semiconductor layer 10 It can remove hydrogen or water contained in or adsorbed on the surface of 8. Heat treatment improves the film quality of the metal oxide film 108f or semiconductor layer 108 (for example, defects (This may result in a reduction of defects, an improvement in crystallinity, etc.)

[0178] Heat treatment causes the metal oxide film 108f or the semiconductor layer 108 to be acid-based from the insulating layer 103. It is also possible to supply the raw material. In this case, heat treatment is performed before processing into semiconductor layer 108. That is preferable.

[0179] The heat treatment temperature is typically 150°C or higher but below the strain point of the substrate, or 200°C or higher but below 5°C. The temperature must be below 00°C, or between 250°C and 450°C, or between 300°C and 450°C. It is possible.

[0180] The heat treatment can be carried out in an atmosphere containing a noble gas or nitrogen. After heating with gas, it may be heated in an oxygen-containing atmosphere. Alternatively, it may be heated in a dry air atmosphere. It is also preferable that the atmosphere during the above heat treatment contains as little hydrogen, water, etc. as possible. The heat treatment is carried out in an electric furnace or RTA (Rapid Thermal Annealing). al) Equipment can be used. By using an RTA device, the heat treatment time can be shortened. It is possible.

[0181] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0182] [Formation of insulating layer 110] Next, the insulating layer 110 is formed by covering the insulating layer 103 and the semiconductor layer 108 (Figure 8D). ).

[0183] In particular, each insulating layer constituting the insulating layer 110 is preferably formed by the PECVD method. The method for forming each layer constituting the insulating layer 110 can be described by referring to the above example of configuration 1.

[0184] Plasma treatment is performed on the surface of the semiconductor layer 108 before the deposition of the insulating layer 110. This is preferable. The plasma treatment removes impurities such as water adsorbed on the surface of the semiconductor layer 108. This can be reduced. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 110 can be reduced. Because material can be reduced, highly reliable transistors can be realized. In particular, semiconductor layer 108 When the surface of the semiconductor layer 108 is exposed to the atmosphere between formation and deposition of the insulating layer 110 This is preferable. For plasma treatment, for example, oxygen, ozone, nitrogen, nitrous oxide, algonium It can be carried out in an atmosphere such as [unclear]. Also, the plasma treatment and the deposition of the insulating layer 110 are different. It is preferable that the process be carried out continuously without exposure to the atmosphere.

[0185] Here, it is preferable to perform a heat treatment after forming the insulating layer 110. This allows for the removal of hydrogen or water contained in or adsorbed on the insulating layer 110. This also reduces defects in the insulating layer 110.

[0186] The conditions for heat treatment can be based on the description above.

[0187] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0188] [Formation of metal oxide film 114f] Next, a metal oxide film 114f is formed on the insulating layer 110 (Figure 8E).

[0189] The metal oxide film 114f is preferably formed in an atmosphere containing oxygen, for example. It is preferable to form it by sputtering in an oxygen-containing atmosphere. Oxygen can be supplied to the insulating layer 110 during the formation of the metal oxide film 114f.

[0190] The metal oxide film 114f is made of an oxide containing the same metal oxide as in the case of the semiconductor layer 108. When forming by sputtering using a target, the above description can be applied. .

[0191] For example, as a film deposition condition for metal oxide film 114f, oxygen is used as the deposition gas, and the metal target... A metal oxide film may be formed by a reactive sputtering method using a metal target. For example, if aluminum is used as the base material, an aluminum oxide film is formed. It is possible.

[0192] The thicker the metal oxide film 114f, the greater the region 108 will be when the subsequent metal oxide layer 114 is formed. The width L2 of L can be reduced. The thinner the thickness of the metal oxide film 114f, the less likely the subsequent gold The width L2 of region 108L can be increased when the oxide layer 114 is formed. By adjusting the thickness of the metal oxide film 114f, the width L2 of region 108L can be controlled. ru.

[0193] The width L2 of region 108L can be controlled by adjusting the deposition conditions of the metal oxide film 114f. Yes, it is possible. For example, when depositing a metal oxide film 114f, if the pressure inside the deposition chamber of the deposition apparatus is low, However, the crystallinity of the metal oxide film 114f increases, and when the subsequent metal oxide layer 114 is formed, region 1 The width L2 of 08L can be reduced. The higher the pressure inside the deposition chamber, the more the metal oxide film 1 The crystallinity of 14f decreases, and the width L2 of region 108L increases during the subsequent formation of the metal oxide layer 114. This can be achieved. In this way, the pressure inside the deposition chamber during the deposition of the metal oxide film 114f can be controlled. By adjusting it, the width L2 of region 108L can be controlled.

[0194] During the deposition of the metal oxide film 114f, the higher the power supply, the more the metal oxide film 114f crystallizes. This improves the properties and reduces the width L2 of region 108L when the metal oxide layer 114 is formed later. This can be achieved. The lower the power supply, the lower the crystallinity of the metal oxide film 114f, and the subsequent metal acid The width L2 of region 108L can be increased when the ionized layer 114 is formed. In this way, gold By adjusting the power supply during the deposition of the oxide film 114f, the width L2 of region 108L can be adjusted. It can be controlled.

[0195] The higher the substrate temperature during deposition of the metal oxide film 114f, the more the crystallinity of the metal oxide film 114f increases. This increases the width L2 of region 108L when the metal oxide layer 114 is formed later. Yes, it is possible. The lower the substrate temperature, the lower the crystallinity of the metal oxide film 114f, and the subsequent metal oxidation The width L2 of region 108L can be increased when forming the material layer 114. In this way, the metal By adjusting the substrate temperature during the deposition of the oxide film 114f, the width L2 of region 108L can be controlled. It is possible.

[0196] As the metal oxide layer 114, an oxide material containing one or more of the same elements as the semiconductor layer 108 is used. If present, the substrate temperature during the deposition of the metal oxide film 108f and the temperature during the deposition of the metal oxide film 114f It is preferable to make the substrate temperature the same as the temperature of the metal oxide film 114f. Gold formed using the same sputtering target and substrate temperature as the oxide film 108f Applying an oxide film is preferable because it allows for the use of common equipment.

[0197] When forming the metal oxide film 114f, the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus is The higher the ratio of oxygen flow rate (oxygen flow rate ratio), or the higher the oxygen partial pressure in the deposition chamber, the more metal oxidation occurs. The crystallinity of the material film 114f increases, and the width L of region 108L is increased during the subsequent formation of the metal oxide layer 114. 2 can be reduced. This is due to a low oxygen flow rate ratio or oxygen partial pressure in the deposition chamber. The crystallinity of the metal oxide film 114f decreases, and the region during subsequent metal oxide layer 114 formation The width L2 of 108L can be increased. In this way, the metal oxide film 114f can be formed. By adjusting the oxygen flow rate ratio or oxygen partial pressure in the deposition chamber at that time, region 10 The width L2 of the 8L can be controlled.

[0198] Furthermore, when forming the metal oxide film 114f, the total amount of the deposition gas introduced into the deposition chamber of the deposition apparatus The higher the ratio of oxygen flow rate to total flow rate (oxygen flow rate ratio), or the higher the partial pressure of oxygen in the deposition chamber, the greater the oxygen flow rate. It is preferable to increase the amount of oxygen supplied to the margin layer 110. Oxygen flow rate ratio or oxygen content The pressure is, for example, higher than 0% and less than or equal to 100%, preferably between 10% and 100%, more preferably between 10% and 100%. Preferably 20% to 100%, more preferably 30% to 100%, even more preferably The ratio should be between 40% and 100%. In particular, the oxygen flow rate ratio should be 100%, and the oxygen partial pressure should be It is preferable to get as close to 100% as possible.

[0199] In this way, a metal oxide film 114f is formed by sputtering in an oxygen-containing atmosphere. By doing so, when the metal oxide film 114f is formed, oxygen is supplied to the insulating layer 110. In both cases, it is possible to prevent oxygen from detaching from the insulating layer 110. As a result, the insulating layer 1 A very large amount of oxygen can be trapped in a 10.

[0200] The thickness of the metal oxide film 114f and the deposition conditions (pressure, etc.) mentioned above are combined accordingly. Therefore, it is preferable to control the width L2 of region 108L.

[0201] It is preferable to perform a heat treatment after the formation of the metal oxide film 114f. By performing the heat treatment, The oxygen contained in the insulating layer 110 can be supplied to the semiconductor layer 108. When 114f is heated while covering the insulating layer 110, acid is released from the insulating layer 110 to the outside. This prevents the element from being detached and allows for a large supply of oxygen to the semiconductor layer 108. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced, enabling the realization of highly reliable transistors.

[0202] The conditions for heat treatment can be based on the description above.

[0203] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) In some cases, such as in the film deposition process, this heat treatment can be carried out in conjunction with other processes.

[0204] [Formation of opening 142 and conductive film 112f] Next, the metal oxide film 114f, the insulating layer 110, and a portion of the insulating layer 103 are etched. This creates an opening 142 that reaches the conductive layer 106. The conductive layer 112 and the conductive layer 106 can be electrically connected through the opening 142. .

[0205] Next, a conductive film 112f, which will become the conductive layer 112, is formed on the metal oxide film 114f. Figure 9A).

[0206] The conductive film 112f preferably uses a low-resistance metal or alloy material. As the film 112f, a material that does not easily release hydrogen and does not easily diffuse hydrogen is used. It is preferable to use a material that is resistant to oxidation as the conductive film 112f. It's nice.

[0207] For example, the conductive film 112f is produced using a sputtering target containing a metal or alloy. It is preferable to deposit the film by the puttering method.

[0208] For example, the conductive film 112f is a conductive film that is resistant to oxidation and hydrogen diffusion, and has low resistance. It is preferable to form a laminated film by stacking a conductive film.

[0209] [Formation of conductive layer 112 and metal oxide layer 114 1] Next, a resist mask 115 is formed on the conductive film 112f (Figure 9B). After that, In the region not covered by the dystomask 115, the conductive film 112f and the metal oxide film 1 14f is removed, and the conductive layer 112 and the metal oxide layer 114 are formed (Figure 9C).

[0210] A wet etching method is preferably used to form the conductive layer 112 and the metal oxide layer 114. It is possible. Wet etching methods include, for example, oxalic acid, phosphoric acid, acetic acid, nitric acid, An etchant containing one or more hydrochloric acid or sulfuric acid can be used. In particular, conductive layer 112 When using a material containing copper, an etchant containing phosphoric acid, acetic acid, and nitric acid is preferably used. It can be used.

[0211] The etching rate of the metal oxide layer 114 is faster than the etching rate of the conductive layer 112. By doing so, the metal oxide layer 114 and the conductive layer 112 can be formed in the same process. Furthermore, the end of the metal oxide layer 114 can be positioned inward from the end of the conductive layer 112. Furthermore, the width L2 of region 108L can be controlled by adjusting the etching time. By being able to form them in the same process, the process can be simplified and productivity can be increased. .

[0212] When a wet etching method is used to form the conductive layer 112 and the metal oxide layer 114, As shown in 9C, the edges of the conductive layer 112 and the metal oxide layer 114 are located on the resist mask 11 It may be located inside the contour of 5. In that case, it is wider than the width of resist mask 115. However, this also reduces the width L1 of the conductive layer 112, so the width L1 of the conductive layer 112 is reduced. You just need to make the width of the Gist Mask 115 larger.

[0213] Next, remove the resist mask 115.

[0214] In this way, without etching the insulating layer 110, the top and side surfaces of the semiconductor layer 108, and By creating a structure in which an insulating layer 103 is covered, when forming the conductive layer 112, etc., the semiconductor layer 10 This prevents etching and thinning of parts of 8 and the insulating layer 103.

[0215] [Formation of conductive layer 112 and metal oxide layer 114 2] A method different from the method for forming the conductive layer 112 and the metal oxide layer 114 shown in Figures 9B and 9C. I will explain about that.

[0216] A resist mask 115 is formed on the conductive film 112f (Figure 10A).

[0217] Next, the conductive film 112f is etched using anisotropic etching, and the conductive layer 112 Form (Figure 10B). Dry etching is preferably used as the anisotropic etching method. It is possible.

[0218] Next, the metal oxide film 114f is etched using wet etching, and the metal acid A metal oxide layer 114 is formed (Figure 10C). At this time, metal oxide is formed from the edge of the conductive layer 112. Adjust the etching time so that the edges of layer 114 are etched inward. Also, adjust the etching time By adjusting it, the width L2 of region 108L can be controlled.

[0219] An anisotropic etching method is used to form the conductive layer 112 and the metal oxide layer 114. After etching film 112f and metal oxide film 114f, an isotropic etching method is used. Then, the sides of the conductive film 112f and the metal oxide film 114f are etched to recess the end faces. This may also be done (also called side etching). This allows the conductive layer 112 to be removed in a plan view. A metal oxide layer 114 can be formed, located further inside.

[0220] Note that different etching conditions or manual processes are used to form the conductive layer 112 and the metal oxide layer 114. The etching may be performed in at least two separate steps using the method. For example, the conductive film 112f First, the metal oxide film 114f was etched, and then etched under different etching conditions. That's fine.

[0221] When forming the conductive layer 112 and the metal oxide layer 114, areas that do not come into contact with the metal oxide layer 114 The thickness of the insulating layer 110 in certain areas may be reduced (see Figures 2A, 2B, 3A, and 3B). .

[0222] Next, remove the resist mask 115.

[0223] [Processing of supplying impurity elements] Next, using the conductive layer 112 as a mask, impurities are introduced into the semiconductor layer 108 via the insulating layer 110. The process involves supplying (adding or injecting) element 140 (Figure 11A). Therefore, region 108N is formed in the region of the semiconductor layer 108 that is not covered by the conductive layer 112. Yes, it is possible. At this time, in the region of the semiconductor layer 108 that overlaps with the conductive layer 112, the conductive layer 112 is As a result, impurity element 140 is not supplied.

[0224] The supply of impurity element 140 is preferably by plasma ion doping or ion implantation. These methods can be used to obtain a depth-direction concentration profile, and to accelerate ions. It can be controlled with high precision by adjusting voltage and dose. Plasma ion doping By using this method, productivity can be increased. Also, ion implantation using mass separation can be used. By using this method, the purity of the supplied impurity elements can be increased.

[0225] In the supply process of impurity element 140, at the interface between the semiconductor layer 108 and the insulating layer 110, The portion of the semiconductor layer 108 near the interface, or the portion of the insulating layer 110 near the interface, It is preferable to control the processing conditions to achieve the highest possible concentration. The principle is to supply both the semiconductor layer 108 and the insulating layer 110 with an optimal concentration of impurity elements 140. It is possible.

[0226] The 140 impurity elements are hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, Examples include aluminum, magnesium, silicon, or noble gases. Typical examples include helium, neon, argon, krypton, and xenon. In particular, boron, phosphorus, aluminum, magnesium, or silicon are preferred. It's nice.

[0227] As a raw material gas for impurity element 140, a gas containing the above-mentioned impurity element can be used. When supplying boron, typical gases such as B2H6 gas and BF3 gas can be used. Furthermore, when supplying phosphorus, pH3 gas can typically be used. A mixed gas obtained by diluting these source gases with a noble gas may also be used.

[0228] Other raw material gases include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Furthermore, the ion source is not limited to gases; solids or liquids that have been heated and vaporized can also be used. good.

[0229] The addition of impurity element 140 affects the composition, density, and thickness of the insulating layer 110 and the semiconductor layer 108. By taking these factors into consideration and setting conditions such as acceleration voltage and dose amount, it can be controlled.

[0230] For example, when adding boron using ion implantation or plasma ion doping, The acceleration voltage is, for example, 5kV to 100kV, preferably 7kV to 70kV, Preferably, the voltage can be in the range of 10kV to 50kV. Also, the dose amount is, for example... ba 1 × 10 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following is preferably 1 ×10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 More convenient 1 ×10 15 ions / cm 2 The above is 3 x 10 16 ions / cm 2 The following range It is possible.

[0231] When adding phosphorus ions using ion implantation or plasma ion doping, acceleration The voltage is, for example, 10kV to 100kV, preferably 30kV to 90kV. Preferably, the voltage can be in the range of 40kV to 80kV. Also, the dose amount is, for example, e.g. 1 x 10 13 ions / cm 2 The above 1 x 10 17 ions / cm 2 The following are preferred 1 x 10 14 ions / cm 2 The above 5 x 10 16 ions / cm 2 The following is more 1 x 10 15 ions / cm 2 The above is 3 x 10 16 ions / cm 2 The following ranges apply. It is possible.

[0232] Furthermore, the method of supplying impurity element 140 is not limited to this; for example, plasma processing or heating... Treatment methods utilizing thermal diffusion may also be used. In the case of plasma treatment, impurities to be added By generating plasma in an element-containing gas atmosphere and performing plasma processing, Pure elements can be added. A device for generating the above plasma is a dry ec. Using chipping equipment, ashing equipment, plasma CVD equipment, high-density plasma CVD equipment, etc. It is possible.

[0233] In one aspect of the present invention, impurity elements 140 are supplied to the semiconductor layer 108 via the insulating layer 110. Therefore, even if the semiconductor layer 108 has crystalline properties, impurities The damage to the semiconductor layer 108 during the supply of element 140 is reduced, and its crystallinity is not impaired. This can suppress the occurrence of this problem. Therefore, the decrease in crystallinity can increase electrical resistance. It is suitable in such cases.

[0234] [Formation of insulating layer 118] Next, the insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are covered by the insulating layer 11 Forms 8 (Figure 11B).

[0235] When forming the insulating layer 118 by plasma CVD, if the deposition temperature is too high, region 1 Impurities contained in 08N, etc., diffuse into the peripheral region of the semiconductor layer 108, including the channel formation region. This may cause the electrical resistance of region 108N to increase, therefore the formation of the insulating layer 118 The membrane temperature should be determined by taking these factors into consideration.

[0236] For example, the film deposition temperature for the insulating layer 118 is preferably between 150°C and 400°C. The temperature should be between 180°C and 360°C, more preferably between 200°C and 250°C. Preferably, by forming the insulating layer 118 at a low temperature, transistors with short channel lengths can be formed. Even if present, it can impart good electrical characteristics.

[0237] After the formation of the insulating layer 118, a heat treatment may be performed. This heat treatment makes it more stable. In some cases, the resistance can be reduced to a low-resistance region of 10⁸N. For example, by performing a heat treatment. As a result, impurity element 140 diffuses appropriately and becomes locally homogenized, achieving an ideal concentration of impurity element. A region 108N with a gradient can be formed. Note that if the heat treatment temperature is too high (for example, 5 At temperatures above 0°C, impurity element 140 diffuses into the channel formation region, and the transistor This could lead to a deterioration in electrical characteristics and reliability.

[0238] The conditions for heat treatment can be based on the description above.

[0239] Note that this heat treatment may be omitted if it is not necessary. Also, heat treatment is not performed here. Furthermore, it may be combined with the heat treatment performed in a later step. Also, high-temperature treatment in a later step (e.g.) For example, if there is a film formation process, it may be possible to combine it with the heat treatment.

[0240] [Formation of openings 141a and 141b] Next, by etching a portion of the insulating layer 118 and the insulating layer 110, region 108N Openings 141a and 141b are formed that reach the bottom.

[0241] [Formation of conductive layer 120a and conductive layer 120b] Next, a conductive film is applied to the insulating layer 118 so as to cover the openings 141a and 141b. By forming a film and processing the conductive film into a desired shape, conductive layer 120a and conductive layer 120b are formed. It forms (Figure 11C).

[0242] By following the above steps, transistor 100A can be manufactured. For example, When applying Sta100A to the pixels of a display device, a protective insulating layer, a planarizing layer, The process can be simplified by adding a step to form one or more of the pixel electrodes or wiring.

[0243] The above is an explanation of manufacturing method example 1.

[0244] Note that when manufacturing the transistor 100 exemplified in Configuration Example 1, refer to the above manufacturing method example 1. The steps for forming the conductive layer 106 and the opening 142 can be omitted. Transistor 100 and transistor 100A are formed on the same substrate through the same process. It is possible.

[0245] <Components of a semiconductor device> The following describes the components included in the semiconductor device of this embodiment.

[0246] 〔substrate〕 There are no major restrictions on the material of the substrate 102, but it should at least be able to withstand subsequent heat treatment. It must have heat resistance. For example, a single crystal made of silicon or silicon carbide. Semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI groups Plates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., are used as substrate 102. It is also acceptable to have semiconductor elements mounted on these substrates as substrate 102. You may use it.

[0247] Even if a flexible substrate is used as the substrate 102 and a semiconductor device is formed directly on the flexible substrate, That's fine. Alternatively, a release layer may be provided between the substrate 102 and the semiconductor device. The release layer is on top of that. After partially or completely completing the semiconductor device, it is separated from the substrate 102 and transferred to another substrate. It can be used for this purpose. In this case, the semiconductor device is a substrate with poor heat resistance or a flexible substrate. It can also be reprinted.

[0248] [Conductive film] Conductive layers 112 and 106 function as gate electrodes, and source electrodes or A conductive layer 120a that functions as one of the rain electrodes and a conductive layer 120 that functions as the other b is chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tan Metallic elements selected from gusten, manganese, nickel, iron, and cobalt, or the aforementioned gold Using alloys composed of the group elements, or alloys combining the aforementioned metallic elements, each shape It is possible.

[0249] The conductive layer 112, conductive layer 106, conductive layer 120a, and conductive layer 120b contain In-Sn Oxides, In-W oxides, In-W-Zn oxides, In-Ti oxides, In-Ti-Sn Oxides such as In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, etc. A material conductor or a metal oxide film can also be applied.

[0250] Here, we will explain oxide conductors (OC). For example, an oxygen vacancy is formed in a metal oxide having semiconductor properties, and hydrogen is added to the oxygen vacancy. Then, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive. It becomes conductive. A metal oxide that has been made conductive can be called an oxide conductor.

[0251] The conductive layer 112, etc., is a conductive film containing the above oxide conductor (metal oxide) and a metal or A laminated structure of conductive films containing an alloy may also be used. By using a conductive film containing a metal or alloy, This allows for reduced wiring resistance. At this time, the insulating layer that functions as a gate insulating film and It is preferable to apply a conductive film containing an oxide conductor to the contacting side.

[0252] The conductive layers 112, 106, 120a, and 120b contain the aforementioned metal elements. Among these, the selection is particularly made from titanium, tungsten, tantalum, and molybdenum. It is preferable to have one or more of these. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film is electrically conductive and has high barrier properties against copper, oxygen, or hydrogen. Furthermore, because it releases little hydrogen from itself, the conductive film in contact with the semiconductor layer 108, This can be suitably used as a conductive film in the vicinity of the semiconductor layer 108.

[0253] [Semiconductor layer] The semiconductor layer 108 preferably contains a metal oxide.

[0254] For example, semiconductor layer 108 is made of indium and M (where M is gallium, aluminum, and silicon). N, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel Germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium (One or more elements selected from luminous, tantalum, tungsten, or magnesium), It is preferable that it contains zinc. In particular, M is aluminum, gallium, yttrium, It is preferable to use one or more types selected from tin.

[0255] If the semiconductor layer 108 is In-M-Zn oxide, then to deposit the In-M-Zn oxide film... The atomic ratio of metal elements in the sputtering target used is In:M:Zn=1: 1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Z n=1:3:4, In:M:Zn=1:3:6, In:M:Zn=2:2:1, In:M :Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In :M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1: 7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5: Examples include 2:5.

[0256] When a target containing a polycrystalline oxide is used as a sputtering target, the crystal This is preferable because it facilitates the formation of a semiconductor layer 108 having properties. The atomic ratio of 10⁸ is the atomic ratio of the metal elements contained in the above sputtering target. Includes a variation of plus or minus 40%. For example, the sputtering process used for semiconductor layer 108 When the composition of the film is In:Ga:Zn=4:2:4.1 [atomic ratio], the resulting film is semi-semi The composition of the conductive layer 108 is close to In:Ga:Zn=4:2:3 [atomic ratio]. be.

[0257] Note that when the atomic ratio is stated as In:Ga:Zn=4:2:3 or close to it, In When we set the ratio to 4, this includes the case where Ga is between 1 and 3, and Zn is between 2 and 4. Furthermore, when stating that the atomic ratio is In:Ga:Zn = 5:1:6 or close to it, When n is set to 5, Ga is greater than 0.1 and less than or equal to 2, and Zn is between 5 and 7. This includes cases where the atomic ratio is In:Ga:Zn = 1:1:1 or close to it. When listing, if In is set to 1, Ga must be greater than 0.1 and less than or equal to 2, and Zn must be 0. This includes cases where the value is greater than 1 and less than or equal to 2.

[0258] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using metal oxides with a wider energy gap than silicon, This can reduce the transistor's off-current.

[0259] It is preferable to use a metal oxide with a low carrier concentration in the semiconductor layer 108. When reducing the carrier concentration of the oxide, the impurity concentration in the metal oxide is reduced, The defect level density should be lowered. In this specification, the impurity concentration is low and the defect level density is A low level is referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, impurities in metal oxides and For example, hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon There are things like n.

[0260] In particular, the hydrogen contained in metal oxides reacts with the oxygen bonded to the metal atoms to form water. In some cases, oxygen vacancies may form in the metal oxide. If a primary defect is present, the transistor may exhibit normally-on characteristics. A defect where hydrogen fills an oxygen vacancy acts as a donor, generating electrons, which act as carriers. Sometimes, some of the hydrogen combines with oxygen that is bonded to a metal atom, and the hydrogen acts as a carrier. Transients may be produced. Therefore, transients using metal oxides that contain a lot of hydrogen Stamina tends to have the Normalion trait.

[0261] Defects where hydrogen is present in an oxygen vacancy can function as donors for metal oxides. However, Therefore, it is difficult to quantitatively evaluate the defect. In metal oxides, - In some cases, evaluation is based on carrier concentration rather than concentration. Therefore, in this specification, etc., metal The parameter for the oxide is not the donor concentration, but rather the value assuming a state where no electric field is applied. Carrier concentration may be used. In other words, the "carrier concentration" described in this specification, etc., is "d It can sometimes be rephrased as "ener concentration."

[0262] Therefore, it is preferable that the hydrogen content in the metal oxide be reduced as much as possible. Specifically, In metal oxides, secondary ion mass spectrometry (SIMS) is used. The hydrogen concentration obtained by mass spectrometry is 1 × 10⁻⁶ 20 at oms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than, more 5 x 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 It shall be less than. Metal oxides with sufficiently reduced impurities such as hydrogen are used as transistor channels. By using it in the region where the material is formed, stable electrical properties can be imparted.

[0263] The carrier concentration of the metal oxide in the channel-forming region is 1 × 10⁻⁶ 18 cm -3 The following Preferably, 1 × 10 17 cm -3 It is more preferable that it be less than 1 × 10 16 cm -3 It is even more preferable that it be less than 1 × 10 13 cm -3 It is even better if it is less than Mashiku, 1 x 10 12 cm -3 It is even more preferable that it be less than [a certain value]. Note that the channel formation region There are no particular limitations on the lower limit of the carrier concentration of metal oxides in the region, but for example, 1 × 1 0 -9 cm -3It can be done this way.

[0264] The semiconductor layer 108 is preferably a non-single crystal structure. A non-single crystal structure is, for example, later This includes the CAAC structure, polycrystalline structure, microcrystalline structure, or amorphous structure described below. Non-single-crystal structure In this context, the amorphous structure has the highest defect level density, while the CAAC structure has the lowest defect level density. stomach.

[0265] The following explains CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0266] A CAAC structure is a structure that has multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). It is one of the crystalline structures of thin films, in which each nanocrystal has its c-axis oriented in a specific direction, and its a-axis and The b-axis does not have orientation, and the nanocrystals are continuously connected to each other without forming grain boundaries. This crystal structure has the following characteristics. In particular, thin films with a CAAC structure have each nanocrystal The c-axis is oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film. It has the characteristic of being inexpensive.

[0267] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. It is a conductor. On the other hand, CAAC-OS does not allow for the identification of clear grain boundaries, It can be said that a decrease in electron mobility caused by grain boundaries is less likely to occur in oxide semiconductors. Crystallinity may decrease due to the inclusion of impurities or the formation of defects, therefore CAAC-OS It can also be described as an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, CAAC- Oxide semiconductors containing OS have stable physical properties. Therefore, CAAC-OS is used. Oxide semiconductors are highly heat-resistant and reliable.

[0268] In crystallography, the three axes a, b, and c constitute the unit cell (crystal). Regarding the axis, it is common to take a unit cell with a specific axis as the c-axis. Especially in layered structures In crystals with a structure, the two axes parallel to the plane direction of the layer are defined as the a-axis and the b-axis, and the axis intersecting the layer is defined as the axis intersecting the layer. It is common to use the c-axis. A typical example of a crystal having such a layered structure is... There is graphite, which is classified as a hexagonal crystal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane. The row is oriented, and the c-axis is perpendicular to the cleavage plane. For example, the layered structure of YbFe2O4 type crystal structure. InGaZnO4 crystals can be classified as hexagonal, and their unit cell a-axis and The b-axis is parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (i.e., the a-axis and b-axis).

[0269] Oxide semiconductor films with a microcrystalline structure (microcrystalline oxide semiconductor films) can be observed using TEM. In some cases, the crystalline portion cannot be clearly identified. The crystalline portion is between 1 nm and 100 nm in size, or between 1 nm and 10 nm in size. This is often the case. In particular, with microcrystals between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor film having a certain nanocrystal (nc) is called nc-OS (Nanocrystalline Oxide Semiconductor) film Furthermore, in nc-OS films, grain boundaries can be clearly observed, for example, in TEM observation images. It may not be possible.

[0270] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region below 3 nm. Furthermore, the nc-OS film exhibits different characteristics. There is no regularity in the crystal orientation between the crystalline regions. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this occurs. For example, XRD using X-rays with a diameter larger than that of the crystalline region on an nc-OS film. When structural analysis is performed using the apparatus, the out-of-plane method analyzes the crystal planes. The indicated peak is not detected. Also, the probe diameter is larger than that of the crystalline region in the nc-OS film. Electron diffraction (also called limited-field electron diffraction) using electron beams (for example, 50 nm or greater). When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, when applied to an nc-OS film... Furthermore, the probe diameter should be close to or smaller than the size of the crystal (for example, 1 nm to 30 nm). When electron diffraction (also called nanobeam electron diffraction) is performed using the electron beam shown below, a circle is drawn. A ring-shaped region of high brightness was observed, and within this ring-shaped region, multiple spots were observed. A retched object may be observed.

[0271] nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, nc-O The S film shows no regularity in crystal orientation between different crystalline regions. Therefore, the nc-OS film is Compared to CAAC-OS films, nc-OS films have a higher defect level density. Therefore, nc-OS films are CAAC- Compared to OS films, it may have a higher carrier density and higher electron mobility. Therefore, nc Transistors using OS films may exhibit high field-effect mobility.

[0272] Compared to CAAC-OS films, nc-OS films require a lower oxygen flow rate ratio during deposition. It can be formed by [method]. Furthermore, compared to CAAC-OS films, nc-OS films have [processing time] It can also be formed by lowering the substrate temperature. For example, the nc-OS film can be formed by lowering the substrate temperature. A state where the temperature is set to a relatively low temperature (for example, below 130°C), or a state where the substrate is not heated. However, because it can form thin films, it is suitable for use with large glass substrates or resin substrates. Therefore, productivity can be increased.

[0273] An example of a metal oxide crystal structure is described. In-Ga-Zn oxide target ( Using In:Ga:Zn=4:2:4.1 (atomic ratio), the substrate temperature was set to 100°C or higher. At temperatures below 30°C, metal oxides formed by sputtering are nc(nano C Either a crystalline structure (rystal) or a CAAC structure, or a mixture of both. It is easy to form such a structure. On the other hand, metal oxides formed with the substrate temperature at room temperature (RT) It readily adopts an nc crystal structure. Note that room temperature (RT) here refers to the temperature when the substrate is not heated. This includes the temperature in the case of [unspecified].

[0274] [Composition of metal oxides] Hereinafter, CAC(C) that can be used in the transistor disclosed in one aspect of the present invention will be described. This document describes the configuration of a loud-Aligned Composite (Loud) OS.

[0275] Note that CAAC (c-axis aligned crystal) is an example of a crystal structure. This represents CAC (Cloud-Aligned Composite), which is a function or material. This shows an example of the composition of the ingredients.

[0276] CAC-OS or CAC-metal oxide is a material in which some parts are conductive. It has both electrical and insulating properties in some parts of the material, and the material as a whole has semiconductor properties. Furthermore, CAC-OS or CAC-metal oxide is used to activate the transistor. When used in layers, the conductive function is the function of allowing electrons (or holes) that act as carriers to flow. In other words, the insulating function is the function of preventing the flow of electrons, which act as carriers. Conductive function and insulating function By making the functions of sex and other functions work complementaryly, a switching function (On / O) is created. The function of ff (fastening) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, the respective functions are separated. By doing so, the functions of both can be maximized.

[0277] CAC-OS or CAC-metal oxide has conductive and insulating regions. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. It has the ability to conduct electricity. Furthermore, within the material, the conductive region and the insulating region are separated at the nanoparticle level. They may be separated. Also, conductive regions and insulating regions are unevenly distributed within the material. This can sometimes occur. Also, conductive regions may appear as a cloud-like, connected area with a blurred periphery. There is a match.

[0278] In CAC-OS or CAC-metal oxide, conductive region and insulating region Each region is defined as being between 0.5 nm and 10 nm, preferably between 0.5 nm and 3 nm. These particles may be dispersed within the material at a certain size.

[0279] CAC-OS or CAC-metal oxide has different band gaps. It is composed of the following components. For example, CAC-OS or CAC-metal oxide. This consists of a component with a wide gap due to the insulating region and a component with a narrow gap due to the conductive region. It is composed of a component having a gap. In this configuration, when the carrier is flowed, In components with a low gap, the carrier mainly flows. Also, in components with a narrow gap The component acts complementaryly with the component having a wide gap, and the component having a narrow gap Carriers also flow to components with a wide gap in conjunction with the minutes. Therefore, the above CAC - OS or CAC-metal oxide is used in the channel formation region of the transistor. In this case, the transistor has a high current driving force in the ON state, that is, a large ON current, and High field-effect mobility can be obtained.

[0280] In other words, CAC-OS or CAC-metal oxide is a matrix composite Material (matrix composite), or metal matrix composite material (metal It can also be called a matrix composite.

[0281] The above is an explanation of the composition of metal oxides.

[0282] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0283] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0284] (Embodiment 2) In this embodiment, an example of a display device having a transistor as illustrated in the previous embodiment is provided. I will explain about that.

[0285] <Example Configuration> Figure 12A shows a top view of the display device 700. The display device 700 is sealed by a sealing material 712 It has a first substrate 701 and a second substrate 705 that are bonded together. In the region sealed by the second substrate 705 and the sealing material 712, on the first substrate 701 The pixel section 702, source driver circuit section 704, and gate driver circuit section 706 are provided. Furthermore, the pixel section 702 is provided with multiple display elements.

[0286] In the portion of the first substrate 701 that does not overlap with the second substrate 705, FPC716 (FPC:F The FPC terminal section 708 to which the lexible printed circuit is connected It is provided. FPC716 is provided via FPC terminal section 708 and signal line 710 , the same as the pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 Various signals are supplied to each of them.

[0287] Multiple gate driver circuits 706 may be provided. The path section 706 and the source driver circuit section 704 are each formed separately on a semiconductor substrate or the like. The IC chip may be in the form of a packaged IC chip. The IC chip is on the first substrate 70 It can be implemented on 1 or on FPC716.

[0288] The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 have A transistor, which is a semiconductor device according to one aspect of the present invention, can be applied to the transistor. ru.

[0289] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light-emitting elements. Liquid crystal elements include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. It can be. Also, as a light-emitting element, it can be an LED (Light Emitting). Diode), OLED (Organic LED), QLED (Quantum-do Examples include self-luminous light-emitting elements such as LEDs and semiconductor lasers. Also, shutters - Method or optical interferometry MEMS (Micro Electro Mechanics) (Systems) Elements, microcapsule method, electrophoresis method, electrowet By using a display element that employs a lighting method or an electronic powder fluid (registered trademark) method, etc. It can also be done this way.

[0290] The display device 700A shown in Figure 12B uses a flexible resin instead of the first substrate 701. An example of a display device to which layer 743 is applied and which can be used as a flexible display. That is the case.

[0291] The display device 700A has a pixel section 702 that is not rectangular in shape, but has an arc-shaped corner. Furthermore, as shown in region P1 in Figure 12B, the pixel portion 702 and a part of the resin layer 743 It has a notched portion. A pair of gate driver circuit sections 706 are located in the pixel section 702 It is provided on both sides of the . The gate driver circuit section 706 is located at the corner of the pixel section 702. It is provided along an arc-shaped contour.

[0292] The resin layer 743 has a shape in which the portion where the FPC terminal portion 708 is provided protrudes. Furthermore, a portion of the resin layer 743, including the FPC terminal portion 708, is folded to the back side in area P2 in Figure 12B. It can be folded back. By folding back a part of the resin layer 743, the FPC 716 can be folded back into the pixel section 70 With the display device 700A placed on top of the back of 2, it can be mounted on the electronic device. This allows for space-saving in electronic devices.

[0293] The FPC716 connected to the display device 700A has the IC717 mounted on it. 717 has a function, for example, as a source driver circuit. At this time, the display device 700 The source driver circuit section 704 in A includes a protection circuit, a buffer circuit, and a demultiplexer. The configuration may include at least one circuit or the like.

[0294] The display device 700B shown in Figure 12C is suitable for use in electronic devices having a large screen. It is a display device capable of doing so. For example, television equipment, monitor equipment, personal computers Tablet devices (including notebook and desktop models), digital signage, etc. It can be suitably used for the following purposes.

[0295] The display device 700B consists of multiple source driver ICs 721 and a pair of gate driver circuits. It has part 722.

[0296] Multiple source driver IC721s are each attached to the FPC723. Furthermore, multiple FPC723s have one terminal connected to the first substrate 701 and the other terminal connected to the printed circuit board Each is connected to board 724. By bending FPC723, the printed circuit board 7 By placing 24 on the back side of the pixel unit 702, it can be mounted on electronic devices, reducing the size of the electronic device. This allows for a more controlled pace.

[0297] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. This makes it possible to create electronic devices with even narrower bezels.

[0298] This configuration makes it possible to realize a large and high-resolution display device. For example, Surface size is 30 inches or more diagonally, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. The above display device can be realized. Also, the resolution can be as high as 4K2K or 8K4K. This enables the creation of high-resolution display devices.

[0299] <Example of cross-sectional configuration> The following describes configurations using liquid crystal elements and EL elements as display elements. This will be explained using Figures 13 to 16. Note that Figures 13 to 15 are shown in Figure 12A. Figure 16 is a cross-sectional view along the dashed line QR. Figure 16 also shows the display device 7 shown in Figure 12B. This is a cross-sectional view along the dashed line ST in 00A. Figures 13 and 14 show the display elements as Figures 15 and 16 show configurations using liquid crystal elements, while Figure 16 shows configurations using electroluminescent (EL) elements.

[0300] <Explanation of common parts of display devices> The display device shown in Figures 13 to 16 comprises a wiring section 711, a pixel section 702, and a saw It has a screwdriver circuit section 704 and an FPC terminal section 708. The routing wiring section 711 is , has a signal line 710. The pixel section 702 has a transistor 750 and a capacitive element 790. The source driver circuit section 704 has a transistor 752. In Figure 14, the capacitance This shows the case where element 790 is absent.

[0301] Transistors 750 and 752 are the transistors exemplified in Embodiment 1. It can be applied.

[0302] The transistor used in this embodiment is made of an oxide that has been purified to suppress the formation of oxygen vacancies. It has a semiconductor film. The transistor can reduce the off-current. Therefore, it can handle electrical signals such as image signals. The holding time for signal signals can be extended, and the writing interval for image signals, etc., can also be set to be longer. This reduces the frequency of fresh cycles, resulting in lower power consumption.

[0303] The transistor used in this embodiment can obtain relatively high field-effect mobility, High-speed driving is possible. For example, if such a high-speed driving transistor is used in a display device... This allows for the switching transistors in the pixel section and the driver transistors used in the drive circuit section. The inverter can be formed on the same substrate, that is, formed on a silicon wafer or the like. A configuration that does not apply the specified drive circuit is also possible, which reduces the number of components in the display device. It is possible. Furthermore, by using transistors capable of high-speed driving in the pixel section, high image quality can be achieved. We can provide images.

[0304] The capacitive element 790 shown in Figures 13, 15, and 16 is a part of the transistor 750. The lower electrode is formed by processing the same film as the gate electrode of 1, and the same metal oxide as the semiconductor layer. It has an upper electrode formed by processing a material. The upper electrode is the saw of transistor 750 The resistance is reduced, similar to the drain region. Also, between the lower electrode and the upper electrode A portion of the insulating film, which functions as the first gate insulating layer of transistor 750, is provided therein. In other words, the capacitive element 790 has an insulating film that functions as a dielectric film sandwiched between a pair of electrodes. It has a stacked structure. In addition, the upper electrode has the source electrode and drain electrode of the transistor. Wiring obtained by processing the same film as the electrodes is connected.

[0305] A planarizing insulating film 7 is applied to transistors 750, 752, and capacitive element 790. 70 is provided.

[0306] The transistor 750 in the pixel section 702 and the source driver circuit section 704 Transistors with different structures than the 752 transistor may be used. For example, any one of them A top-gate transistor is applied to one side, and a bottom-gate transistor is applied to the other side. A configuration using the above gate driver circuit section 706 may also be used. Similar to the IBA circuit section 704, a transistor with the same structure as transistor 750 may be used. Alternatively, transistors with different structures may be used.

[0307] Signal line 710 connects to the source electrode and drain of transistors 750 and 752. It is formed with the same conductive film as electrodes, etc. At this time, a low-resistance material such as a material containing copper elements is used. Using this method reduces signal delays caused by wiring resistance, and enables display on large screens, making it preferable. It seems so.

[0308] The FPC terminal section 708 includes wiring 760, part of which functions as a connecting electrode, and an anisotropic conductive film 78. It has 0 and FPC716. Wiring 760 is connected to FPC71 via an anisotropic conductive film 780. It is electrically connected to the terminals of 6. Here, wiring 760 is connected to transistor 750 and It is formed from the same conductive film as the source electrode and drain electrode of transistor 752.

[0309] The first substrate 701 and the second substrate 705 are, for example, a glass substrate or a plastic substrate. Flexible substrates such as acrylic substrates can be used. When using a substrate, water or hydrogen is placed between the first substrate 701 and the transistor 750, etc. It is preferable to provide an insulating layer that has barrier properties against [the element].

[0310] On the second substrate 705 side, there is a light-shielding film 738, a colored film 736, and an insulating film 7 in contact with them. 34 and are provided.

[0311] <Example configuration of a display device using liquid crystal elements> The display device 700 shown in Figure 13 has a liquid crystal element 775 and a spacer 778. The crystal element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 between them. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. Furthermore, the conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. They are connected. The conductive layer 772 is formed on the planar insulating film 770 and functions as a pixel electrode. To be able to.

[0312] The conductive layer 772 contains a material that is transparent to visible light or a material that is reflective to visible light. It can be used. Examples of translucent materials include indium, zinc, tin, etc. It is preferable to use oxide materials containing these properties. Examples of reflective materials include aluminum and silver. It is recommended to use materials containing the following:

[0313] If a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, if a translucent material is used for the conductive layer 772, a transmissive liquid crystal display device is obtained. In the case of a transmissive liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device... A pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0314] The display device 700 shown in Figure 14 uses a transverse electric field method (for example, FFS mode) liquid crystal element 77 An example using 5 is shown. A common electrode is formed on the conductive layer 772 via an insulating layer 773. A conductive layer 774 is provided. Due to the electric field generated between the conductive layer 772 and the conductive layer 774, The orientation state of the liquid crystal layer 776 can be controlled.

[0315] In Figure 14, the laminated structure of conductive layer 774, insulating layer 773, and conductive layer 772 provides retention capacity. It can be configured in terms of quantity. Therefore, there is no need to provide a separate capacitive element, and the aperture ratio can be increased. It is possible.

[0316] Although not shown in Figures 13 and 14, the configuration includes an alignment film in contact with the liquid crystal layer 776. This is also fine. In addition, optical components (optical substrates) such as polarizing members, phase difference members, and anti-reflective members, and Light sources such as backlights and sidelights can be provided as needed.

[0317] The liquid crystal layer 776 contains thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, and polymer dispersion liquid. Crystal (PDLC: Polymer Dispersed Liquid Crystal) Polymer Network Liquid Crystal (PNLC) d Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. When employing a transverse electric field method, a liquid crystal exhibiting a blue phase without an alignment layer may be used.

[0318] The modes of the liquid crystal element include TN (Twisted Nematic) mode, VA ( Vertical Alignment) mode, IPS (In-Plane-Swiss) Ching mode, FFS (Fringe Field Switching) mode , ASM(Axially Symmetric aligned Micro-cel l) Mode, OCB (Optically Compensated Birefringence) gence) mode, ECB (Electrically Controlled Bicycle) You can use modes such as refringence mode and guest host mode.

[0319] A scattering type liquid crystal layer 776 using polymer dispersed liquid crystal or polymer network liquid crystal A liquid crystal can also be used. In this case, a configuration that displays in black and white without providing a colored film 736 is also possible. Alternatively, a configuration may be used in which a colored film 736 is used to display color.

[0320] As a method for driving liquid crystal elements, color display is performed based on the time-division table, which uses a time-division table. A display method (also called a field sequential drive method) may be applied. In that case, A configuration without a color film 736 is possible. When a time-division display method is used, for example, There is no need to provide subpixels that exhibit the respective colors R (red), G (green), and B (blue). Therefore, it offers advantages such as improving the aperture ratio of pixels and increasing the resolution.

[0321] <Display devices that use light-emitting elements> The display device 700 shown in Figure 15 has a light-emitting element 782. The light-emitting element 782 is a conductive layer It has 772, an EL layer 786, and a conductive film 788. The EL layer 786 is an organic compound, and It contains luminescent materials such as inorganic compounds.

[0322] Examples of light-emitting materials include fluorescent materials, phosphorescent materials, and thermally activated delayed fluorescence (A ctivated delayed fluorescence (TADF) materials, inorganic Compounds (such as quantum dot materials) can be used.

[0323] The display device 700 shown in Figure 15 has a conductive layer 772 covering a portion of the planar insulating film 770. An insulating film 730 is provided. Here, the light-emitting element 782 has a light-transmitting conductive film 788, This is a top-emission type light-emitting element. The light-emitting element 782 emits light towards the conductive layer 772. The bottom emission structure that is ejected emits light, and light is emitted to both the conductive layer 772 side and the conductive film 788 side. It may also be a dual-emission structure.

[0324] The colored film 736 is provided in a position that overlaps with the light-emitting element 782. The light-shielding film 738 is an insulating film. It is provided in a position overlapping with 730, in the routing wiring section 711, and in the source driver circuit section 704. Furthermore, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. 86 are formed in island-like patterns for each pixel or in striped patterns for each row of pixels, that is, by coloring. In some cases, the colored film 736 may not be provided.

[0325] Figure 16 shows a display device configuration that is suitably applicable to a flexible display. Figure 16 is a cross-sectional view of the display device 700A shown in Figure 12B along the dashed line ST. be.

[0326] The display device 700A shown in Figure 16 replaces the first substrate 701 shown in Figure 15 with a support base The structure has a laminated configuration consisting of a plate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744. The transistor 750 and the capacitive element 790 are located on the insulating layer 744 provided on the resin layer 743. It is located at [location].

[0327] The support substrate 745 is a substrate containing organic resin, glass, etc., and is thin enough to be flexible. The resin layer 743 is a layer containing organic resins such as polyimide and acrylic. Insulating layer 744 This includes an inorganic insulating film such as silicon oxide, silicon oxide nitride, and silicon nitride. Resin layer 74 3 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is It is preferable that the substrate is thinner than the support substrate 745.

[0328] The display device 700A shown in Figure 16 has a protective layer 7 instead of the second substrate 705 shown in Figure 15. It has 40. The protective layer 740 is bonded to the sealing film 732. Furthermore, glass substrates and resin films can be used. Also, as the protective layer 740, Optical components such as polarizing plates and scattering plates, input devices such as touch sensor panels, or these A configuration with two or more layers stacked on top of each other may also be applied.

[0329] The EL layer 786 of the light-emitting element 782 is provided in an island-like manner on the insulating film 730 and the conductive layer 772. It is made that the EL layer 786 is made so that each sub-pixel emits a different color of light. Color display can be achieved without using the color film 736. Also, the light-emitting element 782 is covered. A protective layer 741 is provided. The protective layer 741 protects the light-emitting element 782 from impurities such as water. It has the function of preventing diffusion. It is preferable that the protective layer 741 be an inorganic insulating film. Furthermore, it is preferable to have a laminated structure that includes one or more inorganic insulating films and one or more organic insulating films. stomach.

[0330] Figure 16 shows the foldable region P2. In region P2, the support substrate 745, In addition to the adhesive layer 742, there are portions where no inorganic insulating film such as an insulating layer 744 is provided. Furthermore, in region P2, a resin layer 746 is provided covering the wiring 760. In the functional region P2, an inorganic insulating film is provided as little as possible, and a conductive layer containing a metal or alloy is provided. By constructing a structure in which only layers containing organic materials are laminated, cracks will not occur when bent. This can be prevented. Also, by not providing the support substrate 745 in region P2, extremely small curves can be prevented. By adjusting the radius, a portion of the 700A display device can be bent.

[0331] <Example configuration of providing an input device to the display device> An input device is provided in the display device 700 or display device 700A shown in Figures 13 to 16. This is also acceptable. Examples of such input devices include touch sensors.

[0332] For example, sensor types include capacitive, resistive, surface acoustic wave, and infrared. Various methods can be used, such as formula, optical, and pressure-sensitive methods. Or, two or more of these can be used. They may be used in combination.

[0333] The touch panel configuration is a so-called in-cell type, where the input device is formed between a pair of circuit boards. A so-called on-cell type touch panel, which forms the touch panel and input device on the display device 700. A so-called out-cell type touch, in which a ru or input device is attached to the display device 700. There are panels and other things.

[0334] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0335] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0336] (Embodiment 3) In this embodiment, Figure 17 shows a display device having a semiconductor device according to one aspect of the present invention. We will use this to provide an explanation.

[0337] The display device shown in Figure 17A comprises a pixel unit 502, a drive circuit unit 504, and a protection circuit 506. It has a terminal section 507 and a protective circuit 506.

[0338] Transistors in the pixel section 502 and the drive circuit section 504 are configured according to one aspect of the present invention. A transistor can be applied. Also, a transistor according to one aspect of the present invention can be applied to the protection circuit 506. You may apply this.

[0339] The pixel section 502 is arranged in X rows and Y columns (where X and Y are independent natural numbers greater than or equal to 2). It has multiple pixel circuits 501 that drive a number of display elements.

[0340] The drive circuit section 504 outputs a scanning signal to gate lines GL_1 to GL_X. The driver 504a supplies data signals to data lines DL_1 through DL_Y. It has a drive circuit such as a source driver 504b. The gate driver 504a is at least It is also possible to have a configuration that includes a shift register. In addition, the source driver 504b can be, for example, multiple It is constructed using a number of analog switches, etc. It also uses shift registers, etc. Driver 504b may be configured.

[0341] The terminal section 507 inputs power, control signals, and image signals, etc., from an external circuit to the display device. This refers to the part that is equipped with terminals for that purpose.

[0342] The protection circuit 506, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires. The protection circuit 506 shown in Figure 17A is, for example, For example, the gate line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, or - Various wirings such as data lines DL, which are the wiring between driver 504b and pixel circuit 501. It will continue.

[0343] The gate driver 504a and the source driver 504b are based on the same base as the pixel unit 502. It may be provided on the board, or the gate driver circuit or source driver circuit may be provided separately. A completed substrate (for example, a drive circuit substrate formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) ) are created using COG or TAB (Tape Automated Bonding), pixels The configuration may also involve mounting the component 502 on a substrate.

[0344] The multiple pixel circuits 501 shown in Figure 17A have configurations such as those shown in Figure 17B or Figure 17C. It can be done this way.

[0345] The pixel circuit 501 shown in Figure 17B consists of a liquid crystal element 570, a transistor 550, and a capacitance element. It has a sub-unit 560 and a gate line GL_m. The pixel circuit 501 also has a data line DL_n and a gate line GL_m The potential supply line VL and other connections are connected.

[0346] The potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written to it. A common potential is set on one of the pairs of electrodes of the liquid crystal element 570 that each of the pixel circuits 501 possesses. (Common potential) may be applied. Also, a pair of liquid crystal elements 570 of the pixel circuit 501 of each row One of the electrodes may be given a different potential.

[0347] The pixel circuit 501 shown in Figure 17C includes transistor 552, transistor 554, and It has a quantitative element 562 and a light-emitting element 572. The pixel circuit 501 also has data lines DL _n, gate line GL_m, potential supply line VL_a, and potential supply line VL_b are connected. Yes, they are.

[0348] Furthermore, a high power supply potential VDD is supplied to one of the potential supply lines VL_a and VL_b. On the other hand, a low power supply potential VSS is applied to the gate of transistor 554. Depending on the potential, the current flowing through the light-emitting element 572 is controlled, thereby controlling the light-emitting element 5 The luminescence is controlled from 72 onwards.

[0349] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc., are at least a part of them. This can be implemented by combining it with other configuration examples or drawings as appropriate.

[0350] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0351] (Embodiment 4) Below, we have a pixel circuit equipped with memory for correcting the gradation displayed in the pixel, and this The display device will be described below. The transistor exemplified in Embodiment 1 is exemplified below. This can be applied to transistors used in pixel circuits.

[0352] <Circuit Configuration> Figure 18A shows the circuit diagram of the pixel circuit 400. The pixel circuit 400 consists of transistor M1, It has a transistor M2, a capacitor C1, and a circuit 401. The pixel circuit 400 also has wiring S1, wiring S2, wiring G1, and wiring G2 are connected.

[0353] Transistor M1 has its gate connected to wiring G1, and one of its sources or drains connected to wiring S1. The other end is connected to one electrode of capacitance C1. Transistor M2 has a gate that is wired G2, one of the source and drain is connected to wiring S2, the other electrode is connected to capacitance C1, and rotation It connects to Route 401, respectively.

[0354] Circuit 401 is a circuit that includes at least one display element. Various elements can be used as the display element. While various types can be used, typically light-emitting elements such as organic EL elements and LED elements, and liquid crystal elements are used. Child, or MEMS (Micro Electro Mechanical System) ms) elements and the like can be applied.

[0355] The node connecting transistor M1 and capacitor C1 is node N1, and the node connecting transistor M2 and... Let node N2 be the node connecting to path 401.

[0356] The pixel circuit 400 maintains the potential of node N1 by turning off transistor M1. It can be maintained. Also, by turning off transistor M2, the power of node N2 can be controlled. It can maintain its position. Also, with transistor M2 in the OFF state, By writing a predetermined potential to node N1 via station M1, capacitive coupling via capacitor C1 is achieved. This allows the potential of node N2 to be changed in accordance with the potential displacement of node N1.

[0357] Here, in the embodiment, one or both of transistors M1 and M2 are The transistor using oxide semiconductors, as exemplified in 1, can be applied. Therefore, the extremely low off-current maintains the potential of node N1 or node N2 for an extended period. This is possible. However, if the period for which the potential of each node is maintained is short (specifically, if the freight Transistors using semiconductors such as silicon are used when the frequency is 30Hz or higher. You may use "sta".

[0358] <Example of driving method> Next, an example of how the pixel circuit 400 operates will be explained using Figure 18B. This is a timing chart related to the operation of the pixel circuit 400. For simplicity of explanation, this chart is presented here. Therefore, various resistors such as wiring resistance, parasitic capacitance of transistors and wiring, and transistors The effects of the threshold voltage of the staccato are not considered.

[0359] In the operation shown in Figure 18B, one frame period is divided into period T1 and period T2. Period T2 is the period during which the potential is written to node N2, and period N1 is the period during which the potential is written to node N1. That is the case.

[0360] [Period T1] During period T1, a potential is applied to both wire G1 and wire G2 that turns the transistor ON. Also, the wiring S1 has a fixed potential V ref It supplies the first day to wiring S2. Potential V w To supply.

[0361] Node N1 receives a potential V from wiring S1 via transistor M1. ref It is given. Furthermore, node N2 has a first data potential V via transistor M2. wIt is given. Therefore, capacitance C1 has a potential difference V w -V ref This state is maintained.

[0362] [Period T2] Next, during period T2, a potential is applied to wiring G1 to turn on transistor M1, and The wire G2 is given a potential that turns off transistor M2. Also, the wiring S1 is supplied with the second diode DATA potential V data It supplies a predetermined constant potential to the wiring S2, or a floating It may also be in a ling state.

[0363] Node N1 has a second data potential V via transistor M1. data It is given. At this time, due to capacitive coupling by capacitance C1, the second data potential V data Node N The potential of point 2 changes by a potential dV. That is, in circuit 401, the first data potential Vw and the current The potential with the potential dV added will be input. Note that in Figure 18B, the potential dV is a positive value. Although it is indicated as such, a negative value is also acceptable. That is, the second data potential V data The potential is V ref It can be lower.

[0364] Here, the potential dV is roughly determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. If the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, the potential dV is the second dV. DATA potential V data The potential will be close to that.

[0365] Thus, the pixel circuit 400 combines two types of data signals to form a display element. Since it is possible to generate the potential supplied to path 401, grayscale correction can be performed within the pixel circuit 400. It becomes possible to do so.

[0366] The pixel circuit 400 is supplied by the source driver connected to wiring S1 and wiring S2. It also becomes possible to generate potentials exceeding high potentials. For example, when using a light-emitting element, It can display HDR (High Dynamic Range) and other features. In combination, overdrive operation and other similar features can be achieved.

[0367] <Examples of application> [Examples using liquid crystal elements] The pixel circuit 400LC shown in Figure 18C has circuit 401LC. Circuit 401LC is It has a liquid crystal element LC and a capacitance C2.

[0368] In a liquid crystal element (LC), one electrode is the electrode of node N2 and capacitance C2, and the other electrode is Potential V com2 Connect to the wiring provided. Capacitor C2 is connected when the other electrode is at potential V com1 Connect to the provided wiring.

[0369] Capacity C2 functions as the retention capacity. Note that capacity C2 can be omitted if it is not needed. Cut.

[0370] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example High-speed display is achieved through overdrive operation, and high-voltage liquid crystal materials are applied. It is possible to do things like this. Also, by supplying a correction signal to wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the degradation state of the liquid crystal elements (LC).

[0371] [Examples using light-emitting elements] The pixel circuit 400EL shown in Figure 18D has circuit 401EL. Circuit 401EL is It has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0372] One electrode of the gate of the transistor M3 is connected to one of the node N2 and the capacitor C2, and one of the source and the drain is connected to a wiring to which a potential V H is applied, and the other is connected to one electrode of the light-emitting element EL, and they are respectively connected. The other electrode of the capacitor C2 is connected to a wiring to which a potential V com is applied. The other electrode of the light-emitting element EL is connected to a wiring to which a potential V L is applied.

[0373] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a holding capacitor. The capacitor C2 can be omitted if it is not necessary.

[0374] Here, a configuration in which the anode side of the light-emitting element EL is connected to the transistor M3 is shown, but the transistor M3 may be connected to the cathode side. In that case, the values of the potential V H and the potential V L can be appropriately changed.

[0375] By applying a high potential to the gate of the transistor M3, the pixel circuit 400EL can cause a large current to flow through the light-emitting element EL, so that, for example, HDR display can be realized. Also, by supplying a correction signal to the wiring S1 or the wiring S2, variations in the electrical characteristics of the transistor M3 and the light-emitting element EL can be corrected.

[0376] Note that the present invention is not limited to the circuits illustrated in FIGS. 18C and 18D, and a configuration in which transistors, capacitors, etc. are separately added may be used.

[0377] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0378] (Embodiment 5) In this embodiment, a display module that can be manufactured using one aspect of the present invention is provided. I will explain.

[0379] The display module 6000 shown in Figure 19A consists of an upper cover 6001 and a lower cover 6002 Between them are the display device 6006, frame 6009, and print, with the FPC6005 connected. It has a circuit board 6010 and a battery 6011.

[0380] For example, a display device manufactured using one aspect of the present invention may be used in the display device 6006. This is possible. The display device 6006 enables the realization of an extremely low-power display module. It is possible.

[0381] The upper cover 6001 and the lower cover 6002 are sized to fit the display device 6006. The shape and dimensions can be changed as needed.

[0382] The display device 6006 may also have the functionality of a touch panel.

[0383] Frame 6009 is determined by the protection function of the display device 6006 and the operation of the printed circuit board 6010. It may also have functions such as blocking electromagnetic waves generated, or functioning as a heat sink.

[0384] Printed circuit board 6010 is a power supply circuit and a signal for outputting video signals and clock signals. It includes a processing circuit, a battery control circuit, and the like.

[0385] Figure 19B is a schematic cross-sectional view of a display module 6000 equipped with an optical touch sensor. ru.

[0386] The display module 6000 includes a light-emitting section 6015 and a receiver provided on the printed circuit board 6010. It has a light-emitting section 6016. It is also surrounded by an upper cover 6001 and a lower cover 6002. The region has a pair of light guides (light guide 6017a, light guide 6017b).

[0387] The display device 6006 connects to the printed circuit board 6010 and the battery via the frame 6009. - It is installed overlapping with 6011. The display device 6006 and frame 6009 are connected to the light guide section 6 017a is fixed to the light guide section 6017b.

[0388] Light 6018 emitted from the light-emitting unit 6015 is directed by the light guide unit 6017a to the display device 600. It passes through the upper part of 6, through the light guide part 6017b, and reaches the light receiving part 6016. For example, a finger or a stand Touch operation is detected when light 6018 is blocked by an object to be detected, such as an illustration. It is possible.

[0389] Multiple light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are provided at positions opposite to the light-emitting unit 6015. This allows for... Information about the location where the operation was performed can be obtained.

[0390] The light-emitting section 6015 can use a light source such as an LED element, and in particular, infrared light It is preferable to use a light source that emits light. The light receiving unit 6016 receives the light emitted by the light emitting unit 6015. A photoelectric element that converts light into an electrical signal can be used. Preferably, one that can receive infrared light. A photodiode can be used.

[0391] The light-emitting section 6015 and the light-emitting section 6015 are separated by the light-transmitting light-emitting section 6017a and light-transmitting section 6017b. The light receiving unit 6016 can be positioned below the display device 6006, and ambient light can be received by the light receiving unit 601 Reaching 6 can suppress the malfunction of the touch sensor. In particular, it absorbs visible light and infrared light. Using a resin that allows light to pass through can more effectively suppress malfunctions in touch sensors.

[0392] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0393] (Embodiment 6) This embodiment describes an example of an electronic device to which a display device according to one aspect of the present invention can be applied. I will reveal it.

[0394] The electronic device 6500 shown in Figure 20A is a portable device that can be used as a smartphone. It is a news terminal device.

[0395] The electronic device 6500 consists of a housing 6501, a display unit 6502, a power button 6503, and a button 6 It includes 504, speaker 6505, microphone 6506, camera 6507, and light source 6508, etc. The display unit 6502 is equipped with a touch panel function.

[0396] A display device according to one aspect of the present invention can be applied to the display unit 6502.

[0397] Figure 20B is a schematic cross-sectional view of the housing 6501, including the end on the microphone 6506 side.

[0398] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and the housing 650 Within the space surrounded by 1 and protective member 6510, display panel 6511, optical member 6512, The touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged. Yes, they are.

[0399] The protective member 6510 includes a display panel 6511, an optical member 6512, and a touch sensor panel. Nel 6513 is fixed by an adhesive layer (not shown).

[0400] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back. It is there. Also, the FPC6515 is connected to the folded portion. FPC651 IC6516 is mounted on board 5. FPC6515 is mounted on printed circuit board 6517. It is connected to a terminal provided there.

[0401] A flexible display panel according to one aspect of the present invention is applied to the display panel 6511. This makes it possible to create extremely lightweight electronic devices. Also, the display panel 651 Because it is extremely thin, it allows for a reduction in the thickness of electronic devices while incorporating a large-capacity battery, the 6518. It is also possible to fold back a portion of the display panel 6511 and place an FPC on the back of the pixel area. By positioning the connection point with 6515, it is possible to realize electronic devices with narrow bezels.

[0402] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0403] (Embodiment 7) In this embodiment, an electronic device equipped with a display device manufactured using one aspect of the present invention is provided. I will explain.

[0404] The electronic device described below is equipped with a display device according to one embodiment of the present invention in its display unit. Therefore, it is an electronic device that achieves high resolution. Also, high resolution and a large screen It can be made into an electronic device that is compatible with both systems.

[0405] The display unit of an electronic device according to one aspect of the present invention may display, for example, Full HD, 4K2K, 8K4 It can display video with resolutions of K, 16K, 8K, or higher.

[0406] Examples of electronic devices include television equipment, notebook personal computers, Equipped with relatively large screens such as monitors, digital signage, pachinko machines, and game machines. In addition to electronic devices, digital cameras, digital video cameras, digital photo frames, and portable devices are also available. Examples include mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0407] An electronic device to which one aspect of the present invention is applied includes the interior or exterior walls of houses and buildings, the interior of automobiles, etc. It can be incorporated along the flat or curved surfaces of the fittings or exterior.

[0408] Figure 21A shows the external appearance of the camera 8000 with the viewfinder 8100 attached. That is the case.

[0409] The camera 8000 consists of a housing 8001, a display unit 8002, operation buttons 8003, and a shutter. It has buttons 8004, etc. The camera 8000 also has a detachable lens 8006. It is attached.

[0410] The camera 8000 may have the lens 8006 and the housing integrated into a single unit.

[0411] Camera 8000 can be operated by pressing the shutter button 8004, or by using the touch panel function. Image capture can be performed by touching the display unit 8002.

[0412] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, it also has a strobe It can be connected to devices such as power supply units.

[0413] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc. .

[0414] The housing 8101 engages with the mount of the camera 8000 via a mount, and the camera 800 It is attached to the 0. The viewfinder 8100 receives images and other data from the camera 8000. This can be displayed on the display unit 8102.

[0415] Button 8103 functions as a power button, etc.

[0416] The display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100 are equipped with this A display device according to one embodiment of the invention can be applied. Note that a camera with a built-in viewfinder can also be used. It could also be 8000.

[0417] Figure 21B shows the external appearance of the head-mounted display 8200.

[0418] The head-mounted display 8200 consists of a mounting part 8201, lenses 8202, and a main body 82 03, it has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has It has a built-in 8206 battery.

[0419] Cable 8205 supplies power from battery 8206 to main unit 8203. Unit 203 is equipped with a wireless receiver and can display the received video information on the display unit 8204. It can do that. Furthermore, the main unit 8203 is equipped with a camera that inputs information about the user's eyeball and eyelid movements. It can be used as a step.

[0420] The attachment part 8201 is located at a position that touches the user, and current flows in accordance with the user's eye movements. Multiple electrodes capable of detecting gaze may be provided, and the device may have a function to recognize gaze. The device may also have a function to monitor the user's pulse rate based on the current flowing through the electrode. The mounting section 8201 has various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor. It may also have a function to display the user's biometric information on the display unit 8204, and to detect the user's head movements. The display unit 8204 may also have a function to change the image displayed on it.

[0421] A display device according to one aspect of the present invention can be applied to the display unit 8204.

[0422] Figures 21C, 21D, and 21E show the appearance of the head-mounted display 8300. This is a diagram. The head-mounted display 8300 consists of a housing 8301 and a display unit 8302 It also includes a band-shaped fastener 8304 and a pair of lenses 8305.

[0423] The user can view the display on the display unit 8302 through the lens 8305. Furthermore, by arranging the display unit 8302 in a curved shape, the user can experience a high level of realism. This is preferable. Also, another image displayed in a different area of ​​the display unit 8302 is displayed by the lens 8 By viewing through the 305, it is also possible to perform 3D displays using parallax. The configuration is not limited to having one display unit 8302, but can also have two display units 8302, allowing one of the users to... One display unit may be placed for each eye.

[0424] Furthermore, a display device according to one embodiment of the present invention can be applied to the display unit 8302. A display device having a semiconductor device according to one embodiment has extremely high resolution, as shown in Figure 21E. Even when magnified using lens 8305, the user cannot see the individual pixels, resulting in a more detailed view. It can display highly realistic images.

[0425] The electronic equipment shown in Figures 22A to 22G consists of a housing 9000, a display unit 9001, and a speaker 9 003, Operation key 9005 (including power switch or operation switch), Connection terminal 900 6. Sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, Magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity (Including functions for measuring degrees, inclines, vibrations, odors, or infrared radiation), Microphone 900 8, etc.

[0426] The electronic devices shown in Figures 22A to 22G have various functions. For example, they can provide various information ( Functions to display still images, videos, text images, etc. on the display unit, touch panel function, calendar A function that displays the date or time, etc., through various software (programs) Functions that control processing, wireless communication functions, programs or data recorded on recording media It can have functions such as reading and processing data. Furthermore, the functions of electronic devices are related to these. It is not limited and can have a variety of functions. Even if an electronic device has multiple display units Good. Also, an electronic device can be equipped with a camera, etc., to take still images and videos, and the recording medium (external or It has features such as saving to the camera (built-in), and displaying the captured image on the display unit. That's good too.

[0427] Details of the electronic equipment shown in Figures 22A to 22G will be explained below.

[0428] Figure 22A is a perspective view showing the television equipment 9100. 0 is a display unit 9001 with a large screen, for example, 50 inches or larger, or 100 inches or larger. It is possible to insert it.

[0429] Figure 22B is a perspective view showing a personal digital assistant (PDA) 9101. For example, For example, it can be used as a smartphone. Note that the mobile information terminal 9101 is a speed A connector (9003), connection terminal (9006), sensor (9007), etc. may be provided. Also, a portable information terminal may be provided. The 9101 can display text and image information on its multiple surfaces. Figure 22B shows three of them. This shows an example of displaying icon 9050. Also, information 9051, indicated by a dashed rectangle, is shown. The information can also be displayed on other sides of the display unit 9001. An example of information 9051 is electronic mail. Notifications of incoming calls, SNS messages, and phone calls; subject, sender name, and date / time for emails and SNS messages. This includes the time, battery level, and antenna signal strength. Alternatively, information 9051 may be displayed. You may display icons such as icon 9050 in the designated location.

[0430] Figure 22C is a perspective view showing the personal digital assistant 9102. The personal digital assistant 9102 is a table The display unit 9001 has the function of displaying information on three or more sides. Here, information 9052, information This shows an example where information 9053 and information 9054 are displayed on different sides. For example, the user With the mobile information terminal 9102 stored in the breast pocket of his clothing, the mobile information terminal 9102 Information 9053, displayed in a position visible from above, can also be viewed. The user can, You can check the display without taking the 9102 personal digital assistant out of your pocket, for example, to answer a phone call. It is possible to determine whether or not to do so.

[0431] Figure 22D is a perspective view showing a wristwatch-type personal information terminal 9200. Personal information terminal 92 00 can be used, for example, as a smartwatch. Also, the display unit 9001 is The display surface is curved, allowing the display to follow the curved surface. The personal information terminal 9200 communicates with, for example, a wireless communication headset. It also allows for hands-free calling. Furthermore, the 9200 mobile information terminal has a connection terminal 9 006 allows for mutual data transmission with other information terminals and also enables charging. Charging may also be performed via wireless power supply.

[0432] Figures 22E, 21F, and 21G show a perspective view of the foldable portable information terminal 9201. This is a diagram. Figure 22E shows the mobile information terminal 9201 in its unfolded state, and Figure 22G shows it in its folded state. In this state, Figure 22F is a perspective view of the intermediate state in which one of Figures 22E and 22G changes to the other. Yes. The 9201 personal digital assistant offers excellent portability when folded and is convenient when unfolded. The seamless, wide display area provides excellent readability of the display. The indicator part 9001 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. ru.

[0433] Figure 23A shows an example of a television system. The television system 7100 has a housing 710 The display unit 7500 is incorporated into 1. Here, the stand 7103 connects to the housing 710. This shows the configuration that supports option 1.

[0434] The television device 7100 shown in Figure 23A is operated by the operation switches provided on the housing 7101. This can be done by using the remote control unit 7111 or by using the display unit 7500. A touch panel can be applied to it, allowing the television device 7100 to be operated by touching it. The remote control unit 7111 may have a display unit in addition to the operation buttons.

[0435] The television equipment 7100 is a television broadcast receiver and for network connectivity. It may have a communication device.

[0436] Figure 23B shows the 7200 notebook personal computer. The Computer 7200 consists of a casing 7211, a keyboard 7212, and a pointing device 7 It has external connection ports 7214, etc. The display unit 7500 is incorporated into the housing 7211. It is being made.

[0437] Figures 23C and 23D show digital signage. An example of a small sign is shown.

[0438] The digital signage 7300 shown in Figure 23C consists of a housing 7301, a display unit 7500, and It has a speaker 7303, etc. Furthermore, it has an LED lamp, operation keys (power switch, or It may include an operating switch, connection terminals, various sensors, a microphone, etc. .

[0439] Figure 23D shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7500 that is installed along the curved surface of the column 7401. To possess.

[0440] The larger the display unit 7500, the more information can be provided at once, and the more human eyes... Because it is easily absorbed, it can, for example, enhance the effectiveness of advertising.

[0441] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. This means that it can be used not only for advertising purposes, but also for route information, traffic information, and commercial facility information, It can also be used to provide users with the information they are looking for.

[0442] As shown in Figures 23C and 23D, the Digital Signage 7300 or Digital Signage The Neige 7400 communicates wirelessly with the user's smartphone or other information terminal 7311. It is preferable that the information displayed on the display unit 7500 is linked. To display this on the screen of the information terminal 7311, or by operating the information terminal 7311 The display on the 7500 display unit can be switched.

[0443] Digital signage 7300 or digital signage 7400, information terminal 731 It is also possible to run a game using 1 as the control device (controller). A large number of users can participate in and enjoy the game simultaneously.

[0444] A display device according to one embodiment of the present invention is applied to the display unit 7500 in Figures 23A to 23D. It is possible.

[0445] Although the electronic device in this embodiment has a display unit, electronic devices that do not have a display unit can also be used. An embodiment of the present invention can also be applied.

[0446] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination. [Examples]

[0447] In this example, the etching rate of the material that can be used for the metal oxide layer 114 was evaluated. did.

[0448] For evaluation, samples (sample A1 to sa) in which a metal oxide film was formed on a glass substrate were used. I used a 3D A4 sheet.

[0449] The metal oxide film is an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1 The film was deposited by sputtering using [atomic ratio]. The substrate temperature during deposition was 100°C. In this study, oxygen gas (oxygen flow rate ratio 100%) was used as the film-forming gas. Four samples (sample A1 to samp) were prepared using different power supplies and pressures during film deposition. I created a sheet of paper (A4 size).

[0450] Sample A1 uses a power supply of 2.5 kW (AC) and a pressure of 0.3 Pa. Sample A2 uses a power supply of 2.5 kW (AC) and a pressure of 0.6 Pa. Sample A3 uses a power supply of 4.5 kW (AC) and a pressure of 0.3 Pa. Sample A4 uses a power supply of 4.5 kW (AC) and a pressure of 0.6 Pa. .

[0451] The etching rate was evaluated using the wet etching method. Oxalic acid was used as the etchant. A mixture of (5% or less), additive (concentration undisclosed), and water (95% or more) was used for etching. The etching temperature was set to 45°C. The etching rate was obtained by optical interferometry of the film thickness. It was calculated from the film thickness. Note that the etching rate shown in this example is in the direction of the metal oxide film thickness. This refers to the etching rate.

[0452] The etching rates (ER) for each sample are shown in Table 1. Table 1 shows the deposition rates of the metal oxide film. DR) is also indicated.

[0453] [Table 1]

[0454] As shown in Table 1, increasing the power supply during metal oxide film deposition results in... We were able to confirm that the etching rate of the metal oxide film tends to slow down. Also, when forming a metal oxide film... Lowering the pressure slows down the etching rate of the metal oxide film. The direction was confirmed. The power supply during metal oxide film deposition can be increased or the pressure decreased. This is thought to have increased the crystallinity of the metal oxide film, resulting in a slower etching rate. Oh, we were able to confirm that increasing the power supply during metal oxide film deposition tends to increase the deposition rate. No significant difference in deposition rate was observed depending on the pressure used during metal oxide film formation. [Examples]

[0455] In this embodiment, the sample corresponding to transistor 100 shown in Figure 1 (sample B1) Sample B4 was prepared, and its cross-sectional shape was evaluated.

[0456] For evaluation, samples were used in which an insulating layer, a metal oxide layer, and a conductive layer were formed on a glass substrate.

[0457] <Sample preparation> First, an insulating layer with a thickness of 150 nm was deposited on the glass substrate. The insulating layer was approximately 5 nm thick. A first silicon oxide nitride film of thickness m, a second silicon oxide nitride film with a thickness of approximately 140 nm, and thickness A third silicon oxidizride film, approximately 5 nm thick, was deposited using plasma CVD.

[0458] The deposition of the first silicon oxidizride film is performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 24 sccm and 18000 sccm, with a pressure of 200 Pa and a deposition power of 130 W, and the substrate was set to 18000 sccm. The temperature was set to 350°C.

[0459] The deposition of the second silicon oxidnitride film was performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 200 sccm and 4000 sccm, the pressure to 300 Pa, and the deposition power to 750 W, on a substrate. The temperature was set to 350°C.

[0460] The deposition of the third silicon oxidizride film involves controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rates were set to 20 sccm and 3000 sccm, with a pressure of 40 Pa, a deposition power of 500 W, and a substrate temperature of 20 sccm and 3000 sccm. The temperature was set to 350°C.

[0461] Next, a metal oxide film with a thickness of approximately 20 nm is deposited on the insulating layer by sputtering. The metal oxide film was deposited using an In-Ga-Zn oxide target (In:Ga:Zn=1 The deposition was carried out by sputtering using a 1:1 atomic ratio. The substrate temperature during film deposition was set to 1 The temperature was set to 0°C, and oxygen gas (oxygen flow rate ratio 100%) was used as the film-forming gas. Here, metal acid Four samples (samples B1 to s) were prepared using different power supplies and pressures during the deposition of the phosphate film. I created an ample B4.

[0462] Sample B1 uses a power supply of 2.5 kW (AC) and a pressure of 0.3 Pa. Sample B2 uses a power supply of 2.5 kW (AC) and a pressure of 0.6 Pa. Sample B3 uses a power supply of 4.5 kW (AC) and a pressure of 0.3 Pa. Sample B4 uses a power supply of 4.5 kW (AC) and a pressure of 0.6 Pa. .

[0463] Next, the material was subjected to a heat treatment at 350°C for 1 hour in a nitrogen-containing atmosphere.

[0464] Next, a conductive film was deposited on the metal oxide film. The conductive film was made of molybdenum with a thickness of approximately 100 nm. A butene film was deposited using the sputtering method.

[0465] Next, a resist pattern was formed on the conductive film.

[0466] Next, the conductive film was etched using the resist pattern as a mask to obtain a conductive layer. Dry etching was used for the etching process, and SF6 gas was used as the etching gas.

[0467] Next, the metal oxide film was etched to obtain a metal oxide layer. Wet etching was performed. An etching method was used. For details on the etching process, please refer to the description in Example 1. Omitted. Note that the etching time is for sample B1 to sample B4. Both times were set at 75 seconds.

[0468] <Cross-sectional observation of the sample> Next, samples B1 to B4 are subjected to a focused ion beam (FIB: Fo The section is thinned using a cused ion beam, and the cross-section is examined by scanning transmission electron microscopy (STE). M:Scanning Transmission Electron Microsc Observed using opy.

[0469] STEM images of cross-sections of samples B1 to B4 are shown in Figure 24. Image 24 is a transmission electron image (TE image) at a magnification of 100,000x, showing the electrons during the deposition of the metal oxide layer in the vertical direction. This indicates the power source, and the horizontal direction shows the pressure during film formation of the metal oxide layer. This shows (ure). Also, in Figure 24, the glass substrate is Glass and the insulating layer is Si ON, IGZO for the metal oxide layer, Mo for the conductive layer, and a P for the antistatic film used for cross-sectional observation. The platinum coating is denoted as Pt, and the carbon coating used as a protective layer is denoted as C. Furthermore, the width L is the difference in position between the edge of the conductive layer (Mo) and the edge of the metal oxide layer (IGZO). It shows a value of 2.

[0470] As shown in Figure 24, in all samples, the metal oxide layer is located at the edge of the conductive layer (Mo). It was confirmed that the edges of (IGZO) are located on the inside. Also, during the deposition of the metal oxide film We observed a tendency for the width L2 to decrease when the power supply power was increased. We observed a tendency for the width L2 to decrease when the pressure was reduced. Note that the metal shown in Example 1... We also confirmed that there is an almost linear correlation between the etching rate of the oxide film and its width L2.

[0471] As shown above, the width L2 can be controlled by varying the film deposition conditions for the metal oxide. It was discovered that... [Examples]

[0472] In this example, the sample corresponding to transistor 100A shown in Figure 5 (sample C1) Samples C3 through C3 were prepared, and their electrical properties and cross-sectional shape were evaluated.

[0473] <Sample preparation> The configuration of the fabricated transistor is based on the transistor 100A exemplified in Embodiment 1. can.

[0474] First, a tungsten film with a thickness of approximately 100 nm is formed on a glass substrate using the sputtering method. This was then processed to obtain the first gate electrode. Subsequently, the thickness of the first gate insulating layer was determined. A first silicon nitride film with a thickness of approximately 240 nm, a second silicon nitride film with a thickness of approximately 60 nm, and A silicon oxidoxide-nitride film approximately 3 nm thick was formed by layering using plasma CVD.

[0475] The deposition of the first silicon nitride film is carried out by controlling the flow rates of silane gas, nitrogen gas, and ammonia gas. The pressures were set to 290 sccm, 2000 sccm, and 2000 sccm respectively, and the pressure was set to 200 Pa. The film power was set to 3000W and the substrate temperature to 350°C.

[0476] The deposition of the second silicon nitride film is carried out by controlling the flow rates of silane gas, nitrogen gas, and ammonia gas. The pressures were set to 200 sccm, 2000 sccm, and 100 sccm respectively, and the pressure was 100 Pa for film deposition. The power was set to 2000W and the board temperature to 350°C.

[0477] The silicon oxidizride film is deposited by flowing silane gas and nitrous oxide gas at flow rates of 20 s. Set to ccm, 3000 sccm, pressure to 40 Pa, deposition power to 3000 W, substrate temperature to 3 The temperature was set to 50℃.

[0478] Next, a 40 nm thick metal oxide film is deposited on the first gate insulating layer, and then processed. A semiconductor layer was obtained. The metal oxide film was deposited using an In-Ga-Zn oxide target (In The deposition was carried out by sputtering using a Ga:Zn (atomic ratio: 1:1:1). The substrate temperature was set to 100°C. A mixed gas of oxygen and argon was used as the film deposition gas. The oxygen flow rate ratio was set to 50%. The power supply was set to 2.5 kW (AC), and the pressure was set to 0. The pressure was set to 0.6 Pa.

[0479] After the semiconductor layer is formed, it is subjected to a heat treatment at 350°C for 1 hour under a nitrogen gas atmosphere, The sample was heated at 350°C for 1 hour in a mixed atmosphere of nitrogen and oxygen gas.

[0480] Next, as the second gate insulating layer, a first silicon oxide nitride film with a thickness of approximately 5 nm, thickness A second silicon oxide nitride film with a thickness of approximately 140 nm, and a third silicon oxide nitride film with a thickness of approximately 5 nm. The films were deposited using plasma CVD.

[0481] The deposition of the first silicon oxidizride film is performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 24 sccm and 18000 sccm, with a pressure of 200 Pa and a deposition power of 130 W, and the substrate was set to 18000 sccm. The temperature was set to 350°C.

[0482] The deposition of the second silicon oxidnitride film was performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 200 sccm and 4000 sccm, the pressure to 300 Pa, and the deposition power to 750 W, on a substrate. The temperature was set to 350°C.

[0483] The deposition of the third silicon oxidizride film involves controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rates were set to 20 sccm and 3000 sccm, with a pressure of 40 Pa, a deposition power of 500 W, and a substrate temperature of 20 sccm and 3000 sccm. The temperature was set to 350°C.

[0484] Next, a metal oxide film was deposited on the second gate insulating layer by sputtering. Metal oxide films are deposited using an In-Ga-Zn oxide target (In:Ga:Zn=1:1 The deposition was carried out by sputtering using :1 [atomic ratio]. The substrate temperature during film formation was 100°C. The temperature was set to °C. Oxygen gas (oxygen flow rate ratio 100%) was used as the film-forming gas. Also, the power supply was set to °C. The power output was set to 4.5 kW (AC) and the pressure to 0.3 Pa. Here, the thickness of the metal oxide film was varied. Three samples (sample C1 to sample C3) were prepared.

[0485] Sample C1 had a metal oxide film thickness of 20 nm. Sample C2 was The thickness of the metal oxide film was set to 30 nm. Sample C3 had a metal oxide film thickness of 30 nm. The nm size was set to 40nm.

[0486] Subsequently, the material was heat-treated at 350°C for 1 hour in a nitrogen-containing atmosphere.

[0487] Next, a molybdenum film with a thickness of approximately 100 nm is sputtered onto the metal oxide film as a conductive film. The film was deposited using the ring method.

[0488] Next, a resist pattern was formed on the conductive film.

[0489] Next, the conductive film was etched using the resist pattern as a mask to obtain a conductive layer. Dry etching was used for the etching process, and SF6 gas was used as the etching gas.

[0490] Next, the metal oxide film was etched to obtain a metal oxide layer. Wet etching was performed. An etching method was used. For details on the etching process, please refer to the description in Example 1. Omitted. Note that the etching time is for sample C1 to sample C3. Both times were set at 75 seconds.

[0491] Next, using the conductive layer as a mask, boron was added as an impurity element. The addition of substances was performed using a plasma ion doping device. The gas used to supply boron was B2H6 gas was used.

[0492] Next, a silicon oxide-nitride film with a thickness of approximately 300 nm is applied as a protective insulating layer to cover the transistor. The film was deposited using plasma CVD.

[0493] The protective insulating layer is deposited using silane gas and nitrogen gas flow rates of 290 sccm and 400 sccm, respectively. The temperature was set to 0 sccm, the pressure to 133 Pa, the deposition power to 1000 W, and the substrate temperature to 350°C. .

[0494] Next, a portion of the protective insulating layer and the second gate insulating layer is opened by etching, and molybdenum After depositing the film by sputtering, it is processed to form the source electrode and drain electrode. An electrode was obtained. Subsequently, an acrylic film with a thickness of approximately 1.5 μm was formed as a planarization layer, under a nitrogen atmosphere. The following heat treatment was performed at a temperature of 250°C for 1 hour.

[0495] Through the above process, each of the transistors formed on the glass substrate is SAM We obtained sample C1 to sample C3.

[0496] <Cross-sectional observation of the sample> Next, the samples C1 to C3 prepared above are placed in a focused ion beam. The sample is thinned using a Focused Ion Beam (FIB), and the cross-section is scanned using a transmission electron beam (ESB). Microscope (STEM: Scanning Transmission Electron) Observed using a microscope.

[0497] <Transistor Id-Vg characteristics> Next, the Id-Vg characteristics of the transistor fabricated as described above were measured.

[0498] Measuring the Id-Vg characteristics of a transistor involves applying a voltage to the gate electrode (hereinafter referred to as gate voltage). A voltage (also called Vg) was applied in steps of 0.25V from -15V to +20V. Also, the voltage applied to the source electrode (hereinafter also called the source voltage (Vs)) is set to 0V (com Let m) be the voltage applied to the drain electrode (hereinafter also called drain voltage (Vd)), and set to 0 The voltages were set to 0.1V and 10V.

[0499] Transistor reliability Next, using the above transistor, a gate bias stress test was performed to evaluate its reliability. A Gate Bias Stress Test (GBT) was performed.

[0500] Here, the gate bias stress test (GBT) evaluates the reliability of the transistor. As one indicator, the characteristic changes of the transistor are evaluated by holding it with an electric field applied to the gate. It is worthwhile. Among gate bias stress tests (GBTs), source potential and drain potential In contrast, a test called PBTS (Pos) is performed by applying a positive potential to the gate and holding it at a high temperature. (Positive Bias Temperature Stress) test, negative voltage applied to the gate A test in which a position is applied and held at a high temperature is called NBTS (Negative Bias Test). This is called an emperor stress test. It also involves irradiating the subject with light such as white LED light. The PBTS test and NBTS test, which are performed under the following conditions, are referred to as PBTIS (Positiv e Bias Temperature Illumination Stress) test experiment, NBTIS (Negative Bias Temperature Illumi This is called the Nation Stress Test.

[0501] In particular, in n-type transistors using oxide semiconductors, the transistor is in the ON state. When the gate is set to a state where current is flowing, a positive potential is applied to it, therefore in PBTS testing... The fluctuation in key voltage is one of the important factors to consider as an indicator of transistor reliability. This is the result.

[0502] This embodiment describes the PBTS test and the NBTIS test. TIS testing involves holding the substrate on which the transistor is formed at 60°C and testing the transistor's sonar. Apply 0V to the drain and casing, and 20V or -20V to the gate, and maintain this state for 1 The test was held for a set time. The light irradiation in the NBTIS test was white LED at approximately 10,000 lux. D-light was used.

[0503] The Id-Vg characteristics and cross-sectional STEM image of the transistor in sample C1. This is shown in Figure 25. The Id-Vg characteristics and cross-sectional view of the transistor in sample C2 are shown. The STEM image is shown in Figure 26. The Id-Vg characteristics of the transistor in sample C3. Figure 27 shows the STEM images of the transistor in the vertical direction. The Id-Vg characteristics are shown under conditions with different channel lengths, specifically 2 μm and 3 μm. This shows two types of transistors with a channel width of 50 μm. Figures 25 to 27. In the Id-Vg characteristic, the horizontal axis shows the gate voltage (Vg), and the vertical axis shows the drain current (Id The Id-Vg characteristics of 10 transistors were measured for each sample, and the figure shows the results. Figures 25 through 27 show the Id-Vg characteristic results of 10 transistors superimposed on each other. It is. Furthermore, the bottom row of each of Figures 25 to 27 shows a STEM image of the cross-section. In the TEM image, the silicon nitride layer is SiN, the silicon oxide nitride layer is SiON, and the metal oxide The material layer is denoted as IGZO, and the conductive layer as Mo. Also, the edges of the conductive layer (Mo) and the metal oxide... This shows the width L2 value, which is the difference in position between the edges of the material layer (IGZO).

[0504] As shown in Figures 25 to 27, the width L2 tends to decrease as the metal oxide layer becomes thicker. This means that the width L2 can be controlled by varying the film thickness of the metal oxide. I understand.

[0505] As shown in Figures 25 to 27, good electrical characteristics were obtained in all samples. We were able to confirm that.

[0506] PBTS test and NBTIS test in sample C1 to sample C3 Figure 28 shows the change in threshold voltage (ΔVth) before and after the experiment. In Figure 28, the horizontal axis is The thickness of the metal oxide layer is shown, and the vertical axis shows the variation in threshold voltage (ΔVth).

[0507] As shown in Figure 28, in all samples, the threshold voltage fluctuation (ΔVth) is We were able to confirm that it is small and has good reliability. Also, the threshold voltage was determined by the thickness of the metal oxide layer. No difference was observed in the pressure fluctuation (ΔVth). [Examples]

[0508] In this example, the resistance of the metal oxide film was evaluated.

[0509] For the evaluation, a sample (sample D) in which a metal oxide film was formed on a glass substrate was used. The cross-sectional structure of sample D is shown in Figure 29.

[0510] <Sample preparation> First, a metal oxide film 214 with a thickness of 100 nm was deposited on the glass substrate 200. The oxide film 214 is deposited on an In-Ga-Zn oxide target (In:Ga:Zn=1: The deposition was carried out by sputtering using a 1:1 (atomic ratio) method. The substrate temperature during film deposition was set to 10 The temperature was set to 0°C. Oxygen gas (oxygen flow rate ratio 100%) was used as the film-forming gas. Also, the power supply was... The power output was set to 4.5 kW (AC), and the pressure to 0.3 Pa.

[0511] Subsequently, the material was heat-treated at 350°C for 1 hour in a nitrogen-containing atmosphere.

[0512] Next, a conductive film 212 was deposited on the metal oxide film 214. The conductive film 212 was made of a certain thickness. A molybdenum film approximately 50 nm thick was deposited by sputtering.

[0513] Next, an insulating film 218 was deposited on the conductive film 212. The insulating film 218 was made with a thickness of approximately 3 A 00 nm silicon oxidnitride film was deposited by plasma CVD. Deposition of insulating film 218 The flow rates of silane gas and nitrous oxide gas were set to 290 sccm and 4000 sccm, respectively. The pressure was set to 133 Pa, the deposition power to 1000 W, and the substrate temperature to 350°C.

[0514] Next, the insulating film 218 and the conductive film 212 were removed by dry etching. SF6 gas was used for the filtration.

[0515] Sample D was obtained through the above process.

[0516] <Resistance Measurement> In this example, the resistance of the metal oxide film 214 in the film thickness direction was evaluated. Specifically, the resistance of the metal oxide film 214 was evaluated. The thickness and resistance of the oxide film 214 are measured, and then a portion of the surface side of the metal oxide film 214 is etched. The process of removing the film by ching to reduce the thickness, then measuring the film thickness and resistance again, was repeated.

[0517] The sheet resistance of the metal oxide film 214 is shown in Figure 30. In Figure 30, the horizontal axis is the metal oxide film. The film thickness of material film 214 is shown, and the sheet resistance is shown on the vertical axis.

[0518] As shown in Figure 30, the metal oxide film 214 extends from the surface to a depth of approximately 80 nm. The resistance is 1 × 10 3 It was found that the resistance was low, less than Ω / □. The metal oxide film 214 was approximately 8 We were able to confirm that it functions as a conductive film even when its thickness is around 0 nm. [Examples]

[0519] In this embodiment, the sample corresponding to transistor 100 shown in Figure 1 (sample E1) Sample E4) was prepared and its cross-sectional shape was evaluated. Here, the protective insulating layer was... The film type and deposition conditions for the insulating layer corresponding to the margin layer 118 were varied.

[0520] The evaluation involved forming an insulating layer, a metal oxide layer, a conductive layer, and a protective insulating layer on a glass substrate. A special ingredient was used.

[0521] <Sample preparation> First, an insulating layer with a thickness of 150 nm was deposited on the glass substrate. The insulating layer was approximately 5 nm thick. A first silicon oxide nitride film of thickness m, a second silicon oxide nitride film with a thickness of approximately 140 nm, and thickness A third silicon oxidizride film, approximately 5 nm thick, was deposited using plasma CVD.

[0522] The deposition of the first silicon oxidizride film is performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 24 sccm and 18000 sccm, with a pressure of 200 Pa and a deposition power of 130 W, and the substrate was set to 18000 sccm. The temperature was set to 350°C.

[0523] The deposition of the second silicon oxidnitride film was performed by controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rate was set to 200 sccm and 4000 sccm, the pressure to 300 Pa, and the deposition power to 750 W, on a substrate. The temperature was set to 350°C.

[0524] The deposition of the third silicon oxidizride film involves controlling the flow rates of silane gas and nitrous oxide gas, respectively. The film deposition rates were set to 20 sccm and 3000 sccm, with a pressure of 40 Pa, a deposition power of 500 W, and a substrate temperature of 20 sccm and 3000 sccm. The temperature was set to 350°C.

[0525] Next, a metal oxide film with a thickness of approximately 20 nm is deposited on the insulating layer by sputtering. The metal oxide film was deposited using an In-Ga-Zn oxide target (In:Ga:Zn=1 The deposition was carried out by sputtering using a 1:1 atomic ratio. The substrate temperature during film formation was 1 The temperature was set to 0°C, and oxygen gas (oxygen flow rate ratio 100%) was used as the film-forming gas. Also, the power supply was... The power output was set to 4.5 kW (AC), and the pressure to 0.3 Pa.

[0526] Next, the material was subjected to a heat treatment at 350°C for 1 hour in a nitrogen-containing atmosphere.

[0527] Next, a conductive film was deposited on the metal oxide film. The conductive film was made of molybdenum with a thickness of approximately 100 nm. A butene film was deposited using the sputtering method.

[0528] Next, a resist pattern was formed on the conductive film.

[0529] Next, the conductive film was etched using the resist pattern as a mask to obtain a conductive layer. Dry etching was used for the etching process, and SF6 gas was used as the etching gas.

[0530] Next, the metal oxide film was etched to obtain a metal oxide layer. Wet etching was performed. An etching method was used. For details on the etching process, please refer to the description in Example 1. Omitted. Note that the etching time is for sample E1 to sample E4. Both times were set at 75 seconds.

[0531] Next, an insulating film with a thickness of approximately 300 nm is deposited as a protective insulating layer using plasma CVD. Here, four samples (sample E) were prepared with different protective insulating layer film types and deposition conditions. Samples 1 through E4 were prepared.

[0532] Sample E1 had a silicon oxide nitride film deposited as a protective insulating layer. The deposition of the ricon film was performed using silane gas and nitrous oxide gas flow rates of 290 sccm and 4 Assuming a pressure of 000 sccm, a deposition power of 133 Pa, a substrate temperature of 1000 W, and a substrate temperature of 350°C... did.

[0533] Sample E2 had a silicon oxide nitride film deposited as a protective insulating layer. The deposition of the ricon film was performed using silane gas and nitrous oxide gas flow rates of 150 sccm each. The pressure is set to 000 sccm, the deposition power to 200 Pa, the substrate temperature to 350°C. did.

[0534] Sample E3 had a silicon nitride film deposited as a protective insulating layer. The deposition of the ricon film involves controlling the flow rates of silane gas, nitrous oxide gas, nitrogen gas, and ammonia gas. The sizes are set to 150 sccm, 1000 sccm, 5000 sccm, and 100 sccm respectively. The pressure was set to 200 Pa, the deposition power to 2000 W, and the substrate temperature to 350°C.

[0535] Sample E4 had a silicon nitride film deposited as a protective insulating layer. The film deposition was carried out using silane gas, nitrogen gas, and ammonia gas flow rates of 150 sccm and 5 The film deposition capacity was set to 000 sccm and 100 sccm, the pressure to 200 Pa, and the deposition power to 2000 W, and the substrate was set to 100 sccm. The temperature was set to 350°C.

[0536] Through the above process, samples E1 to E4 were obtained.

[0537] <Cross-sectional observation of the sample> Next, samples E1 to E4 are subjected to a focused ion beam (FIB: Fo The section is thinned using a cused ion beam, and the cross-section is examined by scanning transmission electron microscopy (STE). M:Scanning Transmission Electron Microsc Observed using opy.

[0538] STEM images of cross-sections of samples E1 to E4 are shown in Figure 31. Figure 31 is a transmitted electron image (TE image) at a magnification of 100,000x. Also, in Figure 31, the glass substrate is The glass is labeled as having an insulating layer of SiON1, a conductive layer of Mo, and a metal oxide layer of IGZO. Furthermore, the protective insulating layer is made of silicon oxide nitride film (SiON2) and silicon nitride oxide film (SiNO The silicon nitride film is denoted as SiN.

[0539] In Figure 31, a pale color is observed between the conductive layer (Mo) and the metal oxide layer (IGZO). The region indicates a void. A sample using silicon oxynitride as a protective insulating layer. In sample E1 and sample E2, compared to sample E1, sample E2 has small voids and a protective insulating layer between the conductive layer (Mo) and the metal oxide layer (IGZO). It was found that (SiON2) was formed. By changing the film deposition conditions for the protective insulating layer... This allows us to control the size of the void between the conductive layer (Mo) and the metal oxide layer (IGZO). That's what I found out.

[0540] Compared to sample E1, sample using silicon nitride oxide as the protective insulating layer le E3 tended to have smaller voids. By using different types of protective insulating layers, the conductive layer It was found that the size of the void between (Mo) and the metal oxide layer (IGZO) can be controlled. .

[0541] In sample E4, which uses silicon nitride as the protective insulating layer, the protective insulating layer has porosity (Figure) The arrow in 31 was observed. [Explanation of Symbols]

[0542] C1: Capacity, C2: Capacity, DL_1: Data line, G1: Wiring, G2: Wiring, GL_1: G Node line, M1: transistor, M2: transistor, M3: transistor, N1: node N2: Node, P1: Region, P2: Region, S1: Routing, S2: Routing, T1: Period, T2 : Period, 100: Transistor, 100A: Transistor, 100B: Transistor, 1 00C: Transistor, 102: Substrate, 103: Insulating layer, 103a: Insulating layer, 103b: Insulating layer, 103c: insulating layer, 103d: insulating layer, 103i: region, 106: conductive layer, 10 8: Semiconductor layer, 108C: Region, 108f: Metal oxide film, 108L: Region, 108N: Region, 110: insulating layer, 110a: insulating layer, 110b: insulating layer, 110c: insulating layer, 11 0i: region, 112: conductive layer, 112f: conductive film, 114: metal oxide layer, 114f: gold 115: Oxide film, 116: Resist mask, 118: Insulating layer, 120a: Conductor Electrode layer, 120b: conductive layer, 130: void, 140: impurity element, 141a: opening, 14 1b: Opening, 142: Opening, 150: Insulating area, 200: Glass substrate, 212: Conductive Film, 214: Metal oxide film, 218: Insulating film, 400: Pixel circuit, 400EL: Pixel circuit ,400LC: pixel circuit, 401: circuit, 401EL: circuit, 401LC: circuit, 501 : Pixel circuit, 502: Pixel section, 504: Drive circuit section, 504a: Gate driver, 504 b: Source driver, 506: Protection circuit, 507: Terminal section, 550: Transistor, 55 2: Transistor, 554: Transistor, 560: Capacitive element, 562: Capacitive element, 57 0: Liquid crystal element, 572: Light-emitting element, 700: Display device, 700A: Display device, 700B: Display device, 701: substrate, 702: pixel section, 704: source driver circuit section, 705: base Board, 706: Gate driver circuit section, 708: FPC terminal section, 710: Signal line, 711: Wiring section, 712: sealing material, 716: FPC, 717: IC, 721: source driver I C, 722: Gate driver circuit section, 723: FPC, 724: Printed circuit board, 730: Insulating film, 732: Sealing film, 734: Insulating film, 736: Colored film, 738: Light-shielding film, 740: Protective layer, 741: Protective layer, 742: Adhesive layer, 743: Resin layer, 744: Insulating layer, 745: Support substrate, 746: resin layer, 750: transistor, 752: transistor, 760: distribution Line, 770: Planarizing insulating film, 772: Conductive layer, 773: Insulating layer, 774: Conductive layer, 775 : Liquid crystal element, 776: Liquid crystal layer, 778: Spacer, 780: Anisotropic conductive film, 782: Light emission Element, 786: EL layer, 788: conductive film, 790: capacitive element, 6000: display module 6001: Upper cover, 6002: Lower cover, 6005: FPC, 6006: Display unit Placement, 6009: Frame, 6010: Printed circuit board, 6011: Battery, 6015: Light-emitting part, 6016: Light-receiving part, 6017a: Light-guiding part, 6017b: Light-guiding part, 6018: Light, 6500: Electronic device, 6501: Enclosure, 6502: Display unit, 6503: Power button, 65 04: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective component, 6511: Display panel, 6512: Optical component, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 65 18: Battery, 7100: Television equipment, 7101: Enclosure, 7103: Stand 7111: Remote control unit, 7200: Notebook personal computer, 7211: Enclosure, 7212: Keyboard, 7213: Pointing device, 7214: External connection Port, 7300: Digital signage, 7301: Enclosure, 7303: Speaker, 731 1: Information terminal, 7400: Digital signage, 7401: Pillar, 7500: Display unit, 8 000: Camera, 8001: Housing, 8002: Display unit, 8003: Operation buttons, 8004 : Shutter button, 8006: Lens, 8100: Viewfinder, 8101: Body, 8 102: Display unit, 8103: Button, 8200: Head-mounted display, 8201 : Mounting part, 8202: Lens, 8203: Main unit, 8204: Display unit, 8205: Cable , 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8 302: Display unit, 8304: Fixture, 8305: Lens, 9000: Housing, 9001: Front Display unit, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor S, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information 9053: Information, 9054: Information, 9055: Hinge, 9100: Television equipment, 9101: Mobile information terminal, 9102: Mobile information terminal, 9200: Mobile information terminal, 9201 Mobile information terminal

Claims

[Claim 1] It has a semiconductor layer, a first insulating layer, a metal oxide layer, a conductive layer, and an insulating region. The first insulating layer covers the upper and side surfaces of the semiconductor layer. The conductive layer is located on the first insulating layer, The metal oxide layer is located between the first insulating layer and the conductive layer. The end of the metal oxide layer is located inward from the end of the conductive layer. The insulating region is adjacent to the metal oxide layer and located between the first insulating layer and the conductive layer. The semiconductor layer has a first region, a pair of second regions, and a pair of third regions. The first region overlaps with the metal oxide layer and the conductive layer, The second region encloses the first region and overlaps with the insulating region and the conductive layer. The third region sandwiches the first region and the pair of second regions and does not overlap with the conductive layer. The third region includes a portion that has lower resistance than the first region. The semiconductor device includes a portion of the second region that has higher resistance than the third region.

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