Nitride semiconductor equipment

Abstract

The present invention provides a nitride semiconductor device that can introduce Mg at a high concentration while keeping the threshold low. [Solution] The normally-off transistor of the nitride semiconductor device has a gate insulating film provided on the first surface side of the nitride semiconductor substrate, a gate electrode provided on the gate insulating film, a p-type layer facing the gate electrode with the gate insulating film in between, and an n-type layer facing the gate electrode with the p-type layer in between and in contact with the p-type layer. The Mg concentration of the p-type layer is 1 × 10 18 cm -3 The above 1 x 10 20 cm -3 The following applies: The effective acceptor concentration in the p-type layer is Np(cm -3 Let the thickness of the p-type layer be dp (nm), and the effective donor concentration of the n-type layer be Nn (cm³). -3 If we assume that the thickness of the n-type layer is dn (nm), then equations (1) and (2) hold true, respectively.

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a field-effect transistor formed on a SiC substrate. The channel region of this field-effect transistor consists of a p-type gate semiconductor region, an n-type embedded channel region, and a p-type body semiconductor region. Non-Patent Document 1 discloses a DioMOS provided on a SiC substrate. In this DioMOS, the channel region on the surface is formed with N-type delta doping. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2003-31802 [Non-patent literature]

[0004] [Non-Patent Document 1] MRS BULLETIN·VOLUME40·MAY 2015·www.mrs.org / bulletin ■425-430 [Overview of the project] [Problems that the invention aims to solve]

[0005] In MOSFETs formed on a GaN substrate, a large number of hole traps exist at the interface between the GaN substrate and the gate insulating film. These hole traps can be deactivated by introducing a high concentration of Mg at the interface. However, introducing a high concentration of Mg, which acts as an acceptor, raises the threshold voltage of the MOSFET too high, making it impractical. This disclosure aims to provide a nitride semiconductor device that can introduce a high concentration of Mg while keeping the threshold voltage low. [Means for solving the problem]

[0006] To solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure comprises a nitride semiconductor substrate and a normally-off transistor provided on the nitride semiconductor substrate. The transistor has a gate insulating film provided on the first surface side of the nitride semiconductor substrate, a gate electrode provided on the gate insulating film, a p-type layer facing the gate electrode with the gate insulating film in between, and an n-type layer facing the gate electrode with the p-type layer in between and in contact with the p-type layer. The Mg concentration of the p-type layer is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following applies: In the p-type layer, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). -3 Let the thickness of the p-type layer be dp (nm), and let the effective donor concentration obtained by offsetting the acceptor concentration from the donor concentration in the n-type layer be Nn (cm³). -3 If we assume that the thickness of the n-type layer is dn (nm), then the following equations (1) and (2) hold true, respectively.

[0007]

number

[0008] According to one aspect of this disclosure, it is possible to provide a nitride semiconductor device that can introduce Mg at a high concentration while keeping the threshold low. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a cross-sectional view showing an example configuration of a normally-off lateral MOSFET according to the present disclosure. [Figure 2] Figure 2 is a cross-sectional view showing a p+-type well region, an n+-type layer, and an enlarged view of the p+-type layer. [Figure 3]Figure 3 shows the results of a simulation performed by the Discloser, and is a graph showing the relationship between the effective acceptor concentration of the p+ type layer and the thickness of the n+ type layer. [Figure 4] Figure 4 shows the results of a simulation performed by the Discloser, and is a graph showing the relationship between the effective acceptor concentration of the p+-type layer and the thickness of the p+-type layer. [Figure 5] Figure 5 is a cross-sectional view showing a modified example of a horizontal MOSFET according to Embodiment 1 of this disclosure. [Figure 6] Figure 6 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET according to Embodiment 2 of this disclosure. [Figure 7] Figure 7 is a cross-sectional view showing a modified example of a vertical MOSFET according to Embodiment 2 of this disclosure. [Figure 8] Figure 8 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET according to Embodiment 3 of this disclosure. [Figure 9] Figure 9 is a cross-sectional view showing a modified example of a vertical MOSFET according to Embodiment 3 of this disclosure. [Figure 10] Figure 10 is a cross-sectional view showing an example configuration of a normally-off vertical MOSFET according to Embodiment 4 of this disclosure. [Figure 11] Figure 11 is a cross-sectional view showing an example of the configuration of a vertical MOSFET according to Embodiment 4 of this disclosure. [Figure 12] Figure 12 is a plan view showing an example of the configuration of a vertical MOSFET according to Embodiment 4 of this disclosure. [Figure 13] Figure 13 is a cross-sectional view showing a modified example of a vertical MOSFET according to Embodiment 4 of this disclosure. [Figure 14A] Figure 14A is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure, in order of steps. [Figure 14B] Figure 14B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure, in order of steps. [Figure 14C] Figure 14C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure, in order of steps. [Figure 14D]Figure 14D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure, in order of steps. [Figure 14E] Figure 14E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure, in order of steps. [Figure 14F] Figure 14F is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure, in order of steps. [Figure 15] Figure 15 is a graph showing a modified example 1 of the manufacturing method according to Embodiment 5. [Figure 16] Figure 16 is a graph showing a modified example 2 of the manufacturing method according to Embodiment 5. [Figure 17A] Figure 17A is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure, in order of steps. [Figure 17B] Figure 17B is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure, in order of steps. [Figure 17C] Figure 17C is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure, in order of steps. [Figure 17D] Figure 17D is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure, in order of steps. [Figure 17E] Figure 17E is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure, in order of steps. [Figure 17F] Figure 17F is a cross-sectional view showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure in order of steps. [Figure 18] Figure 18 is a cross-sectional view showing an example of the configuration of a normally-off IGBT according to Embodiment 7 of this disclosure. [Figure 19] Figure 19 is a cross-sectional view showing a modified example of an IGBT according to Embodiment 7 of this disclosure. [Modes for carrying out the invention]

[0010] Embodiments of the present disclosure are described below. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thickness of each device and component, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0011] Furthermore, in the following explanation, the terms X-axis, Y-axis, and Z-axis may be used to describe directions. For example, the X-axis and Y-axis directions are parallel to the surface 10a of the GaN substrate 10, which will be described later. The Z-axis direction is perpendicular to the surface 10a of the GaN substrate 10. The X-axis, Y-axis, and Z-axis directions are mutually orthogonal.

[0012] Furthermore, in the following explanation, the direction of the Z-axis arrow may be referred to as "up," and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of this disclosure. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0013] Furthermore, in the following explanation, the + and - attached to p and n indicating conductivity types mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - attached. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of each semiconductor region are exactly the same.

[0014] <Embodiment 1> Figure 1 is a cross-sectional view showing an example configuration of a normally-off lateral MOSFET 1 (an example of a "transistor" in this disclosure) according to an embodiment of this disclosure. Normally-off characteristics mean that when no voltage is applied to the gate electrode, there is no channel and no drain current flows. As shown in Figure 1, the lateral MOSFET 1 is provided on a gallium nitride substrate (an example of a "nitride semiconductor" in this disclosure; hereinafter referred to as a GaN substrate) 10. The lateral MOSFET 1 includes a gate insulating film 42 provided on the surface 10a (an example of the "first surface" in this disclosure) side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+ type well region 23 provided on the GaN substrate 10, an n+ type source region 26 and drain region 27 provided on the surface of the well region 23 and in its vicinity, below both sides of the gate electrode 44, a p+ type contact region 25 provided on the surface 10a of the GaN substrate 10 and in contact with the well region 23, a source electrode 54 provided on the surface 10a side of the GaN substrate 10 and in contact with the source region 26 and the contact region 25, and a drain electrode 56 provided on the surface 10a side of the GaN substrate 10 and in contact with the drain region 27. The surfaces of the well region 23, the contact region 25, the source region 26, and the drain region 27 are also the surface 10a of the GaN substrate 10.

[0015] The GaN substrate 10 is, for example, a GaN single crystal substrate. The GaN substrate 10 is, for example, an N-type substrate. The GaN substrate 10 has a surface 10a and a back surface located on the opposite side of surface 10a. For example, the GaN substrate 10 has a threading dislocation density of 1 × 10⁻⁶ 7 cm -2 This is a low-dislocation self-supporting GaN substrate with a dislocation count of less than [value missing].

[0016] The donor (N-type impurity) contained in the GaN substrate 10 may be one or more elements such as Si (silicon), Ge (germanium), and O (oxygen). The acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more elements such as Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

[0017] Because the GaN substrate 10 is a low-dislocation self-supporting GaN substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This makes it possible to manufacture power devices with a high yield rate. In addition, during the heat treatment included in the manufacturing process of the lateral MOSFET 1, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0018] The GaN substrate 10 may include a GaN single crystal substrate and a single crystal GaN layer epitaxially grown on the GaN single crystal substrate. In this case, the GaN single crystal substrate may be N+ type or N type, and the GaN layer may be N type or N- type. Furthermore, the surface 10a of the GaN substrate 10 may be a polar surface, the C-plane (Ga-plane), or it may be a non-polar surface, the m-plane.

[0019] In the lateral MOSFET 1, the semiconductor material is GaN, but the semiconductor material may also contain one or more elements such as aluminum (Al) and indium (In). The semiconductor material may also be a mixed crystal semiconductor containing trace amounts of Al and In, i.e., AlxInyGa1-x-yN (0≦x<1, 0≦y<1). Note that GaN is the case where x=y=0 in AlxInyGa1-x-yN.

[0020] The P+ type well region 23 is provided in the depth direction (for example, in the opposite direction to the Z-axis arrow) from the surface 10a of the GaN substrate 10. For example, the well region 23 is formed by ion implantation of acceptor elements (P-type impurities) to a predetermined depth from the surface 10a of the GaN substrate 10, and activation of the acceptor elements by heat treatment. Alternatively, the P+ type well region 23 may be formed by epitaxial growth on the N-type GaN single crystal substrate or N-type GaN layer of the GaN substrate 10.

[0021] The contact region 25 is a region where acceptor elements are ion-implanted to a predetermined depth from the surface of the well region 23 and the acceptor elements are activated by heat treatment. The contact region 25 is a P+ type region. The contact region 25 has a higher concentration of acceptor elements than the well region 23. Alternatively, the contact region 25 and the well region 23 may have the same concentration of acceptor elements. In that case, the contact region 25 is a part of the well region 23 and may be formed simultaneously with the well region 23 in the same process. The well region 23 and the contact region 25 contain at least one of Mg and Be as acceptor elements.

[0022] For example, the well region 23 and the contact region 25 contain Mg as an acceptor element. The Mg concentration in the well region 23 is 1×10 17 cm -3 or more and 1×10 20 cm -3 or less, and preferably 1×10 19 cm -3 or more and 1×10 20 cm -3 or less. Taking an example, it is 1×10 19 cm -3 . Also, the Mg concentration in the contact region 25 is 1×10 18 cm -3 or more and 2×10 20 cm -3 or less.

[0023] The source region 26 and the drain region 27 are regions where donor elements (N-type impurities) are ion-implanted to a predetermined depth from the surface 10a of the well region 23 and the donor elements are activated by heat treatment. The source region 26 and the drain region 27 are N+ type regions. The source region 26 and the drain region 27 have the same concentration of donor elements. The source region 26 and the drain region 27 are formed simultaneously in the same process. The source region 26 and the drain region 27 contain at least one of Si, Ge, and O as donor elements. For example, the source region 26 and the drain region 27 contain Si as the donor element. The Si concentrations in the source region 26 and the drain region 27 are 1 × 10⁻⁶ each. 19 cm -3 The above 5 x 10 20 cm -3 The following applies:

[0024] The gate insulating film 42 is, for example, a silicon oxide film (SiO2 film). The thickness of the gate insulating film 42 is, for example, 50 nm to 100 nm. The gate insulating film 42 is provided, for example, on a flat surface 10a. The gate electrode 44 is provided on the gate insulating film 42. For example, the gate electrode 44 is a planar type provided on a flat gate insulating film 42. The gate electrode 44 is made of, for example, polysilicon doped with impurities.

[0025] The source electrode 54 and the drain electrode 56 are provided on the surface 10a of the GaN substrate 10, respectively. The source electrode 54 is in contact with the source region 26 and the contact region 25. The drain electrode 56 is in contact with the drain region 27. The source electrode 54 and the drain electrode 56 are made of, for example, an Al or Al-Si alloy. The source electrode 54 and the drain electrode 56 may have a barrier metal layer between the surface 10a of the GaN substrate 10 and the Al (or Al-Si). Titanium (Ti) may be used as the material for the barrier metal layer.

[0026] Figure 2 is an enlarged cross-sectional view showing a p+ type well region 23, an n+ type layer 31 (an example of the "n-type region" in this disclosure), and a p+ type layer 32 (an example of the "p-type region" in this disclosure). As shown in Figures 1 and 2, the lateral MOSFET 1 further includes an n+ type layer 31 and a p+ type layer 32. The p+ type layer 32 is positioned opposite the gate electrode 44 with the gate insulating film 42 in between, and the n+ type layer 31 is positioned opposite the gate electrode 44 with the p+ type layer 32 in between. For example, the n+ type layer 31 and the p+ type layer 32 are arranged in this order from the well region 23 toward the gate electrode 44.

[0027] The n+ type layer 31 is sandwiched between the p+ type well region 23 and the p+ type layer 32. The n+ type layer 31 is in contact with the well region 23 and the p+ type layer 32 in its thickness direction (for example, the Z-axis direction). In addition, the n+ type layer 31 is in contact with the source region 26 and the drain region 27 in its thickness direction (for example, the Z-axis direction) or in a direction intersecting that thickness direction (for example, the X-axis direction). Figure 1 illustrates the case where the n+ type layer 31 is in contact with the source region 26 and the drain region 27 in the X-axis direction (i.e., in contact with the side surface of the source region 26 and the side surface of the drain region 27).

[0028] The n+-type layer 31 contains a donor element (e.g., Si, Ge, or O). The n+-type layer 31 is formed by ion implanting the donor element (e.g., Si, Ge, or O) into the surface 10a side of the GaN substrate 10 and activating the donor element by heat treatment. Alternatively, the n+-type layer 31 may be formed by epitaxial growth of an n-type GaN layer containing the donor element.

[0029] The p+-type layer 32 is a high-mg concentration layer containing a high concentration of Mg as an acceptor element. The Mg concentration of the p+-type layer 32 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following is true: 1 × 10 19 cm -3 The above 1 x 10 20 cm -3 The following is preferable: The p+-type layer 32 may be formed by ion implanting Mg into the surface 10a side of the GaN substrate 10 and activating the Mg by heat treatment. Alternatively, the p+-type layer 32 may be formed by epitaxial growth of a p-type GaN layer containing Mg.

[0030] Let Np be the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration in the p+ layer 32. Let dp be the thickness of the p+ layer 32. Also, let Nn be the effective donor concentration obtained by offsetting the acceptor concentration from the donor concentration in the n+ layer 31. Let dn be the thickness of the n+ layer 31. In this case, equations (1) and (2) below hold true.

[0031]

number

[0032] When equation (2) holds, the p+-type layer 32 is completely depleted when the bias to the gate electrode 44 (gate bias) is 0V. This makes it easy to change the potential of the n+-type layer 31 when the gate bias is greater than 0V. To explain in more detail, the potential of the n+-type layer 31 cannot be changed unless the p+-type layer 32 is depleted. In order to change the potential of the n+-type layer 31, it is necessary to deplete the p+-type layer 32 with the gate bias, which leads to an increase in the threshold voltage (Vth) of the MOSFET. However, when equation (2) holds, the p+-type layer 32 is completely depleted with a gate bias of 0V, so it is not necessary to allocate the gate bias to completely deplete the p+-type layer 32. This makes it possible to change the potential of the n+-type layer 31 with a low gate bias, and thus keep the threshold voltage of the MOSFET low.

[0033] Furthermore, when equation (2) and equation (1) hold, the n+ type layer 31 is completely depleted when the gate bias is 0V. When the gate bias is 0V, the n+ type layer 31 is completely depleted and no drain current flows, so the MOSFET exhibits normally-off characteristics.

[0034] In equation (1), the thickness dn of the n+-type layer 31 is set to be thicker than 3 nm. Similarly, in equation (2), the thickness dp of the p+-type layer 32 is set to be thicker than 3 nm. This is for manufacturing reasons. With current manufacturing technology, there are limitations to thinning (reducing the thickness of the layer), and it is considered that a thickness of 3 nm or more is necessary for the stable production of the n+-type layer 31 and the p+-type layer 32. If future advancements in manufacturing technology make it possible to stably thin (reduc the thickness of the layer) to 3 nm or less, the left-hand terms in equations (1) and (2) may be 2 nm, for example, instead of 3 nm.

[0035] Figure 3 is a graph showing the relationship between the effective acceptor concentration Np of the p+ type layer 32 and the thickness dn of the n+ type layer 31, based on the results of a simulation performed by the Discloser. Figure 4 is a graph showing the relationship between the effective acceptor concentration Np of the p+ type layer 32 and the thickness dp of the p+ type layer 32, based on the results of a simulation performed by the Discloser. As shown in Figures 3 and 4, in this simulation, the effective acceptor concentration Np of the p+ type layer 32 is set to 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 20 cm -3 The following settings were used. Furthermore, the effective donor concentration Nn in the n+ layer 31 was set to 1.0 × 10⁻⁶. 18 cm -3 , 3.0×10 18 cm -3 , 1.0 × 10 19 cm -3 , 3.0×10 19 cm -3 , 1.0 × 10 20 cm -3 The settings were determined using the following five conditions. These settings were applied to equations (1) and (2) to obtain Figures 3 and 4.

[0036] Note that in Figure 3, Nn = 1.0 × 10 18 cm -3 , 3.0×10 18 cm -3 , 1.0 × 10 19 cm -3 For the three conditions, Np is 1.0 × 10 18 cm -3 The above 1.0 × 1020 cm -3 In the entire range below, since dn is larger than 10 nm, its illustration is omitted. Also, "E+" described in FIGS. 3 and 4 indicates a power of 10.

[0037] In this embodiment (Embodiment 1 and Embodiments 2 to 6 described later), the effective acceptor concentration Np of the p+-type layer 32 (for example, the effective Mg concentration obtained by canceling donor elements from the Mg concentration) is 1.0×10 18 cm -3 or more and 1.0×10 20 cm -3 or less. In this case, as shown in FIG. 3, the thickness dn of the n+-type layer 31 is thicker than 3 nm and within a range smaller than each curve for each Nn. Similarly, the thickness dp of the p+-type layer 32 is thicker than 3 nm and within a range smaller than each curve for each Nn.

[0038] As an example of this embodiment, assume a case where Np = 1.0×10 20 cm -3 and Nn = 1.0×10 20 cm -3 . In this assumption, as shown by the arrow in FIG. 3, when the thickness dn of the n+-type layer 31 is thicker than 3 nm and thinner than 8 nm, equations (1) and (2) hold. Similarly, in this assumption, as shown by the arrow in FIG. 4, when the thickness dp of the p+-type layer 32 is thicker than 3 nm and thinner than 4 nm, equations (1) and (2) hold. That is, when Np = 1.0×10 20 cm -3 and Nn = 1.0×10 20 cm -3 , 3 nm < dn < 8 nm and 3 nm < dp < 4 nm are the ranges of this embodiment.

[0039] As another example, when Np = 1.0×10 19 cm -3 and Nn = 1.5×10 18 cm -3 , 3 nm < dn < 88 nm and 3 nm < dp < 7 nm are the ranges of this embodiment. Also, when Np = 1.0×10 19 cm -3 and Nn = 5.0×10 18 cm-3 In the case of, 3 nm < dn < 42 nm, 3 nm < dp < 11 nm are within the scope of this embodiment. Furthermore, Np = 1.0×10 19 cm -3 , Nn = 1.5×10 19 cm -3 In the case of, 3 nm < dn < 19 nm, 3 nm < dp < 14 nm are within the scope of this embodiment.

[0040] In addition, in this embodiment (Embodiment 1 and Embodiments 2 to 6 described later), in addition to the above formulas (1) and (2), it is preferable that the following formula (3) holds. dp×Np - dn×Nn < 1×10 18 ×(dp + dn)…(3) Thereby, the effective surface concentrations of the n+-type layer 31 and the p+-type layer 32 can be made below a certain level (the average acceptor concentration is 1×10 18 cm -3 or less), and the threshold value of the MOSFET can be made within a certain voltage range.

[0041] (Effect of Embodiment 1) As described above, the nitride semiconductor device according to Embodiment 1 of the present disclosure includes a GaN substrate 10 and a normally-off lateral MOSFET 1 provided on the GaN substrate 10. The lateral MOSFET 1 includes a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+-type layer 32 facing the gate electrode 44 with the gate insulating film 42 interposed therebetween, and an n+-type layer 31 facing the gate electrode 44 with the p+-type layer 32 interposed therebetween and contacting the p+-type layer 32. The Mg concentration of the p+-type layer 32 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less. Let the effective acceptor concentration of the p+-type layer 32 be Np (cm -3 ), the thickness of the p+-type layer 32 be dp (nm), the effective donor concentration of the n+-type layer 31 be Nn (cm -3 ), and the thickness of the n+-type layer 31 be dn (nm). Then, the above formulas (1) and (2) hold respectively.

[0042] According to this, the n+-type layer 31 becomes the channel of the lateral MOSFET 1. The n+-type layer 31 is completely depleted when the bias to the gate electrode 44 (i.e., the gate bias) is 0V, achieving normally-off operation. This allows for a low threshold voltage for the lateral MOSFET 1 while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0043] (modified version) Figure 5 is a cross-sectional view showing a modified example of the lateral MOSFET 1 according to Embodiment 1 of the present disclosure. As shown in Figure 5, the lateral MOSFET 1 may have multiple n+-type layers 31 and multiple p+-type layers 32. For example, if an n+-type layer 31 and a p+-type layer 32 are considered as one pair 30, then n (where n is an integer of 2 or more) of these pairs 30 may be stacked on top of each other at a position facing the gate electrode 44 with the gate insulating film 42 in between. That is, the n+-type layer 31 and the p+-type layer 32 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 5 illustrates the case where there are two pairs 30 of n+-type layer 31 and p+-type layer 32 (n=2).

[0044] In the modified example shown in Figure 5, equations (1) and (2) above also hold true. That is, in each of the multiple pairs 30 (hereinafter, each pair 30), the Mg concentration of the p+ type layer 32 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies to each pair 30. In each pair 30, the effective acceptor concentration of the p+ type layer 32 is Np, the thickness of the p+ type layer 32 is dp (nm), the effective donor concentration of the n+ type layer 31 is Nn, and the thickness of the n+ type layer 31 is dn. In this case, in each pair 30, the thickness dn of the n+ type layer 31 and the thickness dp of the p+ type layer satisfy equations (1) and (2) above, respectively. Thus, the modified example shown in Figure 5 also produces the same effects as the embodiment 1 described above.

[0045] <Embodiment 2> In the above-described Embodiment 1, a lateral MOSFET was shown as an example of the "transistor" of the present disclosure. However, the "transistor" of the present disclosure is not limited to the lateral type, and may be a vertical type. FIG. 6 is a cross-sectional view showing a configuration example of a normally-off vertical MOSFET 1A according to Embodiment 2 of the present disclosure. As shown in FIG. 6, the vertical MOSFET 1A is provided on a GaN substrate 10.

[0046] The GaN substrate 10 has, for example, an n+-type GaN single crystal substrate 11 and an n−-type GaN layer 22 provided on the GaN single crystal substrate 11. As shown in FIG. 6, the GaN substrate 10 has a back surface 10b on the opposite side of the front surface 10a. This back surface 10b is also the back surface of the GaN single crystal substrate 11. The n-type dopant contained in the GaN single crystal substrate 11 is one or more elements among Si (silicon), O (oxygen), and Ge (germanium), and an example is O. The impurity concentration of O in the GaN single crystal substrate 11 is 2×10 18 / cm 3 or more.

[0047] The GaN single crystal substrate 11 may be, for example, a low-dislocation free-standing GaN substrate having a threading dislocation density of less than 1×10 7 cm -2 −2. When the GaN single crystal substrate 11 is a low-dislocation free-standing substrate, the dislocation density of the GaN layer 22 formed on the GaN single crystal substrate 11 also becomes low. Further, by using a low-dislocation free-standing substrate for the GaN single crystal substrate 11, even when a large-area power device is formed on the GaN single crystal substrate 11, the leakage current in the power device can be reduced. Thereby, the manufacturing apparatus can manufacture the power device with a high yield. Also, in the heat treatment, it is possible to prevent the impurity implanted by ion implantation from diffusing deeply along the dislocations.

[0048] The GaN layer 22 is provided on the GaN single crystal substrate 11. The GaN layer 22 is an n-type GaN single crystal layer, formed on the GaN single crystal substrate 11 by epitaxial growth. The n-type dopant (n-type impurity) contained in the GaN layer 22 is one or more elements from Si (silicon), O (oxygen), and Ge (germanium), for example, O. Furthermore, the surface 10a of the GaN substrate 10 (i.e., the surface of the GaN layer 22) may be a polar surface, the C-plane (Ga-plane), or it may be a non-polar surface, the m-plane.

[0049] As shown in Figure 6, the vertical MOSFET 1A includes a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+ type well region 23 provided in the GaN layer 22, an n+ type source region 26 provided on the surface of the well region 23 and in its vicinity, below both sides of the gate electrode 44, a p+ type contact region 25 provided on the surface 10a side of the GaN substrate 10 and in contact with the well region 23, a source electrode 54 provided on the surface 10a side of the GaN substrate 10 and in contact with the source region 26 and the contact region 25, an interlayer insulating film 48 that insulates the space between the source electrode 54 and the gate electrode, and a drain electrode 56 provided on the back surface 10b side of the GaN substrate 10.

[0050] Furthermore, the vertical MOSFET 1A has an n-type JFET region 24 provided in the GaN layer 22. The JFET region 24 is provided in a position facing the gate electrode 44, for example, via a gate insulating film 42. The JFET region 24 faces the surface 10a of the GaN substrate 10 and is in contact with the n+-type layer 31 in the thickness direction of the vertical MOSFET 1A (for example, in the Z-axis direction). The JFET region 24 is also in contact with the well region 23 in a direction intersecting the thickness direction of the vertical MOSFET 1A (for example, in the X-axis direction). Figure 6 illustrates the case where the depth of the JFET region 24 from the surface 10a and the depth of the well region 23 from the surface 10a are the same, but the depth of the JFET region 24 from the surface 10a may be greater than the depth of the well region 23 from the surface 10a.

[0051] In the GaN layer 22, the region where the well region 23, source region 26, and contact region 25 are not provided may be called the drift region. The JFET region 24 is also part of the drift region. The drift region functions as a current path between the GaN single crystal substrate 11 and the well region 23.

[0052] As shown in Figure 6, the vertical MOSFET 1A has an n+ type layer 31 and a p+ type layer 32 between the surface 10a of the GaN substrate 10 and the gate insulating film 42. Similar to the horizontal MOSFET 1 shown in Figure 1, in the vertical MOSFET 1A shown in Figure 6, the p+ type layer 32 is positioned opposite the gate electrode 44 with the gate insulating film 42 in between. The n+ type layer 31 is positioned opposite the gate electrode 44 with the p+ type layer 32 in between. For example, the n+ type layer 31 and the p+ type layer 32 are arranged in this order from the well region 23 toward the gate electrode 44.

[0053] The n+ type layer 31 is sandwiched between the p+ type well region 23 and the p+ type layer 32. The n+ type layer 31 is in contact with the well region 23 and the p+ type layer 32 in its thickness direction (for example, the Z-axis direction). The n+ type layer 31 is also in contact with the source region 26 in its thickness direction (for example, the Z-axis direction) or in a direction intersecting its thickness direction (for example, the X-axis direction). Figure 6 illustrates the case where the n+ type layer 31 is in contact with the source region 26 in the Z-axis direction (i.e., in contact with the top surface of the source region 26).

[0054] Similar to the horizontal MOSFET 1 shown in Figure 1, the vertical MOSFET 1A shown in Figure 6 (and the vertical MOSFETs 1B and 1C described later) also contains a donor element (e.g., Si, Ge, or O) in the n+-type layer 31. The n+-type layer 31 is formed by ion implanting a donor element (e.g., Si, Ge, or O) into the surface 10a side of the GaN substrate 10 and activating the donor element by heat treatment. Alternatively, the n+-type layer 31 may be formed by epitaxial growth of an n-type GaN layer containing a donor element.

[0055] Also, in the vertical MOSFET 1A shown in FIG. 6 (and the vertical MOSFETs 1B and 1C described later), the p+-type layer 32 is a Mg high-concentration layer containing Mg at a high concentration as an acceptor element. The Mg concentration of the p+-type layer 32 is 1×10 18 cm -3 or more and 1×10 20 cm -3 or less, and it is preferably 1×10 19 cm -3 or more and 1×10 20 cm -3 or less. The p+-type layer 32 may be formed by ion-implanting Mg on the surface 10a side of the GaN substrate 10 and activating Mg by heat treatment. Alternatively, the p+-type layer 32 may be formed by epitaxially growing a p-type GaN layer containing Mg.

[0056] Also, in the vertical MOSFET 1A shown in FIG. 6, assuming the effective acceptor concentration of the p+-type layer 32 is Np and the effective donor concentration of the n+-type layer 31 is Nn, the thickness dn of the n+-type layer 31 and the thickness dp of the p+-type layer satisfy the above equations (1) and (2), respectively. Accordingly, the examples of the values of Np, dp, Nn, and dn in the lateral MOSFET 1 described with reference to FIGS. 3 and 4 are the same in the vertical MOSFET 1A shown in FIG. 6 (and the vertical MOSFETs 1B and 1C described later). For example, when Np = 1.0×10 20 cm -3 and Nn = 1.0×10 20 cm -3 , 3 nm < dn < 8 nm and 3 nm < dp < 4 nm are within the scope of this embodiment. Also, the numerical ranges given as "other examples" for Np, dp, Nn, and dn are the same.

[0057] Note that the nitride semiconductor device of the present disclosure may have a structure in which, for example, the vertical MOSFET 1A shown in FIG. 6 is used as one unit structure and this unit structure is repeatedly provided in one direction (for example, the X-axis direction). The same applies to Embodiments 3 to 6 described later. The vertical MOSFET 1B or 1C may be used as one unit structure, and this unit structure may be repeatedly provided in one direction.

[0058] (Effects of Embodiment 2) As described above, the nitride semiconductor device according to Embodiment 2 of the present disclosure comprises a GaN substrate 10 and a normally-off vertical MOSFET 1A provided on the GaN substrate 10. The vertical MOSFET 1A has a gate insulating film 42 provided on the surface 10a side of the GaN substrate 10, a gate electrode 44 provided on the gate insulating film 42, a p+ type layer 32 facing the gate electrode 44 with the gate insulating film 42 in between, and an n+ type layer 31 facing the gate electrode 44 with the p+ type layer 32 in between and in contact with the p+ type layer 32. The Mg concentration of the p+ type layer 32 is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following is the effective acceptor concentration of the p+ layer 32, Np(cm²). -3 Let the thickness of the p+-type layer 32 be dp (nm), and the effective donor concentration of the n+-type layer 31 be Nn (cm³). -3 If we assume that the thickness of the n+-type layer 31 is dn (nm), then equations (1) and (2) above will hold true.

[0059] According to this, the n+-type layer 31 becomes the channel of the vertical MOSFET 1A. The n+-type layer 31 is completely depleted when the gate bias is 0V, achieving normally-off operation. This allows for a low threshold voltage for the vertical MOSFET 1A while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0060] (modified version) (1) Figure 7 is a cross-sectional view showing a modified example of a vertical MOSFET 1A according to Embodiment 2 of the present disclosure. As shown in Figure 7, the vertical MOSFET 1A may have multiple n+ type layers 31 and multiple p+ type layers 32. For example, if an n+ type layer 31 and a p+ type layer 32 are considered as one pair 30, then n (n is an integer of 2 or more) of these pairs 30 may be stacked on top of each other at a position facing the gate electrode 44 with the gate insulating film 42 in between. That is, the n+ type layer 31 and the p+ type layer 32 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 7 illustrates the case where there are two pairs 30 of n+ type layer 31 and p+ type layer 32 (n=2).

[0061] In the modified example shown in Figure 7, equations (1) and (2) above also hold true. That is, in each pair 30, the Mg concentration of the p+ type layer 32 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies: In each pair 30, if the effective acceptor concentration of the p+ type layer 32 is Np and the effective donor concentration of the n+ type layer 31 is Nn, then the thickness dn of the n+ type layer 31 and the thickness dp of the p+ type layer in each pair 30 satisfy equations (1) and (2) above, respectively. As a result, the modified example shown in Figure 7 also exhibits the effects of the above embodiment 2.

[0062] (2) Figures 6 and 7 show an embodiment in which an n+ type layer 31 and a p+ type layer 32 are arranged on the JFET region 24. However, the n+ type layer 31 and the p+ type layer 32 do not necessarily have to be arranged on the JFET region 24. That is, the n+ type layer 31 and the p+ type layer 32 are arranged on the well region 23 and do not necessarily have to be arranged on the JFET region 24. In this case, an n-type region connecting the n+ type layer 31 and the JFET region 24 may be provided. Even in this embodiment, the effects of the above embodiment 2 are achieved.

[0063] (3) Figures 6 and 7 show an embodiment in which the vertical MOSFET 1A has a JFET region 24. However, the JFET region 24 is not required. In Figures 6 and 7, an n-type GaN layer 22 may be placed between one well region and the other adjacent well region in the X-axis direction instead of a JFET region. Even in this embodiment, the on-resistance will increase, but the effects of Embodiment 2 described above will be achieved.

[0064] (4) Figures 6 and 7 show an embodiment in which the n+-type layer 31 and the p+-type layer 32 are arranged on the surface 10a of the GaN substrate 10. However, the n+-type layer 31 and the p+-type layer 32 may be provided inside the GaN substrate 10, as in the lateral MOSFET 1 shown in Figure 1, rather than on the surface 10a of the GaN substrate 10. In this case, the n+-type layer 31 may be in contact with the side surface of the source region 26. Even in this embodiment, the effects of the above embodiment 2 are achieved.

[0065] (5) The p+ type contact region 25 may have the same acceptor concentration (or effective acceptor concentration) as the p+ type well region 23. In this case, the p+ type contact region 25 may be a part of the p+ type well region 23. That is, in Figures 6 and 7, the contact region 25 may be a part of the well region 23, and the source electrode 54 may be in contact with this part. Even in this configuration, the effects of the above embodiment 2 are achieved.

[0066] <Embodiment 3> In Embodiment 2 described above, a planar gate type vertical MOSFET was shown as an example of the "transistor" of the present disclosure. However, in embodiments of the present disclosure, the vertical MOSFET is not limited to the planar gate type, but may also be a trench gate type. Figure 8 is a cross-sectional view showing an example of the configuration of a normally-off vertical MOSFET 1B according to Embodiment 3 of the present disclosure. As shown in Figure 8, the vertical MOSFET 1B is a trench gate type and has a trench provided on the surface 10a side of the GaN substrate 10. A gate insulating film 42 is formed on the side and bottom surfaces of this trench. A gate electrode 44 is then arranged in the trench via the gate insulating film 42. The side surface of the trench may be the c-plane or the m-plane.

[0067] Furthermore, the vertical MOSFET 1B has a p+ type region 28 provided on the GaN substrate 10. The p+ type region 28 is located at the bottom of the trench. The depletion layer formed between the p+ type region 28 and the n- type GaN layer 22 can increase the breakdown voltage at gate-off.

[0068] As shown in Figure 8, the vertical MOSFET 1B has an n+ type layer 31 and a p+ type layer 32 between the GaN substrate 10 and the gate insulating film 42. On the trench side, the p+ type layer 32 is positioned opposite the gate electrode 44 with the gate insulating film 42 in between. The n+ type layer 31 is positioned opposite the gate electrode 44 with the p+ type layer 32 in between. For example, the n+ type layer 31 and the p+ type layer 32 are arranged in this order from the well region 23 toward the gate electrode 44 (i.e., from the well region 23 toward the trench).

[0069] The n+ type layer 31 is sandwiched between the p+ type well region 23 and the p+ type layer 32. The n+ type layer 31 is in contact with the well region 23 and the p+ type layer 32 in its thickness direction (in this example, the X-axis direction). In addition, the n+ type layer 31 is in contact with the source region 26 at one end and with the p+ type region 28 at the other end in a direction intersecting its thickness direction (in this example, the Z-axis direction).

[0070] (Effects of Embodiment 3) Similar to the horizontal MOSFET1 and vertical MOSFET1A described above, the vertical MOSFET1B shown in Figure 7 also has an effective acceptor concentration of the p+ type layer 32 set to Np(cm²). -3 Let the thickness of the p+-type layer 32 be dp (nm), and the effective donor concentration of the n+-type layer 31 be Nn (cm³). -3 If we assume that the thickness of the n+-type layer 31 is dn (nm), then equations (1) and (2) above hold true. According to this, the n+-type layer 31 becomes the channel of the vertical MOSFET 1B. The n+-type layer 31 becomes completely depleted when the gate bias is 0V, achieving normally-off operation. This allows for a low threshold voltage for the vertical MOSFET 1B while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0071] (modified version) (1) Figure 9 is a cross-sectional view showing a modified example of the vertical MOSFET 1B according to Embodiment 3 of the present disclosure. As shown in Figure 9, the vertical MOSFET 1B may have multiple n+ type layers 31 and multiple p+ type layers 32. For example, if an n+ type layer 31 and a p+ type layer 32 are considered as one pair 30, then n (n is an integer of 2 or more) of these pairs 30 may be stacked on top of each other at a position facing the gate electrode 44 with the gate insulating film 42 in between. That is, the n+ type layer 31 and the p+ type layer 32 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 9 illustrates the case where there are two pairs 30 of n+ type layer 31 and p+ type layer 32 (n=2).

[0072] In the modified example shown in Figure 9, equations (1) and (2) above also hold true. That is, in each pair 30, the Mg concentration of the p+ type layer 32 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3The following applies: In each pair 30, if the effective acceptor concentration of the p+ type layer 32 is Np and the effective donor concentration of the n+ type layer 31 is Nn, then the thickness dn of the n+ type layer 31 and the thickness dp of the p+ type layer in each pair 30 satisfy equations (1) and (2) above, respectively. As a result, the modified example shown in Figure 9 also exhibits the effects of the above embodiment 2.

[0073] <Embodiment 4> In embodiments of this disclosure, the vertical MOSFET may be a FinFET. In a FinFET, for example, the distance between one adjacent gate electrode and the other gate electrode in one direction (e.g., the X-axis direction) is shorter than that of a trench gate type. Figures 10 to 12 are cross-sectional and plan views showing an example configuration of a normally-off vertical MOSFET 1C according to Embodiment 4 of this disclosure. Figure 10 is a cross-sectional view obtained by cutting the plan view shown in Figure 12 along the line X1-X1'. Figure 11 is a cross-sectional view obtained by cutting the plan view shown in Figure 12 along the line X2-X2'. In Figure 12, the source electrode 54 is shown with a dashed line to clearly indicate the boundary between the n+ type source region 26 and the p+ type contact region.

[0074] The vertical MOSFET 1C shown in Figures 10 to 12 is a FinFET and has a trench provided on the surface 10a side of the GaN substrate 10. A gate insulating film 42 is formed on the side and bottom surfaces of this trench. A gate electrode 44 is then placed inside the trench via the gate insulating film 42. The side surface of the trench may be the c-plane or the m-plane.

[0075] Furthermore, the vertical MOSFET 1C has a fin portion. The fin portion is a part on the surface 10a side of the GaN substrate 10, and is a part sandwiched between one trench and the other adjacent trench in one direction (for example, in the X-axis direction). An n+ type layer 31 and a p+ type layer 32 are provided in this fin portion. For example, as shown in Figures 10 and 11, the fin portion is provided with an n+ type layer 31 and p+ type layers 32 located on both sides of the n+ type layer 31.

[0076] In the vertical MOSFET 1C, the p+ type layer 32 is positioned on the trench side facing the gate electrode 44, with the gate insulating film 42 in between. The n+ type layer 31 is positioned facing the gate electrode 44, with the p+ type layer 32 in between. The n+ type layer 31 is in contact with the p+ type layer 32 on both sides in its thickness direction (in this example, the X-axis direction). Furthermore, the n+ type layer 31 is in contact with the n+ type source region 26 or the p+ type well region 23 at one end in a direction intersecting its thickness direction (in this example, the X-axis direction) (in this example, the Z-axis direction), and in contact with the n- type GaN layer 22 (i.e., the drift region) at the other end.

[0077] (Effects of Embodiment 4) Similar to the horizontal MOSFET 1 and vertical MOSFETs 1A and 1B described above, the vertical MOSFET 1C shown in Figures 10 to 12 also has an effective acceptor concentration Np(cm³) in the p+ type layer 32. -3 Let the thickness of the p+-type layer 32 be dp (nm), and the effective donor concentration of the n+-type layer 31 be Nn (cm³). -3 Assuming that the thickness of the n+-type layer 31 is dn (nm), then equations (1) and (2) above hold true. According to this, the n+-type layer 31 becomes the channel of the vertical MOSFET 1C. The n+-type layer 31 becomes completely depleted when the gate bias is 0V, achieving normally-off operation. This allows for a low threshold voltage for the vertical MOSFET 1C while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0078] (modified version) Figure 13 is a cross-sectional view showing a modified example of a vertical MOSFET 1C according to Embodiment 4 of the present disclosure. As shown in Figure 13, the vertical MOSFET 1C may have multiple n+ type layers 31 and multiple p+ type layers 32. For example, if an n+ type layer 31 and a p+ type layer 32 are considered as one pair 30, then n (where n is an integer of 2 or more) of these pairs 30 may be stacked on top of each other. Figure 11 illustrates a case where two pairs 30 of n+ type layer 31 and p+ type layer 32 (n=2) and the remaining one p+ type layer 32 are provided in one fin section. The remaining one p+ type layer 32 may be a p+ type layer 32 that is in contact with the gate insulating film 42 in the direction of the arrow on the X axis, or a p+ type layer 32 that is in contact with the gate insulating film 42 in the opposite direction of the arrow on the X axis.

[0079] In the modified example shown in Figure 13, equations (1) and (2) above also hold true for the vertical MOSFET 1C. That is, in each pair 30, the Mg concentration of the p+ type layer 32 is 1 × 10⁻¹⁰ 18 cm -3 The above 1 x 10 20 cm -3 The following applies: In each pair 30, if the effective acceptor concentration of the p+ type layer 32 is Np and the effective donor concentration of the n+ type layer 31 is Nn, then the thickness dn of the n+ type layer 31 and the thickness dp of the p+ type layer in each pair 30 satisfy equations (1) and (2) above, respectively. Thus, the modified example shown in Figure 13 also achieves the effects of the above embodiment 2.

[0080] <Embodiment 5> As Embodiment 5 of this disclosure, a method for manufacturing a planar vertical MOSFET (vertical DMOS) will be described. Figures 14A to 14F are cross-sectional views showing the manufacturing method of a vertical MOSFET according to Embodiment 5 of this disclosure in order of steps. Vertical MOSFETs are manufactured using various devices such as a film deposition apparatus, an exposure apparatus, an ion implantation apparatus, an etching apparatus, and a heat treatment apparatus. Hereinafter, these devices will be collectively referred to as manufacturing apparatus.

[0081] As shown in Figure 14A, the manufacturing apparatus epitaxially grows an n-type GaN layer 22 on an n+-type GaN single crystal substrate 11. Next, as shown in Figure 14B, the manufacturing apparatus sequentially ion-implants acceptor elements (e.g., Mg) and donor elements (e.g., O, Si) into the GaN layer 22 using photolithography and ion implantation techniques, and then heat-treats the layer to form a p+-type well region 23, an n-type JFET region 24, a p+-type contact region 25, and an n+-type source region 26. In this example, the formation of the p+-type contact region 25 is shown, but the formation of the contact region 25 may be omitted. In this case, the p+-type well region 23 is extended to the position of the contact region 25.

[0082] Next, as shown in Figure 14C, the manufacturing apparatus epitaxially grows an n+-type layer 31 and a p+-type layer 32 on the surface 10a of the GaN substrate 10 in this order. Here, the Mg concentration of the p+-type layer 32 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following (preferably 1 × 10) 19 cm -3 The above 1 x 10 20 cm -3 The following conditions apply, and the effective donor concentration Nn(cm) in the n+ layer 31 is also the same. -3 ) and its thickness dn (nm), and the effective acceptor concentration Np (cm³) of the p+ type layer 32. -3 The n+-type layer 31 and the p+-type layer 32 are grown epitaxially in succession such that their thickness Nn (nm) satisfies the above equations (1) and (2).

[0083] Next, as shown in Figure 14D, the manufacturing apparatus sequentially forms a gate insulating film 42 and a gate electrode 44 on the p+ type layer 32. Then, as shown in Figure 14E, the manufacturing apparatus forms an interlayer insulating film 48 on the surface 10a side of the GaN substrate 10.

[0084] Next, as shown in Figure 14F, the manufacturing apparatus partially removes the interlayer insulating film 48, the gate insulating film 42, the p+ type layer 32, and the n+ type layer 31 in that order using photolithography and etching techniques to form contact holes H1 on the contact region 25 and the source region 26. Subsequently, the manufacturing apparatus forms a source electrode 54 (see Figure 6) on the surface 10a side of the GaN substrate 10 and brings the source electrode 54 into contact with the n+ type source region 26 and the p+ type well region 23. In addition, a drain electrode 56 (see Figure 6) is formed on the back surface 10b side of the GaN substrate 10 and brings the drain electrode 56 into contact with the n+ type GaN single crystal substrate 11. Through these steps, a planar vertical MOSFET as shown in Figure 6 is completed.

[0085] (modified version) (1) In the process of forming the n+-type layer 31 and the p+-type layer 32 shown in Figure 14C, the n+-type layer 31 and the p+-type layer 32 may be formed in multiple layers by alternating doping of a donor element (e.g., Si, O, or Ge) and an acceptor element (e.g., Mg) by epitaxial growth. Figure 15 is a graph showing a modified example 1 of the manufacturing method according to Embodiment 5. The horizontal axis of Figure 15 shows the depth from the surface of the epitaxially grown layer, and the vertical axis shows the concentration of the dopant element (e.g., Mg concentration, Si concentration). As shown in Figure 15, Si may be used as the donor element and Mg as the acceptor element, and Si and Mg may be alternately doped while epitaxially growing a GaN layer on the surface of the GaN substrate. This makes it possible to manufacture a planar gate type vertical MOSFET in which the n+-type layer 31 and the p+-type layer 32 are formed in multiple layers, as shown in Figure 7. During epitaxial growth, it is desirable for the donor and acceptor concentrations to be as steep as possible, but a concentration gradient of a few nanometers until the concentration becomes constant is also acceptable. In particular, a high Mg concentration at the outermost surface is desirable, so it is good to have a high concentration on the surface and a decreasing concentration towards the interior of the substrate.

[0086] (2) In the process of forming the n+-type layer 31 and p+-type layer 32 shown in Figure 14C, the n+-type layer 31 and p+-type layer 32 may be formed in multiple layers by combining doping of an acceptor element (e.g., Mg) by epitaxial growth and implantation of a donor element (e.g., Si, O, or Ge) by ion implantation. Figure 16 is a graph showing a modified example 2 of the manufacturing method according to Embodiment 5. The horizontal axis of Figure 16 shows the depth from the surface of the epitaxially grown layer, and the vertical axis shows the concentration of the dopant element (e.g., Mg concentration, Si concentration). As shown in Figure 16, a GaN layer may be formed by epitaxially growing a GaN layer on the surface of a GaN substrate while doping it with Mg at regular intervals. At this time, it is desirable for the concentration of the donor and acceptor to be as steep as possible during epitaxial growth, but it is also acceptable to have a concentration gradient of a few nanometers until the concentration becomes constant. In particular, a high Mg concentration on the outermost surface is desirable, so it is preferable to increase the concentration on the surface and decrease the concentration towards the interior of the substrate. Next, Si may be ion-implanted from the surface side of this GaN layer. After that, the GaN layer is heat-treated to activate the Si. Even with this method, a planar gate type vertical MOSFET with a multilayer structure of n+ type layer 31 and p+ type layer 32, as shown in Figure 7, can be manufactured.

[0087] <Embodiment 6> As Embodiment 6 of this disclosure, a method for manufacturing a trench gate type vertical MOSFET will be described. Figures 17A to 17F are cross-sectional views showing the manufacturing method of a vertical MOSFET according to Embodiment 6 of this disclosure in order of steps. As shown in Figure 17A, the manufacturing apparatus epitaxially grows an n-type GaN layer 22, a p-type GaN layer that will become a p-type well region 23, and an n-type GaN layer that will become an n-type source region 26 on an n-type GaN single crystal substrate 11 in this order.

[0088] Next, as shown in Figure 17B, the manufacturing apparatus uses photolithography and etching techniques to partially remove the GaN layer that will become the source region 26, the GaN layer that will become the well region 23, and the n-type GaN layer 22 in that order, thereby forming a trench H2. The trench H2 defines the p+-type well region 23. Next, as shown in Figure 17C, the manufacturing apparatus ion-implants an acceptor element (e.g., Mg) into the bottom surface of the trench H2 and applies heat treatment to form a p+-type region 28.

[0089] Next, as shown in Figure 17D, the manufacturing apparatus epitaxially grows the n+-type layer 31 and the p+-type layer 32 in that order on the bottom and sides of the trench H2. Here, the Mg concentration of the p+-type layer 32 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following (preferably 1 × 10) 19 cm -3 The above 1 x 10 20 cm -3 The following conditions apply, and the effective donor concentration Nn(cm) in the n+ layer 31 is also the same. -3 ) and its thickness dn (nm), and the effective acceptor concentration Np (cm³) of the p+ type layer 32. -3 The n+-type layer 31 and the p+-type layer 32 are grown epitaxially in succession such that their thickness Nn (nm) satisfies the above equations (1) and (2).

[0090] Next, as shown in Figure 17E, the manufacturing apparatus forms a gate insulating film 42 on the side and bottom surfaces of the trench. Then, the manufacturing apparatus forms a gate electrode 44 in the trench where the gate insulating film 42 has been formed. Next, as shown in Figure 17F, the manufacturing apparatus forms an interlayer insulating film 48 on the surface 10a side of the GaN substrate 10.

[0091] Next, the manufacturing apparatus partially removes the interlayer insulating film 48 using photolithography and etching techniques, thereby creating a GaN layer that becomes the N+ type source region 26 from beneath the interlayer insulating film 48. Next, the manufacturing apparatus partially removes the GaN layer that will become the N+ type source region 26 using photolithography and etching techniques. This defines the n+ type source region 26 and exposes the p+ type well region 23 from beneath the n+ type source region 26.

[0092] Subsequently, the manufacturing apparatus forms a source electrode 54 on the surface 10a side of the GaN substrate 10 and brings the source electrode 54 into contact with the n+ type source region 26 and the p+ type well region 23. Furthermore, a drain electrode 56 is formed on the back surface 10b side of the GaN substrate 10 and brings the drain electrode 56 into contact with the n+ type GaN single crystal substrate 11. Through these steps, a trench gate type vertical MOSFET as shown in Figure 8 is completed.

[0093] In Embodiment 6, modifications (1) or (2) of Embodiment 5 may also be applied. Specifically, the n+-type layer 31 and the p+-type layer 32 may be formed in multiple layers by alternating doping of a donor element (e.g., Si, O, or Ge) and an acceptor element (e.g., Mg) by epitaxial growth. Alternatively, the n+-type layer 31 and the p+-type layer 32 may be formed in multiple layers by combining doping of an acceptor element (e.g., Mg) by epitaxial growth and implantation of a donor element (e.g., Si, O, or Ge) by ion implantation. This makes it possible to manufacture a trench gate type vertical MOSFET in which the n+-type layer 31 and the p+-type layer 32 are formed in multiple layers, as shown in Figure 9.

[0094] <Embodiment 7> In Embodiment 1 described above, a lateral MOSFET was shown as an example of the "transistor" of this disclosure. In Embodiments 2 to 4 described above, a vertical MOSFET was shown as an example of the "transistor" of this disclosure. However, the "transistor" of this disclosure is not limited to a MOSFET, but may also be an IGBT. Figure 18 is a cross-sectional view showing an example configuration of a normally-off IGBT1D according to Embodiment 7 of this disclosure. As shown in Figure 18, the IGBT1D is provided on a GaN substrate 10.

[0095] In the IGBT1D shown in Figure 18, the differences from the vertical MOSFET1A shown in Figure 6 are that it has an n+ type emitter region 126 instead of a source region 26, an emitter electrode 154 instead of a source electrode 54, a collector electrode 156 instead of a drain electrode 56, and a p+ type collector layer 29 provided on the back side of the n+ type GaN single crystal substrate 11 (i.e., the back side 10b of the GaN substrate 10). The rest of the configuration is the same as the vertical MOSFET1A shown in Figure 6.

[0096] The emitter region 126 has the same configuration as the source region 26, the emitter electrode 154 has the same configuration as the source electrode 54, and the collector electrode 156 has the same configuration as the drain electrode 56.

[0097] The collector layer 29 is a p+ type GaN layer doped with p-type impurities such as Mg. The collector layer 29 is sandwiched between an n+ type GaN single crystal substrate 11 and a collector electrode 156, and is in contact with both the GaN single crystal substrate 11 and the collector electrode 156. The method for manufacturing the collector layer 29 is not particularly limited, but for example, it can be formed by epitaxial growth on the back surface of the GaN single crystal substrate 11.

[0098] Similar to the horizontal MOSFET 1 and vertical MOSFET 1A described above, the IGBT 1D shown in Figure 18 also has an n+ type layer 31 and a p+ type layer 32. In the IGBT 1D as well, the p+ type layer 32 is positioned opposite the gate electrode 44, with the gate insulating film 42 in between. The n+ type layer 31 is positioned opposite the gate electrode 44, with the p+ type layer 32 in between. For example, the n+ type layer 31 and the p+ type layer 32 are arranged in this order from the well region 23 toward the gate electrode 44.

[0099] (Effects of Embodiment 7) In Embodiment 7 of this disclosure, the Mg concentration of the p+ type layer 32 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 20 cm -3 The following are preferred, preferably 1 × 1019 cm -3 The above 1 x 10 20 cm -3 The following is the effective acceptor concentration of the p+ layer 32, Np(cm²). -3 Let the thickness of the p+-type layer 32 be dp (nm), and the effective donor concentration of the n+-type layer 31 be Nn (cm³). -3 If we assume that the thickness of the n+-type layer 31 is dn (nm), then equations (1) and (2) above will hold true.

[0100] According to this, the n+-type layer 31 becomes the channel of the IGBT1D. The n+-type layer 31 is completely depleted when the gate bias is 0V, achieving normally-off operation. This allows for a low threshold voltage for the IGBT1D while introducing a high concentration of Mg at the interface between the GaN substrate 10 and the gate insulating film 42, thereby inactivating hole traps present at this interface.

[0101] (modified version) Figure 19 is a cross-sectional view showing a modified example of the IGBT 1D according to Embodiment 7 of the present disclosure. As shown in Figure 19, the IGBT 1D may have multiple n+-type layers 31 and multiple p+-type layers 32. For example, if an n+-type layer 31 and a p+-type layer 32 are considered as one pair 30, then n (where n is an integer greater than or equal to 2) of these pairs 30 may be stacked and arranged opposite the gate electrode 44 with the gate insulating film 42 in between. That is, the n+-type layer 31 and the p+-type layer 32 may be repeatedly arranged in this order from the well region 23 toward the gate electrode 44. Figure 19 illustrates the case where there are two pairs 30 of n+-type layer 31 and p+-type layer 32 (n=2). In the modified example shown in Figure 19, equations (1) and (2) above also hold true for each pair 30. Thus, the modified example shown in Figure 19 also produces the same effects as Embodiment 7 described above.

[0102] Furthermore, modifications (2) to (5) of the vertical MOSFET 1A according to Embodiment 2 are also applicable to the IGBT 1D according to Embodiment 7. In this case, the source region 26 described in modification (4) shall be read as the emitter region 126. The source electrode 54 described in modification (5) shall be read as the emitter electrode 154.

[0103] <Other Embodiments> As described above, this disclosure is described by embodiments and modifications thereof, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, the gate insulating film 42 is not limited to an SiO2 film, but may be other insulating films. Silicon oxynitride (SiON) films, strontium oxide (SrO) films, silicon nitride (Si3N4) films, and aluminum oxide (Al2O3) films can also be used for the gate insulating film 42. Furthermore, composite films, such as those made by stacking several single-layer insulating films, can also be used for the gate insulating film 42.

[0104] Thus, this technology naturally includes various embodiments and modifications not described herein. Within the scope of the embodiments and modifications described above, at least one of various omissions, substitutions, and modifications of the components can be made. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0105] Furthermore, this disclosure may also adopt the following structure. (1) Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, It has an n-type layer that faces the gate electrode with the p-type layer in between and is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following: In the aforementioned p-type layer, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). -3 ) and the thickness of the p-type layer is dp (nm), In the aforementioned n-type layer, the effective donor concentration obtained by offsetting the acceptor concentration from the donor concentration is Nn(cm). -3 ) and if the thickness of the n-type layer is dn (nm), A nitride semiconductor device that satisfies equations (1) and (2) above. (2) The aforementioned transistor is The nitride semiconductor substrate further comprises a p-type well region located opposite the gate electrode via the n-type layer and in contact with the n-type layer, The Mg concentration in the aforementioned well region is 1 × 10 18 cm -3 The above 1 x 10 20 cm -3 The nitride semiconductor device described in (1) above, which is as follows: (3) If the p-type layer and the n-type layer are considered as one pair, The nitride semiconductor device according to (1) or (2), wherein the pair is arranged in n (where n is an integer of 2 or more) layers in a stack at a position facing the gate electrode with the gate insulating film in between. (4) The aforementioned transistor is An n-type source region provided on the first surface side of the nitride semiconductor substrate, The system further comprises a source electrode provided on the first surface side and in contact with the source region, The nitride semiconductor device according to any one of (1) to (3), wherein the n-type layer is in contact with the source region. (5) The nitride semiconductor substrate has a trench provided on the first surface side, The gate electrode is positioned in the trench via the gate insulating film, The nitride semiconductor device according to any one of (1) to (4), wherein, on the side surface of the trench, the p-type layer faces the gate electrode with the gate insulating film in between. (6) A nitride semiconductor device according to any one of the above items (1) to (5), wherein the above equation (3) holds true. dp × Np - dn × Nn < 1 × 10 18 ×(dp+dn)…(3) (7) The aforementioned transistor is an IGBT, The aforementioned transistor is An n-type emitter layer provided on the first surface side of the nitride semiconductor substrate, An emitter electrode provided on the first surface side and in contact with the emitter layer, A p-type collector layer is provided on the second surface side of the nitride semiconductor substrate, which is opposite to the first surface, A nitride semiconductor device according to any one of (1) to (3) and (5), further comprising: a collector electrode provided at a position facing the nitride semiconductor substrate across the collector layer and in contact with the collector layer. (8) Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, It has an n-type layer that faces the gate electrode with the p-type layer in between and is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following: A nitride semiconductor device in which the n-type layer is completely depleted when the bias to the gate electrode is 0V. (9) The Mg concentration in the aforementioned p-type layer is 1 × 10 19 cm -3 The above 1 x 10 20 cm -3 The nitride semiconductor device described in any one of the above items (1) to (8), which is as follows: [Explanation of Symbols]

[0106] 1. Lateral MOSFET 1A, 1B, 1C Vertical MOSFETs 10 GaN substrates 10a surface 10b back side 11 GaN single crystal substrate 22 GaN layer 23 well area 24 JFET area 25 Contact area 26 Source Area 27 Drain region 28 p+ type region 29 Collector layer 30 pairs 31 n+ type layer 32 p+ type layer 42 Gate insulating film 44 gate 48 Interlayer insulating film 54 Source electrodes 56 Drain electrode 126 Emitter Region 154 Emitter Electrode 156 Collector electrode H1 Contact Hole H2 Trench

Claims

1. Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, The p-type layer is sandwiched between the gate electrode and an n-type layer that is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following: In the aforementioned p-type layer, the effective acceptor concentration obtained by offsetting the donor concentration from the acceptor concentration is Np(cm²). －３ ) and the thickness of the p-type layer is dp (nm), In the aforementioned n-type layer, the effective donor concentration obtained by offsetting the acceptor concentration from the donor concentration is Nn(cm²). －３ ) and if the thickness of the n-type layer is dn (nm), A nitride semiconductor device such that the following equations (1) and (2) hold true. [Math 1]

2. The aforementioned transistor is The nitride semiconductor substrate further comprises a p-type well region provided at a position opposite the gate electrode via the n-type layer and in contact with the n-type layer, The Mg concentration in the well region is 1×10 １７ cm －３ or more and 1×10 ２０ cm －３ or less. The nitride semiconductor device according to claim 1.

3. If the p-type layer and the n-type layer are considered as one pair, The nitride semiconductor device according to claim 1 or 2, wherein the pair is arranged in n (where n is an integer of 2 or more) layers in a stack at a position facing the gate electrode with the gate insulating film in between.

4. The aforementioned transistor is An n-type source region provided on the first surface side of the nitride semiconductor substrate, The system further comprises a source electrode provided on the first surface side and in contact with the source region, The nitride semiconductor device according to claim 1 or 2, wherein the n-type layer is in contact with the source region.

5. The nitride semiconductor substrate has a trench provided on the first surface side, The gate electrode is positioned in the trench via the gate insulating film, The nitride semiconductor device according to claim 1 or 2, wherein, on the side surface of the trench, the p-type layer faces the gate electrode with the gate insulating film in between.

6. The nitride semiconductor device according to claim 1 or 2, wherein the following equation (3) holds true. dp×Np-dn×Nn < 1×10 １８ ×(dp+dn)…(3)

7. The aforementioned transistor is an IGBT, The aforementioned transistor is An n-type emitter layer provided on the first surface side of the nitride semiconductor substrate, An emitter electrode provided on the first surface side and in contact with the emitter layer, A p-type collector layer is provided on the second surface side of the nitride semiconductor substrate, which is opposite to the first surface, The nitride semiconductor device according to claim 1 or 2, further comprising: a collector electrode provided at a position facing the nitride semiconductor substrate across the collector layer and in contact with the collector layer.

8. Nitride semiconductor substrate and The nitride semiconductor substrate is provided with a normally-off transistor, The aforementioned transistor is A gate insulating film provided on the first surface side of the nitride semiconductor substrate, A gate electrode provided on the gate insulating film, A p-type layer facing the gate electrode with the gate insulating film in between, The p-type layer is sandwiched between the gate electrode and an n-type layer that is in contact with the p-type layer, The Mg concentration in the aforementioned p-type layer is 1 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following: A nitride semiconductor device in which the n-type layer is completely depleted when the bias to the gate electrode is 0V.

9. The Mg concentration in the p-type layer is 1 × 10 １９ cm －３ The above 1 x 10 ２０ cm －３ The nitride semiconductor device according to claim 1 or 8, which is as follows:

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