Voltage level shifter

Abstract

This provides a voltage level shifter that reduces voltage collisions and accelerates signal transition speed. [Solution] The voltage level shifter includes a voltage level shift circuit 110 and a boost circuit 120. The voltage level shift circuit, which operates between a first voltage VH and a second voltage VSS, includes a pair of cross-coupled transistors 111 and a pair of differential transistors 112. The pair of differential transistors are coupled to the pair of cross-coupled transistors and receive a pair of input differential signals IN. The boost circuit is used to perform a pre-charge operation on a plurality of boost input terminals N1, N2 of the pair of cross-coupled transistors and generate at least one voltage pulse based on charge pump operation in response to at least one control pulse signal CS, and to provide voltage pulses to these boost input terminals. The control pulse signal is generated in response to the transition edges of the pair of input differential signals.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to a voltage level shifter.

Background Art

[0002] Generally, electronic products can realize various functions by designing a voltage level shifter according to each need and switching the voltage level shifter within a target operating voltage range. For example, a memory device includes a voltage level shifter and performs a shift operation between different voltage values through the voltage level shifter.

[0003] However, in applications where the power supply voltage is relatively low (for example, 1.8 volts or less), such as energy-saving applications, conventional voltage level shifters cannot effectively complete the voltage shift operation due to severe voltage fighting at the output terminal. Therefore, conventional voltage level shifters are not suitable for realizing energy-saving applications, consume too much power, and thus reduce the signal transition speed.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a voltage level shifter that can reduce voltage fighting and thereby improve the signal transition speed.

Means for Solving the Problems

[0005] The voltage level shifter in an embodiment of the present invention includes a voltage level shift circuit and a boost circuit. The voltage level shift circuit operates between a first voltage and a second voltage. The voltage level shift circuit includes a pair of cross-coupled transistors and a pair of differential transistors. The pair of differential transistors are coupled to the cross-coupled transistors and receive a pair of input signals. The boost circuit is coupled to the voltage level shift circuit. The boost circuit is used to perform a pre-charge operation on a plurality of boost input terminals of the pair of cross-coupled transistors and to generate at least one voltage pulse based on charge pump operation in response to at least one control pulse signal, and to provide voltage pulses to these boost input terminals. The control pulse signal is generated in response to the transition edges of the pair of input signals. [Effects of the Invention]

[0006] Based on the above, the voltage level shifter in the embodiment of the present invention can reduce voltage collisions by increasing the voltage values ​​of multiple boost input terminals through a boost circuit by performing a pre-charge operation on these input terminals. Furthermore, the voltage level shifter can provide voltage pulses to multiple boost input terminals based on a charge pump operation through the boost circuit, protecting the voltage level shift circuit to enable energy-saving applications, further reducing voltage collisions, and accelerating the signal transition speed. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a voltage level shifter illustrated based on one embodiment of the present invention. [Figure 2] This is a circuit diagram of a voltage level shifter illustrated based on one embodiment of the present invention. [Figure 3] This is a schematic diagram illustrating the operation of a voltage level shifter based on an embodiment of the present invention shown in Figure 2. [Figure 4] This is a circuit diagram of a voltage level shifter illustrated according to another embodiment of the present invention. [Figure 5]This is a schematic diagram illustrating the operation of a voltage level shifter based on an embodiment of the present invention shown in Figure 4. [Modes for carrying out the invention]

[0008] Referring to Figure 1, the voltage level shifter 100 may be, for example, a high-voltage voltage level shifter. The voltage level shifter 100 can realize applications where the power supply voltage is a relatively low voltage value (for example, 1.8 volts or less) (for example, energy-saving applications). The aforementioned power supply voltage may be, for example, the power supply voltage VCC shown in Figure 2 or Figure 4, where the voltage value of the power supply voltage VCC may be, for example, 1.2 volts. The voltage level shifter 100 may have a circuit configuration that includes, for example, a single-terminal output and a differential input.

[0009] In the embodiment shown in Figure 1, the voltage level shifter 100 includes a voltage level shift circuit 110 and a boost circuit 120. The voltage level shift circuit 110 is coupled to the boost circuit 120. The voltage level shift circuit 110 is used to operate between a first voltage VH and a second voltage VSS, and performs a shift operation between the voltage value of the first voltage VH and the voltage value of the second voltage VSS. The first voltage VH may be, for example, a high power supply voltage. The second voltage VSS may be, for example, a low power supply voltage.

[0010] In this embodiment, the voltage level shift circuit 110 includes a pair of cross-coupled transistors 111 and a pair of differential transistors 112. The pair of cross-coupled transistors 111 are coupled to the pair of differential transistors 112. The pair of cross-coupled transistors 111 have a plurality of boost input terminals N1 to N2. These boost input terminals N1 to N2 are coupled to the boost circuit 120. The pair of differential transistors 112 receive a pair of input signals IN. The pair of input signals IN may be, for example, differential signals used to drive the pair of differential transistors 112.

[0011] During the shift operation, the boost circuit 120 performs a pre-charge operation on multiple boost input terminals N1 to N2 of a pair of cross-coupled transistors 111. Furthermore, the boost circuit 120 generates at least one voltage pulse PS based on a charge pump operation in response to at least one control pulse signal CS. In other words, the boost circuit 120 performs a charge pump operation controlled by the control pulse signal CS and generates a voltage pulse PS corresponding to the control pulse signal CS. The boost circuit 120 provides the voltage pulse PS to the multiple boost input terminals N1 to N2.

[0012] In this embodiment, the control pulse signal CS is generated in response to the transition edge of a pair of input signals IN. That is, when the input signal pair IN switches between different voltage levels, generating a rising edge or falling edge, the control pulse signal CS is generated, the boost circuit 120 is driven, and the charge pump operation is performed.

[0013] Furthermore, by performing a pre-charge operation on multiple boost input terminals N1 to N2 via the boost circuit 120, the voltage level shifter 100 can increase the voltage values ​​on these boost input terminals N1 to N2. Based on the increased voltage values, the pull-down capability of the pair of cross-coupled transistors 111 is enhanced, reducing voltage collisions. In addition, by providing voltage pulses PS to the multiple boost input terminals N1 to N2 based on charge pump operation via the boost circuit 120, the voltage level shifter 100 can reduce voltage collisions and protect the pair of differential transistors 112 from damage by the first voltage VH. In this way, energy-saving applications for the voltage level shifter 100 can be realized, and the signal transition speed can be accelerated.

[0014] Referring to Figure 2, the voltage level shifter 200 includes a voltage level shift circuit 210 and a boost circuit 220. The voltage level shift circuit 210 includes a pair of cross-coupled transistors 211 and a pair of differential transistors 212. The voltage level shift circuit 210 and the boost circuit 220 can be inferred by analogy with the description relating to the voltage level shifter 100.

[0015] In the embodiment shown in Figure 2, the boost circuit 220 includes a first boost block 221 and a second boost block 222. The first boost block 221 receives the power supply voltage VCC. The first boost block 221 is coupled to the first boost input terminal N1 of a pair of cross-coupled transistors 211. The first boost block 221 is coupled to the first reference input terminal N3 of a pair of differential transistors 212. The first boost block 221 receives the first input signal IN1 as a first control pulse signal (i.e., the control pulse signal CS in the embodiment of Figure 1) at the first reference input terminal N3.

[0016] Specifically, the first boost circuit block 221 includes a transistor M1 and a capacitor C1. Transistor M1 may be implemented by, for example, an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET). In this embodiment, transistor M1 is a native transistor. That is, the critical voltage value of transistor M1 is close to zero. In other embodiments, transistor M1 may be a normal transistor, and its critical voltage value is smaller than the voltage value of the power supply voltage VCC (for example, the third voltage value V3 shown in Figure 3).

[0017] In detail, the control terminal (i.e., gate terminal) and first terminal (i.e., first source / drain terminal) of transistor M1 are coupled to each other and receive the power supply voltage VCC. In other words, transistor M1 is in a diode connection state. The second terminal of transistor M1 (i.e., second source / drain terminal) is coupled to the first boost input terminal N1 and the first terminal of capacitor C1. The second terminal of capacitor C1 is coupled to the first reference input terminal N3.

[0018] In this embodiment, the second boost block 222 receives the power supply voltage VCC. The second boost block 222 is coupled to the second boost input terminal N2 of a pair of cross-coupled transistors 211. The second boost block 222 is coupled to the second reference input terminal N4 of a pair of differential transistors 212. The second boost block 222 receives the second input signal IN2 as a second control pulse signal (i.e., the control pulse signal CS in the embodiment of Figure 1) at the second reference input terminal N4.

[0019] Specifically, the second boost block 222 includes a transistor M2 and a capacitor C2. Transistor M2 may be implemented by, for example, an NMOSFET. In this embodiment, transistor M2 is a native transistor and has a critical voltage value close to zero. In other embodiments, transistor M2 is a normal transistor and its critical voltage value is smaller than the voltage value of the power supply voltage VCC (for example, the third voltage value V3 shown in Figure 3). Hereafter, transistors M1 and M2 will be described as native transistors.

[0020] In detail, the control terminal (i.e., gate terminal) and first terminal (i.e., first source / drain terminal) of transistor M2 are coupled to each other and receive the power supply voltage VCC. In other words, transistor M2 is in a diode connection state. The second terminal (i.e., second source / drain terminal) of transistor M2 is coupled to the second boost input terminal N2 and the first terminal of capacitor C2. The second terminal of capacitor C2 is coupled to the second reference input terminal N4.

[0021] In this embodiment, the pair of cross-coupled transistors 211 includes a plurality of transistors M3 to M6. The transistors M3 and M4 may be realized by, for example, p-type Metal-Oxide-Semiconductor Field-Effect Transistors (PMOSFETs). The transistors M5 and M6 may be realized by, for example, NMOSFETs.

[0022] Specifically, the first terminal (i.e., the first source / drain terminal) of the transistor M3 receives the first voltage VH. The first terminal (i.e., the first source / drain terminal) of the transistor M4 receives the first voltage VH. The control terminal (i.e., the gate terminal) of the transistor M5 functions as the first boost input terminal N1. The first terminal (i.e., the first source / drain terminal) of the transistor M5 is coupled to the second terminal (i.e., the second source / drain terminal) of the transistor M3 and the control terminal (i.e., the gate terminal) of the transistor M4 at the node N5. The second terminal (i.e., the second source / drain terminal) of the transistor M5 is coupled to the pair of differential transistors 212.

[0023] Continuing with the above description, the control terminal (i.e., the gate terminal) of the transistor M6 functions as the second boost input terminal N2. The first terminal (i.e., the first source / drain terminal) of the transistor M6 is coupled to the second terminal (i.e., the second source / drain terminal) of the transistor M4 and the control terminal (i.e., the gate terminal) of the transistor M3 at the node N6. The node N6 functions as the output terminal of the voltage level shift circuit 210. The second terminal (i.e., the second source / drain terminal) of the transistor M6 is coupled to the pair of differential transistors 212.

[0024] [[ID=1十二]] Furthermore, the pull-down elements of the pair of cross-coupled transistors 211 (i.e., transistors M5 and M6) are inserted between the pull-up elements of the pair of cross-coupled transistors 211 (i.e., transistors M3 and M4) and the pair of differential transistors 212 acting as pull-down elements. Transistors M5 and M6 can withstand a first voltage VH, and their critical voltage values ​​are higher than those of transistors M7 and M8. When the power supply voltage VCC is low (e.g., 1.2V), their critical voltage values ​​even become substantially equal to the voltage value of the power supply voltage VCC (e.g., the third voltage value V3 shown in Figure 3).

[0025] In this embodiment, the pair of differential transistors 212 includes a plurality of low-voltage-tolerant transistors M7 to M8. The multiple critical voltage values ​​of the pair of differential transistors 212 are each smaller than the voltage value of the power supply voltage VCC (for example, the third voltage value V3 shown in Figure 3). In other words, the critical voltage values ​​of transistors M7 and M8 are both smaller than the third voltage value.

[0026] Specifically, the pair of differential transistors 212 include a plurality of transistors M7 to M8. Transistors M7 and M8 may be implemented, for example, by NMOSFETs.

[0027] In detail, the control terminal (i.e., gate terminal) of transistor M7 functions as the first reference input terminal N3 and receives the first input signal IN1. The first terminal of transistor M7 (i.e., the first source / drain terminal) is coupled to the second terminal of transistor M5 (i.e., the second source / drain terminal). The second terminal of transistor M7 (i.e., the second source / drain terminal) receives the second voltage VSS.

[0028] Continuing the above explanation, the control terminal (i.e., gate terminal) of transistor M8 functions as the second reference input terminal N4 and receives the second input signal IN2. The first terminal of transistor M8 (i.e., the first source / drain terminal) is coupled to the second terminal of transistor M6 (i.e., the second source / drain terminal). The second terminal of transistor M8 (i.e., the second source / drain terminal) receives the second voltage VSS.

[0029] In this embodiment, the voltage level shifter 200 further includes an inverter 230. The first terminal (i.e., input terminal) of the inverter 230 is coupled to the control terminal (i.e., first reference input terminal N3) of transistor M7. The second terminal (i.e., output terminal) of the inverter 230 is coupled to the control terminal (i.e., second reference input terminal N4) of transistor M8. In other words, the inverter 230 provides a pair of differential signals IN having inversion (i.e., first differential signal IN1 and second differential signal IN2) to the first reference input terminal N3 and the second reference input terminal N4.

[0030] Referring to Figures 2 and 3 simultaneously, in Figure 3, the horizontal axis represents the operating time of the voltage level shifter 200, and the vertical axis represents the voltage value. In this embodiment, the first voltage VH has a first voltage value V1. The second voltage VSS has a second voltage value V2. The power supply voltage VCC has a third voltage value V3. The first voltage value V1 is greater than the third voltage value V3 and may be, for example, 10 volts (V). The third voltage value V3 is greater than the second voltage value V2 and may be, for example, 1.2 volts. The second voltage value V2 may be, for example, the reference ground voltage value.

[0031] In this embodiment, the boost circuit 220 performs a pre-charge operation in response to the power supply voltage VCC. That is, during different periods corresponding to the shift operation, the boost circuit 220 pre-charges the first boost input terminal N1 and the second boost input terminal N2 to a third voltage value V3 of the power supply voltage VCC, respectively. Furthermore, the boost circuit 220 boosts the first boost input terminal N1 and the second boost input terminal N2 to a different voltage value, respectively, in response to the charge pump operation. In this way, the voltage VM1 of the first boost input terminal N1 and the voltage VM2 of the second boost input terminal N2 are switched between the third voltage value V3 and another voltage value (for example, twice the third voltage value V3), respectively.

[0032] In the shift operation, the voltage level shifter 200, for example at time t1, switches the output voltage O / P from a high voltage value (i.e., a first voltage value V1) to a low voltage value (i.e., a second voltage value V2).

[0033] More specifically, before time t1, transistor M7 conducts. Transistor M1 conducts and performs a pre-charge operation on the first boost input terminal N1 in accordance with the power supply voltage VCC. Since transistor M1 is a native transistor, the voltage VM1 at the first boost input terminal N1 is pre-charged to be equal to or substantially equal to the voltage value of the power supply voltage VCC (i.e., the third voltage value V3). Also, transistor M1 and capacitor C1 generate a voltage pulse (i.e., voltage VM1) at the first boost input terminal N1 based on charge pump operation in response to the first differential signal IN1, which is a control pulse signal. In other words, the voltage at the first reference input terminal N3 (i.e., the first differential signal IN1 with the third voltage value V3) is supplied to the first boost input terminal N1 via capacitor C1 so that voltage VM1 is equal to or substantially equal to twice the third voltage value V3.

[0034] Similarly, the voltage VM2 at the second boost input terminal N2 is precharged via transistor M2 to be equal to, or substantially equal to, the voltage value of the power supply voltage VCC (i.e., the third voltage value V3). Also, since the second differential signal IN2 has a second voltage value V2 (i.e., the reference ground voltage value), the voltage VM2 at the second boost input terminal N2 is maintained at the third voltage value V3.

[0035] At time t1, the first differential signal IN1 switches from the third voltage value V3 to the second voltage value V2. Transistor M7 is controlled by the first differential signal IN1 and disconnected. The second differential signal IN2 switches from the second voltage value V2 to the third voltage value V3. Transistor M8 is controlled by the second differential signal IN2 and conducts. Transistor M2 and capacitor C2 generate a voltage pulse (i.e., voltage VM2) corresponding to the second differential signal IN2 (which is a control pulse signal) at the second boost input terminal N2 based on charge pump operation, and as a result, the voltage VM2 at the second boost input terminal N2 is pulled up to be equal to or substantially equal to twice the third voltage value V3.

[0036] At this point, transistor M6 is controlled by voltage VM2 and conducts. The output voltage O / P of node N6 is pulled down to the voltage value of the second voltage VSS (i.e., the second voltage value V2) via transistors M6 and M8. Transistor M3 is controlled by the output voltage O / P of node N6 and conducts, and the voltage O / PN of node N5 begins to be pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1). Transistor M4 is disconnected and the switching operation ends until the voltage O / PN of node N5 is pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1).

[0037] Furthermore, the voltage VM2 at the second boost input terminal N2 is precharged to the power supply voltage VCC (i.e., the third voltage value V3) via transistor M2, and then further increased to twice the third voltage value V3 via capacitor C2. Therefore, in the switching operation, the conduction capability of the pull-down elements (including transistor M6) within the pair of cross-coupled transistors 211 is improved, thereby reducing voltage collisions.

[0038] In this way, the pull-down elements in the pair of cross-coupled transistors 211 (including transistor M6) and the pull-down elements in the pair of differential transistors 212 (including transistor M8) can more easily and quickly pull down the output voltage O / P to the second voltage value V2, thereby shortening the period during which transistor M8 can withstand the first voltage VH. Therefore, a voltage VM2, which is twice the third voltage value V3, can protect the pair of differential transistors 212 from damage by the first voltage VH. In addition, the voltage O / PN at node N5 is also rapidly pulled up to the first voltage value V1, thereby accelerating the signal transition speed.

[0039] The operation of the voltage level shifter 200 at time t2 can be inferred by referring to the description of the voltage level shifter 200 at time t1.

[0040] At time t2, the voltage VM1 at the first boost input terminal N1 is precharged to the power supply voltage VCC (i.e., the third voltage value V3) via transistor M1, and further increased to twice the third voltage value V3 via capacitor C1. Therefore, in the switching operation, the conduction capability of the pull-down elements (including transistor M5) in the pair of cross-coupled transistors 211 is improved, thereby reducing voltage collisions. Consequently, the pull-down elements (including transistor M5) in the pair of cross-coupled transistors 211 and the pull-down elements (including transistor M7) in the pair of differential transistors 212 can pull down the voltage O / PN to the second voltage value V2 more easily and quickly, thereby accelerating the signal transition speed. In this way, the period during which transistor M7 can withstand the first voltage VH can be shortened, thereby preventing the pair of differential transistors 212 from being damaged by the first voltage VH.

[0041] Referring to Figure 4, the voltage level shifter 400 includes a voltage level shift circuit 410 and a boost circuit 420. The voltage level shift circuit 410 includes a pair of cross-coupled transistors 411 and a pair of differential transistors 412. The voltage level shift circuit 410 and the boost circuit 420 can be inferred by analogy with the description relating to the voltage level shifter 100.

[0042] In the embodiment shown in Figure 4, the boost circuit 420 includes a transistor M41 and a capacitor C41. Transistor M41 may be implemented by, for example, an NMOSFET. In this embodiment, transistor M41 is a native transistor and has a critical voltage value close to zero.

[0043] In detail, the control terminal (i.e., gate terminal) and first terminal (i.e., first source / drain terminal) of transistor M41 are coupled to each other and receive the power supply voltage VCC. In other words, transistor M41 is in a diode-connected state. The second terminal (i.e., second source / drain terminal) of transistor M41 is coupled to the first boost input terminal N1, the second boost input terminal N2, and the first terminal of capacitor C41. The second terminal of capacitor C41 receives the control pulse signal PD.

[0044] In this embodiment, a pair of cross-coupled transistors 411 includes a plurality of transistors M3 to M6. A pair of differential transistors 412 includes a plurality of transistors M7 to M8. The voltage level shifter 400 further includes an inverter 430. Transistors M3 to M6, transistors M7 to M8 and the inverter 430 can be inferred by analogy with the description relating to the voltage level shifter 200.

[0045] Referring to Figures 4 and 5 simultaneously, in Figure 5, the horizontal axis represents the operating time of the voltage level shifter 400, and the vertical axis represents the voltage value.

[0046] Compared to the shift operation in Figures 2 and 3, before time t1, transistor M41 conducts and performs a precharge operation on the first boost input terminal N1 and the second boost input terminal N2 in accordance with the power supply voltage VCC. Since transistor M41 is a native transistor, the voltages Vboost at the first boost input terminal N1 and the second boost input terminal N2 are precharged to be equal to or substantially equal to the voltage value of the power supply voltage VCC (i.e., the third voltage value V3).

[0047] Furthermore, transistor M41 and capacitor C41 generate voltage pulses (i.e., voltage Vboost) corresponding to the control pulse signal PD at the first boost input terminal N1 and the second boost input terminal N2, respectively, based on the charge pump operation in response to the control pulse signal PD. In other words, a control pulse signal PD having a second voltage value V2 (i.e., the reference ground voltage value) is provided to the first boost input terminal N1 and the second boost input terminal N2 via capacitor C41, and the voltage Vboost is maintained at a third voltage value V3.

[0048] At time t1, the first differential signal IN1 switches from the third voltage value V3 to the second voltage value V2. Transistor M7 is controlled by the first differential signal IN1 and disconnected. The second differential signal IN2 switches from the second voltage value V2 to the third voltage value V3. Transistor M8 is controlled by the second differential signal IN2 and conducts.

[0049] The control pulse signal PD is generated in accordance with the rising edge of the second differential signal IN2 (i.e., the falling edge of the first differential signal IN1), and switches from the second voltage value V2 to the third voltage value V3. Transistor M41 and capacitor C41 generate voltage pulses (i.e., voltage Vboost) corresponding to the second differential signal IN2 at the first boost input terminal N1 and the second boost input terminal N2 based on the charge pump operation in response to the control pulse signal PD, and the voltage Vboost is pulled up so that it is equal to or substantially equal to twice the third voltage value V3.

[0050] At this point, transistors M5 and M6 are controlled by the voltage Vboost and conduct. The output voltage O / P of node N6 is pulled down to the voltage value of the second voltage VSS (i.e., the second voltage value V2) via transistors M6 and M8. Next, transistor M3 is controlled by the output voltage O / P of node N6 and conducts, and the voltage O / PN of node N5 begins to be pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1). Transistor M4 is disconnected and the switching operation ends until the voltage O / PN of node N5 is pulled up to the voltage value of the first voltage VH (i.e., the first voltage value V1).

[0051] Furthermore, the voltages Vboost at the first boost input terminal N1 and the second boost input terminal N2 are precharged to the voltage value of the power supply voltage VCC (i.e., the third voltage value V3) via transistor M41, and then further increased to twice the third voltage value V3 via capacitor C41. Therefore, in the switching operation, the pull-down paths (i.e., discharge paths) between the pull-down elements in the pair of cross-coupled transistors 411 (including transistor M6) and the pull-down elements in the pair of differential transistors 412 (including transistor M8) and the second voltage value V2 are improved, thereby reducing voltage collisions.

[0052] In this way, the pull-down elements in the pair of cross-coupled transistors 411 (including transistor M6) and the pull-down elements in the pair of differential transistors 412 (including transistor M8) can more easily and quickly pull down the output voltage O / P to the second voltage value V2, thereby shortening the period during which transistor M8 can withstand the first voltage VH. Therefore, a voltage Vboost of twice the third voltage value V3 can protect the pair of differential transistors 412 from damage by the first voltage VH. In addition, the voltage O / PN at node N5 is also rapidly pulled up to the first voltage value V1, thereby accelerating the signal transition speed.

[0053] The operation of the voltage level shifter 400 at time t2 can be inferred by referring to the description of the voltage level shifter 400 at time t1.

[0054] In summary, the voltage level shifter in the embodiment of the present invention can be applied to situations where the power supply voltage is relatively low. By performing a pre-charge operation on multiple boost input terminals via a boost circuit and then boosting the multiple boost input terminals again based on the charge pump operation, voltage level shifter voltage collisions can be reduced, thereby accelerating the signal transition speed and further protecting a pair of differential transistors from damage caused by high power supply voltages (i.e., the first voltage).

[0055] The present invention is disclosed through the embodiments described above, but is not limited thereto. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the invention, so the scope of protection of the present invention shall be determined by the scope of the appended patent application. [Industrial applicability]

[0056] The voltage level shifter of the present invention can be applied to memory devices. [Explanation of symbols]

[0057] 100, 200, 400: Voltage level shifter 110, 210, 410: Voltage level shift circuit 111, 211, 411: A pair of cross-coupled transistors 112, 212, 412: A pair of differential transistors 120, 220, 420: Boost circuit 221: First Boost Block 222: Second Boost Block 230, 430: Inverter VCC: Power supply voltage C1~C2, C41: Capacitors CS: Control pulse signal IN: Pair of input signals IN1: First input signal IN2: Second input signal M1~M8, M41: Transistors N1: First boost input terminal N2: Second boost input terminal N3: First reference input terminal N4: Second reference input terminal N5~N6: Nodes O / P: Output voltage O / PN: Voltage at node N5 PD: Control pulse signal PS: Voltage pulse t0~t2: Time V1: First voltage value V2: Second voltage value V3: Third voltage value Vboost: Voltage of the 1st boost input terminal and the 2nd boost input terminal VH: First voltage VM1: Voltage at the first boost input terminal VM2: Voltage at the second boost input terminal VSS: Second Voltage

Claims

1. A voltage level shift circuit that operates between a first voltage and a second voltage, and includes a pair of cross-coupled transistors and a pair of differential transistors, wherein the pair of differential transistors are coupled to the pair of cross-coupled transistors and the voltage level shift circuit receives a pair of input signals, A boost circuit coupled to the voltage level shift circuit, which performs a pre-charge operation on a plurality of boost input terminals of the pair of cross-coupled transistors, generates at least one voltage pulse based on a charge pump operation in response to at least one control pulse signal, and provides the plurality of boost input terminals with the at least one voltage pulse; Includes, The at least one control pulse signal is generated in response to the transition edge of the pair of input signals. Voltage level shifter.

2. The boost circuit performs a pre-charge operation according to the power supply voltage, and the power supply voltage has a third voltage value. The voltage level shifter according to claim 1.

3. The multiple critical voltage values ​​of the pair of differential transistors are each smaller than the third voltage value. The voltage level shifter according to claim 2.

4. The pair of differential transistors includes a plurality of low-voltage-tolerant transistors. The voltage level shifter according to claim 1.

5. The aforementioned boost circuit is, A first boost block is coupled to the first boost input terminal of the pair of cross-coupled transistors and to the first reference input terminal of the pair of differential transistors, and receives the first input signal as a first control pulse signal. A second boost block is coupled to the second boost input terminal of the pair of cross-coupled transistors and to the second reference input terminal of the pair of differential transistors, and receives the second input signal as a second control pulse signal. A voltage level shifter according to claim 1, including the following:

6. The first boost block is, A first transistor having a control terminal and a first terminal for receiving the power supply voltage, A first capacitor having a second terminal of the first transistor and a first terminal connected to the first boost input terminal, wherein the second terminal of the first capacitor is connected to the first capacitor connected to the first reference input terminal, A voltage level shifter according to claim 5, including the voltage level shifter described in claim 5.

7. The first transistor is a native transistor. The voltage level shifter according to claim 6.

8. The second boost block is, A second transistor having a control terminal and a first terminal for receiving the power supply voltage, A second capacitor having a first terminal coupled to the second terminal of the second transistor and the second boost input terminal, wherein the second terminal of the second capacitor is coupled to the second capacitor coupled to the second reference input terminal, A voltage level shifter according to claim 6, including the voltage level shifter described in claim 6.

9. The second transistor is a native transistor. The voltage level shifter according to claim 8.

10. The aforementioned boost circuit is, A first transistor having a control terminal and a first terminal for receiving the power supply voltage, A first capacitor having a second terminal of the first transistor, a first boost input terminal, and a first terminal coupled to the second boost input terminal, wherein the second terminal of the first capacitor is connected to the first capacitor that receives the at least one control pulse signal, The voltage level shifter according to claim 1.

11. The first transistor is a native transistor. The voltage level shifter according to claim 10.

12. The aforementioned cross-coupled transistor is A first transistor having a first terminal for receiving the first voltage, A second transistor having a first terminal for receiving the first voltage, A third transistor having a control terminal as a first boost input terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor and the control terminal of the second transistor, and the second terminal of the third transistor is coupled to the pair of differential transistors, A fourth transistor having a control terminal as a second boost input terminal, wherein the first terminal of the fourth transistor is coupled to the second terminal of the second transistor and the control terminal of the first transistor, and the second terminal of the fourth transistor is coupled to the pair of differential transistors, A voltage level shifter according to claim 1, including the following:

13. The pair of differential transistors are A fifth transistor having a control terminal for receiving a first input signal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the third transistor, and the second terminal of the fifth transistor is coupled to the fifth transistor for receiving the second voltage. A sixth transistor having a control terminal for receiving a second input signal, wherein the first terminal of the sixth transistor is coupled to the second terminal of the fourth transistor, and the second terminal of the sixth transistor is coupled to the sixth transistor for receiving the second voltage. A voltage level shifter according to claim 12, including the voltage level shifter according to claim 12.

14. An inverter having a first terminal connected to the control terminal of the fifth transistor, wherein the second terminal of the inverter is connected to the control terminal of the sixth transistor, The voltage level shifter according to claim 13, further comprising:

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