Differential circuit

Abstract

The same mask can be used to create operational amplifiers and comparators, reducing costs. [Solution] The differential circuit (5) comprises a differential input stage (1) configured to receive a differential voltage between an inverting input terminal (Tn) and a non-inverting input terminal (Tp), a gain stage (2) configured to amplify the output of the differential input stage, an output stage (3) configured to receive the signal from the gain stage and output an output signal (OUT), and a first switching circuit (SW11, SW12, SW13) configured to switch the enabled and disabled states of phase compensation elements (C1, C2) included in the output stage based on a switching signal (SW).

Description

Technical Field

[0001] This disclosure relates to a differential circuit.

Background Art

[0002] Conventionally, comparators and operational amplifiers are known. For example, Patent Document 1 discloses an example of an amplifier.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In comparators and operational amplifiers, the differential input stage and the amplification stage (gain stage) have substantially the same structure, but due to the different output formats, different masks (masks for semiconductor integrated circuit manufacturing) are required for fabrication.

[0005] A differential circuit according to one aspect of this disclosure includes: a differential input stage configured to receive a differential voltage between an inverting input terminal and a non-inverting input terminal; a gain stage configured to amplify the output of the differential input stage; an output stage configured to receive the signal of the gain stage and output an output signal; a first switching circuit configured to switch between enabling and disabling a phase compensation element included in the output stage based on a switching signal; and is configured to include the above components.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a diagram showing a measurement circuit using a comparator CMP or an operational amplifier OP. [Figure 2]Figure 2 schematically shows the waveform of the output voltage output from the comparator CMP or operational amplifier OP when the input voltage Vin is applied in the measurement circuit of Figure 1. [Figure 3] Figure 3 shows the configuration of a differential circuit according to the present disclosure. [Figure 4] Figure 4 is a correspondence table showing the states according to the level of the switching signal SW. [Figure 5] Figure 5 shows an example of a measurement circuit for the NULL method. [Figure 6] Figure 6 shows the simulation results of the NULL method. [Figure 7] Figure 7 shows the results of measuring the behavior of a differential circuit using the measurement circuit shown in Figure 1. [Figure 8] Figure 8 shows the configuration of a differential circuit according to a modified example. [Figure 9] Figure 9 shows the configuration of a differential circuit, including a first example of a circuit that generates a switching signal. [Figure 10] Figure 10 shows the configuration of a differential circuit, including a second example of a circuit that generates a switching signal. [Figure 11] Figure 11 shows the configuration of a differential circuit, including a third example of a circuit that generates a switching signal.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <Comparators and operational amplifiers> As mentioned earlier, comparators and operational amplifiers require separate masks for fabrication, leading to increased costs. While it is possible to use an operational amplifier as a comparator, operational amplifiers have capacitors for phase compensation, and these capacitors worsen the propagation delay time, which is a crucial characteristic of comparators.

[0009] Figure 1 shows a measurement circuit using a comparator CMP or operational amplifier OP. An input voltage Vin is applied to the non-inverting input terminal (+) of the comparator CMP or operational amplifier OP, and a reference voltage Vref is applied to the inverting input terminal (-).

[0010] Figure 2 schematically shows the waveform of the output voltage output from the comparator CMP or operational amplifier OP when the input voltage Vin is applied in the measurement circuit of Figure 1.

[0011] The left side of Figure 2 shows the behavior of the output voltage Vout when the input voltage Vin is raised from a voltage lower than the reference voltage Vref to a voltage higher than the reference voltage Vref. In this case, the output voltage Vout switches from a low level to a high level. The propagation delay time t is the time from when the input voltage Vin reaches the reference voltage Vref until the output voltage Vout reaches 50% of the output voltage amplitude. PLH This is stipulated.

[0012] The right side of Figure 2 shows the behavior of the output voltage Vout when the input voltage Vin is lowered from a voltage higher than the reference voltage Vref to a voltage lower than the reference voltage Vref. In this case, the output voltage Vout switches from a high level to a low level. The propagation delay time t is the time from when the input voltage Vin falls below the reference voltage Vref until the output voltage Vout reaches 50% of the output voltage amplitude. PHL This is stipulated.

[0013] Operational amplifiers (OPs) are typically used in negative feedback circuit configurations. However, when using an OP as a comparator without negative feedback, charging and discharging of a phase compensation capacitor is required. This results in a gentler rise / fall slope of the output voltage Vout, and a tendency for longer propagation delay time.

[0014] Furthermore, as shown in Figure 2, the rise time t is defined as the time required for the output voltage Vout to rise from 10% to 90% of the output voltage amplitude. R The fall time t is defined as the time required for the output voltage Vout to fall from 90% to 10% of the output voltage amplitude.F is defined. In the operational amplifier OP, it often defines only the rise time / rise time instead of the propagation delay time, so the variation in the propagation delay time cannot be guaranteed, and there are many products that cannot be used when high-speed response is required.

[0015] <Differential circuit> FIG. 3 shows the configuration of the differential circuit 5 according to an embodiment of the present disclosure. The differential circuit 5 includes a differential input stage 1, a cascode gain stage 2, an output stage 3, an inverter 4, a non-inverting input terminal Tp, an inverting input terminal Tn, an output terminal Tout, and a switching terminal Tsw.

[0016] A differential voltage between the voltage INp applied to the non-inverting input terminal Tp and the voltage INn applied to the inverting input terminal Tn is input to the differential input stage 1. The cascode gain stage 2 amplifies the output of the differential input stage 1. The cascode gain stage 2 increases the open-loop gain of the differential circuit 5.

[0017] The output stage 3 includes an AB-class buffer stage 31, inverter stages IV1 to IV3, capacitors C1 and C2, resistors R1 and R2, switches SW11 to SW16, and switches SW21 to SW24.

[0018] The application terminal of the first output G1 (first gate signal) output from the Class AB buffer stage 31 is connected via switch SW14 to the gate of the PMOS transistor (P-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) that constitutes inverter IV3. The application terminal of the second output G2 (second gate signal) output from the Class AB buffer stage 31 is connected via switch SW15 to the gate of the NMOS transistor (N-channel MOSFET) that constitutes inverter IV3. The PMOS transistor PM3 and the NMOS transistor NM3 are connected between voltage VDD and voltage VSS. Voltage VSS is a lower voltage than voltage VDD. The output terminal Tout is connected to the node where the PMOS transistor PM3 and the NMOS transistor NM3 are connected. The output voltage OUT of the differential circuit 5 is output from the output terminal Tout.

[0019] Capacitors C1 and C2 and resistors R1 and R2 are phase compensation elements. The application terminal of the first output G1 is connected to one end of capacitor C1 via switch SW11. The other end of capacitor C1 is connected to one end of resistor R1. The application terminal of the second output G2 is connected to one end of capacitor C2 via switch SW12. The other end of capacitor C2 is connected to one end of resistor R2. The other ends of resistor R1 and resistor R2 are connected to the output terminal Tout via switch SW13.

[0020] The inverter stage IV1 consists of a PMOS transistor PM1 and an NMOS transistor NM1. The source of the PMOS transistor PM1 is connected to the voltage VDD application terminal. The source of the NMOS transistor NM1 is connected to the voltage VSS application terminal.

[0021] Inverter stage IV2 consists of a PMOS transistor PM2 and an NMOS transistor NM2. The drain of PMOS transistor PM1 is connected to the gate of PMOS transistor PM2 and the gate of NMOS transistor NM2 via switch SW21, and the drain of NMOS transistor NM1 is connected to the gate of PMOS transistor PM2 and NMOS transistor NM2 via switch SW22, respectively. PMOS transistor PM2 and NMOS transistor NM2 are connected between voltage VDD and voltage VSS.

[0022] The drains of the PMOS transistor PM2 and the NMOS transistor NM2 are connected to the gates of the PMOS transistor PM3 via switch SW23 and to the gates of the NMOS transistor NM3 via switch SW24, respectively.

[0023] The gates of the PMOS transistor PM2 and the NMOS transistor NM2 are connected to the voltage VSS application terminals via switch SW16. Alternatively, the gates of the PMOS transistor PM2 and the NMOS transistor NM2 may be connected to the voltage VDD application terminals via switch SW16.

[0024] A changeover signal SW is applied to the changeover terminal Tsw. The changeover terminal Tsw is connected to the control terminals of switches SW21 to SW24. The changeover terminal Tsw is connected to the control terminals of switches SW11 to SW16 via inverter 4.

[0025] The switching signal SW takes either a high or low level. Figure 4 is a correspondence table showing the on / off states of the first switch group SW1 (SW11~SW15), the on / off states of the second switch group SW2 (SW21~SW24), and whether the differential circuit 5 functions as an operational amplifier or a comparator, depending on the level of the switching signal SW.

[0026] As shown in Figure 4, when the switching signal SW is at a low level, the inverter 4 inverts the first switch group SW1, turning it ON and the second switch group SW2 turning it OFF. As a result, the first output G1 is bypassed to the gate of the PMOS transistor PM3 via switch SW14, and the second output G2 is bypassed to the gate of the NMOS transistor PM3 via switch SW15. Also, when switches SW11, 12, and 13 are turned ON, the phase compensation elements (C1, C2, R1, R2) become active. In this state, the class AB buffer stage 31 controls the output voltage OUT by applying the biased outputs G1 and G2 to the gates of the PMOS transistor PM3 and NMOS transistor NM3, respectively, thereby supplying current to the PMOS transistor PM3 and NMOS transistor NM3. In this state, the differential circuit 5 functions as an operational amplifier. In operational amplifier mode, if the differential circuit 5 is used with negative feedback, the output voltage OUT can take the midpoint potential.

[0027] At this time, switches SW21 and SW22 are in the off state, and in order to avoid the gate potentials of PMOS transistor PM2 and NMOS transistor NM2 becoming undefined, switch SW16 is turned on to fix the gates of PMOS transistor PM2 and NMOS transistor NM2 to a low level. As a result, NMOS transistor NM2 is in the off state, and through-current flow through PMOS transistor PM2 and NMOS transistor NM2 is suppressed. Also, since switches SW23 and SW24 are in the off state, the output of inverter stage IV2 is not input to inverter stage IV3.

[0028] On the other hand, when the switching signal SW is at a high level, the first switch group SW1 is turned off and the second switch group SW2 is turned on due to inversion by inverter 4. As a result, the bypass by switches SW14 and SW15 is released, and the phase compensation elements are disabled as switches SW11 to SW13 are turned off. Switches SW21 to SW24 are turned on, and the gates of PMOS transistor PM1 and NMOS transistor NM1 are controlled by outputs G1 and G2, respectively. The signal output from inverter stage IV1 is then inverted sequentially by inverter stages IV2 and IV3, and output as output voltage OUT. In this state, the differential circuit 5 functions as a comparator. In comparator mode, the output voltage OUT is at a high level or a low level depending on the relative magnitudes of voltages INp and INn.

[0029] With this configuration, both comparator and operational amplifier functions can be realized by creating the differential circuit 5 with the same mask, leading to cost reduction. In addition, the comparator and operational amplifier modes are switched by a switching signal SW, and in comparator mode, the phase compensation element is disabled, thus shortening the propagation delay time, which is a critical characteristic of comparators.

[0030] <Effect Confirmation> For the differential circuit 5 described above, the operational stability when the level of the switching signal SW is switched was compared using a simulation of the NULL method, which is one of the methods for measuring the input offset voltage.

[0031] Figure 5 shows an example of a measurement circuit for the NULL method. The differential circuit 5 is applied to the DUT under measurement shown in Figure 5. In the NULL method, a negative feedback amplifier circuit is configured that multiplies the input offset voltage of the DUT under measurement by (1 + Rf / Rs), and minute input offset voltages are measured. Figure 6 shows the simulation results of the NULL method. In Figure 6, from top to bottom, the output voltage OUT of the differential circuit 5, the output voltage VF of the op-amp NULL (Figure 5), and the switching signal SW are shown.

[0032] When the switching signal SW was set to a high level to enter comparator mode, phase compensation was disabled, resulting in oscillation. However, when the switching signal SW was set to a low level to enter operational amplifier mode, phase compensation prevented oscillation, and stable operation was achieved. Therefore, it was confirmed that the switching between comparator and operational amplifier modes was successfully performed by the switching signal SW.

[0033] Figure 7 shows an example of the results of measuring the behavior of differential circuit 5 using the measurement circuit shown in Figure 1 (however, the polarity of the inputs of the operational amplifier and comparator is reversed compared to Figure 1). In Figure 7, from top to bottom, the input voltage Vin, the output voltage OUT in operational amplifier mode (solid line), and the output voltage OUT in comparator mode (dashed line) are shown. As shown, a sufficiently large difference was observed between the propagation delay time t_comp in comparator mode and the propagation delay time t_opa in operational amplifier mode.

[0034] <Variation> Figure 8 shows the configuration of the differential circuit 5 in a modified example. The differences from Figure 3 are as follows: In the output stage 3, the Class AB buffer stage 31 is omitted, and instead, a PMOS transistor 6 and a constant current source 7 are provided. The source of the PMOS transistor 6 is connected to the terminal to which the voltage VDD is applied. The gate and drain of the PMOS 6 are short-circuited. The constant current source 7 is connected between the drain of the PMOS transistor 6 and the terminal to which the voltage VSS is applied.

[0035] The gate of PMOS transistor 6 is connected to the gate of PMOS transistor PM3 via switch SW14. Switch SW11, capacitor C1, and resistor R1 are omitted. Switches SW21 and SW16 are also omitted.

[0036] With this configuration, when the switching signal SW is at a low level, switches SW22 to SW24 are in the off state and switches SW12 to SW15 are in the on state, resulting in op-amp mode. At this time, the gate signal G1 applied to the gate of PMOS transistor PM3 is set as the current mirror voltage by PMOS transistor 6 and constant current source 7, and a constant current flows through PMOS transistor PM3. The gate of NMOS transistor 3 is controlled by the gate signal G2 output from cascode gain stage 2.

[0037] In op-amp mode, switch SW22 is in the off state, cutting off the current path through the NMOS transistor NM1. This eliminates the current path of the current mirror, fixing the input signal of inverter stage IV2 to a high level. As a result, switch SW16 for logic fixing, as shown in the configuration of Figure 3, becomes unnecessary.

[0038] <Method for generating switching signals> Figure 9 shows the configuration of differential circuit 5, including an example of a circuit that generates a switching signal SW. Here, the switching signal SW is generated by adding a pad PD, a pull-up resistor Rp, and a Schmitt trigger ST to the same configuration as in Figure 3.

[0039] The pad PD is pulled up to voltage VDD by a pull-up resistor Rp. The potential of pad PD is input to Schmitt trigger ST. A switching signal SW is output from Schmitt trigger ST. Alternatively, pad PD may be pulled down to voltage VSS.

[0040] With this configuration, applying a low-level signal (the same potential as voltage VSS) to pad PD during wafer testing sets the switching signal SW to a low level, enabling operation in op-amp mode. In a product where the differential circuit 5 is packaged as a semiconductor device, pad PD is open, so the switching signal SW becomes high level, and it operates in comparator mode.

[0041] High-speed response comparators have poor stability in test environments with high stray capacitance or noise. Therefore, switching to op-amp mode only during testing, as described above, improves measurement stability and enables stable shipping tests.

[0042] Figure 10 shows the configuration of the differential circuit 5, including another example of the circuit that generates the changeover signal SW. Here, the changeover signal SW is generated by adding a fuse FS, a constant current source 8, and an inverter 9 to the same configuration as in Figure 3.

[0043] One end of the constant current source 8 is connected to the voltage VDD application terminal. A fuse FS is connected between the other end of the constant current source 8 and the voltage VSS application terminal. The potential of the node where the constant current source 8 and fuse FS are connected is input to the inverter 9. A switching signal SW is output from the inverter 9.

[0044] In this configuration, if fuse FS is not cut, the voltage input to inverter 9 becomes (constant current × fuse resistance) because fuse FS has a low impedance (several ohms), resulting in approximately 0V. This causes the changeover signal SW to be at a high level, resulting in comparator mode. On the other hand, if fuse FS is cut, there is no path for the constant current to flow, and the voltage input to inverter 9 rises to voltage VDD. This causes the changeover signal SW to be at a low level, resulting in operational amplifier mode. Thus, the presence or absence of fuse FS allows selection between comparator mode and operational amplifier mode.

[0045] Figure 11 shows the configuration of differential circuit 5, including yet another example of the circuit that generates the switching signal SW. Here, the configurations of Figures 9 and 10 described above are combined with the same configuration as in Figure 3. Specifically, a pull-up resistor Rp, a pad PD, a fuse FS, a constant current source 8, an inverter 9, a Schmitt trigger ST, and an AND gate 10 are provided. The output of the Schmitt trigger ST and the output of the inverter 9 are input to the AND gate 10. The switching signal SW is output from the AND gate 10.

[0046] With this configuration, if the fuse FS is not cut, the output of the inverter 9 becomes high level, and the level of the switching signal SW is determined according to the output level of the Schmitt trigger ST. That is, when a low-level signal is applied to the pad PD, the switching signal SW becomes low level, resulting in op-amp mode, and when the pad PD is open, the switching signal SW becomes high level, resulting in comparator mode. Therefore, when using a comparator in a product, the op-amp mode can be achieved by applying a signal to the pad PD only during testing without cutting the fuse FS.

[0047] On the other hand, if fuse FS is cut, the output of inverter 9 becomes low level, and the switching signal SW becomes low level regardless of the state of pad PD, resulting in op-amp mode. Therefore, to use the product in op-amp mode, simply cut fuse FS.

[0048] <Number of inverter stages> For example, in the configuration shown in Figure 3, there are three inverter stages (IV1 to IV3). However, this is not the only option; for example, in the configuration shown in Figure 3, inverter stages IV1 and IV2 may be omitted, as may switches SW21 to SW24 and SW14 and SW15. In other words, the number of inverter stages may be reduced to one (IV3 only), and the phase compensation elements may be enabled or disabled using switches SW11 to SW13. However, in this case, if the size of the PMOS and NMOS transistors in the inverter stage is increased to increase their current capability, the responsiveness in comparator mode will decrease. Therefore, if high-speed response in comparator mode is required, it is desirable to provide at least one inverter stage before the final inverter stage (IV3) and to increase the size of the transistors in the final inverter stage.

[0049] However, if the inverter stage preceding the final inverter stage is an odd number of stages, the polarity of the output voltage OUT will be reversed between comparator mode and op-amp mode, so it is preferable to have an even number of stages. The configuration in Figure 3 is an example of the above even number of stages, consisting of two stages.

[0050] <Other> Furthermore, the various technical features disclosed herein can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the technical creation. In other words, the embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of this disclosure should be understood to include all modifications that fall within the meaning and scope equivalent to the claims, rather than being limited to the embodiments described above.

[0051] <Note> As described above, the differential circuit (5) according to one aspect of the present disclosure is A differential input stage (1) is configured such that the differential voltage between the inverting input terminal (Tn) and the non-inverting input terminal (Tp) is input, A gain stage (2) configured to amplify the output of the differential input stage, An output stage (3) is configured to receive the signal from the aforementioned gain stage and output an output signal (OUT), The configuration includes a first switching circuit (SW11, SW12, SW13) configured to switch the enabled and disabled states of the phase compensation elements (C1, C2) included in the output stage based on a switching signal (SW) (first configuration, Figure 3).

[0052] With this configuration, enabling the phase compensation element via a switching signal results in op-amp mode, while disabling it operates in comparator mode. Both op-amps and comparators can be created using the same mask, reducing costs. In comparator mode, propagation delay time can be shortened.

[0053] Furthermore, in the first configuration described above, the output stage (3) is, The final stage is the first inverter stage (IV3), A second inverter stage (IV1, IV2) is provided prior to the first inverter stage, A second switching circuit (SW14, SW15) is configured to enable / disable the bypass between the application terminal of the first gate signal (G1) and the gate of the first PMOS transistor (PM3) in the first inverter stage, and the bypass between the application terminal of the second gate signal (G2) and the gate of the first NMOS transistor (NM3) in the first inverter stage, based on the switching signal. The system may also have a configuration that includes a third switching circuit (SW21~SW24) configured to switch the enabled / disabled state of the second inverter stage based on the switching signal (second configuration).

[0054] Furthermore, in the second configuration described above, the number of stages in the second inverter stage may be an even number (third configuration).

[0055] Furthermore, in the second or third configuration described above, the output stage is A Class AB buffer stage (31) is configured to receive the output of the gain stage and output the first gate signal and the second gate signal, A first switch (SW21) is connected to the drain of the second PMOS transistor (PM1) included in the preceding second inverter stage (IV1), A second switch (SW22) is connected to the drain of the second NMOS transistor (NM1) included in the preceding second inverter stage (IV1), A configuration may also be provided that includes a third switch (SW16) connected between the input terminal and the terminal to which a predetermined potential (VSS) is applied in the downstream second inverter stage (IV2) (fourth configuration, Figure 3).

[0056] Furthermore, in the second or third configuration described above, the output stage includes a third PMOS transistor (6) whose source is connected to the terminal to which the first voltage (VDD) is applied and whose drain and gate are short-circuited, A first constant current source (7) connected to the drain of the third PMOS transistor, It has, The gate signal of the third PMOS transistor is the first gate signal (G1), The output of the gain stage may be the second gate signal (G2) (fifth configuration, Figure 8).

[0057] Furthermore, in the fifth configuration described above, the gate of the fourth PMOS transistor (PM1) included in the preceding second inverter stage (IV1) is connected to the gate of the third PMOS transistor. The second gate signal is input to the gate of the third NMOS transistor (NM1) included in the second inverter stage on the preceding side. The configuration may further include a fourth switch (SW22) connected to the drain of the third NMOS transistor (sixth configuration, Figure 8).

[0058] Furthermore, in any of the above configurations 1 to 6, the pad (PD) and The pad is provided with a resistor (Rp) for pulling up or pulling down the pad, The switching signal may be generated based on the potential of the pad (seventh configuration, Figure 9).

[0059] Furthermore, in any of the first to sixth configurations described above, a constant current source (8) and a fuse (FS) may be provided connected between the application terminal of the first voltage (VDD) and the application terminal of the second voltage (VSS), and the switching signal may be generated depending on whether the fuse is cut or not (eighth configuration, Figure 10).

[0060] Furthermore, in any of the above configurations 1 to 6, the pad (Pd) and A resistor (Rp) that pulls up or pulls down the aforementioned pad, A constant current source (8) and a fuse (FS) are connected between the terminal to which the first voltage is applied and the terminal to which the second voltage is applied. A logic gate (10) may be configured to receive a first input signal based on the potential of the pad and a second input signal depending on whether the fuse is cut, and to output the switching signal (9th configuration, Figure 11). [Industrial applicability]

[0061] This disclosure can be used as a comparator or operational amplifier. [Explanation of symbols]

[0062] 1 Differential Input Stage 2 Cascode Gain Stage 3 Output Stages 4 Inverters 5. Differential Circuits 6 PMOS transistors 7 Constant current source 8 constant current source 9 Inverter 10 AND Gate 31 Class AB buffer stage C1, C2 Capacitors CMP Comparator DUT Measurement Target FS Fuse IV1~IV3 Inverter Stages NM1 NMOS transistor NM2 NMOS transistor NM3 NMOS transistor NULL op-amp OP Op-amp PD pad PM1 PMOS transistor PM2 PMOS transistor PM3 PMOS transistor R1,R2 resistance Rp pull-up resistor ST Schmitt trigger SW11~SW16 Switches SW21~SW24 Switches Tn Inverting Input Terminal Tout output terminal Tp Non-inverting input terminal Tsw switching terminal

Claims

1. A differential input stage configured to receive the differential voltage between an inverting input terminal and a non-inverting input terminal, A gain stage configured to amplify the output of the differential input stage, An output stage configured to receive the signal from the aforementioned gain stage and output an output signal, A first switching circuit is configured to enable or disable a phase compensation element included in the output stage based on a switching signal, A differential circuit comprising:

2. The aforementioned output stage is The final stage is the first inverter stage, A second inverter stage is provided prior to the first inverter stage, A second switching circuit is configured to enable / disable the bypass between the application terminal of the first gate signal and the gate of the first PMOS transistor in the first inverter stage, and the bypass between the application terminal of the second gate signal and the gate of the first NMOS transistor in the first inverter stage, based on the switching signal. A third switching circuit configured to enable or disable the second inverter stage based on the switching signal, A differential circuit according to claim 1, having the following features.

3. The differential circuit according to claim 2, wherein the number of stages in the second inverter stage is an even number.

4. The aforementioned output stage is A Class AB buffer stage is configured to receive the output of the gain stage and output the first gate signal and the second gate signal, A first switch connected to the drain of the second PMOS transistor included in the preceding second inverter stage, A second switch connected to the drain of the second NMOS transistor included in the preceding second inverter stage, A third switch connected between the input terminal and the terminal to which a predetermined potential is applied in the second inverter stage on the downstream side, A differential circuit according to claim 2 or claim 3, having the following features.

5. The aforementioned output stage is A third PMOS transistor, whose source is connected to the terminal to which the first voltage is applied and whose drain gate is short-circuited, A first constant current source connected to the drain of the third PMOS transistor, It has, The gate signal of the third PMOS transistor is the first gate signal, The differential circuit according to claim 2 or 3, wherein the output of the gain stage is the second gate signal.

6. The gate of the fourth PMOS transistor included in the preceding second inverter stage is connected to the gate of the third PMOS transistor. The second gate signal is input to the gate of the third NMOS transistor included in the preceding second inverter stage. The differential circuit according to claim 5, further comprising a fourth switch connected to the drain of the third NMOS transistor.

7. pads and, The pad comprises a resistor for pulling up or pulling down the pad, The differential circuit according to claim 1, wherein the switching signal is generated based on the potential of the pad.

8. The system includes a constant current source and a fuse connected between the terminal for applying a first voltage and the terminal for applying a second voltage. The differential circuit according to claim 1, wherein the switching signal is generated depending on whether the fuse is cut or not.

9. pads and, A resistor for pulling up or pulling down the aforementioned pad, A constant current source and a fuse are connected between the terminal to which the first voltage is applied and the terminal to which the second voltage is applied. A logic gate is configured to receive a first input signal based on the potential of the pad and a second input signal depending on whether the fuse is cut or not, and to output the switching signal. The differential circuit according to claim 1, comprising:

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