Polycrystalline SiC substrates and semiconductor substrates

Abstract

The present invention provides a polycrystalline SiC substrate and a semiconductor substrate suitable for bonding with single-crystal SiC, which can suppress bonding defects with single-crystal SiC by having fewer polar surfaces on the bonding surface that bonds with single-crystal SiC. [Solution] A polycrystalline SiC substrate for a support substrate to form a semiconductor substrate by bonding with a single-crystal SiC substrate, wherein the area ratio of polar surfaces on the bonding target surface that bonds with the single-crystal SiC substrate is 3.0% or less.

Description

Technical Field

[0001] The present invention relates to a polycrystalline SiC substrate and a semiconductor substrate.

Background Art

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor having a wide bandgap of 2.2 to 3.3 eV, and due to its excellent physical and chemical properties, research and development have been carried out as an environmentally resistant semiconductor material. In particular, in recent years, SiC has attracted attention as a material for high-voltage / high-power electronic devices, high-frequency electronic devices, and short-wavelength optical devices from blue to ultraviolet, and research and development have been actively conducted. However, it is difficult to manufacture a high-quality large-diameter single crystal of SiC, which has hitherto hindered the practical application of SiC devices.

[0003] In order to solve this problem, an improved Lely method has been developed in which sublimation recrystallization is performed using a SiC single crystal substrate as a seed crystal. By using this improved Lely method, it is possible to grow a SiC single crystal while controlling the crystal polymorphism (4H-SiC, 6H-SiC, 15R-SiC, etc.), shape, carrier type, and concentration of the SiC single crystal. By optimizing this improved Lely method, the crystal defect density has been greatly reduced, and it has become possible to form electronic devices such as Schottky diodes (SBD) and metal-oxide-semiconductor field-effect transistors (MOSFET) on the substrate.

[0004] However, in the improved Lely method using a SiC single crystal substrate as a seed crystal, the manufacturing cost of the single crystal SiC substrate is high due to the low growth rate of the single crystal SiC crystal and the high processing cost when processing the SiC single crystal ingot into a wafer mainly through processes such as cutting and polishing. This high manufacturing cost is also a factor hindering the practical application of SiC devices, and there has been a strong demand for the development of a technology that can provide SiC substrates for semiconductor device applications, particularly for high-voltage / high-power electronic device applications, at a low cost.

[0005] Therefore, a technology has been provided for manufacturing a semiconductor substrate that combines low cost (support substrate portion) and high quality (SiC portion) by using high-quality single-crystal SiC only for the device formation layer portion and fixing it to the bonding target surface of a support substrate (a material having sufficient strength, heat resistance, and cleanliness to withstand the device manufacturing process: for example, polycrystalline SiC) using a bonding method that does not involve the formation of an oxide film at the bonding interface (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2015-15401 [Overview of the project] [Problems that the invention aims to solve]

[0007] In the bonding process, the surface roughness of the bonding surface of polycrystalline SiC is considered important. If the surface roughness, that is, the fine irregularities on the surface, is large, the polycrystalline SiC substrate and the single-crystal SiC substrate will not be able to adhere sufficiently and bond properly. Alternatively, even if bonding is achieved, fine gaps will form at the bonding interface between the polycrystalline SiC substrate and the single-crystal SiC substrate, resulting in numerous defects (bonding defects).

[0008] If bonding defects occur, there is a possibility that killer defects may be generated starting from these bonding defects during the subsequent epitaxial deposition process, when a single-crystal SiC layer is deposited on the single-crystal SiC substrate. Therefore, to improve the quality of the bonded substrate, it is necessary to reduce the surface roughness of the bonding surface of the polycrystalline SiC substrate to prevent the occurrence of numerous bonding defects.

[0009] Polycrystalline SiC substrates are formed using a method in which polycrystalline SiC is grown on a substrate made of, for example, carbon, by chemical vapor deposition (CVD), and then the substrate is removed.

[0010] The arithmetic surface roughness Ra of the polycrystalline SiC substrate used in the bonding process for joining a single-crystal SiC substrate to a polycrystalline SiC substrate is required to be around 0.1 to 0.5 nm. To achieve this surface roughness, the bonding surface is, for example, subjected to CMP (chemical mechanical polishing) to obtain a CMP-polished surface. However, in order to prevent bonding defects, not only the polishing method but also the physical properties of the polycrystalline SiC substrate (crystal grain size, crystal structure, orientation) are important. In other words, single-crystal SiC is one large crystal grain oriented in the same direction, so the polishing surface of the single-crystal SiC substrate can be polished uniformly by CMP, making it easy to obtain a high-precision polished surface with less surface roughness compared to polycrystalline SiC substrates. On the other hand, polycrystalline SiC is an aggregate of small crystal grains oriented in various directions, so the polishing speed of the polishing surface during CMP differs for each crystal grain, resulting in different amounts of wear for each crystal grain. As a result, countless irregularities tend to occur along the grain boundaries on the polishing surface, making it more difficult to obtain a polished surface with less surface roughness compared to single-crystal SiC substrates.

[0011] In particular, surfaces where the Si or C end faces are exposed on the polishing surface (polar surfaces) exhibit a greater difference in polishing speed by CMP compared to other orientation surfaces, making them more prone to generating irregularities along grain boundaries. Polar surfaces vary depending on the crystal structure of SiC, but specifically, 3C(111) and 6H(0001) are examples of polar surfaces. For example, the orientation of polycrystalline SiC deposited by CVD changes depending on the deposition conditions, but if there are locally polar grains within a nearly unoriented polishing surface, irregularities will develop in those areas according to the Si or C end faces. The change in polishing speed is unique; even when polished under the same conditions, the Si end faces protrude and become convex due to the slower polishing speed and less wear, while the C end faces become concave due to the faster polishing speed and greater wear.

[0012] Therefore, in order to solve the above problems, the present invention aims to provide a polycrystalline SiC substrate and a semiconductor substrate suitable for bonding with single-crystal SiC, which can suppress bonding defects with single-crystal SiC by having fewer polar surfaces on the bonding target surface that bonds with single-crystal SiC. [Means for solving the problem]

[0013] To solve the above problems, the present invention provides a polycrystalline SiC substrate for use as a support substrate to form a semiconductor substrate by bonding it with a single-crystal SiC substrate, wherein the area ratio of polar surfaces on the bonding surface to be bonded with the single-crystal SiC substrate is 3.0% or less.

[0014] The area-weighted average particle diameter of the crystal grains on the bonding surface may be 10 μm or less.

[0015] The arithmetic surface roughness Ra of the bonding surface may be 0.5 nm or less.

[0016] Furthermore, in order to solve the above problems, the semiconductor substrate of the present invention is a semiconductor substrate in which the polycrystalline SiC substrate of the present invention and a single-crystal SiC substrate are bonded together, wherein the number of bonding defects at the bonding interface between the polycrystalline SiC substrate and the single-crystal SiC substrate is 1 / cm². 2 The following applies: [Effects of the Invention]

[0017] The present invention provides a polycrystalline SiC substrate and a semiconductor substrate suitable for bonding with single-crystal SiC, which can suppress bonding defects with single-crystal SiC by reducing the number of polar surfaces on the bonding surface that bonds with single-crystal SiC. [Brief explanation of the drawing]

[0018] [Figure 1] This is a schematic perspective view of a polycrystalline SiC substrate 100. [Figure 2] This is a schematic diagram of the semiconductor substrate 300. [Figure 3] This is a flowchart showing the manufacturing methods for the polycrystalline SiC substrate 100 and the semiconductor substrate 300. [Figure 4] This is a cross-sectional view showing a method for manufacturing a polycrystalline SiC substrate 100. [Figure 5]It is a cross-sectional view showing polycrystalline SiC 22 grown on a carbon substrate 21 which is a lower base material. [Figure 6] It is a diagram showing a schematic configuration of a batch type growth furnace 30.

Embodiments for Carrying out the Invention

[0019] Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

[0020] [Polycrystalline SiC Substrate 100] Fig. 1 shows a schematic perspective view of a polycrystalline SiC substrate 100, and Fig. 2 shows a schematic view of a semiconductor substrate 300. The polycrystalline SiC substrate 100 of the present invention is a polycrystalline SiC substrate for a support substrate that is bonded to a single crystal SiC substrate 200 to form a semiconductor substrate 300 which is a bonded substrate.

[0021] The polycrystalline SiC substrate 100 is formed, for example, in a disk shape with a thickness of about 350 μm, and the polycrystalline SiC is composed of any one of 4H-SiC crystals, 6H-SiC crystals, and 3C-SiC crystals, or a mixture thereof.

[0022] (Area Ratio of Polar Plane on Bonding Target Surface 110) The polycrystalline SiC substrate 100 includes a bonding target surface 110 which is a bonding surface for bonding to the single crystal SiC substrate 200. By the area ratio of the polar plane on the bonding target surface 110 being 3.0% or less, the smoothness of the bonding target surface 110 is maintained well, and the number of bonding defects at the bonding interface 310 per semiconductor substrate 300 described later can be maintained at 1 piece / cm 2 or less. When the area ratio of the polar plane is greater than 3.0%, the smoothness of the bonding target surface 110 decreases, and the number of bonding defects at the bonding interface 310 tends to increase. The lower limit value of the area ratio of the polar plane may be 0%, but in practice, it is about 0.3% as the lower limit value.

[0023] The area ratio of polar surfaces can be calculated using a scanning electron microscope (SEM-EBSD). The procedure involves first acquiring a backscattered electron image of the bonding surface 110, composed of pixels, using a scanning electron microscope (SEM). Then, the image is stratified into crystal systems such as SiC-3C, SiC-2H, SiC-4H, and SiC-6H using a phase map. Furthermore, regions recognized as polar surfaces are identified using the crystal orientation map, and the area ratio of polar surfaces is calculated from these regions. The number of pixels within the field of view was used to quantify the regions recognized as polar surfaces. As shown in equation (1) below, the sum of the number of pixels determined to be polar surfaces in each crystal system is used as the numerator, and the total number of pixels in the field of view is multiplied by 100 to obtain the area ratio of polar surfaces.

[0024] [Formula 1] Area ratio of polar surfaces = Number of pixels recognized as polar surfaces / Total number of pixels in the field of view (1)

[0025] (area weighted average particle diameter) The area-weighted average particle diameter of the crystal grains on the bonding surface 110 is 10 μm or less. If the area-weighted average particle diameter is 10 μm or less, the area of ​​each polar surface becomes small, the smoothness of the bonding surface 110 is well maintained, and the number of bonding defects at the bonding interface 310 per semiconductor substrate 300, as described later, is 1 / cm². 2 The following conditions can be maintained. If the area-weighted average particle diameter is greater than 10 μm, the area per polar surface increases, the smoothness of the bonding surface 110 decreases, and the number of bonding defects at the bonding interface 310 tends to increase. The lower limit of the area-weighted average particle diameter is not particularly limited, but in practice, it is around 0.1 μm.

[0026] The area-weighted average particle diameter can be calculated using a scanning electron microscope (SEM-EBSD). The procedure involves first obtaining a backscattered electron image of the bonding surface 110, which is composed of pixels, using a scanning electron microscope (SEM). Based on the backscattered electron image, grain boundaries are defined as those with an orientation difference of 10° or more, and a crystal grain map is created. Next, each crystal grain is converted to a perfect circle to obtain crystal grain diameter data. Furthermore, using the obtained crystal grain diameter data, a weighted average is calculated based on the area ratio with the area of ​​the field of view, and this is defined as the area-weighted average particle diameter.

[0027] (Arithmetic surface roughness Ra of the surfaces to be joined) The arithmetic surface roughness Ra of the bonding surface 110 is 0.5 nm or less. This arithmetic surface roughness Ra of 0.5 nm or less ensures good smoothness of the bonding surface 110, resulting in a bonding defect count of 1 defect / cm² at the bonding interface 310 per semiconductor substrate 300, as described later. 2 The following conditions can be maintained. If the arithmetic surface roughness Ra is greater than 0.5 nm, the smoothness of the bonding surface 110 decreases, and the number of bonding defects at the bonding interface 310 tends to increase. The lower limit of the arithmetic surface roughness Ra is not particularly limited, but in practice, it is around 0.1 nm.

[0028] Arithmetic surface roughness Ra can be measured using a SiC wafer defect inspection / review system. An example of such a system is the Lasertec SICA88.

[0029] [Semiconductor substrate 300] Next, the semiconductor substrate 300 of the present invention will be described. The semiconductor substrate 300 is a semiconductor substrate formed by bonding the polycrystalline SiC substrate 100 and a single-crystal SiC substrate 200 described above. The semiconductor substrate 300 is formed by bonding the bonding target surface 110 of the polycrystalline SiC substrate 100 and the bonding target surface 210 of the single-crystal SiC substrate 200.

[0030] (Single crystal SiC substrate 200) The single-crystal SiC substrate 200 is made of single-crystal SiC and is formed, for example, in the shape of a disc with a thickness of about 1 μm. The single-crystal SiC of the single-crystal SiC substrate 200 is composed of 4H-SiC crystals, 6H-SiC crystals, and 3C-SiC crystals, or a mixture thereof.

[0031] (Number of joint defects) If the bonding interface 310 is defined as the interface where the bonding target surface 110 of the polycrystalline SiC substrate 100 and the bonding target surface 210 of the single-crystal SiC substrate 200 are joined on the semiconductor substrate 300, then it is preferable that there are no gaps at the bonding interface 310 between the bonding target surface 110 and the bonding target surface 210, and that they are completely joined. It is acceptable for there to be gaps at the bonding interface 310, resulting in unjoined areas, i.e., bonding defects such as voids or untransferred defects. However, since areas with bonding defects cannot be used as materials for electronic devices such as SBDs and MOSFETs, the number of bonding defects at the bonding interface 310 per semiconductor substrate 300 should be 1 / cm². 2 The following is preferable:

[0032] Bonding defects at the bonding interface 310 can be measured using a SiC wafer defect inspection / review system. An example of such a system is the SICA88 manufactured by Lasertec.

[0033] [Manufacturing method for polycrystalline SiC substrate 100 and semiconductor substrate 300] The following describes an example of a manufacturing method for the polycrystalline SiC substrate 100 and the semiconductor substrate 300. Figure 3 is a flowchart showing the manufacturing method for the polycrystalline SiC substrate 100 and the semiconductor substrate 300. Figure 4 is a cross-sectional view showing the manufacturing method for the polycrystalline SiC substrate 100. Figure 5 is a cross-sectional view showing the polycrystalline SiC 22 grown on the carbon substrate 21, which is the base material. Figure 6 is a diagram showing the schematic configuration of the batch-type growth furnace 30.

[0034] As shown in Figure 3, in the manufacturing method of the polycrystalline SiC substrate 100 and semiconductor substrate 300, first in step S10, a base material fabrication step is performed. In this embodiment, the base material refers to the material that serves as the base for growing polycrystalline SiC. In the base material fabrication step, first, as shown in Figure 5, polycrystalline SiC 22 with a thickness of, for example, 2 mm is grown on the surface of a carbon substrate 21 formed in the shape of a carbon disc by chemical vapor deposition (CVD). Examples of raw material gases for Si include tetrachlorosilane, trichlorosilane, and dichlorosilane. Examples of raw material gases for C include ethane, propane, and acetylene. Alternatively, a single gas such as tetramethylsilane may be used as the raw material gas. The growth temperature in this chemical vapor deposition method is, for example, 1400°C. After the growth of the polycrystalline SiC 22, the outer circumference of the disc-shaped member on which the polycrystalline SiC 22 has been formed on the surface of the carbon substrate 21 is ground. Then, this disc-shaped member is heated in an atmospheric atmosphere at 1000°C. As a result, the carbon substrate 21 burns in an atmospheric environment, and the carbon substrate 21 is removed from the polycrystalline SiC 22. Next, the outermost growth surface 22a of the polycrystalline SiC 22 is flattened by grinding, for example, 0.2 mm, and then the carbon substrate side surface 22b of the polycrystalline SiC 22 is ground by, for example, 1.45 mm. This yields a base substrate 11 with a thickness of 0.35 mm (see base substrate 11 in Figure 4).

[0035] Next, in step S20, the SiC growth process is carried out. In the SiC growth process, first, the substrate material 11 is loaded into the growth furnace 30, as shown in Figure 6. After loading the substrate material 11, polycrystalline SiC 12 with a thickness of, for example, 400 μm is grown by chemical vapor deposition. Because this is a chemical vapor deposition method using a growth furnace, polycrystalline SiC 12 grows on the front and back surfaces of the substrate material 11, as shown in Figure 4. Examples of raw material gases for Si include tetrachlorosilane, trichlorosilane, and dichlorosilane. Examples of raw material gases for C include ethane, propane, and acetylene. Alternatively, a single gas such as tetramethylsilane may be used as the raw material gas. The growth temperature in this chemical vapor deposition method is, for example, 1400°C.

[0036] Next, in step S30, a peeling process is performed. In the peeling process, as shown in Figure 4, a laser beam LS (wavelength 532 nm) is irradiated onto the surface of the polycrystalline SiC12 at a depth of, for example, 400 μm, to sublimate the SiC. Then, by scanning the laser beam LS in two dimensions along a plane parallel to the contact surface in which the polycrystalline SiC12 is in contact with the substrate 11, a cut surface is formed at a depth of 400 μm from the surface, and the polycrystalline SiC12 is peeled off from the substrate 11.

[0037] Next, in step S40, a surface polishing process is performed. In the surface polishing process, the amorphous layer formed on the surface of the polycrystalline SiC12 is removed first by high-precision grinding, and then by CMP polishing, and the surface of the polycrystalline SiC12 is made smooth. The polycrystalline SiC12 obtained after the surface polishing process is used as the polycrystalline SiC substrate 100. In step S30, the amorphous layer formed on the surface of the base material 11 is removed by hydrogen gas supplied during the heating process in the growth furnace 30. That is, the second base material 11 can be reused to manufacture the polycrystalline SiC substrate 100.

[0038] Next, in step S50, a bonding process is performed. In the bonding process, first, hydrogen ions with a predetermined implantation energy corresponding to the thickness of the single-crystal SiC substrate 200 are implanted from the surface side of the pre-prepared single-crystal SiC substrate toward the surface of the single-crystal SiC substrate. As a result, an ion implantation layer is formed on the single-crystal SiC substrate at a predetermined depth corresponding to the implantation energy from the surface of the single-crystal SiC substrate. Then, the surface of the single-crystal SiC substrate is bonded to the surface of the polycrystalline SiC 12 manufactured in step S40 using a surface activation method. The polycrystalline SiC 12 and the single-crystal SiC substrate, which are bonded together, are then heated. As a result, the single-crystal SiC substrate breaks at the ion implantation layer, and the single-crystal SiC substrate 200 peels off from the polycrystalline SiC substrate 100 while it is still bonded to the surface of the polycrystalline SiC substrate 100, thereby obtaining the semiconductor substrate 300. [Examples]

[0039] The present invention will be described in more detail below with reference to examples, but the present invention is not limited in any way to the following examples.

[0040] Three 6-inch polycrystalline SiC substrates, A, B, and C, were obtained using CVD deposition under different conditions. For each of these substrates, SEM-EBSD analysis, surface roughness of the polished surface, and the number of junction defects in the semiconductor substrate were investigated.

[0041] For the SEM-EBSD analysis, a Carl Zeiss ULTRA55 SEM and a HKL Channel5 EBSD scanner were used.

[0042] The bonding surface of the polycrystalline SiC substrate was precisely ground using a metal surface plate and diamond fine particle powder, and finally the surface was finished with CMP polishing to create a polished surface.

[0043] For measuring the surface roughness of the bonding surface of the polished polycrystalline SiC substrate and the number of bonding defects at the bonding interface between the polycrystalline SiC substrate and the single-crystal SiC substrate in the semiconductor substrate, a SiC wafer defect inspection / review system (SiC A88, manufactured by Lasertec) was used.

[0044] The bonding surface of the single-crystal SiC was finished to a surface roughness of approximately Ra = 0.1 nm by CMP polishing. Ra = 0.1 nm is the lower limit of surface roughness that can realistically be obtained by polishing a SiC single crystal, and since the typical interatomic distance of SiC is 0.188 nm, it indicates that there are almost no atomic-level steps on the bonding surface. By using a substrate with such a surface texture, the occurrence of bonding defects caused by the surface roughness of the single-crystal SiC substrate was prevented.

[0045] The joining method will now be explained. The joining process is mainly divided into an irradiation process and a contact process. First, in the irradiation process, a particle beam is irradiated onto the joining surfaces of the polycrystalline SiC and the single-crystal SiC. For example, a fast atomic beam (FAB) can be used as the particle beam. The particle beam is irradiated onto the entire surface of the joining surfaces of both the polycrystalline SiC and the single-crystal SiC. This removes the oxide film and adsorbed layer on the joining surfaces, exposing the bonding bonds. This is called the active state. Furthermore, since the irradiation process is performed in a vacuum, the joining surfaces are not oxidized and can maintain their active state. Next, in the contact process, the joining surfaces of the polycrystalline SiC and the single-crystal SiC are brought into contact in a vacuum. This causes the bonding bonds present on the active surface to connect, allowing the polycrystalline SiC and single-crystal SiC to be joined. For the irradiation and contact processes, a room-temperature joining apparatus MWV-06 / 08-AX-FAB manufactured by Mitsubishi Heavy Industries Machine Tools Ltd. was used.

[0046] Table 1 summarizes the area ratio of polar surfaces, area-weighted average particle diameter of crystal grains, arithmetic surface roughness Ra, and the number of bonding defects in the semiconductor substrates for each polycrystalline SiC substrate A, B, and C.

[0047] [Table 1]

[0048] It was observed that as the area ratio of polar surfaces and the area-weighted average particle diameter increased, the irregularities along the grain boundaries increased, and the arithmetic surface roughness Ra tended to deteriorate. In particular, when the area ratio of polar surfaces was 3.0% or higher and the area-weighted average particle diameter was 10.0 μm or higher, the arithmetic surface roughness Ra deteriorated significantly, and the number of bonding defects increased.

[0049] Based on the above, the present invention provides a polycrystalline SiC substrate and a semiconductor substrate suitable for bonding with single-crystal SiC, which can suppress bonding defects with single-crystal SiC by reducing the polarity of the bonding surface that bonds with single-crystal SiC, and is therefore industrially useful. [Explanation of symbols]

[0050] 11…Underlayment substrate, 12, 22…Polycrystalline SiC, 21…Carbon substrate, 100…Polycrystalline SiC substrate, 110…Bonding surface, 200…Single-crystal SiC substrate, 210…Bonding surface, 300…Semiconductor substrate, 310…Bonding interface

Claims

1. A polycrystalline SiC substrate for use as a support substrate to form a semiconductor substrate by bonding with a single-crystal SiC substrate, The bonding target surface comprises an oxide film or an adsorption layer, A polycrystalline SiC substrate without an amorphous layer, wherein the area ratio of polar surfaces on the bonding target surface that is bonded to the single-crystal SiC substrate is 0.3% or more and 3.0% or less.

2. The polycrystalline SiC substrate according to claim 1, wherein the area-weighted average particle diameter of the crystal grains on the bonding surface is 10 μm or less.

3. The polycrystalline SiC substrate according to claim 1 or 2, wherein the arithmetic surface roughness Ra of the bonding surface is 0.5 nm or less.

4. A polycrystalline SiC substrate according to any one of claims 1 to 3, in which the oxide film or the adsorption layer has been removed, A semiconductor substrate in which a single crystal SiC substrate and a bonded substrate are formed, The number of bonding defects at the bonding interface between the polycrystalline SiC substrate and the single-crystal SiC substrate is 1 defect / cm². ２ The following is a semiconductor substrate.

Images