Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce costs. [Solution] The parallel pn layer 43 is formed by epitaxial growth of a single n-type epitaxial layer 23 of a predetermined thickness as a product, and a single ion implantation of p-type impurities into the n-type epitaxial layer 23. This ion implantation is performed at high acceleration energy using an ion implantation mask 61 with a thickness t1 thin enough to form with good pattern dimensional accuracy. This ion implantation forms a p-type column region 42 that reaches a predetermined depth from the surface of the n-type epitaxial layer 23 at the opening 61a of the ion implantation mask 61. The ion-implanted p-type impurities are intentionally allowed to penetrate the ion implantation mask 61, forming a p-type impurity penetration layer 3a that becomes a p-type base region over the entire surface region of the n-type epitaxial layer 23 in the portion covered by the ion implantation mask 61.

Description

[Technical Field]

[0001] This disclosure relates to silicon carbide semiconductor devices and methods for manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, in SJ-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS-type field-effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) that have a superjunction (SJ) structure in which the drift layer is alternately arranged in a direction parallel to the main surface of the semiconductor substrate, it is known that the SJ structure is formed using a multi-stage epitaxial method (see, for example, Patent Document 1 below). A similar technique is also described in Patent Document 2 below. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-216182 [Patent Document 2] International Publication No. 2020 / 110514 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] As described in Patent Document 2 above, in the formation of an SJ structure using a multi-stage epitaxial method, the following steps are repeatedly performed in the same order under the same conditions: stacking of n-type epitaxial layers (epitaxial growth), formation of an ion implantation mask, ion implantation of p-type impurities, and removal of the ion implantation mask. When silicon carbide (SiC) is used as the semiconductor material, impurities do not diffuse easily into SiC, and it is common to increase the number of n-type epitaxial layers (number of stacks) to reduce the thickness of each layer. For this reason, the number of repetitions of the above process in the multi-stage epitaxial method is large, which increases the manufacturing lead time and the manufacturing cost.

[0005] This disclosure aims to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce costs in order to overcome the problems of the prior art described above. [Means for solving the problem]

[0006] A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide. The parallel pn layer is formed by alternately arranging a first conductivity type region and a second conductivity type region in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of the second conductivity type is provided between the first main surface and the parallel pn layer. A second semiconductor region of the first conductivity type is selectively provided between the first main surface and the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer.

[0007] A gate electrode, provided within the trench via a gate insulating film, is located inside the trench. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. The second electrode is located on the second main surface of the semiconductor substrate. The first and second conductivity regions extend linearly in a second direction parallel to the first main surface and perpendicular to the first direction. The trench extends linearly in the depth direction, parallel to the first main surface, and facing the second conductivity region in at least a portion of the trench. The first semiconductor region extends along the side wall of the trench. The second conductivity region penetrates the first semiconductor region.

[0008] Furthermore, a silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide. The parallel pn layer is formed by alternately arranging a first conductivity type region and a second conductivity type region in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of the second conductivity type is provided between the first main surface and the parallel pn layer. A second semiconductor region of the first conductivity type is selectively provided between the first main surface and the first semiconductor region. A trench penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer. A gate electrode is provided inside the trench via a gate insulating film. A first electrode is electrically connected to the first semiconductor region and the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate.

[0009] The first conductivity type region and the second conductivity type region extend linearly in a second direction parallel to the first main surface and perpendicular to the first direction. The trench faces the second conductivity type region in the depth direction and extends linearly in the second direction. The second semiconductor region is scattered along the side wall of the trench in the second direction. A third semiconductor region of the first conductivity type is provided inside the second conductivity type region at a position facing the second semiconductor region in the depth direction and deeper than the first semiconductor region towards the second main surface. The third semiconductor region is in contact with the gate insulating film of the side wall of the trench at one end in the first direction and in contact with the first conductivity type region at the other end in the first direction.

[0010] Furthermore, a method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is a method for manufacturing a silicon carbide semiconductor device comprising a parallel pn layer in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of a semiconductor substrate made of silicon carbide, and is as follows: A first step is performed in which a first conductivity type epitaxial layer that forms the first main surface is epitaxially grown on a starting substrate made of silicon carbide that forms the second main surface of the semiconductor substrate. A second step is performed in which an ion implantation mask is formed on the first conductivity type epitaxial layer, with an opening in the portion facing the formation region of the second conductivity type region.

[0011] A third step is performed in which a second conductivity type impurity is ion-implanted using the ion implantation mask, a second conductivity type region of a predetermined depth is formed in the first conductivity type epitaxial layer at the opening of the ion implantation mask, and the portion of the first conductivity type epitaxial layer excluding the second conductivity type region is left as the first conductivity type region to form the parallel pn layer. A fourth step is performed in which a predetermined device structure is formed between the first main surface and the parallel pn layer. A fifth step is performed in which a first electrode electrically connected to the device structure is formed. A sixth step is performed in which a second electrode is formed on the second main surface.

[0012] In the third step, the second conductivity type impurity penetrates the ion implantation mask and is ion-implanted with acceleration energy that has a range of the surface region of the first conductivity type epitaxial layer, and the second conductivity type impurity that penetrated the ion implantation mask forms a second conductivity type diffusion layer on the surface region of the first conductivity type epitaxial layer. In the fourth step, the device structure is formed through which an electric current flows via the pn junction between the second conductivity type diffusion layer and the first conductivity type region. [Effects of the Invention]

[0013] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device described herein have the effect of providing a silicon carbide semiconductor device that can reduce costs. [Brief explanation of the drawing]

[0014] [Figure 1] This is a perspective view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a perspective view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 3] This is a perspective view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 4] A perspective view (part 1) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 5] A perspective view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 6] A perspective view (part 3) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 7] This is a perspective view (part 4) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 8] A perspective view (part 5) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 9] A perspective view (part 6) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 10] A perspective view (part 7) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 11] This is a perspective view (part 8) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 12] This is a perspective view (part 9) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 13] A perspective view (part 10) showing the silicon carbide semiconductor device according to Embodiment 1 during the manufacturing process. [Figure 14] This is a perspective view (part 11) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 15]This is a perspective view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 16] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 17] This is a schematic diagram illustrating the simulation results of the distribution of p-type impurities ion-implanted into a silicon carbide epitaxial layer through a resist film. [Figure 18] This characteristic diagram shows the simulation results of the impurity concentration profile in the depth direction of the epitaxial layer in Example 2. [Modes for carrying out the invention]

[0015] <Summary of the embodiments of this disclosure> (1) A silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide. The parallel pn layer is formed by alternately arranging a first conductivity type region and a second conductivity type region in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of the second conductivity type is provided between the first main surface and the parallel pn layer. A second semiconductor region of the first conductivity type is selectively provided between the first main surface and the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer.

[0016] A gate electrode, provided within the trench via a gate insulating film, is located inside the trench. The first electrode is electrically connected to the first semiconductor region and the second semiconductor region. The second electrode is located on the second main surface of the semiconductor substrate. The first and second conductivity regions extend linearly in a second direction parallel to the first main surface and perpendicular to the first direction. The trench extends linearly in the depth direction, parallel to the first main surface, and facing the second conductivity region in at least a portion of the trench. The first semiconductor region extends along the side wall of the trench. The second conductivity region penetrates the first semiconductor region.

[0017] According to the disclosure described above, since parallel pn layers can be formed without using a multi-stage epitaxial method, the manufacturing process can be simplified and costs can be reduced.

[0018] (2) In addition, in the semiconductor device relating to this disclosure, in (1) above, the impurity concentration of the portion of the second conductivity type region that penetrates the first semiconductor region may be lower than the impurity concentration of the first semiconductor region.

[0019] According to the disclosure described above, on-resistance can be reduced.

[0020] (3) In addition, in the semiconductor device relating to this disclosure, the depth of the second conductivity type region may be 0.8 μm to 3.2 μm in the case of (1) or (2) described above.

[0021] According to the disclosure described above, the depth of the second conductivity type region can be appropriately set with a single high-acceleration energy ion implantation.

[0022] (4) Another silicon carbide semiconductor device according to one aspect of this disclosure is as follows: A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide. The parallel pn layer is formed by alternately arranging a first conductivity type region and a second conductivity type region in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of the second conductivity type is provided between the first main surface and the parallel pn layer. A second semiconductor region of the first conductivity type is selectively provided between the first main surface and the first semiconductor region. A trench penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer. A gate electrode is provided inside the trench via a gate insulating film. A first electrode is electrically connected to the first semiconductor region and the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate.

[0023] The first conductivity type region and the second conductivity type region extend linearly in a second direction parallel to the first main surface and perpendicular to the first direction. The trench faces the second conductivity type region in the depth direction and extends linearly in the second direction. The second semiconductor region is scattered along the side wall of the trench in the second direction. A third semiconductor region of the first conductivity type is provided inside the second conductivity type region at a position facing the second semiconductor region in the depth direction and deeper than the first semiconductor region towards the second main surface. The third semiconductor region is in contact with the gate insulating film of the side wall of the trench at one end in the first direction and in contact with the first conductivity type region at the other end in the first direction.

[0024] According to the disclosure described above, parallel pn layers can be formed without using a multi-stage epitaxial method, thus simplifying the manufacturing process and reducing costs. In addition, the channel area can be increased, improving channel characteristics.

[0025] (5) The semiconductor device according to this disclosure is characterized in that, in (4) above, a second conductivity type high-concentration region is provided between the bottom surface of the trench and the second conductivity type region, in contact with the second conductivity type region, and having a higher impurity concentration than the first semiconductor region.

[0026] According to the disclosure described above, the electric field applied to the gate insulating film can be mitigated.

[0027] (6) Furthermore, the semiconductor device according to this disclosure is characterized in that, in (4) or (5) above, the second conductivity type region has a relatively low impurity concentration in the portion sandwiched between the third semiconductor regions adjacent to each other in the second direction.

[0028] According to the disclosure described above, on-resistance can be reduced.

[0029] (7) Another method for manufacturing a silicon carbide semiconductor device according to one aspect of this disclosure is a method for manufacturing a silicon carbide semiconductor device comprising a parallel pn layer in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of a semiconductor substrate made of silicon carbide, and is as follows: A first step is performed in which a first conductivity type epitaxial layer that forms the first main surface is epitaxially grown on a starting substrate made of silicon carbide that forms the second main surface of the semiconductor substrate. A second step is performed in which an ion implantation mask is formed on the first conductivity type epitaxial layer, with an opening in the portion facing the region where the second conductivity type region is formed.

[0030] A third step is performed in which a second conductivity type impurity is ion-implanted using the ion implantation mask, a second conductivity type region of a predetermined depth is formed in the first conductivity type epitaxial layer at the opening of the ion implantation mask, and the portion of the first conductivity type epitaxial layer excluding the second conductivity type region is left as the first conductivity type region to form the parallel pn layer. A fourth step is performed in which a predetermined device structure is formed between the first main surface and the parallel pn layer. A fifth step is performed in which a first electrode electrically connected to the device structure is formed. A sixth step is performed in which a second electrode is formed on the second main surface.

[0031] In the third step, the second conductivity type impurity penetrates the ion implantation mask and is ion-implanted with acceleration energy that has a range of the surface region of the first conductivity type epitaxial layer, and the second conductivity type impurity that penetrated the ion implantation mask forms a second conductivity type diffusion layer on the surface region of the first conductivity type epitaxial layer. In the fourth step, the device structure is formed through which an electric current flows via the pn junction between the second conductivity type diffusion layer and the first conductivity type region.

[0032] According to the disclosure described above, since a multi-stage epitaxial method is not used to form the parallel pn layer, the manufacturing process is simplified, the lead time is shortened, and costs can be reduced.

[0033] (8) Furthermore, the semiconductor device according to this disclosure is characterized in that, in the third step described in (7) above, the thickness of the second conductive type diffusion layer is 0.8 μm or more and 1.5 μm or less.

[0034] According to the disclosure described above, it is possible to suppress the formation of a short-channel structure and thereby suppress the increase in leakage current, etc. Furthermore, it becomes easier to remove the second conductivity type diffusion layer in the edge termination region.

[0035] (9) The semiconductor device according to this disclosure is characterized in that, in the second step of (7) or (8) described above, the thickness of the ion implantation mask is 6 μm or less, and in the third step, the acceleration energy of the ion implantation is 1 MeV or more and 8 MeV or less.

[0036] According to the disclosure described above, a second conductivity type region can be formed at a predetermined depth.

[0037] (10) The semiconductor device according to this disclosure, in any one of (7) to (9) above, the device structure comprises the parallel pn layer, a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type, a trench, and a gate electrode. The first semiconductor region is provided between the first main surface and the parallel pn layer. The second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region. The trench penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer. The gate electrode is provided inside the trench via a gate insulating film. The fourth step is to perform the seventh, eighth, and ninth steps. In the seventh step, the second semiconductor region is selectively formed on the surface region of the second conductivity type diffusion layer, leaving the portion of the second conductivity type diffusion layer excluding the second semiconductor region as the first semiconductor region. In the eighth step, a trench is formed that penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer. In the ninth step, the gate electrode is formed inside the trench via the gate insulating film.

[0038] According to the disclosure described above, the manufacturing process for MOS gate type semiconductor devices with a superjunction structure can be simplified.

[0039] (11) The semiconductor device according to this disclosure is characterized in that, in the above-described (10), in the third step, a second conductivity type region is formed which extends linearly in a second direction parallel to the first main surface and perpendicular to the first direction. In the eighth step, a trench is formed which penetrates the second semiconductor region and the first semiconductor region in the depth direction to reach the second conductivity type region and extends linearly in the second direction. In the seventh step, the second semiconductor region is formed which is scattered in the second direction along the side wall of the trench. Before the ninth step, a first conductivity type impurity is ion-implanted into the side wall of the trench from a direction oblique to the first main surface, thereby forming a third semiconductor region of the first conductivity type inside the second conductivity type region at a position facing the second semiconductor region in the depth direction and deeper on the second main surface side than the first semiconductor region, which penetrates the second conductivity type region in the first direction and is in contact with the first conductivity type region.

[0040] According to the disclosure described above, it is possible to fabricate a MOS gate type semiconductor device with a superjunction structure that reduces on-resistance.

[0041] <Knowledge forming the basis of this disclosure> The silicon carbide semiconductor device in the reference example is a vertical SJ-MOSFET with a trench gate structure on the front side of a semiconductor substrate made of silicon carbide (SiC), and a drift layer consisting of parallel pn layers. The parallel pn layers are formed by alternately arranging n-type column regions and p-type column regions adjacent to each other in a direction parallel to the front surface of the semiconductor substrate. The parallel pn layers are the n of the drift layer. + This is the source region side and is formed by a multi-stage epitaxial method. The multi-stage epitaxial method is a method in which epitaxial layers are grown (stacked) in multiple stages, and each time, a diffusion region of the same conductivity type is selectively formed adjacent to each epitaxial layer in the depth direction Z by ion implantation.

[0042] Specifically, as described in Patent Document 2 above, in order to form a parallel pn layer, multiple stages of n-type epitaxial layers, which will serve as drift layers, are grown epitaxially, and p-type impurities are ion-implanted using an ion implantation mask each time. By ion-implanting p-type impurities, p-type regions that will become p-type column regions are selectively formed in each n-type epitaxial layer. The portions between adjacent p-type column regions of the n-type epitaxial layers that remain n-type without ion implantation become n-type column regions. The ion implantation mask has openings in the portions corresponding to the p-type column region formation regions, and these openings are formed each time ion implantation is performed. The ion implantation mask has a thickness that can shield the ion-implanted p-type impurities and can achieve a predetermined implantation depth accuracy at the openings.

[0043] For example, if aluminum (Al) is used as the p-type dopant (p-type impurity) for ion implantation to form the p-type column region, and the acceleration energy is set to a maximum of approximately 700 keV, the maximum depth to which the ion-implanted Al can reach (depth from the ion implantation surface) is approximately 0.7 μm. Therefore, the second and subsequent n-type epitaxial layers, which are epitaxially grown as drift layers, are each epitaxially grown to a thickness of approximately 0.65 μm or less. If the ion implantation mask for forming the p-type column region is an oxide film (silicon oxide (SiO2) film) with a thickness of approximately 2 μm or a resist film with a thickness of approximately 3 μm, it is possible to form the p-type column region with a thickness sufficient to shield the ion-implanted Al under the above conditions, while maintaining good pattern dimensional accuracy.

[0044] By performing ion implantation of Al using an ion implantation mask under these ion implantation conditions, the implanted Al is shielded by the ion implantation mask and does not reach the n-type epitaxial layer beneath the mask. The shielding of implanted p-type impurities by the ion implantation mask means that the concentration of p-type impurities in the portion of the n-type epitaxial layer covered by the ion implantation mask is less than 5 × 10⁻¹⁶, which is the detection limit by SIMS (Secondary ion mass spectrometry).13 / cm 3 The following applies:

[0045] As described above, in the silicon carbide semiconductor device manufacturing method of the reference example, when forming the parallel pn layer, the following steps are repeated in this order until the parallel pn layer reaches a predetermined thickness: stacking of n-type epitaxial layers, formation of an ion implantation mask with an opening corresponding to the formation region of the p-type column region, ion implantation of p-type impurities, and removal of the ion implantation mask. This increases the number of steps and thus the manufacturing cost. When forming a predetermined element structure such as a trench gate structure on the parallel pn layer, the manufacturing cost is further increased because an additional predetermined number of epitaxial layers are epitaxially grown (stacked) on the parallel pn layer. Therefore, the problem to be solved in this embodiment is to simplify the manufacturing process and reduce costs.

[0046] For example, by increasing the thickness of the n-type epitaxial layer grown in a single stage and ion-implanting p-type impurities with high acceleration energy, the number of repetitions of the above process in the multi-stage epitaxial method can be reduced. However, it is difficult to form an ion implantation mask that is thick enough to prevent the p-type impurities ion-implanted with high acceleration energy from penetrating through, while maintaining pattern dimensional accuracy. On the other hand, the inventors have found that by utilizing the fact that p-type impurities ion-implanted with high acceleration energy penetrate the ion implantation mask, it is possible to form a parallel pn layer with a predetermined charge amount with dimensional accuracy in fewer steps than the silicon carbide semiconductor device manufacturing method of the reference example.

[0047] Preferred embodiments of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0048] (Details of Embodiment 1) The silicon carbide semiconductor device according to Embodiment 1, which solves the above-mentioned problems, is described below. Figures 1 to 3 are perspective views showing the structure of the silicon carbide semiconductor device according to Embodiment 1. Figures 1 and 2 show the structure of the active region 51, and Figure 3 shows the structure of the edge termination region 52. Figure 2 shows the cross section at the cutting line A-A' in Figure 1 moved to the front. The silicon carbide semiconductor device 70 according to Embodiment 1 shown in Figures 1 to 3 is a vertical SJ-MOSFET with an SJ structure, having a trench gate structure (device structure) on the front side of a semiconductor substrate (semiconductor chip) 20 made of silicon carbide (SiC), and having a drift layer 2 as a parallel pn layer 43.

[0049] The semiconductor substrate 20 is made of n + The n-type epitaxial layers 22 and 23, which will become the drift layer 2, are epitaxially grown in this order on the front surface of the starting substrate 21. The semiconductor substrate 20 has the first main surface on the n-type epitaxial layer 23 side as the front surface, and n + The second main surface (n) on the mold starting substrate 21 side + The back side of the mold starting substrate 21 is considered the back side. + The starting substrate 21 is n + This is the drain region 1. The active region 51 is the region where the main current (drift current) flows when the device (MOSFET) is in the ON state, and multiple unit cells (functional units of the device) with the same structure (trench gate structure) are arranged adjacent to each other.

[0050] The edge termination region 52 is the region between the active region 51 and the edge (chip edge) of the semiconductor substrate 20, and surrounds the active region 51. A predetermined breakdown voltage structure 34 is provided in the edge termination region 52. The breakdown voltage structure 34 has the function of maintaining breakdown voltage by mitigating the electric field on the front side of the semiconductor substrate 20 of the drift layer 2 near the outer periphery of the active region 51. Breakdown voltage is the upper limit voltage at which the device does not malfunction or break down at the operating voltage. Figure 3 shows a junction termination extension (JTE) structure as the breakdown voltage structure 34.

[0051] The drift layer 2 is provided between a p-type base region (first semiconductor region) 73 and an n-type drain region 1, which will be described later, in contact with these regions. At least a portion of the drift layer 2 on the p-type base region 73 side (the front surface side of the semiconductor substrate 20) is a parallel pn layer 43. As will be described later, the parallel pn layer 43 is formed by epitaxial growth (formation) of a single-stage n-type epitaxial layer 23 and one-time ion implantation 62 of a p-type impurity (second conductivity type impurity) into the n-type epitaxial layer 23 (see FIGS. 4 and 5 described later). This ion implantation 62 is either a single ion implantation with high acceleration energy or a single multi-stage implantation with at least one stage having high acceleration energy. + The parallel pn layer 43 is formed by alternately and repeatedly arranging an n-type region (n-type column region (first conductivity type region)) 41 and a p-type region (p-type column region (second conductivity type region)) 42 adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 20. The n-type column region 41 and the p-type column region 42 extend linearly in a second direction Y parallel to the front surface of the semiconductor substrate 20 and orthogonal to the first direction X and are arranged in a stripe shape. The parallel pn layer 43 is arranged in substantially the same layout from the active region 51 to the edge termination region 52. The n-type column region 41 reaches the n-type buffer region 2a or the n-type drain region 1 from the lower surface of the p-type base region 73 (the end on the n-type drain region 1 side) in the depth direction Z.

[0052] The parallel pn layer 43 is formed by alternately and repeatedly arranging an n-type region (n-type column region (first conductivity type region)) 41 and a p-type region (p-type column region (second conductivity type region)) 42 adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 20. The n-type column region 41 and the p-type column region 42 extend linearly in a second direction Y parallel to the front surface of the semiconductor substrate 20 and orthogonal to the first direction X and are arranged in a stripe shape. The parallel pn layer 43 is arranged in substantially the same layout from the active region 51 to the edge termination region 52. The n-type column region 41 reaches the n-type buffer region 2a or the n-type drain region 1 from the lower surface of the p-type base region 73 (the end on the n-type drain region 1 side) in the depth direction Z. + type drain region 1 side end) to the n-type buffer region 2a or the n + type drain region 1. The p-type column region 42 reaches the n + type source region 74 and the p ++ type contact region 75 from the lower surface of the n-type buffer region 2a or the n + type drain region 1 in the depth direction Z.

[0053] The outermost part (chip edge side) of the repeating n-type column regions 41 and p-type column regions 42 of the parallel pn layer 43 is the n-type column region 41 (hereinafter referred to as the n-type outer peripheral column region 41a) (see Figure 3). The n-type outer peripheral column region 41a is exposed at the chip edge (side). The n-type outer peripheral column region 41a is provided along the outer periphery of the semiconductor substrate 20 and surrounds the portion inside the n-type outer peripheral column region 41a (towards the center of the semiconductor substrate 20 (chip center)). The n-type outer peripheral column region 41a is in contact with both ends of all other n-type column regions 41 and both ends of all p-type column regions 42.

[0054] The thickness Tsj1 of the parallel pn layer 43 is the distance from the interface with the p-type base region 73 (the p-type impurity penetration layer 3a, described later) to the bottom surface of the p-type column region 42. The depth position of the bottom surface of the p-type column region 42 is the maximum depth reached by the p-type impurities implanted by ion implantation 62 (see Figure 4) to form the p-type column region 42. It is sufficient that the adjacent n-type column region 41 and p-type column region 42 are roughly in charge balance, and the width in the short direction (first direction X) and the impurity concentration profile of the n-type column region 41 and p-type column region 42 can be set as appropriate.

[0055] For example, the n-type column region 41 and the p-type column region 42 may have a linear cross-sectional shape with a substantially uniform width in the shorter direction along the depth direction Z. + The n-type column region 41 has an inverted trapezoidal cross-sectional shape, with the width in the shorter direction narrowing towards the drain region 1 side (the back side of the semiconductor substrate 20), and the n-type column region 41 is made according to the cross-sectional shape of the p-type column region 42. + The cross-sectional shape may be trapezoidal, with the width in the shorter direction increasing towards the drain region 1. The impurity concentration profile of the p-type column region 42 may be a box profile with substantially uniform impurity concentration in the depth direction Z, or it may have a predetermined gradient in the depth direction Z.

[0056] For adjacent n-type column regions 41 and p-type column regions 42 to be approximately charge-balanced means that the charge amount, expressed as the product of the carrier concentration (concentration of activated n-type impurities) and the width in the short direction of the n-type column region 41, and the charge amount, expressed as the product of the carrier concentration (concentration of activated p-type impurities) and the width in the short direction of the p-type column region 42, are approximately balanced. Approximately uniform width, approximately uniform impurity concentration, and approximately balanced charge amount means that, within the range including tolerances due to process variability, they are the same width, the same impurity concentration, and the same charge amount, and that each is at least within ±5%.

[0057] Of the n-type epitaxial layers 22 and 23, the parallel pn layer 43 and n + The portion between the n-type drain region 1 and the n-type buffer region 2a may be an n-type buffer region (an n-type region that is not an SJ structure) 2a. The impurity concentration of the n-type buffer region 2a is less than or equal to the impurity concentration of the n-type column region 41, and preferably lower than the impurity concentration of the n-type column region 41. Lowering the impurity concentration of the n-type buffer region 2a below that of the n-type column region 41 makes it easier to maintain pressure resistance. The n-type epitaxial layer 22 does not need to be provided.

[0058] The trench gate structure is provided in the active region 51 between the front surface of the semiconductor substrate 20 and the parallel pn layer 43. The trench gate structure is provided in the p-type base region 73, n + Type source region (second semiconductor region) 74, p ++ It consists of a p-type contact region 75, a trench 76, a gate insulating film 77, and a gate electrode 78. + Type source region 74 and p ++ The n-type contact region 75 is a diffusion region formed in the n-type epitaxial layer 23 by ion implantation. Of the n-type epitaxial layers 22 and 23, the p-type base region 73 and n + Type source area 74, p ++ Type contact area 75 and p described later + The portion excluding the type region 71 is the drift layer 2.

[0059] Trench 76 is opposed to and parallel to the p-type column region 42 in the depth direction Z within the active region 51. That is, trench 76 extends in a stripe-like manner in the active region 51 in a direction parallel to the longitudinal direction (second direction Y) of the p-type column region 42. The width of trench 76 in the short direction (first direction X) is narrower than the width of the p-type column region 42 in the short direction. Trench 76 is n + Type source area 74, p ++ It penetrates the type contact region 75 and the p-type base region 73, and passes through the n-type current diffusion region (third semiconductor region) 72 and the p-type column region 42, which will be described later. + The type region (second conductivity type high concentration region) reaches 71.

[0060] The gate electrode 78 is located inside the trench 76 via the gate insulating film 77. One unit cell is formed in one trench 76 (i.e., between the mesa centers of adjacent trenches 6), or between the centers of adjacent trenches 76. n is more n than p-type base region 73. + At a deep position on the drain region 1 side, the n-type current diffusion region 72 and the p-type column region 42 are alternately and repeatedly exposed in the second direction Y on the side wall of the trench 76 and are in contact with the gate insulating film 77 on the side wall of the trench 76.

[0061] n + Type source region 74 and p ++ The p-type contact region 75 is selectively provided between the front surface of the semiconductor substrate 20 and the p-type base region 73, in contact with the p-type base region 73. + Type source area 74 and p ++ The contact area 75 is formed by alternately and repeatedly adjacent trenches 76 in the longitudinal direction of the trenches 76 between adjacent trenches 76. + Type source region 74 and p ++ The type contact region 75 is in contact with the gate insulating film 77 on the side wall of the trench 76. ++ The type contact area 75 does not need to be provided. In this case, p ++ Instead of the type contact region 75, the p-type base region 73 extends to the front surface of the semiconductor substrate 20.

[0062] n + Type source region 74 and p ++ The portion excluding the type contact region 75 becomes the p-type base region 73. The p-type base region 73 is the portion along the trench 76 (hereinafter referred to as p - This is the p-type region: (See Figures 16 and 18(b) described later) The p-type impurity concentration may be lower in 42a than in the p-type base region 73. - Type region 42a is n + It is provided between the type source region 74 and the n-type current diffusion region 72, which will be described later, and is in contact with these regions. - A channel is formed in type region 42a when the SJ-MOSFET is turned on.

[0063] Between the p-type base region 73 and the parallel pn layer 43, n is greater than the bottom surface of the trench 6. + Deep within the drain region 1 side, p + A type 71 region and an n-type current diffusion region 72 are selectively provided. + The n-type region 71 and the n-type current diffusion region 72 are diffusion regions formed by ion implantation 82, 84, 85 (see Figures 10, 11) from the inner wall of the trench 6 into the n-type epitaxial layer 23. + The type region 71 has the function of expanding the depletion layer when the MOSFET is off, thereby mitigating the electric field applied to the gate insulating film 77. + The type region 71 is located between the bottom surface of the trench 76 and the p-type column region 42, separated from the p-type base region 73.

[0064] p + The type region 71 extends in the longitudinal direction of the trench 76 for approximately the same length as the trench 76 and runs parallel to the p-type column region 42. + The mold region 71 is in contact with the gate insulating film 77 at the bottom of the trench 76. + The p-type region 71 is adjacent to and surrounded by the p-type column region 42. +The p-type region 71 is fixed to the potential of the source electrode 12 via the p-type column region 42 and the p-type base region 73. + The p-type region 71 may be in contact with the n-type current diffusion region 72 on its upper surface (the surface on the p-type base region 73 side). + The width of the type region 71 in the short direction (first direction X) is narrower than the width of the p-type column region 42 in the short direction.

[0065] The n-type current spreading region 72 is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The n-type current spreading region 72 is n + Directly below type source area 74 (n + The n-type current diffusion region 72 is located inside the p-type column region 42 at a position deeper than the p-type base region 73 on the drain region 1 side, and is provided along the side wall of the trench 76. ++ It is not located directly below the type contact area 75. ++ Directly below the n-type contact region 75, between adjacent n-type current diffusion regions 72 in the second direction Y, there is a p-type column region 42. + The current reaches the n-type source region 74. That is, the n-type current diffusion regions 72 are scattered in the second direction Y.

[0066] Between adjacent trenches 76, the n-type column region 41 extends to the p-type base region 73 between adjacent n-type current diffusion regions 72 in the first direction X. Therefore, the n-type current diffusion region 72 is in contact with the p-type column region 42 on its upper and lower surfaces. The n-type current diffusion region 72 is in contact with the p-type column region 42 on both sides in the second direction Y, in contact with the gate insulating film 7 of the sidewall of the trench 6 on one side in the first direction X, and in contact with the n-type column region 41 on the other side in the first direction X. The n-type current diffusion region 72 is located between the channel and the n-type column region 41 and serves as the current path for the main current of the SJ-MOSFET. The p-type column region 42 may have a relatively lower impurity concentration in the portion between adjacent n-type current diffusion regions 72 in the second direction Y (see Figure 18(a)).

[0067] Because the trench 76 is parallel to the p-type column region 42, the channel width (the width of the channel along the longitudinal direction of the trench 76) is not limited by the width of the n-type column region 41 in the short direction (first direction X). + Increasing the width of the second direction Y of the type source region 74 increases the channel width and thus the channel area, thereby increasing the ratio of the effective region through which the main current flows relative to the surface area of ​​the semiconductor substrate 20. Furthermore, increasing the channel area improves the channel characteristics, allowing for a reduction in the cell pitch.

[0068] The interlayer insulating film 79 is provided over the entire surface of the front surface of the semiconductor substrate 20 and covers the gate electrode 78. The contact electrode (first electrode) 11 is located in the contact hole 79a of the interlayer insulating film 79. + Type source region 74 and p ++ Ohmic contact is made to the type contact region 75. The contact electrode 11 is, for example, a nickel silicide (NixSiy, where x and y are any positive numbers) layer. The source electrode (first electrode) 12 is connected to the contact electrode 11 via p ++ Type contact area 75, n + The p-type source region 74 and the p-type base region 73 are electrically connected. The contact electrode 13 is provided on the entire back surface of the semiconductor substrate 20, n + Type drain region 1(n + It makes ohmic contact with the starting substrate 21). The contact electrode (second electrode) 13 is, for example, a nickel silicide layer. The drain electrode (second electrode) 14 is connected to the contact electrode 13 via n + It is electrically connected to the drain region 1.

[0069] In the edge termination region 52, p-type regions 32 and 33 constituting a JTE structure are provided between the front surface of the semiconductor substrate 20 and the parallel pn layer 43 as a breakdown structure 34. The JTE structure is a structure in which multiple p-type regions 32 and 33 are arranged concentrically adjacent to the active region 51, such that the p-type regions 32 and 33 have lower impurity concentrations as they move from the inside to the outside. The p-type regions 32 and 33 are electrically connected to the p-type base region 3 and are fixed to the potential of the source electrode 12 via the p-type base region 3.

[0070] Outside the breakdown structure 34, an n-type channel stop region 35 is provided between the front surface of the semiconductor substrate 20 and the n-type outer peripheral column region 41a, separated from the breakdown structure 34. The n-type channel stop region 35 is exposed at the chip edge. Between the breakdown structure 34 and the n-type channel stop region 35, a parallel pn layer 43 extends to the front surface of the semiconductor substrate 20. The breakdown structure 34, the n-type channel stop region 35, and the parallel pn layer 43 are in contact with the interlayer insulating film 9 on the front surface of the semiconductor substrate 20.

[0071] Figure 3 shows a pair of adjacent n-type column regions 41 and p-type column regions 42, and an n-type outer peripheral column region 41a adjacent to the outside of the p-type column region 42, between the pressure-resistant structure 34 and the n-type channel stop region 35. However, there are also cases where multiple n-type column regions 41 and p-type column regions 42 of a parallel pn layer 43 are arranged alternately between the pressure-resistant structure 34 and the n-type channel stop region 35.

[0072] The operation of the silicon carbide semiconductor device 70 (SJ-MOSFET) according to Embodiment 1 will be described. When a positive voltage is applied to the drain electrode 14 relative to the source electrode 12, p ++ Type contact region 75, p-type base region 73, p-type column region 42 and p + n-type region 71, n-type current diffusion region 72, n-type column region 41, n-type buffer region 2a and n +The drain region 1 and the pn junction (main junction) are reverse-biased. In this state, if the voltage applied to the gate electrode 78 is less than the gate threshold voltage, the MOSFET remains in the off state.

[0073] When the MOSFET is off, p from the main junction + The depletion layer extending across the p-type region 71 and the p-type column region 42 reduces the electric field applied to the gate insulating film 77. The depletion layer extends outward, ensuring a predetermined breakdown voltage. Furthermore, when the MOSFET is off, the pn junction between the p-type column region 42 and the n-type column region 41 is reverse-biased, causing the depletion layer to extend from this pn junction, and the parallel pn layer 43 bears the breakdown voltage. This ensures a predetermined breakdown voltage that exceeds the breakdown voltage achievable with the impurity concentration of the drift layer 2 (n-type column region 41).

[0074] On the other hand, when a positive voltage is applied to the drain electrode 14 relative to the source electrode 12 and a gate voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 78, a channel (n-type inversion layer) is formed along the side wall of the trench 76 in the p-type base region 73. As a result, n + n-type drain region 1 through n-type buffer region 2a, n-type column region 41, n-type current diffusion region 72 and channel + The main current flows towards the source region 74, and the MOSFET turns on.

[0075] A method for manufacturing the silicon carbide semiconductor device 70 according to Embodiment 1 will now be described. Figures 4 to 14 are perspective views showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. Figures 4 and 5 show the process of forming the parallel pn layer 43, which is common to the active region 51 and the edge termination region 52. Figures 7 to 14 show the active region 51 in the process of manufacturing, and Figure 6 shows the edge termination region 52 in the process of manufacturing.

[0076] First, as shown in Figure 4, n made of SiC +On the front surface of the starting substrate (starting wafer) 21, n-type epitaxial layers (first conductivity type epitaxial layers) 22 and 23, which will become the drift layer 2, are epitaxially grown in this order (first step). Both n-type epitaxial layers 22 and 23 are epitaxially grown in a single stage to a predetermined thickness as the product (silicon carbide semiconductor device 10). As a result, n + A semiconductor substrate (semiconductor wafer) 20 is fabricated (manufactured) by epitaxially growing n-type epitaxial layers 22 and 23 in that order on the front surface of a mold starting substrate 21.

[0077] Next, an ion implantation mask 61 is formed on the front surface of the semiconductor substrate 20 (the surface of the n-type epitaxial layer 23), with an opening corresponding to the area where the p-type column region 42 is formed (second step). The ion implantation mask 61 can be made of, for example, an oxide film (SiO2 film) or a resist film. The thickness t1 of the ion implantation mask 61 is made thin enough so that the p-type impurities implanted 62 to form the p-type column region 42 can penetrate (through) and be introduced into the surface area of ​​the n-type epitaxial layer 23, as will be described later. The thickness t1 of the ion implantation mask 61 is preferably 1.5 μm to 4.8 μm for an oxide film and 1.8 μm to 6.0 μm for a resist film, taking into account that it can be formed with good pattern dimensional accuracy and that penetration can occur.

[0078] Next, p-type impurities are ion-implanted 62 using an ion implantation mask 61 at a high acceleration energy (for example, a maximum energy of about 1 MeV to 8 MeV), forming a p-type column region 42 that reaches a predetermined depth in the n-type epitaxial layer 23 from the front surface (ion implantation surface) of the semiconductor substrate 20 at the opening 61a of the ion implantation mask 61. The predetermined depth reached by the p-type column region 42 formed by this ion implantation 62 is from the front surface of the semiconductor substrate 20 to the n-type epitaxial layer 23. + The depth is the sum of the thicknesses of the p-type source region 74, the p-type base region 73, and the parallel pn layer 43.

[0079] Furthermore, at this time, the p-type impurities implanted 62 are intentionally made to penetrate the ion implantation mask 61, forming a p-type impurity penetration layer (second conductive diffusion layer) 3a that becomes a p-type base region 73 over the entire surface region of the n-type epitaxial layer 23. That is, ion implantation 62 is performed with a high acceleration energy such that a p-type column region 42 reaching a predetermined depth of the n-type epitaxial layer 23 is formed at the opening 61a of the ion implantation mask 61, and the p-type impurity penetration layer 3a is formed in the portion covered by the ion implantation mask 61 with the surface region of the n-type epitaxial layer 23 as the range. The gradient of impurity concentration in the depth direction Z is the same for the p-type impurity penetration layer 3a and the lower end portion of the p-type column region 42. Since this is a single ion implantation 62 using one ion implantation mask 61, the impurity concentration in the portion of the p-type column region 42 at the same depth as the p-type impurity penetration layer 3a may differ from that of the p-type impurity penetration layer 3a.

[0080] The thickness t2 of the p-type impurity penetration layer 3a (depth from the ion implantation surface) is, for example, about 0.8 μm or more. When the thickness t2 of the p-type impurity penetration layer 3a falls below the above lower limit, n + This is because, after the formation of the p-type source region 74, the p-type base region 3 becomes thinner, resulting in a short-channel structure and an increase in leakage current, etc. Furthermore, the thickness t2 of the p-type impurity penetration layer 3a is preferably about 1.5 μm or less, for example, as it is easier to remove the p-type impurity penetration layer 3a by etching in the edge termination region 52.

[0081] More specifically, when a resist film is used as the ion implantation mask 61, the thickness t1 of the ion implantation mask 61 is set to about 3.2 μm, and aluminum (Al), which is a p-type dopant (p-type impurity), is ion-implanted 62 with a high acceleration energy of, for example, about 5 MeV. Simulations have confirmed that the ion-implanted Al penetrates the ion implantation mask 61 and reaches a depth of 0.8 μm in the n-type epitaxial layer 23 from the front surface (ion implantation surface) of the semiconductor substrate 20 (see Figure 17). At the opening 61a of the ion implantation mask 61, the Al ion-implanted with a high acceleration energy of about 5 MeV reaches a depth of about 2.4 μm in the n-type epitaxial layer 23. As a result, a p-type column region 42 with a depth t3 that is deeper than the thickness t2 of the p-type impurity penetration layer 3a and within the range of about 0.8 μm to 3.2 μm can be formed with a single high-acceleration energy ion implantation 62.

[0082] At least one stage of ion implantation 62 may be a multi-stage implantation with a high acceleration energy, and the impurity concentration profile of the p-type column region 42 may be a box profile. Multi-stage implantation means implanting a predetermined dose of impurity in multiple stages with different acceleration energies. For example, ion implantation 62 may be a multi-stage implantation with an acceleration energy in the range of approximately 60 keV to 8 MeV, and at least one stage of this multi-stage implantation may be performed with a high acceleration energy of 1 MeV or more to the extent that the p-type column region 42 reaches a predetermined depth.

[0083] The portion of the n-type epitaxial layer 23 between adjacent p-type column regions 42, directly below the p-type impurity penetration layer 3a, that remains n-type without ion implantation 62, becomes the n-type column region 41. As a result, a parallel pn layer 43 consisting of n-type column regions 41 and p-type column regions 42 is formed in the n-type epitaxial layer 23 (third step). The n-type epitaxial layer 23 is n-type, which is more n-type than the parallel pn layer 43. + The portion of the starting substrate 21 that remains n-type without ion implantation 62, along with the n-type epitaxial layer 22, forms the n-type buffer region 2a. This state is shown in Figure 5.

[0084] Next, as shown in Figure 6, after removing the ion implantation mask 61, an etching mask (not shown) with an opening corresponding to the edge termination region 52 is formed on the front surface of the semiconductor substrate 20. Next, the semiconductor substrate 20 is etched using the etching mask to remove the p-type impurity penetration layer 3a in the edge termination region 52, thereby exposing the parallel pn layer 43 over the entire front surface of the semiconductor substrate 20 in the edge termination region 52. Then, the etching mask is removed.

[0085] Next, as shown in Figure 7, n + An ion implantation mask 63 is formed with an opening corresponding to the p-type source region 74. The opening 63a of the ion implantation mask 63 extends in a stripe shape perpendicular to the longitudinal direction of the p-type column region 42. Next, n-type impurities are ion implanted 64 using the ion implantation mask 63 to implant n-type impurities into the surface region of the p-type impurity penetration layer 3a. + A type source region 74 is selectively formed. Although not shown in the diagram, the ion implantation mask 63 also has an opening in the area corresponding to the formation region of the n-type channel stop region 35, and this ion implantation 64 forms the n-type channel stop region 35 on the surface region of the n-type outer periphery column region 41a. Then the ion implantation mask 63 is removed.

[0086] Next, as shown in Figure 8, p ++ An ion implantation mask 65 is formed with an opening in the portion corresponding to the formation region of the p-type contact region 75. The opening 65a of the ion implantation mask 65 extends in a stripe shape in a direction perpendicular to the longitudinal direction of the p-type column region 42. Next, p-type impurities are ion implanted 66 using the ion implantation mask 65 to the surface region of the p-type impurity penetration layer 3a. ++ A type contact region 75 is selectively formed. Then, the ion implantation mask 65 is removed. The n of the p-type impurity penetration layer 3a + Type source region 74 and p ++ The portion excluding the type contact area 75 becomes the p-type base area 73 (fourth step (seventh step)).

[0087] The introduction of implantation defects into the n-type epitaxial layer 23 by ion implantation 64,66 also occurs from the underside of the p-type impurity penetration layer 3a, which can reduce the lifetime of the n-type epitaxial layer 23. Furthermore, since the p-type column region 42 and the trench 76 are parallel and the channel region is not sacrificed, low resistance can be achieved.

[0088] Next, although not shown in the diagram, the formation of an ion implantation mask, ion implantation of p-type impurities under predetermined conditions, and removal of the ion implantation mask are repeatedly performed in this order to selectively form p-type regions 32 and 33 (see Figure 3) that constitute the breakdown structure 34 on the surface region of the front surface of the semiconductor substrate 20 in the edge termination region 52 (the surface region of the parallel pn layer 43 in the edge termination region 52). The breakdown structure 34 and the n-type channel stop region 35 can be formed at any time after the removal of the p-type impurity penetration layer 3a in the edge termination region 52 and before the parallel pn layer 43 exposed on the front surface of the semiconductor substrate 20 in the edge termination region 52 is covered with an insulating film (such as the gate insulating film 7 or the interlayer insulating film 9).

[0089] Next, as shown in Figure 9, an etching mask 81 is formed on the front surface of the semiconductor substrate 20, with an opening corresponding to the trench 76 formation region. The opening 81a of the etching mask 81 is parallel to the p-type column region 42. The opening 81a of the etching mask 81 has n in the longitudinal direction of the opening 81a. + Type source area 74 and p ++ The contact area 75 is repeatedly and alternately exposed.

[0090] Next, the semiconductor substrate 20 is etched using the etching mask 81, and n is etched in the depth direction Z. + Type source area 74, p ++ The type contact region 75 penetrates to reach the p-type column region 42, and within the p-type column region 42, n is greater than the p-type base region 73. +Form a trench 76 that terminates at a deep position on one side of the p-type drain region 1 (fourth step (eighth step)). n + On the side of the p-type source region 74 and deeper than n + On the entire inner wall surface of the trench 76 at a position deeper on the side of the p-type drain region 1, the p-type column region 42 is exposed.

[0091] Next, as shown in FIG. 10, using the etching mask 81 used for forming the trench 76 as it is, p-type impurities such as Al are ion-implanted 82 from a direction orthogonal to the front surface of the semiconductor substrate 20, and p + type region 71 is formed in the surface region of the p-type column region 42 exposed on the bottom surface of the trench 76. Then, the etching mask 81 is removed.

[0092] Next, as shown in FIG. 11, an ion implantation mask 83 having an opening corresponding to the formation region of the n-type current diffusion region 72 is formed on the front surface of the semiconductor substrate 20. In the opening 83a of the ion implantation mask 83, n + type source region 74 and the inner wall of the trench 76 between the n + type source regions 74 adjacent to each other in the first direction X are exposed.

[0093] Next, using the ion implantation mask 83, n-type impurities (first conductivity type impurities) are ion-implanted (hereinafter referred to as oblique ion implantation) 84, 85 into both side walls of the trench 76 from an oblique direction with respect to the front surface of the semiconductor substrate 20. By this oblique ion implantation 84, 85, the portion of the p-type column region 42 along the side wall of the trench 76 is turned back to n-type to form the n-type current diffusion region 72.

[0094] The n-type current diffusion region 72 is formed to a depth reaching the n-type column region 41 from the side wall of the trench 76 in a direction orthogonal to the side wall of the trench 76. The p-type column region 42 is preferably formed such that the p-type impurity concentration is relatively lower than other portions of the p-type column region 42 at the depth portion turned back to n-type by the oblique ion implantation 84, 85 (see FIG. 18(a)).

[0095] Also, due to this oblique ion implantation 84, 85, the p-type impurity concentration of the portion along the sidewall of the trench 76 in the p-type column region 42 may be lowered. In this case, between the n + type source region 74 and the n-type current diffusion region 72, a p - type region 42a (see FIGS. 16 and 18(b) described later) is formed in contact with these regions. Then, the ion implantation mask 83 is removed.

[0096] Next, as shown in FIG. 12, a gate insulating film 77 is formed along the front surface of the semiconductor substrate 20 and the inner wall of the trench 76. Next, a gate electrode 78 made of, for example, polysilicon (poly-Si) is embedded on the gate insulating film 77 inside the trench 76 (the fourth step (the ninth step)).

[0097] Next, as shown in FIG. 13, an interlayer insulating film 79 is formed on the entire front surface of the semiconductor substrate 20. Next, as described using FIG. 14, the interlayer insulating film 79 is etched and selectively removed to form a contact hole 79a, and the n + type source region 74 and the p ++ type contact region 75 are exposed.

[0098] Next, a contact electrode 11 that makes an ohmic contact with the front surface of the semiconductor substrate 20 is formed in the contact hole 79a of the interlayer insulating film 79 (the fifth step). A contact electrode 13 that makes an ohmic contact with the back surface of the semiconductor substrate 20 is formed (the sixth step). This is shown in FIG. 14. Then, source electrodes 12 and drain electrodes 14 are formed on both main surfaces of the semiconductor substrate 20, respectively (the fifth and sixth steps). Thereafter, the semiconductor wafer (semiconductor substrate 20) is diced (cut) into individual chip-like pieces, and thus the silicon carbide semiconductor device 70 shown in FIGS. 1 to 3 is completed.

[0099] As described above, according to Embodiment 1, when forming a parallel pn layer as a drift layer, a p-type column region of a predetermined depth is formed by a single ion implantation at a high acceleration energy (or a single multi-stage implantation with at least one stage using a high acceleration energy). At this time, penetration of the ion implanted p-type impurities through the ion implantation mask is intentionally caused to form a p-type impurity penetration layer that becomes the p-type base region. In other words, since a multi-stage epitaxial method is not used to form the parallel pn layer, the manufacturing process is simplified, the lead time is shortened, and costs can be reduced.

[0100] Furthermore, according to Embodiment 1, since the p-type region implanted to form the p-type column region may penetrate the ion implantation mask, the thickness of the ion implantation mask can be reduced. This reduces the cost of the ion implantation mask formation process. Also, according to Embodiment 1, because the ion implantation mask used for ion implantation to form the p-type column region is thin, the ion implantation mask can be formed with high pattern dimensional accuracy, improving the dimensional accuracy of the p-type column region. This reduces manufacturing variability.

[0101] Furthermore, according to Embodiment 1, since the longitudinal direction of the trench 76 is parallel to the longitudinal direction of the p-type column region 42, the channel width is not limited by the width in the short direction of the n-type column region, and the channel area can be increased. As a result, the channel characteristics are improved, and the cell pitch can be reduced.

[0102] (Details of Embodiment 2) The silicon carbide semiconductor device according to Embodiment 2, which solves the above-mentioned problems, is described below. Figure 15 is a perspective view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 15 shows the structure of the active region 51. The structure of the edge termination region 52 is the same as in Embodiment 1 (see Figure 3). The difference between the silicon carbide semiconductor device 10 according to Embodiment 2 and the silicon carbide semiconductor device 70 according to Embodiment 1 (see Figures 1 and 2) is that the longitudinal direction of the trench 6 (first direction X) is perpendicular to the longitudinal direction of the p-type column region 42 (second direction Y). The configuration of the parallel pn layer 43 is the same as in Embodiment 1.

[0103] In Embodiment 2, the trench 6 has a depth of n in the depth direction Z. + It penetrates the p-type source region 4 and the p-type base region 3, and passes through the parallel pn layer 43, as described later. + It reaches the type region 31. The trench 6 extends in a stripe-like manner in the first direction X in the active region 51. It is n greater than the p-type base region 3. + At a deep position on the drain region 1 side, the n-type column region 41 and the p-type column region 42 are alternately and repeatedly exposed in the first direction X on the side wall of the trench 6. The n-type column region 41 and the p-type column region 42 are in contact with the gate insulating film 7 on the side wall of the trench 6. The configuration of the trench gate structure other than the trench 6 is substantially the same as the corresponding parts of the trench gate structure of Embodiment 1.

[0104] Specifically, a gate electrode 8 is provided inside the trench 6 via a gate insulating film 7. One unit cell is formed in one trench 6. A unit cell may also be formed between the centers of adjacent trenches 6. The p-type base region 3 is provided in the entire area between the front surface of the semiconductor substrate 20 and the parallel pn layer 43 in the active region 51, in contact with the n-type column region 41 and the p-type column region 42. The p-type base region 3 is in contact with the gate insulating film 7 on the side wall of the trench 6. The p-type base region 3 is formed simultaneously with the p-type column region 42, similar to the p-type base region 73 in Embodiment 1 (see Figures 4 and 5).

[0105] n + Type source region 4 and p++ The type contact regions 5 are selectively provided between the front surface of the semiconductor substrate 20 and the p-type base region 3, in contact with the p-type base region 3. + Type source region 4 and p ++ The contact region 5 extends in the longitudinal direction of the trench 6 for approximately the same length as the trench 6 and is adjacent to the second direction Y. + The mold source region 4 is in contact with the gate insulating film 7 on the side wall of the trench 6. ++ The contact area 5 is positioned away from the trench 6. ++ The type contact area 5 does not need to be provided. In this case, p ++ Instead of the type contact region 5, the p-type base region 3 extends to the front surface of the semiconductor substrate 20.

[0106] Between the p-type base region 3 and the parallel pn layer 43, n is greater than the bottom surface of the trench 6. + Deep within the drain region 1 side, p + A type region 31 is selectively provided. + The type region 31 has the function of expanding the depletion layer when the MOSFET is off, protecting the gate insulating film 7 at the bottom of the trench 6, and mitigating the electric field applied to the gate insulating film 7. + The type region 31 is the p of Embodiment 1. + Similar to type region 71 (see Figure 10), this is a diffusion region formed by ion implantation from the bottom of the trench 6 into the n-type epitaxial layer 23. + The mold region 31 extends in the longitudinal direction (first direction X) of the trench 6 for approximately the same length as the trench 6. + The longitudinal direction of the type region 31 is perpendicular to the longitudinal direction of the p-type column region 42.

[0107] p + The mold region 31 is provided separately from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction Z. + The mold region 31 is in contact with the gate insulating film 7 at the bottom of the trench 6. + The width of the mold region 31 in the shorter direction is, for example, greater than or equal to the width of the trench 6 in the shorter direction. +The type region 31 is adjacent to the parallel pn layer 43 (n-type column region 41 and p-type column region 42) and is surrounded by the parallel pn layer 43. + The p-type region 31 is fixed to the potential of the source electrode 12 via the p-type column region 42 and the p-type base region 3. + The lower surface of the type region 31 is located at a shallower depth on the p-type base region 3 side than the lower surface of the parallel pn layer 43. No n-type current diffusion region is provided.

[0108] The interlayer insulating film 9 is provided over the entire surface of the front surface of the semiconductor substrate 20 and covers the gate electrode 8. The contact electrode 11 is located in the contact hole 9a of the interlayer insulating film 9. + Type source region 4 and p ++ Ohmic contact is made with the contact region 5. The material of the contact electrode 11 is the same as in Embodiment 1. The source electrode 12 is connected to the contact electrode 11 via p ++ Type contact area 5, n + The p-type source region 4 and the p-type base region 3 are electrically connected. The configuration of the contact electrodes 13 and drain electrodes 14 on the back surface of the semiconductor substrate 20 is the same as in Embodiment 1.

[0109] The method for manufacturing the silicon carbide semiconductor device 10 according to Embodiment 2 is the same as the method for manufacturing the silicon carbide semiconductor device 70 according to Embodiment 1, but with a modified pattern of the etching mask for forming the trench 6, and p + Ion implantation of p-type impurities is performed to form the type region 31, while ion implantation to form the n-type current diffusion region can be omitted.

[0110] Specifically, first, similar to Embodiment 1, the formation of the parallel pn layer 43 begins, n + Type source region 4 and p ++ The steps to form the type contact region 5 are carried out sequentially (see Figures 4-8). + Type source region 4 and p ++ The method for forming the type contact region 5 is as follows: n + Type source region 74 and p ++This is similar to the type contact region 75. Similar to Embodiment 1, the p-type impurity penetration layer 3a (see Figure 5) is not removed, n + Type source region 4 and p ++ The portion excluding the type contact region 5 becomes the p-type base region 3 (i.e., the parts with reference numerals 73 to 75 in Figures 7 and 8 replaced with reference numerals 3 to 5, respectively).

[0111] In Embodiment 2, the introduction of implantation defects into the n-type epitaxial layer 23 by ion implantation also occurs from the lower surface of the p-type impurity penetration layer 3a, thereby reducing the lifetime of the n-type epitaxial layer 23. Furthermore, below the p-type impurity penetration layer 3a (n + Since the drain region 1 side becomes a parallel pn layer 43 consisting of an n-type column region 41 and a p-type column region 42, it can be formed with good dimensional accuracy.

[0112] Next, an etching mask is formed on the front surface of the semiconductor substrate 20, with openings corresponding to the trench formation region of the trench 6. The openings of the etching mask extend in a stripe pattern perpendicular to the longitudinal direction of the p-type column region 42. + Only the type source region 4 is exposed. Next, the semiconductor substrate 20 is etched using this etching mask, and n in the depth direction Z. + A trench 6 is formed that penetrates the p-type source region 4 and the p-type base region 3 and terminates inside the parallel pn layer 43. On the inner wall of the trench 6, n-type column regions 41 and p-type column regions 42 are alternately and repeatedly exposed in the longitudinal direction of the trench 6. On the side wall of the trench 6, the n-type column region 41 is adjacent to the lower surface of the p-type base region 3, and the p-type column region 42 is adjacent to the n + It is adjacent to the lower surface of type source region 4.

[0113] Next, using the same etching mask used to form the trench 6, p-type impurities such as Al are ion-implanted from a direction perpendicular to the front surface of the semiconductor substrate 20, and p-type impurities are implanted into the surface region of the parallel pn layer 43 exposed at the bottom of the trench 6. +A mold region 31 is formed. Then, the etching mask is removed. Next, a gate insulating film 7 is formed along the front surface of the semiconductor substrate 20 and the inner wall of the trench 6. Next, a gate electrode 8 is embedded on the gate insulating film 7 inside the trench 6. Next, an interlayer insulating film 9 is formed over the entire front surface of the semiconductor substrate 20. Next, a contact hole 9a is formed by etching and selectively removing the interlayer insulating film 9, and n + Type source region 4 and p ++ Expose the contact area 5.

[0114] Next, contact electrodes 11 are formed in the contact holes 9a of the interlayer insulating film 9 to make ohmic contact with the surface of the semiconductor substrate 20. Then, in the same manner as in Embodiment 1, the processes from the formation of the contact electrodes 13 onward are carried out in order to complete the silicon carbide semiconductor device 10 shown in Figure 15.

[0115] As described above, according to Embodiment 2, the same effects as in Embodiment 1 can be obtained even when the longitudinal direction of the trench is perpendicular to the longitudinal direction of the p-type column region.

[0116] Furthermore, according to Embodiment 2, the longitudinal direction of the trench is perpendicular to the longitudinal direction of the p-type column region. Therefore, the electric field applied to the gate insulating film is relaxed by the p-type column region. In addition, the carrier spreading resistance in the second direction is reduced by the n-type column region, thus reducing the JFET (Junction FET) resistance. For this reason, for example, in the above-mentioned Patent Document 2, a p-type column region for electric field relaxation is placed between adjacent trenches near the bottom surface of the trench. + Although a type region and an n-type current diffusion region are provided, according to Embodiment 2, these regions do not need to be provided. This further simplifies the manufacturing process.

[0117] (Details of Embodiment 3) The silicon carbide semiconductor device according to Embodiment 3, which solves the above-mentioned problems, is described below. Figure 16 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The silicon carbide semiconductor device 90 according to Embodiment 3 is characterized in that a second parallel pn layer 93 is formed by a multi-stage epitaxial method before the formation process of the parallel pn layer (hereinafter referred to as the first parallel pn layer) 43 of the silicon carbide semiconductor device 70 according to Embodiment 1 (see Figures 1 and 2), thereby making the portion 2b of the drift layer 2 that is in contact with the lower surface of the first parallel pn layer 43 a second parallel pn layer 93 formed by a multi-stage epitaxial method.

[0118] Specifically, in Embodiment 3, the first parallel pn layer 43 reaches the interface of the n-type epitaxial layers 22 and 23 in the depth direction Z. The second parallel pn layer 93 is formed on the n-type epitaxial layer 22 by a multi-stage epitaxial method, similar to the parallel pn layer in the reference example described above. The second parallel pn layer 93 is in contact with the first parallel pn layer 43 on its upper surface. The sum of the thickness Tsj1 of the first parallel pn layer 43 and the thickness Tsj2 of the second parallel pn layer 93 is the total thickness of the parallel pn layer of the drift layer 2. Of the n-type epitaxial layer 22, the second parallel pn layer 93 and n + The portion between the drain region 1 and the n-type buffer region 2a may also be an n-type buffer region 2a.

[0119] The second parallel pn layer 93 is formed by repeatedly arranging n-type column regions 91 and p-type column regions 92 alternately adjacent to each other in the first direction X. When viewed from the front side of the semiconductor substrate 20, the n-type column regions 91 and p-type column regions 92 are arranged in substantially the same layout as the n-type column regions 41 and p-type column regions 42 of the first parallel pn layer 43. The n-type column regions 91 and p-type column regions 92 are in contact with the n-type column regions 41 and p-type column regions 42 on their upper surfaces, and are in contact with the n-type buffer regions 2a or n-type buffer regions on their lower surfaces. + It is adjacent to the type drain region 1.

[0120] The manufacturing method for the silicon carbide semiconductor device 90 according to Embodiment 3 is obtained by adding a step of forming a second parallel pn layer 93 by a multi-stage epitaxial method to the manufacturing method for the silicon carbide semiconductor device 70 according to Embodiment 1 (Figures 4-14). That is, n + On the front surface of the mold starting substrate 21, the first-stage n-type epitaxial layer, which will become the n-type buffer region 2a of the n-type epitaxial layer 22, is epitaxially grown. Then, before epitaxially growing the n-type epitaxial layer 23, the second parallel pn layer 93 is formed.

[0121] The second parallel pn layer 93 is formed by dividing the n-type epitaxial layer 22 into multiple stages (in this case, three stages in addition to one stage that becomes the n-type buffer region 2a) using a multi-stage epitaxial method, and selectively forming p-type regions that become the p-type column region 92 by ion implantation of p-type impurities each time the n-type epitaxial layer 22 is epitaxially grown in multiple stages. After that, the n-type epitaxial layer 23 is epitaxially grown on the second parallel pn layer 93, and the steps from the formation of the first parallel pn layer 43 onwards are carried out in the same manner as in Embodiment 1.

[0122] The silicon carbide semiconductor device 90 according to Embodiment 3 may be modified by applying Embodiment 2 (see Figure 15) to make the longitudinal direction of the trench 76 perpendicular to the longitudinal direction of the p-type column regions 42 and 92.

[0123] As explained above, according to Embodiment 3, the same effects as in Embodiments 1 and 2 can be obtained by the first parallel pn layer. Furthermore, according to Embodiment 3, if the length in the depth direction of the p-type column region of the first parallel pn layer is insufficient to meet the design value, the first parallel pn layer and n + The p-type column region of the second parallel pn layer, formed between the drain region and the p-type column region using a multi-stage epitaxial method, can increase the total length of the p-type column region in the depth direction (i.e., the total thickness of the parallel pn layer).

[0124] (Example 1) The diffusion depth of p-type impurities (i.e., p-type impurities that penetrated the resist film) ion-implanted into a SiC epitaxial layer through a resist film was investigated. Figure 17 is a schematic diagram illustrating the simulation results of the distribution of p-type impurities ion-implanted into a silicon carbide epitaxial layer through a resist film. When p-type impurities are ion-implanted into a SiC epitaxial layer (SiC substrate) 201 through a resist film (resist mask) 202, Figure 17 shows the simulation results of the spread of p-type impurities ion-implanted from a predetermined point (1 point) 203 on the surface (ion-implantation surface) of the resist film 202.

[0125] The horizontal axis of Figure 17 represents the depth [μm] of the p-type impurity 204 (hatched portion) extending in the depth direction from the ion implantation surface (surface of the resist film 202). The vertical axis of Figure 17 represents the length [μm] of the lateral extension of the p-type impurity 204 from a predetermined point 203 (=0 [μm]) on the ion implantation surface in a direction parallel to the ion implantation surface (lateral direction). As ion implantation conditions, aluminum (Al) was used as the dopant and the acceleration energy was set to 5 MeV. The thickness d1 of the resist film 202 was set to 3.2 μm. The ion implantation, resist film 202, and SiC epitaxial layer 201 correspond to the ion implantation 62, ion implantation mask 61, and n-type epitaxial layer 23 in Embodiments 1 to 3, respectively (see Figures 4 and 5).

[0126] As shown in Figure 17, it was confirmed that Al ion-implanted with a high acceleration energy of approximately 5 MeV penetrated the resist film 202 and reached a depth d2 of 0.8 μm from the surface of the SiC epitaxial layer 201. Although not shown in the figure, the inventors have confirmed that in order to completely prevent Al ion-implanted with a high acceleration energy of approximately 5 MeV from penetrating the resist film 202 (i.e., to shield the ion-implanted Al from the resist film 202), the thickness d1 of the resist film 202 needs to be approximately 6 μm.

[0127] Therefore, it was confirmed that the thickness d1 of the resist film 202 can be reduced to approximately half by allowing p-type impurities to penetrate the resist film 202. In embodiments 1 to 3, it was confirmed that by appropriately setting the acceleration energy of the ion implantation 62 of p-type impurities for forming the p-type column region 42 and the thickness t1 of the ion implantation mask 61 used for the ion implantation 62 (corresponding to the thickness d1 of the resist film 202), it is possible to form a p-type impurity penetration layer 3a with a predetermined thickness t2, which becomes the p-type base region 3, simultaneously with the p-type column region 42.

[0128] (Example 2) For an SJ-MOSFET (hereinafter referred to as Example 1) manufactured by the silicon carbide semiconductor device 70 manufacturing method according to Embodiment 1 described above (see Figure 11), the impurity concentration profile in the depth direction of the p-type column region 42 was verified. Figure 18 is a characteristic diagram showing the simulation results of the impurity concentration profile in the depth direction of the epitaxial layer of Example 1. Figure 18(a) shows the n-type impurity concentration profile 211 and the p-type impurity concentration profile 212 at the cutting line B-B' in Figure 18(b).

[0129] In Figure 18(a), the horizontal axis represents the depth from the front surface (=0.0 μm) of the semiconductor substrate 20, and the vertical axis represents the impurity concentration. Figure 18(b) shows the cross-sectional structure of Example 1 (corresponding to the front view in the perspective view shown in Figure 1). The cutting line B-B' in Figure 18(b) is along the side wall of the trench 76 in the depth direction Z from the front surface of the semiconductor substrate 20 to n + Type source area 74, p - This position passes through the p-type base region 73a (the portion of the p-type base region 73 where the p-type impurity concentration is low along the side wall of the trench 76), the n-type current diffusion region 72, and the p-type column region 42.

[0130] Figure 18(a) shows the simulation results of the impurity concentration profiles 211 and 212 at the cutting line B-B' for Example 1. Also in Figure 18(a), the n-type impurity concentration profile 213 for oblique ion implantation 84 and 85 of n-type impurities to form the n-type current diffusion region 72 is shown as a dashed line. In Figure 18(a), the n-type impurity concentration profile 213 and the portion of the n-type impurity concentration profile 211 due to oblique ion implantation 84 and 85 are shown so as not to overlap, but these are the same impurity concentration profile.

[0131] The n-type impurity concentration profile 211 is calculated from the front surface of the semiconductor substrate 20 in the depth direction Z, n + The n-type impurity concentration profile obtained by ion implantation 64 (see Figure 7) to form the n-type source region 74, the n-type impurity concentration profile obtained by oblique ion implantation 84,85 (see Figure 11) of n-type impurities to form the n-type current diffusion region 72, and the n-type impurity concentration profile of the n-type epitaxial layer 23 are continuous. The n-type impurity concentration profile 211 uses nitrogen (N) as a dopant.

[0132] The p-type impurity concentration profile 212 is formed by ion implantation 62 (see Figures 3 and 4) to form the p-type column region 42. In the depth direction Z, the p-type impurity concentration profile of the p-type impurity penetration layer 3a and the p-type impurity concentration profile of the p-type column region 42 are continuous from the front surface of the semiconductor substrate 20. Aluminum (Al) was used as the dopant for the p-type impurity concentration profile 212. The diffusion of p-type impurities in SiC is very small, and the p-type impurity concentration profile 212 is maintained as it was during ion implantation 62.

[0133] The p-type impurity concentration profile of the p-type column region 42 was determined by a box profile achieved by multi-stage ion implantation 62 for forming the p-type column region 42 using acceleration energies in the range of 60 keV to 8 MeV. By lowering the dose of ion implantation at a specific acceleration energy within the range of the n-type current diffusion region 72 formation region, the p-type impurity concentration of the p-type column region 42 in the region corresponding to the formation region of the n-type current diffusion region 72 can be relatively lowered.

[0134] As shown in Figure 18(a), it was confirmed that by relatively lowering the p-type impurity concentration in the p-type column region 42 at the depth corresponding to the n-type current diffusion region 72 formation region, it becomes easier to convert the p-type column region 42 back to n-type even with a lower dose of oblique ion implantation 84,85. Furthermore, by lowering the dose of oblique ion implantation 84,85, the amount of n-type impurities obliquely implanted into the p-type base region 73 is reduced, thereby suppressing the adverse effect of oblique ion implantation 84,85 on channel mobility.

[0135] Furthermore, as shown in Figure 18(a), in the edge termination region 52 (see Figure 3), the n of the p-type column region 42 + The portion 42b adjacent to the n-type current diffusion region 72 in the second direction Y, which is the surface layer on the source region 74 side, is n- + The Al concentration is lower on the drain region 1 side compared to the deeper portion 42c. This allows for precise control of the impurity concentration of the pressure-resistant structure 34 (p-type regions 32, 33: see Figure 3) when forming the pressure-resistant structure 34 on the surface of the p-type column region 42.

[0136] In summary, this disclosure is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of this disclosure. For example, this disclosure is not limited to MOSFETs, but can be applied to silicon carbide semiconductor devices with a structure that includes a p-type region that can be formed between the front surface of the semiconductor substrate and a parallel pn layer using a p-type impurity penetration layer, such as the p-type base region of an IGBT or the p-type anode region of a diode. In addition, as a breakdown voltage structure, a field limiting ring (FLR), which is a floating p-type region, may be provided instead of the JTE structure. [Industrial applicability]

[0137] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to this disclosure are useful for power semiconductor devices used in power converters, power supply devices for various industrial machines, and the like. [Explanation of Symbols]

[0138] 1 n + Type drain region 2,2b Drift layer 2a n-type buffer area 3.73 p-type base region 3a p-type impurity penetration layer 4.74 n + Type source area 5.75 p ++ Type Contact Area 6.76 Trench 7.77 Gate Insulator 8.78 gate gate 9.79 Interlayer insulating film 9a,79a Contact Holes 10,70,90 Silicon Carbide Semiconductor Devices 11,13 Contact electrodes 12 Source electrodes 14 Drain electrode 20 Semiconductor substrates 21 n + Mold starting substrate 22,23 n-type epitaxial layer 31,71 p + type area 32 pages - type area 33 p -- type area 34 Pressure-resistant structure 35 n-type channel stop region 41,91 n-type column region 41a n-type outer periphery column region 42,92 p-type column regions 42a p - type area 43,93 parallel pn layer 51 Active area 52 Edge Termination Region 61, 63, 65, 83 Ion implantation mask 61a, 63a, 65a, 83a Opening of ion implantation mask 62, 64, 66, 68, 69, 82 Ion implantation 67,81 Etching mask 67a, 81a Openings in etching masks 72 n-type current diffusion region 84,85 Oblique ion implantation 211,213 n-type impurity concentration profiles 212 p-type impurity concentration profiles t1 Thickness of ion implantation mask t2 thickness of the p-type impurity penetration layer Depth of the t3 p-type column region Thickness of parallel pn layers Tsj1, Tsj2 X First direction parallel to the front surface of the semiconductor substrate Y is a second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide, in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of a second conductivity type is provided between the first main surface and the parallel pn layer, A second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region, A trench that penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the first semiconductor region and the second semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, Equipped with, The first conductivity type region and the second conductivity type region extend linearly in a second direction parallel to the first main surface and perpendicular to the first direction. The trench extends linearly in the depth direction in at least part of the way, facing the second conductive type region and parallel to the first main surface, The first semiconductor region extends along the side wall of the trench, A silicon carbide semiconductor device characterized in that the second conductive type region penetrates the first semiconductor region.

2. The silicon carbide semiconductor device according to claim 1, characterized in that the impurity concentration in the portion of the second conductivity type region that penetrates the first semiconductor region is lower than the impurity concentration in the first semiconductor region.

3. The silicon carbide semiconductor device according to claim 1, characterized in that the depth of the second conductivity type region is 0.8 μm to 3.2 μm.

4. A parallel pn layer is provided inside a semiconductor substrate made of silicon carbide, in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of the semiconductor substrate. A first semiconductor region of a second conductivity type is provided between the first main surface and the parallel pn layer, A second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region, A trench that penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the first semiconductor region and the second semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, Equipped with, The first conductivity type region and the second conductivity type region extend linearly in a second direction parallel to the first main surface and perpendicular to the first direction. The trench faces the second conductive region in the depth direction and extends linearly in the second direction, The second semiconductor region is scattered along the side wall of the trench in the second direction, A silicon carbide semiconductor device characterized by comprising a third semiconductor region of a first conductivity type, provided inside the second conductivity type region at a position facing the second semiconductor region in the depth direction and deeper on the second main surface side than the first semiconductor region, with one end in contact with the gate insulating film of the side wall of the trench in the first direction and the other end in contact with the first conductivity type region in the first direction.

5. The silicon carbide semiconductor device according to claim 4, further comprising a second conductivity type high-concentration region with a higher impurity concentration than the first semiconductor region, selectively provided between the bottom surface of the trench and the second conductivity type region, in contact with the second conductivity type region.

6. The silicon carbide semiconductor device according to claim 4, characterized in that the second conductivity type region is a portion sandwiched between the third semiconductor regions adjacent to each other in the second direction, and the impurity concentration is relatively low in that portion.

7. A method for manufacturing a silicon carbide semiconductor device comprising a parallel pn layer in which a first conductivity type region and a second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the first main surface of a semiconductor substrate made of silicon carbide, A first step involves epitaxially growing a first conductive type epitaxial layer, which forms the first main surface, on a starting substrate made of silicon carbide, which forms the second main surface of the semiconductor substrate; A second step involves forming an ion implantation mask on the first conductive epitaxial layer, with an opening in the portion facing the region where the second conductive region is formed. A third step is to form the parallel pn layer by ion implanting a second conductivity type impurity using the ion implantation mask, forming a second conductivity type region of a predetermined depth in the first conductivity type epitaxial layer at the opening of the ion implantation mask, and leaving the portion of the first conductivity type epitaxial layer excluding the second conductivity type region as the first conductivity type region. A fourth step involves forming a predetermined element structure between the first main surface and the parallel pn layer, A fifth step involves forming a first electrode electrically connected to the element structure, A sixth step of forming a second electrode on the second main surface, Includes, In the third step, the second conductive impurity penetrates the ion implantation mask and is ion-implanted with acceleration energy that has a range of the surface region of the first conductive epitaxial layer, and the second conductive diffusion layer is formed on the surface region of the first conductive epitaxial layer by the second conductive impurity that has penetrated the ion implantation mask. A method for manufacturing a silicon carbide semiconductor device, characterized in that the fourth step involves forming the element structure through which an electric current flows between the second conductivity type diffusion layer and the first conductivity type region.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, characterized in that the thickness of the second conductive diffusion layer is 0.8 μm or more and 1.5 μm or less in the third step.

9. In the second step, the thickness of the ion implantation mask is set to 6 μm or less. The method for manufacturing a silicon carbide semiconductor device according to claim 7, characterized in that the acceleration energy for ion implantation in the third step is 1 MeV or more and 8 MeV or less.

10. The aforementioned device structure is The parallel pn layer and, A first semiconductor region of a second conductivity type is provided between the first main surface and the parallel pn layer, A second semiconductor region of a first conductivity type is selectively provided between the first main surface and the first semiconductor region, A trench that penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer, The trench comprises a gate electrode provided inside the trench via a gate insulating film, The aforementioned fourth step is, A seventh step involves selectively forming the second semiconductor region on the surface region of the second conductivity type diffusion layer, leaving the portion of the second conductivity type diffusion layer excluding the second semiconductor region as the first semiconductor region, An eighth step is to form the trench that penetrates the second semiconductor region and the first semiconductor region in the depth direction and reaches the parallel pn layer, A method for manufacturing a silicon carbide semiconductor device according to claim 7, comprising a ninth step of forming the gate electrode inside the trench via the gate insulating film.

11. In the third step, a second conductive type region is formed that extends linearly in a second direction parallel to the first main surface and perpendicular to the first direction. In the eighth step, the trench is formed which penetrates the second semiconductor region and the first semiconductor region in the depth direction to reach the second conductivity type region and extends linearly in the second direction. In the seventh step, the second semiconductor regions are formed, which are scattered in the second direction along the side wall of the trench. The method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized in that, prior to the ninth step, a first conductivity type impurity is ion-implanted into the side wall of the trench from a direction oblique to the first main surface, thereby forming a third semiconductor region of the first conductivity type within the second conductivity type region at a position facing the second semiconductor region in the depth direction and deeper on the second main surface side than the first semiconductor region, penetrating the second conductivity type region in the first direction and in contact with the first conductivity type region.

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