Semiconductor equipment

Abstract

Suppresses the formation of voids. [Solution] The semiconductor device 100 includes a first wiring board 110, an electronic component 140, a second wiring board 120, a plurality of connecting members 130, and a sealing resin 101. The electronic component is provided on the first wiring board. The second wiring board is laminated on the first wiring board with the electronic component in between. The plurality of connecting members connect the first wiring board and the second wiring board. The sealing resin is filled between the first wiring board and the second wiring board and covers the electronic component and the plurality of connecting members. The first wiring board has a first pad 113 connected to a connecting member located around the electronic component, and the second wiring board has a second pad 125 connected to a connecting member located around the electronic component and positioned offset from the first pad in a direction intersecting the lamination direction of the first and second wiring boards.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In recent years, in order to achieve high-density component mounting, semiconductor devices that incorporate electronic components such as semiconductor chips inside a substrate have attracted attention. Such a semiconductor device has, for example, two wiring substrates. An electronic component such as a semiconductor chip is mounted on one wiring substrate, and such an electronic component is sandwiched between the electronic component and the other organic substrate. The two wiring substrates are connected by a plurality of connection members such as solder. Further, the space between the two wiring substrates is filled with, for example, a sealing resin.

[0003] By incorporating an electronic component between two wiring substrates in this way, three-dimensional component mounting becomes possible, and high-density and miniaturization of the semiconductor device can be achieved.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a semiconductor device incorporating an electronic component, there is a problem that voids occur in the sealing resin filled between the two wiring substrates sandwiching the electronic component.

[0006] In other words, since multiple connecting members are located around the electronic component to connect two wiring boards, the sealing resin that fills the space between the two wiring boards flows through the gaps between the connecting members into the space between the electronic component and the wiring board facing it. However, the space between the electronic component and the wiring board is relatively narrow, which tends to reduce the fluidity of the sealing resin. Therefore, especially when the width of the connecting members located around the electronic component is relatively large, the gaps between these connecting members become smaller, and the fluidity of the sealing resin around the electronic component decreases when the sealing resin is filled between the two wiring boards. As a result, voids are more likely to occur in the sealing resin.

[0007] The disclosed technology has been made in view of the above and aims to provide a semiconductor device that can suppress the generation of voids. [Means for solving the problem]

[0008] In one embodiment, the semiconductor device disclosed in this application includes a first wiring board, an electronic component, a second wiring board, a plurality of connecting members, and a sealing resin. The electronic component is provided on the first wiring board. The second wiring board is laminated on the first wiring board with the electronic component in between. The plurality of connecting members connect the first wiring board and the second wiring board. The sealing resin is filled between the first wiring board and the second wiring board and covers the electronic component and the plurality of connecting members. The first wiring board has a first pad connected to a connecting member located around the electronic component among the plurality of connecting members. The second wiring board has a second pad connected to a connecting member located around the electronic component and positioned offset from the first pad in a direction intersecting the lamination direction of the first and second wiring boards. [Effects of the Invention]

[0009] According to one embodiment of the semiconductor device disclosed in this application, the effect is achieved that the generation of voids can be suppressed. [Brief explanation of the drawing]

[0010] [Figure 1]Figure 1 is a diagram showing the configuration of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment, cut by a plane intersecting the stacking direction. [Figure 3] Figure 3 is a flowchart showing the manufacturing method of the first wiring board according to the embodiment. [Figure 4] Figure 4 is a schematic diagram showing a cross-section of the first wiring board. [Figure 5] Figure 5 is a diagram illustrating the mounting of electronic components. [Figure 6] Figure 6 shows a specific example of the solder ball mounting process. [Figure 7] Figure 7 is a flowchart showing the method for manufacturing the second wiring board according to the embodiment. [Figure 8] Figure 8 is a schematic diagram showing a cross-section of the second wiring board. [Figure 9] Figure 9 shows a specific example of the solder ball mounting process. [Figure 10] Figure 10 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] Figure 11 illustrates the stacking of the first and second wiring boards. [Figure 12] Figure 12 shows a specific example of the joining process. [Figure 13] Figure 13 shows a specific example of the molding process. [Figure 14] Figure 14 shows a specific example of the individualization process. [Figure 15] Figure 15 shows the configuration of a semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0011] Embodiments of the semiconductor device disclosed in this application will be described in detail below with reference to the drawings. However, these embodiments do not limit the disclosed technology.

[0012] (Embodiment) FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to an embodiment. In FIG. 1, a cross-section of the semiconductor device 100 is schematically shown. In the following, for convenience, the direction from the first wiring substrate 110 to the second wiring substrate 120 is defined as the upward direction, the direction from the second wiring substrate 120 to the first wiring substrate 110 is defined as the downward direction, and the vertical direction of the semiconductor device 100 is defined accordingly. However, the semiconductor device 100 may be manufactured and used, for example, with the top and bottom reversed, or may be manufactured and used in any orientation.

[0013] The semiconductor device 100 shown in FIG. 1 has a first wiring substrate 110 and a second wiring substrate 120, and has a sealing resin 101 that covers an electronic component 140 disposed between the first wiring substrate 110 and the second wiring substrate 120. Specifically, the semiconductor device 100 is configured such that the first wiring substrate 110 and the second wiring substrate 120 are connected by a plurality of connection members 130. An electronic component 140 is mounted on the upper surface of the first wiring substrate 110, and this electronic component 140 is sandwiched between the first wiring substrate 110 and the second wiring substrate 120 and covered with the sealing resin 101.

[0014] The sealing resin 101 is an insulating resin such as a thermosetting epoxy resin containing an inorganic filler such as alumina, silica, aluminum nitride, or silicon carbide. The electronic component 140 is, for example, a semiconductor chip.

[0015] The first wiring substrate 110 has a substrate 111, a protective insulating layer 112 (an example of a first insulating layer), an upper surface pad 113, a solder resist layer 114, and a lower surface pad 115. Although not shown in FIG. 1, the upper surface pad 113 and the lower surface pad 115 are electrically connected by via wirings provided in the substrate 111.

[0016] The substrate 111 is an insulating plate-shaped member and is the base material for the first wiring board 110. As the material for the substrate 111, for example, a glass epoxy resin can be used, which is obtained by impregnating a reinforcing material, such as glass cloth (glass woven fabric), with a thermosetting insulating resin mainly composed of epoxy resin and then curing it. The reinforcing material is not limited to glass cloth; for example, glass nonwoven fabric, aramid woven fabric, aramid nonwoven fabric, liquid crystal polymer (LCP) woven fabric, and LCP nonwoven fabric can be used. In addition to epoxy resin, other thermosetting insulating resins such as polyimide resin and cyanate resin can also be used. Wiring layers, including an upper pad 113 and a lower pad 115, are formed on both sides of the substrate 111. As the material for the wiring layers, for example, copper or a copper alloy can be used.

[0017] The substrate 111 is not limited to a single-layer insulating material, but may also be a multilayer substrate with an insulating layer and a wiring layer laminated together. When the substrate 111 is a multilayer substrate, the wiring layers sandwiching the insulating layer are electrically connected by vias that penetrate the insulating layer. As the material for the insulating layer, for example, insulating resins such as epoxy resin and polyimide resin, or resin materials in which fillers such as silica and alumina are mixed into these resins can be used. As the material for the wiring layer, for example, copper (Cu) or a copper alloy can be used.

[0018] The protective insulating layer 112 is an insulating layer that covers the upper surface of the substrate 111. An opening is provided in a part of the protective insulating layer 112, and the upper surface pad 113 is exposed through the opening. As the material for the protective insulating layer 112, an insulating resin such as epoxy resin or acrylic resin can be used.

[0019] The top pad 113 is formed in the wiring layer on the top surface of the substrate 111 and is exposed through an opening in the protective insulating layer 112 for connection to the connecting member 130 and mounting of the electronic component 140. Specifically, the connecting member 130 is connected to the top pad 113a of the top pad 113. The top pad 113a includes an inner pad 113-1 (an example of a first pad) and an outer pad 113-2. The inner pad 113-1 is connected to the connecting member 130a, which is located around the electronic component 140, and the outer pad 113-2 is connected to the connecting member 130b, which is located further away from the electronic component 140 than the connecting member 130a. The electronic component 140 is also connected to the top pad 113b of the top pad 113. Specifically, for example, the electronic component 140 is flip-chip connected to the top pad 113b by a solder bump 141. Then, an underfill material 142 is filled between the first wiring board 110 and the electronic component 140. As for the material of the top pad 113, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0020] The solder resist layer 114 is an insulating layer that covers the underside of the substrate 111. An opening is provided in a part of the solder resist layer 114, and the underside pad 115 is exposed through the opening. As the material for the solder resist layer 114, an insulating resin such as epoxy resin or acrylic resin can be used.

[0021] The bottom pad 115 is formed in the wiring layer on the bottom surface of the substrate 111 and is exposed through an opening in the solder resist layer 114 for the formation of external connection terminals. That is, external connection terminals (not shown), such as solder balls, are formed on the bottom pad 115. As for the material of the bottom pad 115, copper or a copper alloy can be used, similar to the wiring layer.

[0022] The second wiring board 120 includes a substrate 121, a solder resist layer 122, an upper pad 123, a protective insulating layer 124 (an example of a second insulating layer), and a lower pad 125. Although not shown in Figure 1, the upper pad 123 and the lower pad 125 are electrically connected by via wiring provided in the substrate 121.

[0023] The substrate 121 is an insulating plate-shaped member and serves as the base material for the second wiring board 120. As the material for the substrate 121, for example, a glass epoxy resin can be used, which is obtained by impregnating a reinforcing material, such as glass cloth (glass woven fabric), with a thermosetting insulating resin mainly composed of epoxy resin and then curing it. The reinforcing material is not limited to glass cloth; for example, glass nonwoven fabric, aramid woven fabric, aramid nonwoven fabric, LCP woven fabric, and LCP nonwoven fabric can be used. Furthermore, as the thermosetting insulating resin, in addition to epoxy resin, for example, polyimide resin and cyanate resin can be used. Wiring layers, including an upper pad 123 and a lower pad 125, are formed on both sides of the substrate 121. As the material for the wiring layers, for example, copper or a copper alloy can be used.

[0024] The substrate 121 is not limited to a single-layer insulating material, but may also be a multilayer substrate with an insulating layer and a wiring layer laminated together. When the substrate 121 is a multilayer substrate, the wiring layers sandwiching the insulating layer are electrically connected by vias that penetrate the insulating layer. As the material for the insulating layer, for example, insulating resins such as epoxy resin and polyimide resin, or resin materials in which fillers such as silica and alumina are mixed into these resins can be used. As the material for the wiring layer, for example, copper (Cu) or a copper alloy can be used.

[0025] The solder resist layer 122 is an insulating layer that covers the upper surface of the substrate 121. An opening is provided in a part of the solder resist layer 122, and the upper surface pad 123 is exposed through the opening. As the material for the solder resist layer 122, an insulating resin such as epoxy resin or acrylic resin can be used.

[0026] The top pad 123 is formed on the wiring layer on the top surface of the substrate 121 and is exposed through an opening in the solder resist layer 122 for the formation of external connection terminals. That is, external connection terminals (not shown), such as solder balls, are formed on the top pad 123. As for the material of the top pad 123, copper or a copper alloy can be used, similar to the wiring layer.

[0027] The protective insulating layer 124 is an insulating layer that covers the lower surface of the substrate 121. An opening is provided in a part of the protective insulating layer 124, and the lower surface pad 125 is exposed through the opening. As the material for the protective insulating layer 124, an insulating resin such as epoxy resin or acrylic resin can be used.

[0028] The bottom pad 125 is formed in the wiring layer on the bottom surface of the substrate 121 and is exposed through an opening in the protective insulating layer 124 for connection with the connecting member 130. That is, the connecting member 130 is bonded to the bottom pad 125. The bottom pad 125 includes an inner pad 125-1 (an example of a second pad) and an outer pad 125-2. The inner pad 125-1 is connected to a connecting member 130a, which is located around the electronic component 140 from among the multiple connecting members 130, and the outer pad 125-2 is connected to a connecting member 130b, which is located further away from the electronic component 140 than the connecting member 130a. As for the material of the bottom pad 125, similar to the wiring layer, for example, copper or a copper alloy can be used.

[0029] In this embodiment, the inner pad 125-1 connected to the connecting member 130a is positioned offset from the inner pad 113-1, which is similarly connected to the connecting member 130a, in a direction intersecting the stacking direction Z of the first wiring board 110 and the second wiring board 120. Specifically, the inner pad 125-1 is positioned offset from the inner pad 113-1 in a direction that intersects the stacking direction Z and moves closer to the electronic component 140.

[0030] Thus, in this embodiment, the inner pad 125-1 connected to one end of the connecting member 130a around the electronic component 140 is positioned offset from the inner pad 113-1 connected to the other end of the connecting member 130a in a direction intersecting the stacking direction Z. As a result, the straight-line distance of the connecting member 130a connecting the center of the inner pad 125-1 and the center of the inner pad 113-1 is longer than the straight-line distance of the connecting member 130b connecting the center of the outer pad 125-2 and the center of the outer pad 113-2. Therefore, the amount of elongation of the connecting member 130a between the inner pad 125-1 and the inner pad 113-1 is larger than the amount of elongation of the connecting member 130b between the outer pad 125-2 and the outer pad 113-2, and the width of the connecting member 130a can be narrowed. By narrowing the width of the connecting member 130a, the gap between adjacent connecting members 130a is widened, which improves the fluidity of the sealing resin 101 around the electronic component 140 when filling the space between the first wiring board 110 and the second wiring board 120 with the sealing resin 101. As a result, the sealing resin 101 can flow smoothly into the relatively narrow space between the electronic component 140 and the first wiring board 110, and consequently, the generation of voids in the sealing resin 101 can be suppressed.

[0031] Furthermore, the inner pad 125-1 is positioned offset from the inner pad 113-1, intersecting the stacking direction Z and moving closer to the electronic component 140. This allows the connecting member 130a between the inner pad 125-1 and the inner pad 113-1 to be extended in the direction closer to the electronic component 140. As a result, the flow of the sealing resin 101 to the electronic component 140 can be promoted around the electronic component 140, thereby further suppressing the generation of voids in the sealing resin 101.

[0032] Multiple connecting members 130 are formed from, for example, solder, and connect the first wiring board 110 and the second wiring board 120. Specifically, each connecting member 130 is an integrated unit formed by integrating solder balls mounted on the first wiring board 110 and solder balls mounted on the second wiring board 120. Each connecting member 130 has a barrel shape in which the width of the lower end connected to the second wiring board 120 is greater than the width of the upper end connected to the first wiring board 110, and the sides bulge outward.

[0033] Figure 2 is a schematic cross-sectional view of the semiconductor device 100 according to the embodiment, cut by a plane intersecting the stacking direction Z. Figure 2 corresponds to the cross-section of the semiconductor device 100 along line II-II in Figure 1. For the sake of clarity, the sealing resin 101 is not shown in Figure 2.

[0034] As shown in Figure 2, the multiple connecting members 130 have different widths along the direction intersecting the stacking direction Z (see Figure 1) depending on their relative position to the electronic component 140. Specifically, the connecting member 130a located around the electronic component 140 has a smaller width along the direction intersecting the stacking direction Z than the connecting member 130b (an example of another connecting member) located further away from the electronic component 140 than the connecting member 130a. That is, the width w1 of the connecting member 130a along the direction intersecting the stacking direction Z is smaller than the width w2 of the connecting member 130b along the direction intersecting the stacking direction Z. For example, above the center of the connecting members 130a and 130b in the stacking direction Z, the width w1 of the connecting member 130a is smaller than the width w2 of the connecting member 130b.

[0035] Because the width w1 of the connecting member 130a is smaller than the width w2 of the connecting member 130b, the gap between adjacent connecting members 130a can be widened compared to the gap between adjacent connecting members 130b. As a result, when filling the space between the first wiring board 110 and the second wiring board 120 with the sealing resin 101, the fluidity of the sealing resin 101 around the electronic component 140 is improved. This allows the sealing resin 101 to flow smoothly into the relatively narrow space between the electronic component 140 and the first wiring board 110, and as a result, the generation of voids in the sealing resin 101 can be suppressed.

[0036] Next, a method for manufacturing the semiconductor device 100 configured as described above will be explained. Below, a method for manufacturing the first wiring board 110 and a method for manufacturing the second wiring board 120 will be explained, followed by a method for manufacturing the semiconductor device 100 having the first wiring board 110 and the second wiring board 120.

[0037] Figure 3 is a flowchart showing the manufacturing method of the first wiring board 110 according to the embodiment.

[0038] First, wiring layers are formed on the upper and lower surfaces of the substrate 111 (step S101). Specifically, the wiring layers on the upper and lower surfaces of the substrate 111 are formed sequentially, for example, by a semi-additive method. The wiring layer on the upper surface of the substrate 111 includes an upper pad 113, and the wiring layer on the lower surface of the substrate 111 includes a lower pad 115. Then, a solder resist layer 114 having an opening at the position of the lower pad 115 is formed on the lower surface of the substrate 111 (step S102), and a protective insulating layer 112 having an opening at the position of the upper pad 113 is formed on the upper surface of the substrate 111 (step S103). The protective insulating layer 112 and the solder resist layer 114 can be obtained, for example, by laminating a photosensitive resin film onto the upper and lower surfaces of the substrate 111, or by applying a liquid or paste-like resin, and then exposing and developing the laminated or applied resin by photolithography to pattern it into the desired shape.

[0039] Through the steps completed so far, a first wiring board 110 is formed in which, for example as shown in Figure 4, the upper surface pads 113a and 113b are exposed on the upper surface of the substrate 111 through the opening 112a of the protective insulating layer 112, and the lower surface pad 115 is exposed on the lower surface of the substrate 111 through the opening 114a of the solder resist layer 114. Figure 4 is a schematic diagram showing a cross-section of the first wiring board. The upper surface pad 113a is a pad that connects to the connecting member 130, and includes an inner pad 113-1 and an outer pad 113-2. The inner pad 113-1 is a pad that connects to the connecting member 130a located around the electronic component 140 among the multiple connecting members 130, and the outer pad 113-2 is a pad that connects to the connecting member 130b located further away from the electronic component 140 than the connecting member 130a. The upper surface pad 113b is a pad that flip-chip connects the electronic component 140. The exposed areas of these upper pads 113a and 113b may be different from each other. Furthermore, the width of the exposed portion of the upper pad 113a can be, for example, about 120 to 160 μm.

[0040] Solder paste is printed on the top pad 113b because an electronic component 140 will be mounted there (step S104). Then, the electronic component 140 is mounted at the position of the top pad 113b (step S105). The electronic component 140 is mounted on the first wiring board 110 after undergoing a reflow process (step S106). In addition, if necessary, an underfill material 142 made of insulating resin is filled between the electronic component 140 and the top surface of the first wiring board 110 (step S107).

[0041] Since the electronic components 140 are mounted on the top surface of the first wiring board 110, and the top surface of the first wiring board 110 surrounding the electronic components 140 is covered by the underfill material 142, the degree of freedom in positioning the top pad 113a is lower than that of the inner pad 125-1, which will be explained later.

[0042] As a result of the steps taken so far, an electronic component 140, which is flip-chip connected to the top pad 113b by solder bumps 141, is mounted on the top surface of the first wiring board 110, for example, as shown in Figure 5. Figure 5 is a diagram illustrating the mounting of the electronic component 140.

[0043] When the electronic component 140 is mounted on the upper surface of the first wiring board 110, solder balls 131 used to form the connecting member 130 are placed at the position of the upper pad 113a (step S108). Then, a reflow process is performed (step S109) to bond the solder balls 131 to the upper pad 113a.

[0044] Through the steps described so far, solder balls 131 (an example of a first conductor ball) are bonded to the upper pad 113a, as shown in Figure 6. This results in a first wiring board 110 that forms the lower layer of the semiconductor device 100. Figure 6 shows a specific example of the solder ball mounting process. Electronic components 140 are mounted on the upper surface of the obtained first wiring board 110, and solder balls 131 are bonded to the upper pad 113a exposed through the opening of the protective insulating layer 112. The diameter of the solder balls 131 can be, for example, about 100 to 250 μm.

[0045] Furthermore, it is preferable that the first wiring board 110 is not manufactured as a single unit, but rather as an assembly of multiple first wiring boards 110 arranged in a grid. In the assembly, for example, the first wiring board 110 is manufactured in individual sections divided in a grid pattern.

[0046] Next, Figure 7 is a flowchart showing the manufacturing method of the second wiring board 120 according to the embodiment.

[0047] First, wiring layers are formed on the upper and lower surfaces of the substrate 121 (step S201). Specifically, the wiring layers on the upper and lower surfaces of the substrate 121 are formed sequentially, for example, by a semi-additive method. The wiring layer on the upper surface of the substrate 121 includes an upper pad 123, and the wiring layer on the lower surface of the substrate 121 includes a lower pad 125. Then, a protective insulating layer 124 having an opening at the position of the lower pad 125 is formed on the lower surface of the substrate 121 (step S202), and a solder resist layer 122 having an opening at the position of the upper pad 123 is formed on the upper surface of the substrate 121 (step S203). The solder resist layer 122 and the protective insulating layer 124 can be obtained, for example, by laminating a photosensitive resin film onto the upper and lower surfaces of the substrate 121, or by applying a liquid or paste-like resin, and then exposing and developing the laminated or applied resin by photolithography to pattern it into the desired shape.

[0048] As a result of the steps taken so far, a second wiring board 120 is formed in which, for example as shown in Figure 8, the upper pad 123 is exposed on the upper surface of the substrate 121 through an opening 122a in the solder resist layer 122, and the lower pad 125 is exposed on the lower surface of the substrate 121 through an opening 124a in the protective insulating layer 124. Figure 8 is a schematic diagram showing a cross-section of the second wiring board. The lower pad 125 is a pad that connects to the connecting member 130, and includes an inner pad 125-1 and an outer pad 125-2. The inner pad 125-1 is a pad that connects to the connecting member 130a located around the electronic component 140 among the plurality of connecting members 130, and the outer pad 125-2 is a pad that connects to the connecting member 130b located further away from the electronic component 140 than the connecting member 130a.

[0049] Furthermore, the inner pad 125-1 is positioned offset from the inner pad 113-1 in a direction intersecting the stacking direction Z (see Figure 1). The opening 124a of the protective insulating layer 124 is positioned offset from the opening 112a of the protective insulating layer 112 in a direction intersecting the stacking direction Z. This allows the area of ​​the inner pad 125-1 exposed from the opening 124a of the protective insulating layer 124 to be maintained at an area suitable for connection with the connecting member 130a located around the electronic component 140.

[0050] Because the inner pad 125-1 offers greater flexibility in placement compared to the upper pad 113a, it can be offset in relatively free directions.

[0051] Since the connecting member 130 is connected to the lower pad 125, solder balls 132 used to form the connecting member 130 are placed at the position of the lower pad 125 (step S204). Then, through a reflow process (step S205), the solder balls 132 are bonded to the lower pad 125.

[0052] Through the steps described so far, solder balls 132 (an example of a second conductor ball) are bonded to the bottom pad 125, as shown in Figure 9. This results in a second wiring board 120 that forms the upper layer of the semiconductor device 100. Figure 9 shows a specific example of the solder ball mounting process. In the obtained second wiring board 120, solder balls 132 are bonded to the bottom pad 125 exposed from the opening of the protective insulating layer 124. The diameter of the solder balls 132 can be, for example, about 100 to 250 μm, similar to the solder balls 131. The diameter of the solder balls 132 may differ from that of the solder balls 131.

[0053] Furthermore, it is preferable that the second wiring board 120 is not manufactured individually, but rather as an assembly of multiple second wiring boards 120 arranged in a grid. In the assembly, for example, the second wiring board 120 is manufactured in individual sections divided in a grid pattern.

[0054] Next, Figure 10 is a flowchart illustrating a method for manufacturing the semiconductor device 100 according to the embodiment. The semiconductor device 100 is manufactured using the first wiring board 110 and the second wiring board 120 described above.

[0055] The first wiring board 110 and the second wiring board 120 are joined together (step S301). First, as shown in Figure 11, for example, a solder ball 132 joined to the lower pad 125 of the second wiring board 120 is placed above a solder ball 131 joined to the upper pad 113a of the first wiring board 110, and the second wiring board 120 is stacked on top of the first wiring board 110. Figure 11 is a diagram illustrating the stacking of the first wiring board 110 and the second wiring board 120. Electronic components 140 are placed between the first wiring board 110 and the second wiring board 120. The inner pad 125-1 of the second wiring board 120 is offset from the inner pad 113-1 of the first wiring board 110 in a direction intersecting the stacking direction Z. From the viewpoint of properly integrating solder ball 131 and solder ball 132, it is preferable that the offset amount d of the inner pad 125-1 of the second wiring board 120 relative to the inner pad 113-1 of the first wiring board 110 is smaller than the diameter of solder ball 131 or solder ball 132. For example, the offset amount d can be about 1 to 10% of the diameter of solder ball 131 or solder ball 132. If the diameters of solder ball 131 and solder ball 132 are different, the offset amount d is adjusted based on the diameter of the larger solder ball.

[0056] Next, a reflow process is performed, causing the solder balls 131 and 132 to melt and fuse together, forming a single connecting member 130. As a result, the first wiring board 110 and the second wiring board 120 are joined by multiple connecting members 130, as shown in Figure 12, for example. At this time, due to the offset between the inner pads 125-1 and 113-1, the amount of elongation of the connecting member 130a between the inner pads 125-1 and 113-1 is greater than the amount of elongation of the connecting member 130b between the outer pads 125-2 and 113-2, allowing the connecting member 130a to be narrowed. Narrowing the connecting member 130a widens the gap between adjacent connecting members 130a. Figure 12 shows a specific example of the joining process.

[0057] Then, for example, by performing a transfer mold (step S302), the sealing resin 101 is filled into the space between the first wiring board 110 and the second wiring board 120. In the transfer mold, the joined first wiring board 110 and the second wiring board 120 are placed in a mold, and the fluidized sealing resin 101 is injected into the mold. The sealing resin 101 is then heated to a predetermined temperature (for example, 175 degrees) and hardened. As a result, as shown in Figure 13, for example, the sealing resin 101 is filled into the space between the first wiring board 110 and the second wiring board 120, sealing the connecting member 130 and the electronic component 140. Figure 13 is a diagram showing a specific example of the molding process. At this time, since the gap between adjacent connecting members 130a is widened, the sealing resin 101 flows smoothly around the electronic component 140. This allows the sealing resin 101 to flow smoothly into the relatively narrow space between the electronic component 140 and the first wiring board 110, and as a result, the generation of voids in the sealing resin 101 can be suppressed.

[0058] Through the steps performed so far, a structure having the same structure as the semiconductor device 100 is obtained, for example, as shown in Figure 14. Since this structure is composed of an assembly containing a plurality of first wiring boards 110 and an assembly containing a plurality of second wiring boards 120, individual pieces are cut out of the individual first wiring boards 110 and second wiring boards 120 (step S303). Figure 14 is a diagram showing a specific example of the individual piece cutting process. Specifically, the structure shown in Figure 14 is cut along a cutting line A located outside the connecting member 130b, for example, by a dicer or slicer, thereby obtaining the semiconductor device 100.

[0059] (modified version) Next, a modified example of the embodiment will be described with reference to Figure 15. In the modified examples shown below, the same reference numerals are used for parts that are the same as in the embodiment, and redundant explanations may be omitted.

[0060] Figure 15 shows the configuration of a semiconductor device 100 according to a modified embodiment. In Figure 15, a schematic cross-section of the semiconductor device 100 is shown. The semiconductor device 100 according to the modified embodiment differs from the embodiment in the arrangement of the inner pads 125-1 of the second wiring board 120.

[0061] Specifically, in the modified configuration, the inner pad 125-1 is positioned offset from the inner pad 113-1, intersecting the stacking direction Z and moving away from the electronic component 140. This allows the connecting member 130a between the inner pads 125-1 and 113-1 to be stretched away from the electronic component 140. As a result, the flow of the sealing resin 101 to the electronic component 140 can be promoted around the electronic component 140, thereby further suppressing the generation of voids in the sealing resin 101.

[0062] (Other variations) In the above embodiment, the case in which the inner pad 125-1 connected to the connecting member 130a located around the electronic component 140 is offset was described as an example, but the offset is not limited to the inner pad 125-1. That is, the outer pad 125-2 connected to the connecting member 130b, which is located further away from the electronic component 140 than the connecting member 130a, may be offset relative to the outer pad 113-2 in a direction intersecting the stacking direction Z.

[0063] As described above, the semiconductor device according to the embodiment (for example, semiconductor device 100) comprises a first wiring board (for example, first wiring board 110), an electronic component (for example, electronic component 140), and a second wiring board (for example, second wiring board 120) The wiring board has a plurality of connecting members (for example, connecting member 130) and a sealing resin (for example, sealing resin 101). The electronic component is provided on the first wiring board. The second wiring board is laminated on the first wiring board with the electronic component in between. The plurality of connecting members connect the first wiring board and the second wiring board. The sealing resin is filled between the first wiring board and the second wiring board and covers the electronic component and the plurality of connecting members. The first wiring board has a first pad (for example, an inner pad 113-1) connected to a connecting member (for example, connecting member 130a) located around the electronic component among the plurality of connecting members. The second wiring board has a second pad (for example, an inner pad 125-1) connected to a connecting member located around the electronic component and offset from the first pad in a direction intersecting the lamination direction of the first and second wiring boards (for example, lamination direction Z). This makes it possible to suppress the generation of voids.

[0064] Furthermore, the second pad may be positioned offset from the first pad, intersecting the stacking direction of the first and second wiring boards and moving closer to the electronic component. This can further suppress the generation of voids.

[0065] Furthermore, the second pad may be positioned offset from the first pad in a direction that intersects the stacking direction of the first and second wiring boards and moves away from the electronic components. This can further suppress the generation of voids.

[0066] Furthermore, each connecting member may be an integrated product formed by integrating a first conductor ball (for example, a solder ball 131) mounted on a first wiring board and a second conductor ball (for example, a solder ball 132) mounted on a second wiring board. The offset amount of the second pad relative to the first pad (for example, offset amount d) may be smaller than the diameter of the first conductor ball or the second conductor ball. This allows the first conductor ball and the second conductor ball to be properly integrated.

[0067] Furthermore, among the multiple connecting members, the connecting member located around the electronic component may have a smaller width in the direction intersecting the stacking direction than other connecting members located further away from the electronic component (for example, connecting member 130b). This can suppress the generation of voids.

[0068] Furthermore, the first wiring board may have a first insulating layer (for example, a protective insulating layer 112) that covers the upper surface of the substrate of the first wiring board (for example, substrate 111) and has an opening (for example, an opening 112a) that exposes the first pad. The second wiring board may have a second insulating layer (for example, a protective insulating layer 124) that covers the lower surface of the substrate of the second wiring board (for example, substrate 121) and has an opening (for example, an opening 124a) that exposes the second pad. The opening of the second insulating layer may be offset from the opening of the first insulating layer in a direction intersecting the stacking direction of the first and second wiring boards. This makes it possible to maintain the area of ​​the second pad exposed from the opening of the second insulating layer as an area suitable for connection with a connecting member located around the electronic component. [Explanation of symbols]

[0069] 100 Semiconductor Devices 101 Sealing resin 110 First Wiring Board 111 circuit board 112 Protective insulating layer 112a opening 113-1 Inner pad 120 Second Wiring Board 121 circuit boards 124 Protective insulating layer 124a opening 125-1 Inner pad 130, 130a, 130b connecting members 131, 132 Solder balls 140 Electronic Components 142 Underfill material

Claims

1. First wiring board and Electronic components provided on the first wiring board, A second wiring board is laminated on the first wiring board with the electronic components sandwiched in between, A plurality of connecting members that connect the first wiring board and the second wiring board, A sealing resin is filled between the first wiring board and the second wiring board and covers the electronic components and the plurality of connecting members. It has, The first wiring board is, It has a first pad that is connected to a connecting member located around the electronic component among the plurality of connecting members, The aforementioned second wiring board is The electronic component has a second pad that is connected to a connecting member located around the electronic component and is offset from the first pad in a direction intersecting the stacking direction of the first and second wiring boards. A semiconductor device characterized by the following features.

2. The aforementioned second pad is The first pad is positioned offset from the first pad in a direction that intersects the stacking direction of the first and second wiring boards and approaches the electronic component. The semiconductor device according to feature 1.

3. The aforementioned second pad is The first pad is positioned offset from the first pad in a direction that intersects the stacking direction of the first and second wiring boards and moves away from the electronic component. The semiconductor device according to feature 1.

4. Each of the aforementioned connecting members is It is an integrated product formed by integrating a first conductor ball mounted on the first wiring board and a second conductor ball mounted on the second wiring board. The offset amount of the second pad relative to the first pad is, Smaller than the diameter of the first conductor ball or the second conductor ball The semiconductor device according to feature 1.

5. The aforementioned plurality of connecting members are The connecting member located around the electronic component has a smaller width in the direction intersecting the stacking direction than other connecting members located further away from the electronic component. The semiconductor device according to feature 1.

6. An underfill material is provided between the first wiring board and the electronic component. The semiconductor device according to feature 1.

7. The first wiring board is, The first insulating layer covers the upper surface of the substrate of the first wiring board and has an opening that exposes the first pad, The aforementioned second wiring board is The second insulating layer covers the lower surface of the substrate of the second wiring board and has an opening that exposes the second pad, The opening in the second insulating layer is It is positioned offset from the opening of the first insulating layer in a direction intersecting the stacking direction of the first and second wiring boards. The semiconductor device according to feature 1.

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