Signal processing circuit

Abstract

To provide a signal processing circuit that can process input signals with high accuracy. [Solution] The signal processing circuit 1 comprises an amplification circuit (operational amplifiers 10a, 10b) that outputs an output voltage corresponding to the input voltage, a comparison circuit 15 that outputs a comparison result obtained by comparing the output voltage with a predetermined voltage, and a control circuit that, based on the comparison result, when the offset adjustment of one of the selected operational amplifiers 10a, 10b is completed, stops the processing of the input signal of the other operational amplifier while allowing the other operational amplifier to process the input signal, and further performs the offset adjustment of the other operational amplifier based on a signal of a predetermined period. The control circuit, based on the comparison result, when the offset adjustment of the other operational amplifier is completed, stops the processing of the input signal of the one operational amplifier while allowing the other operational amplifier to process the input signal, and further performs the offset adjustment of the one operational amplifier based on a signal of a predetermined period.

Description

Technical Field

[0001] The present invention relates to a signal processing circuit.

Background Art

[0002] There are operational amplifiers having a circuit for adjusting an offset voltage (for example, Patent Documents 1 to 6).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, generally, after adjusting the offset voltage of an operational amplifier, if a long time elapses, the offset voltage may shift due to the influence of temperature or the like. As a result, the operational amplifier may not be able to process an input signal accurately.

[0005] The present invention has been made in view of the above conventional problems, and an object thereof is to provide a signal processing circuit capable of accurately processing an input signal.

Means for Solving the Problems

[0006] A first aspect of the signal processing circuit according to the present invention, which solves the aforementioned problems, comprises: an offset-adjustable first operational amplifier; an offset-adjustable second operational amplifier; an amplification circuit that uses an operational amplifier selected from the first and second operational amplifiers and outputs an output voltage corresponding to an input voltage; a comparison circuit that outputs a comparison result obtained by comparing the output voltage with a predetermined voltage; and a control circuit that, based on the comparison result, when the offset adjustment of the selected operational amplifier is completed, stops the processing of the input signal of the other operational amplifier while allowing the first operational amplifier to process the input signal, and further executes the offset adjustment of the first operational amplifier based on the predetermined period signal.

[0007] A second aspect of the signal processing circuit according to the present invention, which solves the aforementioned problems, is a signal processing circuit comprising: an amplification circuit that uses an operational amplifier and outputs an output voltage corresponding to an input voltage; an adjustment circuit that adjusts the offset of the operational amplifier based on the value of adjustment data; a comparison circuit that outputs a comparison result obtained by comparing the output voltage with a predetermined voltage; and a control circuit that, after performing a process of storing the comparison result of the operational amplifier offset adjusted by the comparison circuit as a first state with the value of the adjustment data set as a first value, storing the comparison result of the operational amplifier offset adjusted by the comparison circuit as a second state with the value of the adjustment data set as a second value, and storing the comparison result of the operational amplifier offset adjusted by the comparison circuit as a third state with the value of the first value, determines whether the comparison result of the first state and the comparison result of the third state are the same. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a signal processing circuit that can process input signals with high accuracy. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of the configuration of signal processing circuit 1. [Figure 2] This figure shows an example of the configuration of the signal processing circuit 1 when the operational amplifier 10a is selected to operate as an amplification circuit. [Figure 3] This figure shows an example of the configuration of operational amplifiers 10a and 10b. [Figure 4] This figure shows an example flowchart illustrating the operation of signal processing circuit 1. [Figure 5] This figure shows an example of a timing chart when offset adjustment is completed within period T. [Figure 6] This figure shows an example of a timing chart in the case where offset adjustment is not completed within period T. [Modes for carrying out the invention]

[0010] The following matters become clear from this specification and the accompanying drawings:

[0011] In the following, identical or equivalent components, parts, etc., shown in each drawing will be denoted by the same reference numeral, and redundant explanations may be omitted as appropriate.

[0012] Furthermore, in this embodiment, "connection" refers to a state in which two components are electrically connected unless otherwise specified. Therefore, "connection" includes not only cases where two components are connected not only by wiring, but also, for example, by a resistor.

[0013] ===Configuration of Signal Processing Circuit 1=== FIG. 1 is a diagram showing an example of the configuration of the signal processing circuit 1. The signal processing circuit 1 has two operational amplifiers, and while one operational amplifier is processing an input signal, it adjusts the offset of the other operational amplifier. Specifically, based on the comparison result of the comparator 15 (described later), when the offset adjustment of, for example, the operational amplifier 10a (described later) is completed, the signal processing circuit 1 causes the operational amplifier 10a to process the input signal while stopping the processing of the input signal of the operational amplifier 10b, and executes the offset adjustment of the operational amplifier 10b based on the signal of the period T. Similarly, when the offset adjustment of, for example, the operational amplifier 10b is completed, the signal processing circuit 1 causes the operational amplifier 10b to process the input signal while stopping the processing of the input signal of the operational amplifier 10a, and executes the offset adjustment of the operational amplifier 10a based on the signal of the period T. The signal processing circuit 1 includes operational amplifiers 10a and 10b, counters 11 and 16, a control circuit 12, resistors 13 and 14, a comparator 15, and analog switches 20 to 27.

[0014] The operational amplifier 10a is selected to operate as an amplifier circuit when the control circuit 12 described later outputs a signal SelA of a high level (hereinafter referred to as the "H" level) and outputs a signal SelB of a low level (hereinafter referred to as the "L" level), and processes the input signal. Specifically, in this case, as shown in FIG. 2, the operational amplifier 10a is used as an amplifier circuit that outputs an output voltage Vo corresponding to the input voltage Vin.

[0015] On the other hand, the operational amplifier 10a is selected as an object of offset adjustment and its offset is adjusted when the control circuit 12 outputs a signal SelA of the "L" level and a signal SelB of the "H" level. Also, in this case, although details will be described later, the operational amplifier 10a is used in a non-inverting amplifier circuit and theoretically outputs a reference voltage Vref.

[0016] Also, when the control circuit 12 described later outputs a signal SelA of "L" level and a signal SelB of "H" level, the operational amplifier 10b is selected to operate as an amplifier circuit and processes the input signal. Specifically, in this case, the operational amplifier 10b is used as an amplifier circuit that outputs an output voltage Vo corresponding to the input voltage Vin.

[0017] On the other hand, when the control circuit 12 outputs a signal SelA of "H" level and a signal SelB of "L" level, the operational amplifier 10b is selected as an object for offset adjustment, and the offset is adjusted. Also, in this case, although details will be described later, the operational amplifier 10b is used in a non-inverting amplifier circuit and theoretically outputs a reference voltage Vref.

[0018] ==Configuration of Operational Amplifier 10a== As shown in FIG. 3, the operational amplifier 10a includes PMOS transistors 100 to 103, 110, 111, 120, 121, a variable resistor 112, NMOS transistors 113, 122, 123, 130, a capacitor 140, and a resistor 141.

[0019] PMOS transistors 100 to 103 form a current mirror circuit. Specifically, a bias current Ibias flows through the PMOS transistor 100, and currents corresponding to the bias current Ibias flow through the PMOS transistors 101 to 103.

[0020] PMOS transistors 110 and 111 form a differential pair, and voltages IN_P applied to the non-inverting input of the operational amplifier 10a and IN_M applied to the inverting input are respectively applied to their gates. Also, currents Ip and Im corresponding to the voltages IN_P and IN_M applied to each of the PMOS transistors 110 and 111 flow through them.

[0021] The variable resistor 112 is a circuit for adjusting the offset of the operational amplifier 10a based on the count value CNTa of the counter 11. As will be explained in detail later, the count value CNTa is the count value of the 8-bit counter 11 and changes from 0 to 255. The variable resistor 112 is a resistor whose resistance value changes each time the count value CNTa changes by one, and therefore includes 255 resistors with predetermined resistance values ​​(e.g., 1kΩ) and 256 connection nodes to which the drain of the NMOS transistor 113 (described later) is connected. For convenience, in Figure 3, only five of the 255 resistors, resistors 150 to 154, are shown.

[0022] Furthermore, the variable resistor 112 changes the position of the connection node of the resistor to which the drain of the NMOS transistor 113 is connected, according to the count value CNTa. As a result, the variable resistor 112 generates voltages Vp and Vm corresponding to the count value CNTa and currents Ip and Im at the connection nodes Np and Nm with the PMOS transistors 110 and 111, respectively. As a result, as will be explained in detail later, the variable resistor 112 operates to cancel the offset of the PMOS transistors 120 and 121. Specifically, the variable resistor 112 cancels the offset of the operational amplifier 10a by changing the connection node of the resistor to which the drain of the NMOS transistor 113 is connected, according to the count value CNTa, so that the voltages IN_P and IN_M match. Therefore, the operational amplifier 10a is an operational amplifier with adjustable offset.

[0023] The NMOS transistor 113 is diode-connected and acts as an active load for a differential pair consisting of PMOS transistors 110 and 111.

[0024] PMOS transistors 120 and 121 form a differential pair, with voltages Vp and Vm applied to their respective gates. NMOS transistors 122 and 123 act as active loads for the differential pair formed by PMOS transistors 120 and 121.

[0025] Furthermore, NMOS transistors 122 and 123 are active elements that constitute the current mirror circuit.

[0026] Furthermore, the NMOS transistor 130, together with the PMOS transistor 103, constitutes the output stage of the operational amplifier 10a, and the voltage Vout changes depending on the relative magnitudes of the currents flowing through the PMOS transistor 103 and the NMOS transistor 130. In other words, the PMOS transistor 103 and the NMOS transistor 130 function as a voltage divider circuit that outputs a voltage Vout that changes according to their respective on-resistances.

[0027] Capacitor 140 and resistor 141 are phase compensation elements and are connected in series between the drain and gate of NMOS transistor 130. In this embodiment, the operational amplifier 10b has the same configuration as operational amplifier 10a, so its description is omitted.

[0028] The counter 11 in Figure 1 is an 8-bit counter that changes the count value CNTa from 0 to 255 based on the control signal CntlA from the control circuit 12, thereby controlling the variable resistor 112 in the operational amplifier 10a.

[0029] The control circuit 12 outputs control signals CntlA and CntlB based on the comparison results of the comparator 15 (described later), and changes the count values ​​CNTa and CNTb of the counters 11 and 16. The control circuit 12 also outputs signals SelA and SelB to select which of the operational amplifiers 10a and 10b will operate as the amplification circuit, and controls the analog switches 20 to 27.

[0030] Resistors 13 and 14 are components used to adjust the offset of operational amplifier 10b when operational amplifier 10a is selected to operate as an amplification circuit, as shown in Figure 2. The specific circuit used to adjust the offset is as follows: a reference voltage Vref is applied to the non-inverting input of operational amplifier 10b, and the voltage at the connection point of resistors 13 and 14 is applied to the inverting input. Furthermore, the reference voltage Vref is applied to one end of resistor 13, and one end of resistor 14 is connected to the other end. The other end of resistor 14 is connected to the output of operational amplifier 10b. Comparator 15 outputs a comparison result Scmp, which compares the output voltage Voa of operational amplifier 10b with the reference voltage Vref. The reference voltage Vref corresponds to a "predetermined voltage".

[0031] In this case, if we let the voltage at the non-inverting input of op-amp 10b be voltage Vinp and the voltage at the inverting input be voltage Vinm, then the following equation holds. Note that the resistance value of resistor 13 is R1 and the resistance value of resistor 14 is R2. Vinp=Vref...Equation (1) Vinm=(Voa-Vref)×(R1 / (R1+R2))+Vref...Equation (2)

[0032] Furthermore, since the operational amplifier 10b operates so that the voltages Vinp and Vinm are equal, using equations (1) and (2), the following equation holds true. Vref=(Voa-Vref)×(R1 / (R1+R2))+Vref...Equation (3)

[0033] Therefore, theoretically, voltage Voa is equal to voltage Vref.

[0034] However, in the differential pair consisting of PMOS transistors 110 and 111 or PMOS transistors 120 and 121 shown in Figure 3, an offset voltage generally occurs because their threshold voltages are different. Therefore, contrary to the theoretical formula, the voltage Voa is not equal to the voltage Vref. The same applies to the operational amplifier 10a.

[0035] Therefore, the control circuit 12 adjusts the offset of the operational amplifiers 10a and 10b by adjusting the count values ​​CNTa and CNTb. Operational amplifier 10a corresponds to the "first operational amplifier," operational amplifier 10b corresponds to the "second operational amplifier," and comparator 15 corresponds to the "comparison circuit." In addition, the count values ​​CNTa and CNTb correspond to the "adjustment data," and variable resistor 112 corresponds to the "adjustment circuit."

[0036] ===Operation of Signal Processing Circuit 1=== Figure 4 is a diagram illustrating an example flowchart explaining the operation of the signal processing circuit 1. Figure 5 is a diagram illustrating an example timing chart when offset adjustment is completed within period T. In Figure 4, the control circuit 12 outputs an "H" level signal SelA and an "L" level signal SelB so that op-amp 10a is selected to operate as an amplification circuit and op-amp 10b is selected as the target of offset adjustment. The count value CNTb is also assumed to be already set to an initial value (for example, 128, which is the midpoint between 0 and 255). When op-amps 10a and 10b are selected as targets for offset adjustment, the offset adjustment operation is triggered at the beginning of period T (for example, 80 msec). Period T corresponds to a "predetermined period".

[0037] The control circuit 12 triggers the start of period T to execute a process that sets the count value CNTb to a predetermined count value in a first state, to a second state where the count value CNTb is one less than the predetermined count value, and to a third state where the count value CNTb is the predetermined count value (step S11). For example, if the count value CNTb is currently set to 128, the count value CNTb will be 128 in the first and third states, and to 127 in the second state. The start of step S11 corresponds to time t0 in Figure 5. The predetermined count value corresponds to the "first value," and the count value obtained by one less than the predetermined count value corresponds to the "second value."

[0038] The control circuit 12 executes the processes for each of the first to third states, and then stores each of the comparison results of the comparator 15 after a predetermined waiting time Ta has elapsed in a memory circuit (not shown) (that is, for each of the first to third states, the three comparison results obtained after the waiting time Ta has elapsed are stored together in the memory circuit) (step S12). Note that the waiting time Ta corresponds to the "set time". Furthermore, by storing the comparison results of the comparator 15 after the waiting time Ta has elapsed, the operation of the operational amplifier 10b can be stabilized while the comparison results are stored.

[0039] The control circuit 12 checks the comparison results in the first to third states (steps S13, S15, S19, S21). Specifically, if all the comparison results in the first to third states are at the "H" level (step S13), the control circuit 12 counts down the count value CNTb by one because the voltage Vout is higher than the reference voltage Vref (step S14). That is, the count value CNTb decreases to 127. As the count value CNTb decreases in this way, the voltage Vout decreases. Then, the process returns to step S11.

[0040] Furthermore, if the comparison results in the first and third states are at the "H" level and the comparison result in the second state is at the "L" level (step S15), the control circuit 12 determines that the offset adjustment was performed correctly (i.e., the offset adjustment is OK) (step S16). Then, the control circuit 12 outputs a signal SelA at the "L" level and a signal SelB at the "H" level, and switches the connection of the operational amplifiers 10a and 10b (step S17).

[0041] Specifically, in step S17, the signal processing circuit 1 changes from a state where op-amp 10a is selected to operate as an amplification circuit and op-amp 10b is selected as the target of offset adjustment, to a state where op-amp 10a is selected as the target of offset adjustment and op-amp 10b is selected to operate as an amplification circuit. After that, it waits for period T to elapse (step S18). Then it returns to step S11. Note that the start of step S17 corresponds to times t1 and t3 in Figure 5.

[0042] Thus, based on the comparison results, once the offset adjustment of op-amp 10b is complete, the control circuit 12 causes op-amp 10a to process the input signal Vin to op-amp 10b, and then performs the offset adjustment of op-amp 10a based on the signal with period T. This operation corresponds to the operation at time t2 in Figure 5.

[0043] Conversely, once the offset adjustment of op-amp 10a is complete based on the comparison result, the control circuit 12 causes op-amp 10b to process the input signal Vin to the other op-amp 10a, and then performs the offset adjustment of op-amp 10b based on the signal with period T. This operation corresponds to the operation at time t4 in Figure 5.

[0044] On the other hand, if the comparison results in the first to third states are all at the "L" level (step S19), the control circuit 12 increments the count value CNTb by one because the voltage Vout is lower than the reference voltage Vref (step S20). That is, the count value CNTb increases to 129. In this way, as the count value CNTb increases, the voltage Vout rises. Then, the process returns to step S11.

[0045] Furthermore, if the control circuit 12 determines that the comparison results of the first and third states are not the same, it determines that the comparison result is inappropriate (step S21). Here, "inappropriate comparison result" means that the comparison results of the comparator 15 are different despite the count value CNTb being the same. On the other hand, in this embodiment, "appropriate comparison result" means that the comparison results of the comparator 15 are the same when the count value CNTb is the same.

[0046] Generally, when the variable resistor 112 is changed based on the count value CNTb, it takes a certain amount of time for the output of the operational amplifier 10b to stabilize. If the count value CNTb is changed by only one count, the variable resistor 112 is changed, and the comparison result of the comparator 15 is immediately obtained, the comparison result may be obtained before the output of the operational amplifier 10b stabilizes, and the comparison result may differ from the actual logic level.

[0047] Therefore, while maintaining the count value CNTb (step S22), the waiting time Ta after changing from the first to the third state is increased (i.e., the waiting time Ta is made longer than the initial value) (step S23). Then, the process returns to step S11. By operating in this manner, in this embodiment, comparison results are obtained with the same count value CNTb in the first and third states, and by comparing the comparison results in each case, it is possible to confirm whether the comparison results obtained are those after the output of the operational amplifier 10b has stabilized.

[0048] In this manner, if the control circuit 12 determines that the comparison result of the first state and the comparison result of the third state are the same, it updates the count value CNTb and continues processing until it determines that the comparison result of either the first or third state is not the same as the comparison result of the second state.

[0049] On the other hand, as shown in Figure 6, if the offset adjustment of op-amp 10b is not completed during period T (time t11), the offset adjustment continues until it is completed (times t10-t12). Once the offset adjustment of op-amp 10b is completed, op-amp 10a stops its normal operation as an amplification circuit, and op-amp 10b starts its normal operation as an amplification circuit (time t12).

[0050] Then, after period T has elapsed, op-amp 10a starts offset adjustment, and op-amp 10b continues normal operation as an amplification circuit until op-amp 10a's offset adjustment is completed (time t13).

[0051] In this way, the operation of the signal processing circuit 1 makes it possible to provide a signal processing circuit that can process input signals with high accuracy.

[0052] ===Literal translation=== In this embodiment, a change of one count value CNTb causes the connection node between the variable resistor 112 and the drain of the NMOS transistor 113 to shift by one. However, the control circuit 12 may change the count value CNTb by two in order to shift the connection node by one.

[0053] ===Summary=== The signal processing circuit 1 of this embodiment has been described above. The signal processing circuit 1 comprises operational amplifiers 10a and 10b, a comparator 15, and a control circuit 12. The control circuit 12, triggered by period T, performs offset adjustment of the operational amplifier selected as the target of offset adjustment (for example, operational amplifier 10b) based on the signal Scmp. For example, it stops processing the input signal of operational amplifier 10a while allowing operational amplifier 10b to process the input signal, and then performs offset adjustment of operational amplifier 10a based on the signal of period T. The control circuit 12 also performs operation with operational amplifiers 10a and 10b swapped. This makes it possible to provide a signal processing circuit that can process input signals with high accuracy.

[0054] Furthermore, the signal processing circuit 1 includes a variable resistor 112 that adjusts the offset of the operational amplifier (e.g., operational amplifier 10b) selected as the target for offset adjustment based on a count value (e.g., count value CNTb). The control circuit 12 stores the comparison results of the operational amplifiers offset-adjusted by the comparator 15 as first and third states with a count value CNTb of, for example, 128, in the memory circuit, and after executing the process of storing the comparison results of the operational amplifiers offset-adjusted by the comparator 15 as a second state with a count value CNTb of, for example, 127, in the memory circuit, it determines whether the comparison results (signal Scmp) of the first and third states are the same. This makes it possible to determine whether the waiting time Ta from setting to a predetermined state until obtaining the comparison result is sufficiently long.

[0055] Furthermore, if the control circuit 12 determines that the comparison results of the first and second states are not the same, it increases the waiting time Ta from its initial value and executes step S11 in Figure 4. This ensures that the waiting time Ta is sufficiently long, allowing the operation of the operational amplifiers 10a and 10b to stabilize before the comparison results are obtained, thus enabling correct offset adjustment.

[0056] Furthermore, if the control circuit 12 determines that the comparison results of the first and third states are the same, it updates the count value (e.g., count value CNTb) and repeats the offset adjustment until it determines that the comparison result of either the first or third state is not the same as the comparison result of the second state. This allows the offset adjustment to be performed while taking into account the temperature characteristics of the offset voltage.

[0057] Furthermore, the signal processing circuit 1 includes an amplification circuit using an operational amplifier 10a (or operational amplifier 10b), a variable resistor 112, a comparator 15, and a control circuit 12. The control circuit 12 stores the comparison results of the operational amplifiers, offset by the comparator 15 as first and third states with a count value CNTb of, for example, 128, in a memory circuit, and then stores the comparison results of the operational amplifiers, offset by the comparator 15 as a second state with a count value CNTb of, for example, 127, in the memory circuit. After this process, it determines whether the comparison results (signal Scmp) of the first and third states are the same. This makes it possible to determine whether the waiting time Ta from setting to a predetermined state until obtaining the comparison result is sufficiently long.

[0058] Furthermore, if the control circuit 12 determines that the comparison results of the first and second states are not the same, it increases the waiting time Ta from its initial value and executes step S11 in Figure 4. This ensures that the waiting time Ta is sufficiently long, allowing the operation of the operational amplifiers 10a and 10b to stabilize before the comparison results are obtained, thus enabling correct offset adjustment.

[0059] Furthermore, if the control circuit 12 determines that the comparison results of the first and third states are the same, it updates the count value (e.g., count value CNTb) and repeats the offset adjustment until it determines that the comparison result of either the first or third state is not the same as the comparison result of the second state. This allows the offset adjustment to be performed while taking into account the temperature characteristics of the offset voltage.

[0060] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0061] 1. Signal Processing Circuit 10a, 10b operational amplifiers 11,16 counter 12 Control circuits 13, 14, 141, 150~154 Resistors 15 Comparator 20-27 Analog Switches 100-103, 110, 111, 120, 121 PMOS transistors 112 Variable resistor 113, 122, 123, 130 NMOS transistors 140 Capacitors

Claims

1. A first operational amplifier with adjustable offset, A second operational amplifier with adjustable offset, An amplification circuit is provided that uses an operational amplifier selected from the first and second operational amplifiers and outputs an output voltage corresponding to the input voltage, A comparison circuit that outputs a comparison result obtained by comparing the output voltage with a predetermined voltage, Based on the comparison results, once the offset adjustment of the selected operational amplifier is completed, the control circuit stops processing the input signal of the other operational amplifier while allowing the first operational amplifier to process the input signal, and performs the offset adjustment of the other operational amplifier based on a signal of a predetermined period. Equipped with, The aforementioned control circuit is Based on the comparison results, once the offset adjustment of the selected other operational amplifier is completed, the processing of the input signal of the first operational amplifier is stopped, while the other operational amplifier is allowed to process the input signal, and further, the offset adjustment of the first operational amplifier is performed based on the signal of the predetermined period. Signal processing circuit.

2. A signal processing circuit according to claim 1, It includes an adjustment circuit that adjusts the offset of the selected operational amplifier based on the values ​​of the adjustment data, The aforementioned control circuit is After performing the process of storing the comparison result of the operational amplifier offset-adjusted by the comparison circuit as a first state with the value of the adjustment data set to a first value, storing the comparison result of the operational amplifier offset-adjusted by the comparison circuit as a second state with the value set to a second value, and storing the comparison result of the operational amplifier offset-adjusted by the comparison circuit as a third state with the value set to a first value, it is determined whether the comparison result of the first state and the comparison result of the third state are the same. Signal processing circuit.

3. The signal processing circuit according to claim 2, The aforementioned control circuit is If it is determined that the comparison result of the first state and the comparison result of the third state are not the same, the setting time for setting each of the first state, second state, and third state is made longer than the initial value, and the process is executed. Signal processing circuit.

4. The signal processing circuit according to claim 3, The aforementioned control circuit is If it is determined that the comparison result of the first state and the comparison result of the third state are the same, the first value and the second value are updated and the process is executed until it is determined that the comparison result of either the first or third state is not the same as the comparison result of the second state. Signal processing circuit.

5. An amplification circuit that uses an operational amplifier to output an output voltage corresponding to the input voltage, An adjustment circuit that adjusts the offset of the operational amplifier based on the value of the adjustment data, A comparison circuit that outputs a comparison result obtained by comparing the output voltage with a predetermined voltage, A control circuit that, after performing the process of storing the comparison result of the operational amplifier offset-adjusted by the comparison circuit as a first state with the value of the adjustment data set to a first value, storing the comparison result of the operational amplifier offset-adjusted by the comparison circuit as a second state with the value set to a second value, and storing the comparison result of the operational amplifier offset-adjusted by the comparison circuit as a third state with the value set to a first value, determines whether the comparison result of the first state and the comparison result of the third state are the same. A signal processing circuit equipped with the following features.

6. A signal processing circuit according to claim 5, The aforementioned control circuit is If it is determined that the comparison result of the first state and the comparison result of the third state are not the same, the setting time for setting each of the first state, second state, and third state is made longer than the initial value, and the process is executed. Signal processing circuit.

7. A signal processing circuit according to claim 6, The aforementioned control circuit is If it is determined that the comparison result of the first state and the comparison result of the third state are the same, the first value and the second value are updated and the process is executed until it is determined that the comparison result of either the first or third state is not the same as the comparison result of the second state. Signal processing circuit.

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