Conformal titanium nitride-based thin film and method for forming the same

Abstract

This invention provides a conformal and smooth titanium nitride-based thin film and a method for forming the same. [Solution] In one embodiment, a method for forming a thin film comprising one or both TiSiN and TiAlN comprises exposing a semiconductor substrate to one or more deposition processes under a reaction chamber pressure of more than 1 Torr, wherein the multiple deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both a silicon (Si) precursor or an aluminum (Al) precursor.

Description

[Technical Field]

[0001] The disclosed technology relates in general to the formation of titanium nitride-based thin films, and more specifically to conformal and smooth titanium nitride-based thin films. [Background technology]

[0002] Titanium nitride (TiN) thin films are widely used in the fabrication of various structures within integrated circuits (ICs). For example, TiN has been used in diffusion barriers, various electrodes, and metallization structures. This widespread use of TiN in IC manufacturing can be attributed to its structural, thermal, and electrical properties. As IC structures shrink in size, TiN is formed on characteristic shapes with increasingly smaller sizes and complex topologies. For example, when technology nodes exceed the 10 nm node, thin films, such as diffusion barriers, are needed that can conformally line trenches and vias with high aspect ratios at small sizes, such as a few nanometers. While the IC industry has used techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) to form TiN diffusion barriers, their use may eventually be limited as the need for conformability of TiN films deposited on smaller trenches and vias increases. On the other hand, while atomic layer deposition (ALD) has been demonstrated for conformal TiN films, some electrical properties (e.g., conductivity) and physical properties (e.g., surface roughness) of the films may be inferior to those of TiN films formed using other methods such as physical vapor deposition (PVD). Therefore, in IC manufacturing, there is a need for a film deposition method to form TiN-based films that have superior properties, including barrier properties, surface smoothness, and step coverage, compared to TiM films formed by, for example, PVD and CVD. [Overview of the Initiative] [Means for solving the problem]

[0003] In one embodiment, a method for forming a diffusion barrier includes forming a thin film containing one or both TiSiN and TiAlN on a semiconductor substrate in a reaction chamber. The formation of the thin film includes exposing the semiconductor substrate to multiple vapor deposition cycles under a pressure in the reaction chamber of more than 1 Torre. In this case, the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor at different frequencies. The semiconductor substrate has a surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2.

[0004] In another embodiment, a method for forming a diffusion barrier includes providing a semiconductor substrate on which a plurality of trenches or vias are formed thereon, wherein the trenches or vias have a dielectric sidewall and an aspect ratio greater than 5. The method further includes lining the surface of the trenches or vias with a diffusion barrier layer comprising at least partially amorphous TiSiN or TiAlN, or both, by exposing the semiconductor substrate to a plurality of vapor deposition cycles, wherein the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to a silicon (Si) precursor or an aluminum (Al) precursor, or both, at different frequencies.

[0005] In another embodiment, a method for forming a thin film comprising one or both TiSiN and TiAlN includes exposing a semiconductor substrate to multiple vapor deposition cycles under a pressure in a reaction chamber exceeding 5 Torr. In this case, the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both a silicon (Si) precursor or an aluminum (Al) precursor at different frequencies.

[0006] In another embodiment, the semiconductor structure includes a semiconductor substrate in which a plurality of pores are formed. In this case, the pores have a dielectric sidewall and an aspect ratio greater than 5. The semiconductor structure additionally has a diffusion barrier layer comprising one or both of TiSiN and TiAlN conformally lining the surface of the pores. The diffusion barrier layer is at least partially amorphous.

[0007] Embodiments of the present disclosure will be described using non-limiting embodiments with reference to the attached drawings. [Brief explanation of the drawing]

[0008] [Figure 1] Figures 1A to 1D schematically show the different nuclei and growth mechanisms of thin films under different growth modes. [Figure 2] Figure 2 is a cross-sectional transmission electron microscope image of a TiN layer grown by atomic layer deposition on a silicon substrate with topography. [Figure 3] Figure 3 schematically shows a cross-sectional view of a semiconductor structure having a thin film containing TiSiN or TiAlN formed on a semiconductor substrate according to an embodiment. [Figure 4] Figure 4 schematically shows a cross-sectional view of a via lined with a thin film containing TiSiN or TiAlN having different thicknesses in different parts of the via. [Figure 5A] Figure 5A is a flowchart illustrating a method for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 5B] Figure 5B is a flow chart showing a film deposition cycle for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 5C] Figure 5C shows a film deposition cycle for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 5D] Figure 5D shows a sequence of deposition cycles for forming a thin film containing TiSiN or TiAlN according to an embodiment. [Figure 6A]Figure 6A shows a cross-sectional transmission electron microscope image and the diffraction pattern of the corresponding selected region obtained from a thin film containing TiSiN lining the top of a high aspect ratio via according to an embodiment. [Figure 6B] Figure 6B shows a cross-sectional transmission electron microscope image and the diffraction pattern of the corresponding selected region obtained from a thin film containing TiSiN lining the middle portion of the high aspect ratio via shown in Figure 6A, according to an embodiment. [Figure 6C] Figure 6C shows a cross-sectional transmission electron microscope image and the diffraction pattern of the corresponding selected region obtained from a thin film containing TiSiN lining the lower part of the high aspect ratio vias shown in Figures 6A and 6B, according to an embodiment. [Figure 7A] Figure 7A shows the diffraction pattern of a selected region obtained from a substantially amorphous thin film containing TiSiN lining with a high aspect ratio, according to an embodiment. [Figure 7B] Figure 7B shows the diffraction pattern of a selected region obtained from a partially crystalline thin film containing TiSiN lining with a high aspect ratio, according to an embodiment. [Figure 7C] Figure 7C shows the diffraction pattern of a selected region obtained from a substantially crystalline thin film containing TiSiN lining with a high aspect ratio, according to an embodiment. [Figure 8] Figure 8 shows the microangle incident X-ray diffraction spectrum obtained from a substantially amorphous thin film containing TiSiN according to an embodiment. [Figure 9] Figure 9 is a graph of the resistivity experimentally measured as a function of silicon content in a thin film containing TiSiN according to the embodiment. [Figure 10A] Figure 10A is a cross-sectional transmission electron microscope image obtained from a substantially homogeneous thin film containing TiSiN according to an embodiment. [Figure 10B] Figure 10B is a cross-sectional transmission electron microscope image obtained from a nanolaminate thin film containing alternating regions or layers of SiN and regions or layers of TiN according to an embodiment. [Figure 11]Figure 11 schematically shows a partial cross-sectional view of a semiconductor device having contact lines or metal lines formed by filling holes lined with a thin film containing TiSiN or TiAlN with metal, according to an embodiment. [Modes for carrying out the invention]

[0009] As described above, there is a need in the integrated circuit (IC) industry for conformal thin films with excellent physical barrier properties, such as TiN-based thin films and methods for forming such thin films. To address these and other needs, thin films comprising TiSiN and / or TiAlN, which may be at least partially amorphous, and a cyclic vapor deposition method, which may be atomic layer deposition (ALD), for forming such thin films are disclosed herein. These thin films exhibit the conformability of films deposited by ALD, while also possessing barrier properties that are superior to or equivalent to those of TiN films formed by existing physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods. Thin films comprising TiSiN and / or TiAlN can be used as conformal diffusion barriers. These thin films are formed by methods adapted to substrates with relatively large areas due to the presence of topography, which are dielectric pores such as vias and trenches, which may be vias and trenches with a high aspect ratio (e.g., >1), in which case the exposed surface area has an area density at least twice that of a flat substrate surface area. This method involves exposing a semiconductor substrate to one or more vapor deposition cycles at relatively high pressures (e.g., >1 Torr). These vapor deposition cycles include exposure to a titanium (Ti) precursor, a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor. Thin films containing TiSiN and / or TiAlN deposited by the methods disclosed herein are advantageous in that they have excellent diffusion barrier properties, as well as excellent conformability, high step coverage, and low surface roughness. These and other properties of the thin films can be advantageously tuned by controlling the morphology of the thin film at the nanoscale, thereby changing the degree of crystallinity and / or homogeneity by adjusting the process conditions.

[0010] As described herein, compounds referred to by their constituent elements without specific stoichiometric ratios are understood to encompass all possible non-zero concentrations of each element unless explicitly limited. For example, titanium nitride (TiN) is given by the general formula Ti xIt is understood to include all possible stoichiometric and non-stoichiometric compositions of titanium nitride that can be represented by N, x > 0, including TiN, Ti3N4, Ti4N3, Ti6N5, Ti2N, and TiN2, as well as other non-stoichiometric compositions of Ti and N. Similarly, silicon nitride (SiN) is understood to include all possible stoichiometric and non-stoichiometric compositions of silicon nitride that can be represented by the general formula Si y N, y > 0, including Si3N4. Aluminum nitride (AlN) is understood to include all possible stoichiometric and non-stoichiometric compositions of aluminum nitride that can be represented by the general formula Al y N, y > 0, including AlN. Titanium silicon nitride (TiSiN) is understood to include all possible stoichiometric and non-stoichiometric compositions of titanium silicon nitride that can be represented by the general formula Ti x Si y N, x > 0 and y > 0. Titanium aluminum nitride (TiAlN) is understood to include all possible stoichiometric and non-stoichiometric compositions of titanium aluminum nitride that can be represented by the general formula Ti x Al y N, x > 0 and y > 0.

[0011] As described above, titanium nitride-based thin films play an important role in the manufacture of integrated circuits (ICs). In the IC industry, techniques such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have been used to deposit TiN. However, there is an increasing need for a film-forming method to form a ternary or quaternary alloy containing Ti, N, and one or more other metals, including a TiN-based film, Si, and / or Al, with high conformality without significantly degrading the electrical and / or physical properties.

[0012] In addition, plasma-enhanced processes such as plasma-enhanced atomic layer deposition (PE-ALD) can be effective in forming conformal films on surfaces with relatively low aspect ratios, but those processes may not be effective in depositing films inside vias and cavities having high aspect ratios. Without being bound by any theory, one possible reason for this is thought to be that in a given situation, the plasma may not reach deep portions of high-aspect-ratio vias. Under such circumstances, different portions of the via may be exposed to different amounts of plasma, which could result in undesirable structural effects arising from non-uniform film deposition. For example, near the opening of the via, a thicker film will be deposited compared to deeper portions (often referred to as cushing or keyhole formation). For these reasons, thermal vapor deposition such as thermal ALD can be more advantageous, because those thermal processes do not depend on the ability of the plasma to reach each portion of the surface on which the film is deposited.

[0013] However, while thermal ALD technology can be suitable for forming relatively conformal TiN-based thin films on topography, particularly on topography with relatively high aspect ratios (e.g., greater than 1:1), the inventors recognized that TiN-based thin films formed by thermal ALD may be inferior to those formed by PVD or CVD in some respects, such as film roughness and electrical resistivity. In this regard, the inventors found that some electrical and / or physical properties of ALD-grown TiN-based films may be adversely affected by the growth mode. In particular, the inventors found that while it is sometimes desirable to grow TiN-based films in a two-dimensional layer-by-layer growth mode in ALD, such a layer-by-layer growth mode may not be easily achieved under certain circumstances. The inventors further found that growing TiN-based thin films by ALD in a layer-by-layer growth mode presents specific challenges in IC manufacturing when forming TiN-based thin films on non-metallic surfaces, particularly on insulating surfaces such as oxide and nitride surfaces or doped and undoped silicon surfaces. Not bound by any theory, the inventors recognized that the extent to which TiN-based thin films can grow in a layer-by-layer growth mode may depend on the initial growth mode, which is dependent on the surface type and crystallinity, as disclosed herein with reference to Figures 1A-1D.

[0014] Figure 1A schematically illustrates the nucleation of the TiN-based layer, and Figures 1B-1D show different growth modes of the TiN-based layer on different surfaces. Referring to Figure 1A, once precursor molecules 104 reach the substrate 100, they are physically adsorbed onto the substrate. Some of the adsorbed molecules 104 can diffuse along the surface of the substrate 100 until they reach energetically favorable positions for chemiadsorption. Surface diffusion is governed, in particular, by the substrate temperature, the substrate material, and the kinetic energy of the adsorbed molecules. When the size of the nuclei formed by chemiadsorbed molecules exceeds a predetermined size (sometimes called the "critical size") determined by the trade-off between volume free energy and surface energy, the nuclei become energetically stable and can begin to grow in size. The layer 108 of stable nuclei thus formed continues to grow by incorporating further precursor molecules 104. Subsequent film growth can be classified by different growth modes, as schematically shown in Figures 1B-1D.

[0015] Figure 1B schematically illustrates the three-dimensional island growth mode, sometimes referred to as the Volmer-Weber growth mode, where layer 112 consisting of three-dimensional islands is formed. While not constrained by any theory, the island growth mode can be dominant when the net surface free energy associated with the three-dimensional islands is positive. This indicates that the deposited atoms are more strongly bonded to each other than to the substrate. For example, when a metallic TiN-based layer is deposited on the surface of a given semiconductor and / or insulating material, the energy theory of ALD growth of the TiN-based layer will be understood to support the island growth mode.

[0016] Figure 1C shows a layer-by-layer growth mode, sometimes referred to as the Frank-van der Merwe growth mode, which forms a relatively smooth two-dimensional layer 116. While not constrained by any theory, the layer-by-layer growth mode may be dominant when the deposited atoms bond more strongly to the substrate than to each other, thereby making the stable two-dimensional layer 116 energetically preferable. The layer-by-layer growth mode can persist when the interlayer bonding energy decreases continuously from the first monolayer of the TiN-based layer down to the bulk crystal value.

[0017] Figures 1B and 1C show two different possible growth modes for TiN-based thin films, but under given conditions, an intermediate growth mode between the layer-by-layer growth mode and the three-dimensional growth mode is possible. Figure 1D shows an example of an intermediate growth mode known as the Stranski-Krastanov (SK) growth mode. Although not bound by any theory, the SK growth mode can occur in thin film growth that begins with the layer-by-layer growth mode. If the layer-by-layer growth mode becomes undesirable after the formation of one or more monolayers, the island growth mode begins and becomes dominant over the layer-by-layer growth mode, resulting in a thin film structure 120 in which three-dimensional islands are formed on top of the two-dimensional initial layers. The SK growth mode can occur as a strain relaxation mechanism (strain-induced roughening).

[0018] In addition to the interaction between the deposited material and the substrate, other factors such as substrate temperature, pressure, and deposition rate can significantly influence the nucleation and initial growth processes. This affects the final nanostructure or microstructure of the resulting thin film. For example, deposition at relatively high substrate temperatures and / or slow deposition rates may promote the growth of relatively large grains, while relatively low substrate temperatures and fast deposition rates may favor the growth of smaller grains.

[0019] In IC manufacturing, when TiN-based thin films are grown by ALD on various intended surfaces, dielectric surfaces, and semiconductor surfaces, it has been discovered that the ALD growth can begin in a three-dimensional island growth mode or a SK growth mode. For example, under given conditions, the ALD growth of TiN-based thin films on substrate surfaces containing doped and undoped Si, SiO2, Si3N4, and other high-K or low-K materials can proceed in either an island growth mode or a SK growth mode. The inventors have found that, in part, due to either the island growth mode or the SK growth mode as the initial growth mode, the subsequent growth of the TiN-based layer by ALD often results in undesirable film morphology in various applications of extremely thin conformal diffusion barriers for high aspect ratio structures, as shown in Figure 2.

[0020] Figure 2 is a cross-sectional transmission electron microscope image of a TiN layer grown by thermal ALD on a topography including an insulating (Si3N4) surface. After initial film growth in either the 3D island growth or SK growth mode, ALD growth of TiN is often characterized by the competitive growth of adjacent crystals with different orientations. As a result, under given conditions, V-shaped grains are formed near the nucleation layer, leading to columnar morphology at larger film thicknesses. As shown in Figure 2, the resulting film morphology includes cross-shaped prism heads that result in high surface roughness and columnar boundaries with lower density than the grains. It can be understood that columnar boundaries may have extremely poor diffusion barrier properties compared to the grains themselves and may function as the least-resistance pathway for transporting undesirable contaminants through the TiN layer. Furthermore, due to the columnar morphology, relatively thick TiN layers may need to be deposited to observe sufficient diffusion barrier properties. Therefore, the effective TiN barrier for acceptable overall contact or line conductivity may become too thick, leaving little room for low-resistivity filler materials such as W or Cu.

[0021] The inventors have found that when thin films containing TiSiN and / or TiAlN that are at least partially amorphous are formed on a nonmetallic surface by a thermal cycling vapor deposition process such as thermal ALD, the three-dimensional mode or SK growth mode is substantially suppressed, and the layer-by-layer growth mode can be promoted. Among other reasons, this is thought to be because, when a TiN-based thin film has Si or Al added as an alloying element and / or an amorphous phase present therein, the nuclei can wet the nonmetallic surface at a relatively low contact angle. The resulting thin film covers a relatively large area of ​​the nonmetallic surface, and island formation is reduced. This is because, for example, the growth of the thin film tends to proceed more favorably in a layer-by-layer growth mode on the substrate surface. As mentioned above, TiN-based thin films usually prefer the three-dimensional island mode or SK growth mode on the substrate in ALD. Therefore, unlike TiN layers grown directly by ALD on some nonmetallic surfaces, where columnar growth tends to be dominant as described above, thin films containing at least partially amorphous TiSiN and / or TiAlN formed on nonmetallic surfaces according to the embodiment tend to exhibit a predominant layer-by-layer growth mode, resulting in higher conformability and surface smoothness. Furthermore, the presence of the amorphous phase reduces grain boundaries, suppressing fast diffusion pathways for some elements such as Cu and W. The presence of the amorphous phase, higher conformability, and / or surface smoothness allow for a reduction in the thickness of the diffusion barrier. When formed for lining high aspect ratio vias or trenches, thinner thicknesses allow for relatively larger pores for subsequent processes such as metal filling of vias or trenches for contact via formation and / or reduction of contact resistance.

[0022] Figure 3 shows a schematic cross-sectional view of a semiconductor structure 300 having a thin film 320 containing TiSiN and / or TiAlN, which can be formed using the methods of the various embodiments disclosed herein. The semiconductor thin film structure 300 has a substrate 310, which is, for example, a semiconductor substrate. The substrate 310 includes a non-metallic surface, which is, for example, a dielectric and / or semiconductor surface, and a thin film 320 containing at least partially amorphous TiSiN and / or TiAlN is formed thereon by the methods disclosed herein. The thin film 320 has excellent conformability, step coverage, and low surface roughness, while having excellent diffusion barrier properties. These and other properties of the thin film can be advantageously tuned by controlling the degree of crystallinity and / or homogeneity of the thin film at the nanoscale, and by adjusting the various process conditions disclosed herein.

[0023] Thin films containing TiSiN and / or TiAlN are shown in Figure 3 as being formed on a flat substrate for clarity, but are not limited to this in embodiments. Thin films containing TiSiN and / or TiAlN have particular advantages when formed on substrates with topography, such as substrates having high aspect ratio (e.g., >1) vias and trenches and / or relatively high density characteristic shapes, thereby providing a relatively large surface area exposed to the precursor during cyclic vapor deposition, such as ALD (e.g., more than twice the surface area of ​​a flat substrate).

[0024] One measure of conformality in the concept of high aspect ratio structures is referred herein and industrially to as step coverage. High aspect ratio structures can be, for example, vias, holes, trenches, cavities, or similar structures. As an illustrated example, Figure 4 schematically shows a semiconductor structure 400 formed inside an example high aspect ratio structure 416, thereby illustrating several exemplary metrics for defining and / or measuring the conformality of a thin film formed on a high aspect ratio structure. The illustrated high aspect ratio structure 416 has an inner surface lined with a thin film 412, which is a thin film containing TiSiN and / or TiAlN having different thicknesses in different parts, for example. As described above, a high aspect ratio structure has an aspect ratio, for example, the ratio of the depth or height (H) in the pore region of the high aspect ratio structure 416 divided by the width (W), which is greater than 1. In the illustrated example, the high aspect ratio structure 416 is a via formed through a dielectric layer 408, which is, for example, an interlayer insulating film (ILD) layer formed on a semiconductor material 404. In the illustrated example, the bottom surface of the high aspect ratio structure 416 exposes the semiconductor substrate 404 located below. The thin film 412 can coat different surfaces of the high aspect ratio structure 416 with different thicknesses. As described above, step coverage can be defined as the ratio between the thickness of the thin film in the lower or bottom region of the high aspect ratio structure and the thickness of the thin film in the upper or top region of the high aspect ratio structure. The upper or top region can be a region of the high aspect ratio structure with a relatively shallow depth, for example, 0-10% or 0-25% from the top surface of the hole. The lower or bottom region can be a region of the high aspect ratio structure with a relatively deep depth, for example, 90-100% or 75-100% from the top surface of the hole. In some high aspect ratio structures, step coverage can be defined or measured by the ratio of the thickness of the thin film 412A formed on the bottom surface to the thin film 412C formed on the top or top sidewall surface of the high aspect ratio structure. However, it will be understood that some high aspect ratio structures may not have a clearly defined bottom surface or a bottom surface with a small radius of curvature.In such a structure, step coverage can be more consistently defined or measured by the ratio of the thickness of the thin film 412A formed on the bottom surface to the thickness of the thin film 412C formed on the top or top sidewall surface in a high aspect ratio structure.

[0025] [Cycle vapor deposition of thin films containing TiSiN and / or TiAlN] Figure 5A shows a flow diagram of a method 500 for forming a thin film containing TiSiN and / or TiAlN according to an embodiment. Method 500 includes providing a substrate 510. The substrate can be a flat semiconductor substrate, or, as described above, a semiconductor substrate having surface topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​an unpatterned semiconductor substrate is greater than 2. The surface topography that produces a relatively large surface area can be a plurality of holes such as trenches and vias formed on the substrate, as described above. The holes have dielectric sidewall surfaces and can have an aspect ratio greater than 5.

[0026] Method 500 further comprises forming a thin film that can function as a diffusion barrier, comprising titanium silicon nitride (TiSiN) or titanium aluminum nitride (TiAlN). The thin film is formed by exposing a semiconductor substrate to multiple vapor deposition cycles under a pressure of more than 1 Torre in a reaction chamber. In this case, the vapor deposition cycles include exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

[0027] As described above and throughout the specification, it will be understood that semiconductor substrates on which a thin film, for example a diffusion barrier layer containing TiSiN and / or TiAlN is formed can be implemented as a variety of substrates. These include, but are not limited to, doped semiconductor substrates, which include alloys formed from group IV elemental materials (e.g., Si, Ge, C, or Sn) or group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.); group III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or alloys formed from group III-V materials; and group II-VI semiconductor materials (e.g., CdSe, CdS, ZnSe, etc.) or alloys formed from group II-VI materials.

[0028] According to a given embodiment, the substrate can be implemented as having a semiconductor on an insulator, such as a silicon-on-insulator (SOI) substrate. An SOI substrate typically includes a silicon-insulator-silicon structure, in which the various structures described above are insulated from the support substrate using an insulating layer such as an embedded SiO2 layer (BOX). Furthermore, it will be understood that the various structures described above can be formed at least partially on an epitaxial layer formed in or near the surface region.

[0029] Referring further to Figure 5A, it will be understood that Method 500 may be performed on a substrate processed by a front-end line and may include a variety of devices such as transistors. Furthermore, the semiconductor substrate may include one or more diverse structures on which Method 500 can be performed, such as pre-formed diffusion regions, insulating regions, electrodes, and metallized structures such as contacts and metal lines. Thus, a diffusion barrier containing TiSiN and / or TiAlN can be formed on a variety of topographic structures including vias, cavities, holes, or trenches. Surfaces on which a diffusion barrier containing TiSiN and / or TiAlN can be formed according to the embodiment include, for example, a metallic surface which is the surface of a metallized structure; a semiconductor surface which is, for example, a doped or undoped Si surface; and / or a dielectric surface which is an interlayer dielectric (ILD) surface, a mask or hard mask surface, or a gate dielectric surface.

[0030] According to a given embodiment, when formed as a diffusion barrier, a thin film containing TiSiN and / or TiAlN can be interposed between a dielectric layer, such as an interlayer insulating film (e.g., 408 in Figure 4), and a metallized structure formed by filling vias or trenches (e.g., 416 in Figure 4), and / or between a semiconductor substrate 404 and a metallized structure formed by filling vias or trenches. Thereafter, it functions as a diffusion barrier between them, among other functions such as electrical contacts. In these embodiments, the dielectric material can be any dielectric material used in integrated circuit manufacturing, such as silicon oxide, silicon nitride, high dielectric constant dielectric, or low dielectric constant dielectric. The metallized structure may include, for example, metallized lines, contact structures, or other conductive structures made of metal or metallic material for electrically connecting the underlying semiconductor material 404, which is a diffusion region, to other parts of the integrated circuit device being manufactured. The metallized structure can be formed from any suitable metal or metallic material, including, for example, metals containing Al, Cu, Ni, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides containing TiN, TaN, WN, and TaCN; conductive metal silide containing tantalum silide, tungsten silide, nickel silide, cobalt silide, and titanium silide; and conductive metal oxides containing RuO2, etc.

[0031] Referring further to Figure 5A, for example, a method 500 for forming a thin film that is a diffusion barrier layer further includes forming a thin film containing TiSiN and / or TiAlN by exposing a semiconductor substrate in a reaction chamber to multiple vapor deposition cycles which can be atomic layer deposition (ALD) cycles. These vapor deposition cycles include one or more exposures to a titanium (Ti) precursor, one or more exposures to a nitrogen (N) precursor, and one or more exposures to either a silicon (Si) precursor or an aluminum (Al) precursor. At least one of the vapor deposition cycles can be carried out under a pressure in the reaction chamber greater than about 1 Torrell.

[0032] As described above and throughout the specification, the reaction chamber means any reaction chamber including a single-wafer processing reaction chamber or a batch-wafer processing reaction chamber appropriately configured for cyclic vapor deposition, which may be, for example, thermal cyclic vapor deposition or atomic layer deposition (ALD). In a thermal cyclic vapor deposition or ALD reaction chamber, the substrate can be placed on a suitable base such as a susceptor or carrier boat. The substrate can be heated directly by heat conduction from a heated susceptor, or indirectly by radiation from an irradiation source such as a lamp or by convection from a heated chamber wall.

[0033] Generally, in cyclic vapor deposition (ALD) processes, reactants, or precursors, such as oxidation and reduction reactants, are alternately introduced into a reaction chamber containing a substrate. The introduction of one or more reactants or precursors can be performed sequentially, alternating with purging and / or pumping steps to remove excess reactants or precursors from the reaction chamber. The reactants can be introduced into the reaction chamber under predetermined conditions for a suitable period of time, such that the surface on which the diffusion barrier is deposited is exposed to the reactants. This allows the substrate surface to be saturated, at least partially, with the precursors or reactants and / or their reaction products. Excess or residual precursors or reactants can then be purged and / or pumped out of the reaction chamber. The pumping step can be performed by a suitable vacuum pumping step, and the purging step can be performed by introducing an unreactive or inert gas, such as nitrogen or a noble gas, into the reaction chamber. Other techniques also exist to prevent reactants that react with each other from mixing in the gas phase.

[0034] Figure 5B is a flow diagram illustrating a method for forming a diffusion barrier containing TiSiN and / or TiAlN according to an embodiment, and Figures 5C and 5D are block diagrams. Figure 5C shows a deposition phase including exposure to a precursor and a cycle including exposure to the deposition phase. Figure 5D shows a sequence of cyclic deposition phases as part of multiple cycles. Referring to Figures 5B-5D, in various embodiments, exposing a semiconductor substrate to one or more vapor deposition cycles which may constitute an ALD cycle 520 (Figure 5A) includes exposing the substrate to one or more first vapor deposition phases ("first deposition phases") 525. In this case, at least one first deposition phase includes exposure to a Ti precursor and exposure to an N precursor. Exposing a semiconductor substrate to one or more vapor deposition cycles that may constitute an ALD cycle 520 (Figure 5A) further includes exposing the substrate to one or more second vapor deposition phases ("second deposition phases") 530, in which case at least one second deposition phase includes exposure to a Si and / or Al precursor, or a combination of exposure to a Si and / or Al precursor and further exposure to an N precursor. One or more first deposition phases and one or more second deposition phases can be combined to form a single cycle, which can be repeated sequentially multiple times or for multiple cycles. Different cycles may have the same or different numbers of first and second deposition phases. By combining exposure of the substrate to one or more first deposition phases 525 and exposure of the substrate to one or more second deposition phases 530, a diffusion barrier layer containing a layer or region of TiSiN and / or TiAlN is obtained. Each of exposure of the substrate to one or more first deposition phases 525 and exposure of the substrate to one or more second deposition phases 530 may sequentially include exposure of individual precursors one or more times, such as in a pulsed manner as described later.

[0035] Referring further to Figures 5B-5D, in various embodiments, exposing the substrate to each of one or more first deposition phases 525 may include one or more exposures of the substrate to a Ti precursor and one or more exposures to an N precursor. Each exposure to the Ti precursor is carried out such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the Ti precursor. This allows the surface to be almost entirely or partially saturated with the Ti precursor. After the substrate has been exposed to the Ti precursor, any excess or residual Ti precursor, or any reaction products that did not remain on the substrate surface due to physicoadsorption or chemiadsorption, may be removed from the substrate surface by pumping or purging the process chamber. Similarly, each exposure to the N precursor is carried out so that the surface of the substrate on which the diffusion barrier is deposited is exposed to the N precursor. This allows the surface to be almost entirely or partially saturated with the N precursor. After the substrate is exposed to the N precursor, any excess or residual N precursor, or any reaction products that did not remain on the substrate surface due to physicoadsorption or chemiadsorption, can be removed from the substrate surface by pumping or purging the process chamber. By exposing the substrate to one or more first deposition phases, each including one or more exposures to a Ti precursor and one or more exposures to an N precursor, one or more monolayers or regions substantially formed from deposited TiN can be locally formed.

[0036] In some embodiments, exposure to a Ti precursor in a given first deposition phase can be performed multiple times consecutively. Similarly, exposure to an N precursor in a given first deposition phase can be performed multiple times consecutively. An advantage is that, under given circumstances, more than one exposure of the substrate to the Ti and / or N precursors can result in a higher level of surface saturation, for example, when a large steric hindrance effect is present, by exposing more reaction sites for the adsorption or reaction of individual precursors.

[0037] Referring further to Figures 5B-5D, in various embodiments, exposing the substrate to one or more second deposition phases 530 includes one or more exposures of the substrate to a Si precursor or an Al precursor. Each exposure to the Si and / or Al precursor is carried out such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the Si and / or Al precursor. This allows the surface to be almost entirely or partially saturated with the Si and / or Al precursor. After the substrate has been exposed to the Si and / or Al precursor, any excess or residual Si and / or Al precursor, or any reaction products that did not remain on the substrate surface by physical or chemical adsorption, can be removed from the substrate surface by pumping or purging the process chamber. By exposing the substrate to one or more second deposition phases, each including one or more exposures to the Si and / or Al precursor, one or more monolayers or regions substantially formed from the deposited Si or Al can be locally formed.

[0038] In some embodiments, exposure to the Si and / or Al precursor in a given second deposition phase can be carried out multiple times consecutively. An advantage is that, under given circumstances, more than one exposure of the substrate to the Si and / or Al precursor can result in a higher level of surface saturation, for example, when a large steric hindrance effect is present, by exposing more reaction sites for the adsorption or reaction of individual precursors.

[0039] Referring further to Figures 5B-5D, in some embodiments, exposing the substrate to each of one or more second deposition phases 530 includes one or more exposures of the substrate to a Si and / or Al precursor, and one or more exposures of the substrate to an N precursor. The N precursor may be the same as or different from the N precursor of the first deposition phase. Each exposure to the Si and / or Al precursor is carried out such that the surface of the substrate on which the diffusion barrier is deposited is exposed to the Si and / or Al precursor. This allows the surface to be saturated with the Si and / or Al precursor almost entirely or partially. After the substrate has been exposed to the Si and / or Al precursor, any excess or residual Si and / or Al precursor, or any reaction products that did not remain on the substrate surface by physical or chemical adsorption, may be removed from the substrate surface by pumping or purging the process chamber. Each exposure to the N precursor is carried out so that the surface of the substrate on which the diffusion barrier is deposited is exposed to the N precursor. This allows the surface to be almost entirely or partially saturated with the N precursor. After the substrate is exposed to the N precursor, any excess or residual N precursor, or any reaction products that did not remain on the substrate surface due to physical or chemical adsorption, can be removed from the substrate surface by pumping or purging the process chamber. By exposing the substrate to one or more second deposition phases, each including one or more exposures to a Si precursor and one or more exposures to an N precursor, one or more monolayers or regions substantially formed from deposited SiN or AlN can be locally formed.

[0040] In some embodiments, exposure to a Si precursor in a given second deposition phase can be performed multiple times consecutively. Similarly, further exposure to an N precursor can be performed multiple times consecutively. An advantage is that, under given circumstances, more than one exposure of the substrate to Si and / or Al and / or N precursors, as described above, can lead to a higher level of surface saturation, for example, when a large steric hindrance effect is present, by exposing more reaction sites for the adsorption of individual precursors.

[0041] In various embodiments, it will be understood that the number of cycles, each including one or both of the first and second deposition phases, the frequency and number of repetitions of the first deposition phase and the second deposition phase, the frequency and number of repetitions of substrate exposure to the Ti precursor and N precursor during the first deposition phase, and the frequency and number of repetitions of substrate exposure to the Si and / or Al precursor or the Si and / or Al precursor and N precursor during the second deposition phase can be modified based on various considerations, including the sensitivity of the precursors to steric hindrance effects, in order to obtain the desired thickness, stoichiometry, and other properties of the resulting TiSiN and / or TiAlN-containing diffusion barrier layer.

[0042] Referring further to Figures 5B-5D, depending on the required conditions or film properties, it may be advantageous to initiate the deposition of a diffusion barrier containing TiSiN and / or TiAlN by either or by exposing the substrate to a first deposition phase or a second deposition phase. For example, the inventors have found that first exposing the substrate to one or more second deposition phases (Si and / or Al precursor or N precursor) 530, followed by exposing the substrate to a first deposition phase (Ti precursor or N precursor) 525, may be particularly advantageous in promoting a layer-by-layer growth mode of the diffusion barrier. This improves conformability and reduces surface roughness, for example, when the substrate surface is a non-metallic surface such as an insulating surface like the sidewalls of trenches or vias formed in the interlayer insulating film (ILD) layer, or a semiconductor surface such as a Si diffusion region.

[0043] However, the embodiments are not limited in this way, and in other embodiments, first exposing the substrate to one or more first deposition phases (Ti precursor or N precursor) 525, and then exposing the substrate to one or more second deposition phases (Si and / or Al precursor or N precursor) 530, may be more advantageous, for example, when the substrate surface includes a metallic surface (e.g., metallization of W, Al, or Cu metal), in order to maintain good conformability and surface roughness while reducing contact resistance.

[0044] Referring to Figure 5D, under certain circumstances, depending on the sequence described above, the sequence of the first and second deposition phases can result in a thin film having regions rich in TiN and Si and / or Al or SiN and / or AlN to a detectable degree. However, under other circumstances, despite different sequences of exposure to the first and second deposition phases, the resulting thin film may be substantially homogeneous TiSiN and / or TiAlN, as will be discussed later.

[0045] In various embodiments, non-limiting examples of Ti precursors for forming thin films that are diffusion barrier layers or regions include titanium tetrachloride (TiCl4), tetrakis(dimethylamino)titanium (TDFMAT), or tetrakis(diethylamino)titanium (TDEAT).

[0046] In various embodiments, non-limiting examples of N precursors for forming a thin film that is, for example, a diffusion barrier layer or region include ammonia (NH3), hydrazine (N2H4), or monomethylhydrazine (CH3(NH)NH2, "MMH"). As described above, different N precursors can be used in the first and second deposition phases, and completely different precursors can be used in different cycles of the same phase.

[0047] In various embodiments, non-limiting examples of the inert gas for purging include nitrogen (N2) or noble gases such as Ar.

[0048] In some embodiments, the Si precursor for forming the diffusion barrier layer can be a hydride precursor. Examples of hydride precursors include silane (SiH4) and disilane (Si2H6). In some other embodiments, the Si precursor for forming the diffusion barrier can be a chlorine-containing precursor such as silicon chloride or chlorosilane. Examples include silicon tetrachloride (SiCl4), monochlorosilane (SiH3Cl, "MCS"), dichlorosilane (SiH2Cl2, "DCS"), trichlorosilane (SiHCl3), hexachlorodisilane (Si2Cl6, "HCDS"), and octachlorotrisilane (Si3Cl8, "OCTS"). The inventors have found that when a higher level of surface saturation by the precursor is desired, a TiSiN-containing diffusion barrier layer can be desirablely formed using silicon and chlorine-containing Si precursors because they exhibit less steric hindrance compared to organosilicon precursors under a wide range of conditions.

[0049] In some embodiments, the Al precursor for forming the diffusion barrier layer can be an organometallic precursor. Examples of organometallic precursors include trimethylaluminum ("TMA"), triisobutylaluminum, and tris(dimethylamide)aluminum. In some other embodiments, the Al precursor for forming the diffusion barrier layer can be a chlorine-containing Al precursor, such as AlCl3.

[0050] While not bound by any theory, the inventors have found that when these Si and Al precursors are introduced as the first non-nitrogen precursor, they may be particularly advantageous compared to other Si or Al precursors for promoting a layer-by-layer growth mode of the TiSiN or TiAlN layer. The layer-by-layer growth mode is achieved by improving the wettability of the substrate surface by the nuclei of the TiSiN or TiAlN layer in the early stages of growth, which can be characterized by a small contact angle between the nuclei and the substrate surface. As a result of the layer-by-layer growth mode, improved conformability and reduced surface roughness can be achieved, which may be particularly advantageous for forming diffusion barriers by deposition at high aspect ratios of small dimensions. Furthermore, while not bound by any theory, chlorine-containing Si and / or Al precursors may allow for more precise control of the composition in the growth direction by suppressing or self-limiting adsorption.

[0051] For example, to realize the various advantages disclosed herein for functioning as an effective diffusion barrier, thin films containing TiSiN and / or TiAlN may, according to embodiments, have a thickness not exceeding about 25 nm, 20 nm, 15 nm, 10 nm, 7 nm, 4 nm, 2 nm, or 1 nm, or a thickness within a range defined by any of these values ​​or other values. These thicknesses may be substantially smaller than those of TiN barriers having similar effectiveness as a diffusion barrier.

[0052] For example, to realize the various advantages disclosed herein for functioning as an effective diffusion barrier, thin films comprising TiSiN and / or TiAlN can be formed, according to embodiments, at substrate temperatures of 250°C to 300°C, 300°C to 400°C, 350°C to 400°C, 400°C to 450°C, 450°C to 500°C, 500°C to 550°C, 550°C to 600°C, 600°C to 650°C, or within a range defined by any of these values, for example, at a temperature of about 400°C.

[0053] For example, in order to realize the various advantages disclosed herein for functioning as an effective diffusion barrier, the exposure time or pulse duration of various precursors is, according to embodiments, a duration within a range defined by approximately 0.1 to 5 seconds, 5 to 10 seconds, 10 to 20 seconds, 20 to 30 seconds, 30 to 40 seconds, 40 to 50 seconds, 50 to 60 seconds, or any of these values ​​or greater.

[0054] In summary, the formation of a thin film, such as a diffusion barrier layer, containing TiSiN and / or TiAlN, involves exposing the substrate to one or more cycles, each cycle comprising one or more first deposition phases and / or one or more second deposition phases. Each of the first deposition phases sequentially comprises alternating exposures to one or more Ti precursors and one or more N precursors. In some embodiments, each of the second deposition phases sequentially comprises alternating exposures to one or more Si precursors and / or Al precursors and one or more N precursors. The resulting diffusion barrier layer comprises layers or regions of TiSiN or layers or regions of TiAlN. In various embodiments, the frequency and number of exposures of the substrate to each of the Ti precursors, N precursors, and Si and / or Al precursors, as well as the frequency and number of exposures of the substrate to each of the cycles, first deposition phases, and second deposition phases, and the order of exposures, can be adjusted to obtain the desired stoichiometry, thickness, and crystallinity, as described herein.

[0055] [Vapor deposition on substrates having a large surface area and / or a high aspect ratio structure] The inventors have found that when a substrate has a relatively large surface area resulting from a relatively large area density, for example, a high aspect ratio structure, coating the exposed surface with a thin film using an ALD process recipe developed based on the characterization of thin films formed on flat or unpatterned substrates or substrates with a relatively small surface area or low area density of a high aspect ratio structure can result in thin films with different properties in different parts of the exposed surface. For example, the conformality and step coverage mentioned above can be significantly degraded in high aspect ratio structures of substrates with relatively large area densities. Other properties that may also differ in different parts of the exposed surface include film stoichiometry, surface roughness, electrical resistivity, and film density. While not bound by any theory, one possible reason for the low homogeneity of properties is the significantly increased exposed surface area of ​​the substrate compared to a flat substrate. Because the exposed surface area is increased, different parts of the exposed surface may receive flux from precursors of different sizes, and thus different amounts of precursor may be adsorbed onto different parts of the exposed surface. In a simplified example, a 330mm semiconductor substrate has hundreds of dies formed on it, each with 1 x 10¹⁶ dimensions. 10 If the transistors described above are present, and each transistor has one or more vias with a diameter of 10-100 nm and an aspect ratio of 1-100, the surface area exposed to the precursor during thin film deposition may exceed 10, 100, 1000 times, or more the surface area of ​​the corresponding unpatterned substrate. Furthermore, local deposition conditions may differ in different parts of the exposed surface. For example, the local pressure inside a deep trench or via may differ, for example, being lower than in the area outside that deep trench or via. In addition, under vacuum conditions, gas molecules collide more frequently with the sidewalls of the trench or via, so the upper part of a deep trench or via may adsorb more precursor molecules due to exposure to a larger flux.

[0056] In the various embodiments described herein, the inventors have found that the deposition methods disclosed herein are particularly advantageous in forming thin films containing TiSiN and / or TiAlN that exhibit higher homogeneity with respect to various physical properties, including conformality, step coverage, film stoichiometry, surface roughness, electrical resistivity, and film density, across different portions of the exposed surface. Accordingly, thin films containing TiSiN and / or TiAlN formed by the deposition methods disclosed herein exhibit higher homogeneity with respect to one or more of these physical properties, both at a local (e.g., inside a trench or via) level and at an overall (e.g., within a wafer) level. Therefore, the deposition method according to the embodiment is particularly advantageous for forming a thin film containing TiSiN and / or TiAlN on a substrate having surface topography, thereby having a ratio of the surface area of ​​a semiconductor substrate exposed to one or more vapor-phase deposition cycles to the surface area of ​​a corresponding unpatterned semiconductor substrate that exceeds 2, 5, 10, 20, 50, 100, 200, 500, 1000, or within a range defined by any one of these values ​​or greater.

[0057] Alternatively or in addition thereto, the deposition method according to the embodiment is particularly advantageous in forming a thin film on a substrate having a high aspect ratio structure having an aperture width in the range defined by 1 micron, 500 nm, 200 nm, 100 nm, 50 nm, 20 nm, or any of these values ​​or less, an aspect ratio exceeding 5, 10, 20, 50, 100, 200, or any of these values, and an area density such that the surface area is larger than that of the flat substrate described above. A substrate having such topography can be conformally coated with a thin film containing TiSiN and / or TiAlN according to the embodiment. In this case, the step coverage defined above is greater than 50%, 60%, 70%, 80%, 90%, 95%, or within the range defined by any of these values ​​or greater. As described above, the inventors have found that process conditions for conformally coating substrates with a high aspect ratio structure and relatively high area density can be optimized in embodiments to achieve these results. The inventors have found that these results can be achieved, in particular, by controlling the reaction chamber pressure or precursor partial pressure during substrate exposure, the deposition rate, the temperature or partial pressure of the precursor introduced into the reaction chamber, the precursor flow rate, and the exposure time.

[0058] The inventors have found that, according to the embodiments, when coating substrates with a relatively high area density and a high aspect ratio structure, relatively high total or partial pressures can lead to improvements in conformality and step coverage. While not bound by any theory, such improvements may, among other things, relate to reducing the effect of locally small precursor partial pressures within high aspect ratio vias or trenches. Therefore, according to the embodiment, referring again to Figures 5B and 5C, during the exposure of the substrate to one or more first deposition phases (Ti precursor and / or N precursor) 525 and / or during the exposure of the substrate to one or more second deposition phases (Si and / or Al precursor and / or N precursor) 530, the total pressure or partial pressure of any individual precursor can be set to a pressure within the range defined by 1.0 to 3.0 Torr, 3.0 to 5.0 Torr, 5.0 to 7.0 Torr, 7.0 to 9.0 Torr, 9.0 to 11.0 Torr, 11.0 to 13.0 Torr, 13.0 to 15.0 Torr, or any of these values. In each exposure to a Ti precursor, an N precursor, and / or a Si and / Al precursor, the individual precursor may account for a proportion within the range defined by 1-2%, 2-5%, 5-10%, 10-20%, 20-50%, 50-100%, or any of these values, of the total amount of gas molecules in the reaction chamber. The inventors have found that, under given conditions, if the total pressure or partial pressure is outside of these values, step coverage may begin to deteriorate, in particular.

[0059] According to the embodiment, the total pressure or partial pressure can be controlled to a relatively high value during the exposure of the substrate to one or more first deposition phases (Ti precursor and / or N precursor) 525 and / or during the exposure of the substrate to one or more second deposition phases (Si and / or Al precursor and / or N precursor) 530, in relation to the flow rates of the individual precursors and inert gases and the pump exhaust capacity of the reaction chamber, thereby making the deposition rate per first and / or second deposition phase relatively high within the range defined by 0.20~0.30 Å / deposition, 0.30~0.40 Å / deposition, 0.40~0.50 Å / deposition, 0.50~0.60 Å / deposition, 0.60~0.70 Å / deposition, 0.70~0.80 Å / deposition, or any of these values.

[0060] In part, in order to supply a relatively large amount of precursor to the reaction chamber for deposition at a relatively high total pressure or partial pressure while enabling a relatively high throughput, the inventors have found that the flow rate of the precursor into the reaction chamber should be much higher than the flow rate used in the process conditions for forming a thin film on a flat substrate or a substrate having a low (e.g., <1) aspect ratio structure. The high flow rate can be achieved by increasing one or both of the temperature or pressure of the precursor before introduction into the reaction chamber. For example, for a precursor in liquid form under manufacturing conditions, the precursor bottle can be heated to a temperature higher than room temperature, e.g., 30 - 60 °C, 60 - 80 °C, 80 - 100 °C, 100 - 120 °C, 120 - 150 °C, or within a range defined by any of these values, to increase the vapor generation rate. In part, lower or higher bottle temperatures can be determined respectively based on the vapor pressure of the precursor and the decomposition temperature of the precursor. As an example, TiCl4 is heated to about 60 - 80 °C. On the other hand, for a precursor in gas form under manufacturing conditions, a high flow rate can be achieved by increasing the gas line pressure to a much higher value compared to the gas line pressure used when forming a thin film on a relatively small area or flat substrate and / or a substrate having a low (e.g., <1) aspect ratio structure, in order to increase the supply pressure. It will be understood that the relatively high flow rates at which the various advantages described herein can be obtained can depend, inter alia, on the pump exhaust speed, the exposure time, and the volume of the reaction furnace. In order to achieve a flow rate suitable for depositing a thin film on a substrate having a large surface area and / or a high aspect ratio structure, the flow rate of each of the Ti, N, Si, and Al precursors can be, for example, 100 - 1000 standard cm 3 / min (sccm), 1000 - 2000 sccm, 2000 - 5000 sccm, 5000 - 10000 sccm, 10000 - 15000 sccm, 15000 - 20000 sccm, or within a range defined by any of these values or a value greater than these, and in particular, the temperature and / or pressure of the precursor can be adjusted. It will be understood that the appropriate flow rate can depend, inter alia, on the volume of the reaction furnace, and that some of these flow rates are suitable for a single wafer reaction furnace having a volume of about 1 - 2 liters.

[0061] Figures 6A–6C show experimental transmission electron microscope (TEM) images of conformal TiSiN films lining high-aspect-ratio vias formed by the deposition technique described herein. The high-aspect-ratio vias have a deposited silicon oxide surface. Figures 6A, 6B, and 6C are TEM images taken of the top, middle, and bottom of TiSiN films formed on vias with an aspect ratio of approximately 40, respectively. In each of Figures 6A–6C, the left image is a bright-field image of each portion of the high-aspect-ratio via, and the right image shows the limited-field diffraction (SAD) pattern obtained from the thin film formed on each portion of the high-aspect-ratio via using an electron beam with a spot diameter approximately equal to the thickness of the TiSiN thin film. Unlike the polycrystalline TiN with a rough surface due to columnar growth shown in Figure 2, the bright-field TEM images in Figures 6A–6C show that the deposited TiSiN is far smoother and more conformal. The inventors found that these and other improvements can be attributed in part to the presence of at least several amorphous phases of TiSiN. These may be present together with several nanocrystalline layers of TiSiN, as indicated by the SAD pattern. The TiSiN thin film is substantially amorphous and substantially conformal throughout the entire via depth and has good step-high coverage (~60%).

[0062] [Control of thin-film morphology at the nanoscale] Advantageously, the diverse embodiments of the cyclic vapor deposition process disclosed herein, which can be an ALD process, enable the nanoscale control and improvement of the film morphology and structure of thin films containing TiSiN and / or TiAlN, due to their ability to control precursor adsorption at the sub-monolayer level using the diverse process parameters described herein. The controlled morphology and structure include the degree of crystallinity, homogeneity, and surface roughness. In particular, the inventors have found that the degree of crystallinity and / or homogeneity at the nanoscale can be advantageously controlled in thin films containing TiSiN and / or TiAlN by controlling the diverse parameters of the exposure cycle as described herein.

[0063] In various embodiments, when forming a thin film, for example a diffusion barrier layer containing TiSiN and / or TiAlN, the thin film morphology can be controlled using a specific ratio of the number of exposures of the substrate to the first deposition phase (including a combination of exposure to a Ti precursor and an N precursor) to the number of exposures of the substrate to the second deposition phase (including exposure to a Si and / or Al precursor or a combination of exposure to a Si and / or Al precursor and an N precursor), in addition to the various parameters described above. The ratio can be approximately 1:30 to 1:15, 1:15 to 1:6, 1:6 to 1:3, 1:3 to 1:2, 1:2 to 2:3, 2:3 to 5:6, 5:6 to 1:1, 1:1 to 6:5, 6:5 to 3:2, 3:2 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or a ratio within the range defined by any of these values. For example, the ratio can be any of the following: 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, and 15:1. Alternatively, exposure to a Ti precursor and a Si and / or Al precursor may have these ratios. Under the combination of process conditions described herein for forming a diffusion barrier containing TiSiN and / or TiAlN, the ratio of exposure to the first deposition phase to exposure to the second deposition phase results in an average concentration of Si or Al in the diffusion barrier that exceeds a value defined by approximately 3%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or any of these values, based on the total number of atoms in the diffusion barrier.

[0064] The inventors found that the crystallinity of the resulting TiSiN and / or TiAlN thin films can be continuously adjusted, as shown in Figures 7A-7C, by controlling the ratio of the number of exposures of the substrate to the first deposition phase (i.e., the Ti precursor) to the number of exposures of the substrate to the second deposition phase (i.e., the Si or Al precursor). Figures 7A-7C show the limited-field diffraction (SAD) patterns obtained from conformal thin films containing TiSiN deposited on the sidewalls of high-aspect-ratio vias at different crystallinity levels, similar to those shown in Figures 6A-6C. Figures 7A-7C show the SAD patterns of a substantially amorphous TiSiN thin film, a partially amorphous TiSiN thin film, and a substantially polycrystalline or nanocrystalline TiSiN thin film, respectively. It will be understood that the presence of nanocrystalline or polycrystalline domains and the quantitative degree of crystallinity can be determined from the location and relative sharpness of diffraction spots and / or rings that can be indexed to the (111), (200), and (220) crystal planes of crystalline TiSiN, as shown in Figure 7C. For example, a SAD pattern dominated by diffusion rings can be associated with substantially amorphous TiSiN, while a SAD pattern dominated by spots can be associated with substantially polycrystalline TiSiN having domain sizes comparable to the restricted field of view used to obtain the SAD pattern. SAD patterns of nanocrystalline and amorphous phases of TiSiN can contain a mixture of both diffusion rings and spots. The inventors have found, among other things, that increasing the proportion of the amorphous phase contributes to improvements in the smoothness, conformability, and step coverage of TiSiN thin films.

[0065] Figure 8 shows the minute-angle incident X-ray diffraction pattern of a blanket TiSiN layer formed on a substantially amorphous Si substrate according to an embodiment. The measured TiSiN layer is similar to the TiSiN layer imaged in the SAD patterns of Figures 7A and 6A-6C. The absence of distinct crystallographic peaks due to the crystalline phase of the TiSiN layer indicates that the TiSiN layer is substantially amorphous.

[0066] As described herein, the relative crystallinity of thin films containing TiSiN and / or TiAlN can be adjusted to optimize various material properties, such as diffusion barrier properties. In some circumstances, a lower degree of crystallinity may be preferable, for example, to reduce grain boundaries. Reducing grain boundaries can suppress the diffusion of a given element through the thin film and improve its smoothness. However, in other circumstances, a higher degree of crystallinity may be preferable, for example, to reduce the electrical resistivity of the thin film. Figure 9 is a graph of experimentally measured resistivity as a function of silicon content in TiSiN thin films according to the examples. This graph shows that the resistivity of TiSiN thin films can be adjusted over a wide range of values ​​by adjusting the relative Si content (atomic %) within the thin film. By extension, this adjustment can also be made by adjusting the number of exposures to the Si precursor in cyclic vapor deposition or ALD cycles. The inventors found that at relatively low Si content, the resistivity of the TiSiN layer increases relatively slowly as a function of Si content, while at relatively high Si content, the resistivity increases relatively rapidly as a function of Si content. The inventors found that the relatively rapid increase in resistivity as a function of Si content generally coincides with the starting point 910 of the appearance of the amorphous layer of TiSiN, which has been experimentally verified by transmission electron microscopy as described above. It will be understood that this starting point 910 and the electrical resistivity may depend, in particular, on the deposition temperature and the precursor used. As described above, it may be desirable for the Si content to be higher than about 10% in order to form at least partially amorphous TiSiN layers. As a result, the resistivity may increase, while the overall thickness can be reduced compared to a perfectly crystalline layer such as a TiN layer.

[0067] Therefore, in situations where thin films with relatively high diffusion barrier performance and / or relatively low surface roughness are advantageous, it is advantageous to be able to adjust the composition of the electrode layer such that the thin film containing TiSiN and / or TiAlN is at least partially amorphous. In such embodiments, the thin film may be substantially amorphous overall or may contain nanocrystalline regions surrounded by an amorphous matrix. For example, the electrode may contain one or more TiSi / TiAl, TiN, and TiAlN / TiSiN nanocrystals in an amorphous matrix containing Ti, Al / Si, and N. In the illustrated embodiment, the starting point 910 at about 1600 μΩ-cm corresponds to an average atomic concentration of Si of about 10%. However, in other embodiments, depending on the deposition conditions and the precursor used, the starting point can correspond to an average atomic concentration of Si of about 10%, 15%, 20%, or 25%, or within the range defined by any of these values. Alternatively, starting point 910 corresponds to the ratio of the number of exposures of the substrate to one or more first deposition phases (each including a combination of exposure to a Ti precursor and exposure to an N precursor, but without exposure to a Si and / or Al precursor) to the number of exposures of the substrate to one or more second deposition phases (each including exposure to a Si and / or Al precursor or a combination of exposure to a Si and / or Al precursor and exposure to an N precursor), where the ratio is within the range defined by 1:1 to 2:1, 2:1 to 3:1, 3:1 to 6:1, 6:1 to 15:1, 15:1 to 30:1, or any of these values. Alternatively, these ratios can represent the ratio of exposures to a Ti precursor to exposures to an N precursor.

[0068] The composition of a thin film containing TiSiN and / or TiAlN can be adjusted to have an electrical resistivity within the range defined by any of the following values: <1000 μΩ-cm, 1000-2000 μΩ-cm, 2000-300 μΩ-cm, 3000-4000 μΩ-cm, 4000-5000 μΩ-cm, 5000-6000 μΩ-cm, 6000-7000 μΩ-cm, 7000-8000 μΩ-cm, 8000-9000 μΩ-cm, 9000-10000 μΩ-cm, or 10000 μΩ-cm or more.

[0069] In addition to crystallinity, the inventors found that the degree of homogeneity at the nanoscale can also be controlled by controlling the number of exposures to the first deposition phase and / or the number of exposures to the second deposition phase. Under certain circumstances, the sequence of the first and second deposition phases can be controlled to form thin films having TiN and Si and / or Al or SiN and / or AlN-rich regions or layers, such as nanolaminates that alternately contain TiN-rich regions or layers and Si and / or Al-rich regions or layers or SiN / AlN-rich regions or layers. Under several other circumstances, the resulting thin film may be a substantially homogeneous TiSiN and / or TiAlN thin film, despite the different sequences of exposure to the first and second deposition phases, as will be discussed later. Examples are shown with reference to Figures 10A and 10B. Figure 10A shows a TEM image of a substantially homogeneous TiSiN layer, while Figure 10B shows a TEM image of a TiSiN layer in the form of a nanolaminate containing alternating TiN-rich regions or layers and SiN-rich regions or layers.

[0070] In various embodiments, when forming a thin film containing, for example, TiSiN and / or TiAlN as a diffusion barrier layer to form a substantially homogeneous layer, the number of consecutive runs of the first and / or second deposition phases can be less than a value defined by approximately 50, 30, 25, 20, 15, 10, 5, or any of these values, when the film is deposited at the temperatures described above. The thin film may have a nanolaminate structure if the number of consecutive runs of the first and / or second deposition phases exceeds these values. It will be understood that the number of consecutive runs of the first and / or second deposition phases to form a substantially homogeneous or laminated structure may depend on various factors, including temperature, pressure, and the precursor used. For example, at relatively high temperatures, a homogeneous composition may prevail due to increased diffusive mixing of atoms. Conversely, at relatively low temperatures, nanolaminate formation may prevail due to reduced diffusive mixing of atoms.

[0071] The inventors have found that, as an advantage, when thin films containing TiSiN and / or TiAlN are formed by the embodiments disclosed herein, the surface roughness can also be reduced compared to other diffusion barrier materials such as TiN or TiSiN formed using other techniques such as CVD or PVD. The reduction in surface roughness is particularly advantageous compared to other materials or techniques when the surface on which the diffusion barrier is deposited includes non-metallic surfaces such as dielectric surfaces and / or semiconductor surfaces exposed by holes such as vias or trenches. A deposited diffusion barrier having the aforementioned thickness can have a root mean square (RMS) surface roughness within the range defined by 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, and 5%, or any of these values ​​or smaller. Alternatively, the deposited diffusion barrier with the aforementioned thickness may have a root-mean-square (RMS) surface roughness less than the range defined by 0.5 nm, 0.4 nm, 0.3 nm, 0.2 nm, 0.1 nm, or any of these values ​​or less. The reduced RMS roughness can, in turn, improve the conformability of the diffusion barrier layer.

[0072] [Application] Thin films containing TiSiN or TiAlN formed using the various process parameters of the various embodiments disclosed herein can be used in a variety of applications. This is particularly true when the substrate has a topography with a relatively large area, a relatively high aspect ratio structure, and / or a non-metallic surface that can benefit from the various advantageous properties disclosed herein. Exemplary applications include, for example, the deposition of films for lining vias, holes, trenches, cavities, or similar structures having an aspect ratio defined as the depth divided by the width of the top surface, where the aspect ratio exceeds a value within the range defined by 1, 2, 5, 10, 20, 50, 100, 200, or any of these values.

[0073] Figure 11 shows one exemplary application of the concept of forming a diffusion barrier for contact structures, such as source or drain contacts, formed on an active semiconductor substrate region that can be heavily doped. A portion of a semiconductor device 1100 is shown, including a material 1104 on which a dielectric layer 1108, such as an interlayer insulating film (ILD) layer containing a dielectric material such as silicon oxide or silicon nitride, is formed. Vias or trenches can be formed through the dielectric layer 1108 to form contacts in various regions of the substrate 1104, including various doping regions such as source and drain regions. Vias or trenches may expose various non-metallic surfaces, such as the exposed bottom surface including the substrate surface such as the silicon substrate surface, or the dielectric sidewalls of the vias. Subsequently, the bottom and sides of the vias can be conformally coated with a thin film containing TiSiN and / or TiAlN in a manner similar to that shown in Figures 6A-6C, according to various embodiments described herein. Then, to form a contact plug 1116, the lined vias can be filled with a more conductive material, in particular a metal or metal alloy such as W, Al, or Cu. For example, vias can be filled with tungsten by CVD using WF6 or similar materials.

[0074] The barrier layer 1112 formed by the embodiment can be advantageous for the various reasons described above. Furthermore, the conformability of the barrier layer 1112 can significantly suppress the occurrence of pinching in the subsequent metal filling process. In addition, as described above, the barrier layer 1112 can effectively prevent cross-transport of substances such as external diffusion of dopants (B, P) from the substrate 1104 and internal diffusion of reactants, etchants, and metals (F, Cl, W, or Cu, etc.) during the contact plug formation process. The barrier effect can be enhanced by reduced surface roughness, improved step coverage, partially amorphous morphology (which can be partially nanocrystalline), and / or homogeneous / nanolaminate morphology. These advantageous effects can be achieved with a smaller thickness compared to a TiN thin film. Furthermore, as described above, the layer-by-layer growth mode can reduce the overall contact resistance of the barrier layer 1112.

[0075] Other applications of thin films containing TiSiN and / or TiAlN formed by the various embodiments disclosed herein include, to name a few, a variety of conductive structures such as recessed substrates (e.g., embedded electrodes or lines), electrodes (e.g., DRAM capacitor electrodes or gate electrodes), higher metallicity barriers (e.g., barriers in vias / trenches for Cu contacts / lines), high aspect ratio vertical rod electrodes or vias for 3D memory, and through-silicon vias (TSVs).

[0076] Although the present invention has been described herein with reference to specific embodiments, these embodiments are not intended to limit the invention but are provided for illustrative purposes only. It will be obvious to those skilled in the art that modifications and improvements can be made without departing from the spirit and scope of the invention.

[0077] Such simple modifications and improvements to the various embodiments disclosed herein fall within the scope of the disclosed technology, and the specific scope of the disclosed technology will be further defined by the appended claims.

[0078] It will be understood from the above that any one feature of an embodiment can be combined with or substituted for any other feature of an embodiment.

[0079] Unless the context clearly requires otherwise, throughout this specification and the claims, words such as “comprise,” “consisting,” “include,” and “including” shall be interpreted in a comprehensive sense, that is, “including but not limited to,” as opposed to an exclusive or exhaustive sense. The term “coupled,” as commonly used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Similarly, the term “connected,” as commonly used herein, refers to two or more elements that are directly connected or connected via one or more intermediate elements. Furthermore, in this specification, “herein,” “above,” “below,” and similar terms refer to this specification as a whole, not to any particular part of this specification. In addition, in the above description of modes for carrying out the invention, words used singular or plural may include plural or singular, respectively, where the context permits. The word "or" referring to a list of two or more items encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0080] Furthermore, conditional words used herein, particularly “can,” “could,” “might,” “may,” “eg,” “for example,” and “such as,” are generally intended to convey that a particular embodiment includes certain features, elements, and / or states, while other embodiments do not, unless otherwise specified or understood within the context in which they are used. Therefore, such conditional words are generally not intended to suggest that features, elements, and / or states are required in any way in one or more embodiments, or that these features, elements, and / or states are included in or performed in any particular embodiment.

[0081] While specific embodiments have been described, these embodiments are presented for illustrative purposes only and are not intended to limit the scope of the disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications to the forms of methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while a function is shown in a given mechanism, in an alternative embodiment, a similar function may be performed with different components and / or sensor topologies, and some functions may be deleted, moved, added, subdivided, combined, and / or modified. Each of these functions can be performed in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. The various functions and processes described above may be performed independently of each other or combined in a variety of ways. All possible combinations and subcombinations of the features of the disclosure are intended to fall within the scope of the disclosure.

Claims

1. A method for forming a diffusion barrier, The process involves forming a thin film containing either TiSiN or TiAlN, or both, on a semiconductor substrate by exposing it to multiple vapor-phase deposition cycles under a pressure in a reaction chamber exceeding 1 Torre. The vapor deposition cycle includes exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to either or both of a silicon (Si) precursor or an aluminum (Al) precursor. The semiconductor substrate has a surface topography such that the ratio of the surface area of ​​the semiconductor substrate subjected to one or more vapor-phase deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2.

2. The method according to claim 1, wherein the surface topography has a plurality of trenches or vias having an aspect ratio greater than 5.

3. The method according to claim 2, wherein the number and size of the trenches or vias are such that the ratio of the surface area exceeds 20.

4. The method according to claim 1, wherein forming the thin film involves exposing the semiconductor substrate to one or more vapor deposition cycles under a pressure of 3 to 10 tors in a reaction chamber.

5. The method according to claim 1, wherein one or more of the Ti precursors, the N precursors, and the Si or Al precursors are liquids at room temperature and atmospheric pressure.

6. Exposing the semiconductor substrate to one or more vapor deposition cycles, The semiconductor substrate is exposed to multiple first deposition phases, This includes exposing the semiconductor substrate to multiple second deposition phases, Each of the first deposition phases includes exposure to the Ti precursor and exposure to the N precursor, The method according to claim 1, wherein each of the second deposition faces includes exposure to one or both of the Si precursor or the Al precursor.

7. The method according to claim 6, wherein at least one of the second deposition phases further comprises further exposure to the N precursor.

8. The method according to claim 6, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the thin film is at least partially amorphous.

9. The method according to claim 8, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is equal to or less than 15:

1.

10. The method according to claim 8, wherein the thin film comprises TiSiN having a silicon concentration of more than about 10 atomic percent.

11. The method according to claim 6, wherein the number of times the first deposition phase and the number of times the second deposition phase are such that the thin film is substantially homogeneous in the depth direction of the layer.

12. The method according to claim 11, wherein the number of times the first deposition phase or the number of times the second deposition phase does not exceed approximately 50 cycles.

13. The thin film contains TiSiN, and the Si precursor is SiH ４ , Si ２ H ６ , SiH ２ Cl ２ , SiH ２ Cl, Si ２ Cl ６ , and Si ３ Cl ８ The method according to claim 1, which is a compound selected from the group consisting of

14. The method according to claim 1, wherein the thin film contains TiAlN, and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamide)aluminum.

15. The method according to claim 1, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450°C to 650°C.

16. A method for forming a diffusion barrier, A semiconductor substrate is provided with multiple holes formed thereon, This includes lining the surface of the pores with a diffusion barrier layer containing at least partially amorphous TiSiN or TiAlN, or both, by exposing the semiconductor substrate to multiple vapor deposition cycles, The hole has a dielectric sidewall and an aspect ratio greater than 5. A method wherein the vapor deposition cycle comprises exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

17. The method according to claim 16, wherein the aspect ratio of the hole exceeds 5.

18. The method according to claim 17, wherein the surface of the hole is lined such that the ratio of the thickness of the diffusion barrier formed in the lower 25% of the height of the hole to the upper 25% of the height of the hole is greater than 0.

6.

19. The method according to claim 16, wherein the number and size of the holes are set such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2.

20. The method according to claim 16, wherein lining the surface of the holes includes exposing the semiconductor substrate to the vapor deposition cycle under a pressure of 3 to 10 Torr in a reaction chamber.

21. The method according to claim 16, wherein the hole further has an exposed semiconductor bottom surface.

22. Exposing the semiconductor substrate to the vapor deposition cycle is The semiconductor substrate is exposed to multiple first deposition phases, This includes exposing the semiconductor substrate to multiple second deposition phases, The first deposition phase includes exposure to the Ti precursor and exposure to the N precursor, The method according to claim 16, wherein the second deposition face includes exposure to one or both of the Si precursor or the Al precursor.

23. The method according to claim 22, wherein the second deposition phase further includes further exposure to the N precursor.

24. The method according to claim 22, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the diffusion barrier layer is at least partially amorphous.

25. The method according to claim 24, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is 2:3, 3:2, 5:4, 7:3, 7:5, 7:1, 10:1, or 15:

1.

26. The method according to claim 22, wherein the number of times the first deposition phase and the number of times the second deposition phase are such that the diffusion barrier layer is substantially homogeneous in the depth direction of the layer.

27. The method according to claim 26, wherein the number of times the first deposition phase or the second deposition phase does not exceed approximately 50 cycles.

28. The method according to claim 22, wherein the number of times the first deposition phase and the number of times the second deposition phase are such that the diffusion barrier layer has a nanolaminate structure.

29. The method according to claim 16, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer.

30. The diffusion barrier layer contains TiSiN, and the Si precursor is SiH ４ Si ２ H ６ SiH ２ Cl ２ SiH ２ Cl, Si ２ Cl ６ , and Si ３ Cl ８ The method according to claim 16, wherein the compound is selected from the group consisting of the following.

31. The method according to claim 16, wherein the diffusion barrier layer contains TiAlN, and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamide)aluminum.

32. The method according to claim 16, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450°C to 650°C.

33. A method for forming a thin film, The process involves forming a thin film containing TiSiN and / or TiAlN on a semiconductor substrate by exposing it to multiple vapor-phase deposition cycles under a pressure exceeding 5 Torr in a reaction chamber. A method wherein the vapor deposition cycle comprises exposure to a titanium (Ti) precursor, exposure to a nitrogen (N) precursor, and exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

34. The method according to claim 33, wherein the pressure in the reaction chamber is less than 10 Torr.

35. The method according to claim 33, wherein the semiconductor substrate has a topography such that the ratio of the surface area of ​​the semiconductor substrate exposed to one or more vapor deposition cycles to the surface area of ​​the corresponding unpatterned semiconductor substrate is greater than 2.

36. The method according to claim 35, wherein the semiconductor substrate has a plurality of trenches or vias formed thereon, and the trenches or vias have an aspect ratio of more than 5 with respect to the dielectric sidewall.

37. Exposing the semiconductor substrate to one or more vapor deposition cycles, The semiconductor substrate is exposed to multiple first deposition phases, This includes exposing the semiconductor substrate to multiple second deposition phases, The first deposition phase includes exposure to the Ti precursor and exposure to the N precursor, The method according to claim 33, wherein the second deposition phase includes exposure to either the Si precursor or the Al precursor.

38. The method according to claim 37, wherein the second deposition phase further comprises further exposure to the N precursor.

39. The method according to claim 37, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is performed such that the thin film is at least partially amorphous.

40. The method according to claim 39, wherein the ratio of the number of times the first deposition phase is performed to the number of times the second deposition phase is equal to or less than 15:

1.

41. The method according to claim 37, wherein the number of times the first deposition phase and the number of times the second deposition phase are such that the diffusion barrier layer is substantially homogeneous in the depth direction of the layer.

42. The method according to claim 41, wherein the number of times the first deposition phase and the number of times the second deposition phase do not exceed approximately 50 cycles.

43. The thin film contains TiSiN, and the Si precursor is SiH ４ Si ２ H ６ SiH ２ Cl ２ SiH ２ Cl, Si ２ Cl ６ , and Si ３ Cl ８ The method according to claim 33, wherein the compound is selected from the group consisting of the following.

44. The method according to claim 33, wherein the thin film contains TiAlN, and the Al precursor is a compound selected from the group consisting of trimethylaluminum, triisobutylaluminum, and tris(dimethylamide)aluminum.

45. The method according to claim 33, wherein the semiconductor substrate is exposed to the vapor deposition cycle at a substrate temperature of 450°C to 650°C.

46. A semiconductor substrate having a plurality of trenches or vias thereon, wherein the trenches or vias have an aspect ratio of more than 5 with respect to the dielectric sidewall surface, A semiconductor structure comprising a diffusion barrier layer comprising one or both of TiSiN or TiAlN conformally lining the surface of the trench or via, wherein the diffusion barrier layer is at least partially amorphous.

47. The semiconductor structure according to claim 46, wherein the aspect ratio of the trench or via exceeds 5.

48. The semiconductor structure according to claim 47, wherein the diffusion barrier layer conformally lining the surface is configured such that the ratio of the thickness of the diffusion barrier layer formed in the lower 25% of the height of the pore to the upper 25% of the height of the pore exceeds 0.

6.

49. The semiconductor structure according to claim 46, wherein the area density of the trenches or vias is such that the ratio of the surface area on which the diffusion barrier layer is formed to the surface area of ​​the corresponding unpatterned semiconductor substrate exceeds 2.

50. The semiconductor structure according to claim 49, wherein the ratio of the surface areas exceeds 100.

51. The semiconductor structure according to claim 46, wherein the diffusion barrier layer is substantially completely amorphous.

52. The semiconductor structure according to claim 46, wherein the diffusion barrier layer is substantially homogeneous in the depth direction of the pore.

53. The semiconductor structure according to claim 46, wherein the diffusion barrier layer has a nanolaminate structure.

54. The semiconductor structure according to claim 46, wherein the root mean square surface roughness of the diffusion barrier layer is less than about 5% based on the average thickness of the diffusion barrier layer.

55. The semiconductor structure according to claim 46, wherein the diffusion barrier layer contains TiSiN having a silicon concentration of more than about 10 atomic percent.

56. The semiconductor structure according to claim 46, wherein the trench or via further has a semiconductor bottom surface.

57. The semiconductor structure according to claim 46, wherein the trench or via is filled with tungsten or copper.

58. The semiconductor structure according to claim 46, wherein the diffusion barrier layer has a thickness of about 1 to 10 nm.

59. The semiconductor structure according to claim 46, wherein the trench or via has a width of about 10 to 1000 nm.

60. The semiconductor structure according to claim 23, wherein the diffusion barrier layer has an electrical resistivity of less than approximately 1600 μΩ-cm.

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