Nitride semiconductor transistor

Abstract

To provide a nitride semiconductor transistor that can improve distortion characteristics. [Solution] The nitride semiconductor transistor has a channel layer and a barrier layer that overlap each other, a nitride semiconductor layer having a first polarization in a first direction, a source electrode, a drain electrode and a gate electrode in contact with the nitride semiconductor layer, a ferroelectric layer located between the gate electrode and the drain electrode in a plan view and having a second polarization in a second direction opposite to the first direction, and a field plate electrically connected to the source electrode and located above the nitride semiconductor layer, wherein the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor transistor.

Background Art

[0002] Conventionally, a high electron mobility transistor (HEMT) provided with a field plate connected to a source electrode has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, there has been an increasing demand for further improvement in distortion characteristics. The distortion characteristics referred to here are the distortion characteristics (amplitude modulation - amplitude modulation: AM - AM characteristics) of the output amplitude with respect to the input amplitude when the transistor is used as an amplifier.

[0005] An object of the present disclosure is to provide a nitride semiconductor transistor capable of improving distortion characteristics.

Means for Solving the Problems

[0006] The nitride semiconductor transistor of this disclosure has a nitride semiconductor layer having a first polarization in a first direction, having a channel layer and a barrier layer that overlap each other, a source electrode, a drain electrode and a gate electrode in contact with the nitride semiconductor layer, a ferroelectric layer located between the gate electrode and the drain electrode in a plan view and having a second polarization in a second direction opposite to the first direction, and a field plate electrically connected to the source electrode and located above the nitride semiconductor layer, wherein the ferroelectric layer is located between the nitride semiconductor layer and the field plate. [Effects of the Invention]

[0007] According to this disclosure, distortion characteristics can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to the first embodiment. [Figure 2] Figure 2 shows an example of the band structure of a nitride semiconductor transistor according to the first embodiment. [Figure 3] Figure 3 is a diagram (part 1) showing the characteristics of a nitride layer semiconductor transistor. [Figure 4] Figure 4 is a diagram (part 2) showing the characteristics of a nitride layer semiconductor transistor. [Figure 5] Figure 5 is a cross-sectional view (part 1) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 2) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 3) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 8] Figure 8 is a cross-sectional view (part 4) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 9] Figure 9 is a cross-sectional view (part 5) showing a method for manufacturing a nitride semiconductor transistor according to the first embodiment. [Figure 10] Figure 10 is a cross-sectional view showing a nitride semiconductor transistor according to the second embodiment. [Figure 11] Figure 11 is a cross-sectional view showing a nitride semiconductor transistor according to the third embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] [1] A nitride semiconductor transistor according to one aspect of the present disclosure has a nitride semiconductor layer having a first polarization in a first direction, having a channel layer and a barrier layer that overlap each other, a source electrode, a drain electrode and a gate electrode in contact with the nitride semiconductor layer, a ferroelectric layer located between the gate electrode and the drain electrode in a plan view and having a second polarization in a second direction opposite to the first direction, and a field plate electrically connected to the source electrode and located above the nitride semiconductor layer, wherein the ferroelectric layer is located between the nitride semiconductor layer and the field plate.

[0011] A ferroelectric layer is present between the nitride semiconductor layer and the field plate. The nitride semiconductor layer has a first polarization, while the ferroelectric layer has a second polarization opposite to the first. As a result, the depletion layer tends to expand in the region located between the gate electrode and the drain electrode in a plan view. Even when the source-drain current increases, the capacitance between the gate electrode and the drain electrode, and the capacitance between the drain electrode and the source electrode, do not increase easily. Therefore, the distortion characteristics of the output amplitude relative to the input amplitude (AM-AM characteristics) can be improved.

[0012] 〔2〕In [1], a first insulating film that is located above the nitride semiconductor layer and has a first opening reaching the nitride semiconductor layer, and a second insulating film that is located above the first insulating film and has a second opening reaching the first insulating film, are provided. The gate electrode may contact the nitride semiconductor layer through the first opening, and the ferroelectric layer may contact the first insulating film through the second opening. In this case, it is easy to stably form the gate electrode and the ferroelectric layer.

[0013] 〔3〕In [1] or [2], the ferroelectric layer may be a nitride layer containing aluminum and at least one selected from the group consisting of scandium, boron, and yttrium. In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer.

[0014] 〔4〕In [3], the ferroelectric layer is an aluminum scandium nitride layer, and in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms may be 40% or less. In this case, the aluminum scandium nitride layer is likely to have a wurtzite crystal structure.

[0015] 〔5〕In [3], the ferroelectric layer is an aluminum yttrium nitride layer, and in the aluminum yttrium nitride layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms may be 80% or less. In this case, the aluminum yttrium nitride layer is likely to have a wurtzite crystal structure.

[0016] 〔6〕In [1] or [2], the ferroelectric layer may be a hafnium oxide layer containing at least one selected from the group consisting of zirconium, yttrium, lanthanum, and silicon. In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer.

[0017] [7] In [1] or [2], the ferroelectric layer may be an oxide layer having a perovskite-type crystal structure and comprising at least one selected from the group consisting of barium, bismuth, lead, and titanium. In this case, a large residual polarization can be easily obtained in the ferroelectric layer.

[0018] [8] In any of [1] to [7], the nitride semiconductor layer has a first surface in contact with the gate electrode, and the first surface may have metallic polarity. In this case, the nitride semiconductor layer is easily formed stably.

[0019] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In this disclosure, "plan view" means viewing the object from above. In this disclosure, the direction in which the nitride semiconductor layer is located relative to the substrate is defined as "up".

[0020] (First Embodiment) The first embodiment relates to a nitride semiconductor transistor. The nitride semiconductor transistor is, for example, a gallium nitride-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a nitride semiconductor transistor according to the first embodiment.

[0021] As shown in Figure 1, the nitride semiconductor transistor 1 according to the first embodiment includes a substrate 10, a nitride semiconductor layer 20, a ferroelectric layer 50, an insulating film 31, an insulating film 32, a gate electrode 43, a source electrode 42S, a drain electrode 42D, and a field plate 45.

[0022] The substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. If the substrate 10 is a SiC substrate, the upper surface of the substrate 10 is the silicon (Si) polar surface.

[0023] The nitride semiconductor layer 20 includes a buffer layer 21, a channel layer 22, and a barrier layer 23. The nitride semiconductor layer 20 may have a nucleation layer between the substrate 10 and the buffer layer 21. The nitride semiconductor layer 20 has an upper surface 20A. The upper surface 20A has metallic polarity. The upper surface 20A is an example of a first surface.

[0024] The buffer layer 21 is located on the substrate 10. The buffer layer 21 is, for example, a gallium nitride (GaN) layer. The thickness of the buffer layer 21 is, for example, between 100 nm and 2000 nm.

[0025] The channel layer 22 is located on top of the buffer layer 21. The channel layer 22 has a metallic polarity on its upper surface. The channel layer 22 is, for example, a gallium nitride (GaN) layer. The thickness of the channel layer 22 is, for example, 5 nm to 40 nm. The conductivity type of the channel layer 22 is, for example, n-type or undoped (i-type). The buffer layer 21 and the channel layer 22 do not need to be distinguished.

[0026] The barrier layer 23 is located on top of the channel layer 22. The channel layer 22 and the barrier layer 23 overlap each other. The barrier layer 23 has a metallic polarity on its upper surface. The barrier layer 23 is, for example, an aluminum gallium nitride (AlGaN) layer. The electron affinity of the barrier layer 23 is smaller than that of the channel layer 22. The band gap of the barrier layer 23 is larger than that of the channel layer 22. The thickness of the barrier layer 23 is, for example, 5 nm to 40 nm. The composition of the barrier layer 23 is, for example, Al Y Ga 1-Y N(0.15≦Y≦0.55). That is, in the AlGaN layer, the ratio of the number of Al atoms to the total number of Al atoms and Ga atoms (Al composition ratio) is between 15% and 55%. The conductivity type of the barrier layer 23 is, for example, n-type or undoped (i-type).

[0027] The nitride semiconductor layer 20 has a polarization P1 that extends from the upper surface 20A to the lower surface. Polarization P1 is an example of a first polarization.

[0028] A source recess 20S and a drain recess 20D are formed in the nitride semiconductor layer 20. The recesses 20S and 20D penetrate the barrier layer 23. The recesses 20S and 20D may further penetrate the channel layer 22. The bottoms of the recesses 20S and 20D may be in the channel layer 22 or in the buffer layer 21.

[0029] The insulating film 31 is located on top of the barrier layer 23. The insulating film 31 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 31 is, for example, 5 nm to 100 nm. An opening 31S for the source, an opening 31D for the drain, and an opening 31G for the gate are formed in the insulating film 31. The opening 31S connects to the recess 20S, and the opening 31D connects to the recess 20D. In a plan view, the opening 31G is located between the openings 31S and 31D. The opening 31G reaches the barrier layer 23. The insulating film 31 is an example of the first insulating film, and the opening 31G is an example of the first opening.

[0030] The source electrode 42S is located within the recess 20S, above the channel layer 22 or buffer layer 21. The drain electrode 42D is located within the recess 20D, above the channel layer 22 or buffer layer 21. The source electrode 42S and the drain electrode 42D are in contact with the nitride semiconductor layer 20. The source electrode 42S and the drain electrode 42D are in ohmic contact with the nitride semiconductor layer 20.

[0031] In a plan view, the gate electrode 43 is located between the source electrode 42S and the drain electrode 42D. The gate electrode 43 is on the insulating film 31 and contacts the barrier layer 23 through the opening 31G.

[0032] A capping layer may be present on top of the barrier layer 23. If a capping layer is present on top of the barrier layer 23, the insulating film 31 is on top of the capping layer, and the gate electrode 43 contacts the capping layer through the opening 31G. The capping layer is, for example, a gallium nitride (GaN) layer.

[0033] The insulating film 32 lies on the insulating film 31, the source electrode 42S, the drain electrode 42D, and the gate electrode 43. The insulating film 32 covers the insulating film 31, the source electrode 42S, the drain electrode 42D, and the gate electrode 43. The insulating film 32 is, for example, a silicon nitride (SiN) film. The thickness of the insulating film 32 is, for example, 5 nm to 100 nm. An opening 32F reaching the insulating film 31 is formed in the insulating film 32. In a plan view, the opening 32F is located between the gate electrode 43 and the drain electrode 42D. The insulating film 32 may also have openings reaching the source electrode 42S, the drain electrode 42D, and the gate electrode 43.

[0034] The ferroelectric layer 50 is in contact with the insulating film 31 through the opening 32F. For example, the ferroelectric layer 50 is located inside the opening 32F. The ferroelectric layer 50 has a polarization P2 that faces from the bottom surface to the top surface. That is, polarization P2 faces the opposite direction to polarization P1. In a plan view, the ferroelectric layer 50 is located between the gate electrode 43 and the drain electrode 42D. Polarization P2 is an example of a second polarization.

[0035] The field plate 45 is located above the nitride semiconductor layer 20, and on top of the insulating film 32 and the ferroelectric layer 50. The field plate 45 has a first portion 45A, a second portion 45B, and a third portion 45C. The first portion 45A overlaps with the gate electrode 43 in a plan view. The second portion 45B overlaps with the ferroelectric layer 50 in a plan view. The third portion 45C is located between the first portion 45A and the second portion 45B in a plan view and connects the first portion 45A and the second portion 45B. The field plate 45 is electrically connected to the source electrode 42S. The ferroelectric layer 50 is located between the nitride semiconductor layer 20 and the field plate 45.

[0036] Here, an example of the band structure of nitride semiconductor transistor 1 will be described. Figure 2 is a diagram showing an example of the band structure of nitride semiconductor transistor 1 according to the first embodiment. Figure 2 shows the Fermi level E F and the lower end E of the conduction band CThis is shown in Figure 2. In Figure 2, the horizontal axis represents the position of the nitride semiconductor transistor 1 in the direction from the top surface to the bottom surface in the region including the ferroelectric layer 50, and the vertical axis represents the Fermi level E F This indicates energy based on a specific value.

[0037] In the nitride semiconductor transistor 1, as shown in Figures 1 and 2, a two-dimensional electron gas (2DEG) 25 is generated near the upper surface of the channel layer 22. However, there is a ferroelectric layer 50 between the nitride semiconductor layer 20 and the field plate 45. Since the nitride semiconductor layer 20 has polarization P1 and the ferroelectric layer 50 has polarization P2 that is opposite to polarization P1, a portion of the polarization is canceled out, reducing the two-dimensional electron gas 25 near the ferroelectric layer 50. As a result, the depletion layer tends to expand in the region located between the gate electrode 43 and the drain electrode 42D in a plan view, and even if the source-drain current Ids becomes large, the capacitance Cgd between the gate electrode 43 and the drain electrode 42D and the capacitance Cds between the drain electrode 42D and the source electrode 42S do not increase easily. Therefore, the distortion characteristics of the output amplitude with respect to the input amplitude (AM-AM characteristics) can be improved. In other words, the nonlinearity in which the output power saturates and deviates from the proportional relationship with respect to a large input power can be reduced.

[0038] Figures 3 and 4 show the characteristics of two nitride layer semiconductor transistors. The first example follows the first embodiment. The second example is one in which, in the first embodiment, no aperture 32F is formed in the insulating film 32, there is no ferroelectric layer 50, and the insulating film 32 is located between the nitride semiconductor layer 20 and the field plate 45. In Figure 3, the horizontal axis represents current Ids and the vertical axis represents capacitance Cgd. In Figure 4, the horizontal axis represents current Ids and the vertical axis represents capacitance Cds.

[0039] As shown in Figures 3 and 4, in the first example, the capacitance Cgd and Cds do not increase as much when the current Ids increases compared to the second example. Therefore, the distortion characteristics can be improved according to the first example compared to the second example.

[0040] The ferroelectric layer 50 is, for example, a nitride layer having a wurtzite-type crystal structure, a hafnium oxide layer, or an oxide layer having a perovskite-type crystal structure.

[0041] Examples of nitride layers include those containing aluminum (Al) and at least one selected from the group consisting of scandium (Sc), boron (B), and yttrium (Y). In this case, a large remanent polarization can be easily obtained in the ferroelectric layer 50. When the ferroelectric layer 50 is an aluminum scandium nitride layer, if the ratio of the number of Sc atoms to the total number of Al and Sc atoms in the aluminum scandium nitride layer (Sc composition ratio) is 40% or less, the aluminum scandium nitride layer tends to have a wurtzite-type crystal structure. When the ferroelectric layer 50 is an aluminum yttrium nitride layer, if the ratio of the number of Y atoms to the total number of Al and Y atoms in the aluminum yttrium nitride layer (Y composition ratio) is 80% or less, the aluminum yttrium nitride layer tends to have a wurtzite-type crystal structure. The ferroelectric layer 50 may further contain gallium (Ga) or indium (In). When the ferroelectric layer 50 contains gallium, the coelectric field of the ferroelectric layer 50 can be lowered.

[0042] The Sc and Y composition ratios can be measured, for example, by transmission electron microscope energy dispersive X-ray spectroscopy (TEM-EDX), secondary ion mass spectrometry (SIMS), or X-ray photoelectron spectroscopy.

[0043] Examples of hafnium oxide layers include those containing at least one element selected from zirconium (Zr), yttrium (Y), lanthanum (La), and silicon (Si). In this case, it is easy to obtain a large remanent polarization in the ferroelectric layer 50.

[0044] Examples of oxide layers having a perovskite-type crystal structure include oxide layers containing at least one selected from the group consisting of barium (Ba), bismuth (Bi), lead (Pb), and titanium (Ti). In this case, a large remanent polarization can be easily obtained in the ferroelectric layer 50.

[0045] The ferroelectric layer 50 may further contain at least one selected from the group consisting of indium (In), selenium (Se), molybdenum (Mo), and tellurium (Te).

[0046] The polarization direction of the ferroelectric layer 50 can be determined by measuring the electric field inside the ferroelectric layer 50 using a transmission electron microscope (TEM) or the like.

[0047] Next, a method for manufacturing the nitride semiconductor transistor 1 according to the first embodiment will be described. Figures 5 to 9 are cross-sectional views showing the method for manufacturing the nitride semiconductor transistor 1 according to the first embodiment.

[0048] First, as shown in Figure 5, a buffer layer 21, a channel layer 22, and a barrier layer 23 are sequentially formed on the substrate 10, for example, by metal-organic chemical vapor deposition (MOCVD). At this point, the upper surfaces of the buffer layer 21, the channel layer 22, and the barrier layer 23 possess metallic polarity, and a two-dimensional electron gas 25 is generated near the upper surface of the channel layer 22. The nitride semiconductor layer 20 has polarization P1 directed from the upper surface 20A to the lower surface. Next, an insulating film 31 is formed on the barrier layer 23.

[0049] Next, as shown in Figure 6, a source opening 31S and a drain opening 31D are formed in the insulating film 31, and a source recess 20S and a drain recess 20D are formed in the nitride semiconductor layer 20. The openings 31S, 31D, 20S, and 20D can be formed, for example, by reactive ion etching (RIE) using a mask (not shown).

[0050] Next, a source electrode 42S is formed on the channel layer 22 or buffer layer 21 within the recess 20S, and a drain electrode 42D is formed on the channel layer 22 or buffer layer 21 within the recess 20D. In forming the source electrode 42S and drain electrode 42D, first, a metal layer (not shown) constituting the source electrode 42S and drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) with an opening formed in the region where the metal layer is to be formed is used for film deposition, and then the growth mask is removed together with the metal layer (not shown) formed thereon. In other words, a lift-off is performed.

[0051] Next, a gate opening 31G is formed in the insulating film 31. The opening 31G can be formed, for example, by RIE using a mask (not shown). Next, a gate electrode 43 that contacts the barrier layer 23 through the opening 31G is formed on the insulating film 31. When forming the gate electrode 43, a metal layer is deposited using, for example, a growth mask (not shown) with an opening formed in the region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0052] Next, as shown in Figure 7, an insulating film 32 is formed on the insulating film 31, source electrode 42S, drain electrode 42D, and gate electrode 43. Next, an opening 32F is formed in the insulating film 32. The opening 32F can be formed, for example, by RIE using a mask (not shown). Next, a ferroelectric layer 50 is formed that contacts the insulating film 31 through the opening 32F. The ferroelectric layer 50 can be formed, for example, by sputtering, CVD, electron beam epitaxy (MBE), or atomic layer deposition (ALD). At this point, the polarization of the ferroelectric layer 50 may be oriented in any direction.

[0053] Next, as shown in Figure 8, a field plate 45 having a first portion 45A, a second portion 45B, and a third portion 45C is formed on the insulating film 32 and the ferroelectric layer 50. At this point, the field plate 45 is electrically insulated from the source electrode 42S. In forming the field plate 45, first, a metal layer (not shown) that constitutes the field plate 45 is formed. When forming the metal layer, for example, a growth mask (not shown) with an opening formed in the region where the metal layer is to be formed is used for film deposition, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, a lift-off is performed.

[0054] Next, as shown in Figure 9, an electric field E greater than or equal to the coelectric field of the ferroelectric layer 50 is applied to the ferroelectric layer 50 so that the ferroelectric layer 50 has a polarization P2 that is opposite to the polarization P1. For example, the electric field E can be applied to the ferroelectric layer 50 by applying a voltage between the source electrode 42S and the field plate 45. When controlling the polarization P2, the ferroelectric layer 50 may be heated to a temperature of about 500°C or less.

[0055] Next, the field plate 45 and the source electrode 42S are electrically connected. For example, a metal layer is formed connecting the field plate 45 and the source electrode 42S.

[0056] In this way, nitride semiconductor transistor 1 can be manufactured.

[0057] The gate electrode 43 contacts the nitride semiconductor layer 20 through the opening 31G, and the ferroelectric layer 50 contacts the insulating film 31 through the opening 32F, making it easier to stably form the gate electrode 43 and the ferroelectric layer 50.

[0058] The upper surface 20A of the nitride semiconductor layer 20 has metallic polarity, which facilitates the stable formation of the nitride semiconductor layer 20. The upper surface 20A of the nitride semiconductor layer 20 may also have nitrogen polarity.

[0059] The method and timing for controlling the polarization of the ferroelectric layer 50 are not particularly limited. Furthermore, the insulating film 32 may be formed after the ferroelectric layer 50 has been formed.

[0060] The depth of the opening 32F is not particularly limited. The opening 32F does not have to penetrate the insulating film 32, and the opening 32F may extend into the interior of the insulating film 31.

[0061] (Second Embodiment) The second embodiment differs from the first embodiment mainly in the configuration of the ferroelectric layer 50. Figure 10 is a cross-sectional view showing a nitride semiconductor transistor according to the second embodiment.

[0062] As shown in Figure 10, in the nitride semiconductor transistor 2 according to the second embodiment, the ferroelectric layer 50 is located not only inside the opening 32F but also on the upper surface of the insulating film 32.

[0063] The other components of nitride semiconductor transistor 2 are the same as those of nitride semiconductor transistor 1.

[0064] The same effect can be obtained with nitride semiconductor transistor 2 as with nitride semiconductor transistor 1.

[0065] (Third embodiment) The third embodiment differs from the first embodiment mainly in the configuration of the insulating film. Figure 11 is a cross-sectional view showing a nitride semiconductor transistor according to the third embodiment.

[0066] As shown in Figure 11, in the nitride semiconductor transistor 3 according to the third embodiment, an opening 31F is formed in the insulating film 31. The opening 31F is located between the gate electrode 43 and the drain electrode 42D in a plan view. The ferroelectric layer 50 contacts the barrier layer 23 through the opening 31F. For example, the ferroelectric layer 50 is located inside the opening 31F. Also, no opening 32F is formed in the insulating film 32.

[0067] The other components of nitride semiconductor transistor 3 are the same as those of nitride semiconductor transistor 1.

[0068] The same effect can be obtained with nitride semiconductor transistor 3 as with nitride semiconductor transistor 1.

[0069] When forming the nitride semiconductor transistor 3, the ferroelectric layer 50 may be formed after the insulating film 31, or the insulating film 31 may be formed after the ferroelectric layer 50. Furthermore, the opening 31F does not need to penetrate the insulating film 31, and the ferroelectric layer 50 does not need to be in contact with the barrier layer 23.

[0070] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of Symbols]

[0071] 1, 2, 3 Nitride semiconductor transistors 10 circuit boards 20 Nitride semiconductor layer 20A top 20D, 20S recess 21 Buffer Layer 22 channel layers 23 Barrier layer 25 Two-dimensional electron gas 31, 32 Insulating film 31D, 31F, 31G, 31S, 32F opening 42D drain electrode 42S Source Electrode 43 gate 45 Field Plate 45A Part 1 45B 2nd part 45C 3rd part 50 Ferroelectric layer E electric field P1, P2 polarization

Claims

1. A nitride semiconductor layer having a channel layer and a barrier layer that overlap each other, and having a first polarization in a first direction, A source electrode, a drain electrode, and a gate electrode that contact the nitride semiconductor layer, A ferroelectric layer located between the gate electrode and the drain electrode in a plan view, having a second polarization in a second direction opposite to the first direction, A field plate is electrically connected to the source electrode and is located above the nitride semiconductor layer, It has, The ferroelectric layer is a nitride semiconductor transistor located between the nitride semiconductor layer and the field plate.

2. A first insulating film is located on the nitride semiconductor layer and has a first opening that reaches the nitride semiconductor layer. A second insulating film is located on the first insulating film and has a second opening formed thereon that reaches the first insulating film, It has, The gate electrode contacts the nitride semiconductor layer through the first opening. The nitride semiconductor transistor according to claim 1, wherein the ferroelectric layer is in contact with the first insulating film through the second opening.

3. The ferroelectric layer is Aluminum and At least one selected from the group consisting of scandium, boron, and yttrium, A nitride semiconductor transistor according to claim 1 or claim 2, wherein the nitride layer contains a nitride layer.

4. The ferroelectric layer is an aluminum scandium nitride layer. The nitride semiconductor transistor according to claim 3, wherein in the aluminum scandium nitride layer, the ratio of the number of scandium atoms to the total number of aluminum atoms and scandium atoms is 40% or less.

5. The ferroelectric layer is an aluminum yttrium nitride layer. The nitride semiconductor transistor according to claim 3, wherein in the aluminum nitride yttrium layer, the ratio of the number of yttrium atoms to the total number of aluminum atoms and yttrium atoms is 80% or less.

6. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the ferroelectric layer is a hafnium oxide layer containing at least one element selected from the group consisting of zirconium, yttrium, lanthanum, and silicon.

7. The nitride semiconductor transistor according to claim 1 or claim 2, wherein the ferroelectric layer is an oxide layer having a perovskite-type crystal structure and comprising at least one selected from the group consisting of barium, bismuth, lead, and titanium.

8. The nitride semiconductor layer has a first surface in contact with the gate electrode, The nitride semiconductor transistor according to claim 1 or claim 2, wherein the first surface has metallic polarity.

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