Conversion circuit and analog signal processing circuit

Abstract

The conversion circuit generates a digital signal with a resolution higher than a predetermined resolution. [Solution] The conversion circuit includes: a first AD converter (21) that converts a signal based on a first amplified signal obtained by amplified an analog input signal with a first gain by a first amplifier (11) into a first digital signal; a first extractor (12) that generates a first extracted signal obtained by extracting the high-frequency components of the analog input signal; a second amplifier (13) that generates a second amplified signal obtained by amplified the first extracted signal with a second gain greater than the first gain; a second AD converter (23) that converts the second amplified signal into a second digital signal; a second extractor (22) that generates a second extracted signal obtained by extracting the low-frequency components of the first digital signal; an adjustment unit (24) that receives the second extracted signal and the second digital signal and generates a third digital signal and a fourth digital signal; and an adder (25) that generates a digital output signal obtained by adding the third digital signal and the fourth digital signal.

Description

Technical Field

[0001] The present disclosure relates to a conversion circuit and an analog signal processing circuit.

Background Art

[0002] In various electronic devices, an ADC [analog-to-digital converter] that converts an analog signal representing these states into a digital signal is used to digitally process the electrical state of an internal circuit or the physical state of an electronic device (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] The ADC has a predetermined resolution and converts and outputs an input analog signal into a digital signal with the predetermined resolution. However, there are cases where a digital signal with a resolution higher than the predetermined resolution is required.

[0005] The conversion circuit according to this disclosure comprises: a first AD converter configured to convert a signal based on an analog input signal or a signal based on a first amplified signal obtained by amplified the analog input signal with a first gain by a first amplifier into a first digital signal; a first extractor configured to generate a first extracted signal obtained by extracting the high-frequency components of the analog input signal; a second amplifier configured to generate a second amplified signal obtained by amplified the first extracted signal with a second gain greater than the first gain; a second AD converter configured to convert the second amplified signal into a second digital signal; a second extractor configured to generate a second extracted signal obtained by extracting the low-frequency components of the first digital signal; an adjustment unit configured to receive the second extracted signal and the second digital signal and generate a third digital signal and a fourth digital signal; and an adder configured to generate a digital output signal obtained by adding the third digital signal and the fourth digital signal, wherein the third digital signal is the second extracted signal itself or a signal obtained by adjusting the magnification of the second extracted signal, and the fourth digital signal is the second digital signal itself or a signal obtained by adjusting the magnification of the second digital signal. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 shows a first comparative example of the conversion circuit. [Figure 2] Figure 2 shows a second comparative example of the conversion circuit. [Figure 3] Figure 3 shows a first embodiment of the conversion circuit. [Figure 4] Figure 4 shows a bit conversion in the first embodiment. [Figure 5] Figure 5 shows the frequency characteristics of the extractor. [Figure 6] Figure 6 shows a first specific example of the extractor and adjustment unit in the first embodiment. [Figure 7] Figure 7 shows a second specific example of the extractor and adjustment unit in the first embodiment. [Figure 8] Figure 8 shows a second embodiment of the conversion circuit. [Figure 9A] Figure 9A shows an example of the input and output signal waveforms of the amplifier according to the second embodiment. [Figure 9B] Figure 9B shows other waveform examples of the input and output signals of the amplifier in the second embodiment. [Figure 10] Figure 10 shows a third embodiment of the conversion circuit. [Figure 11] Figure 11 shows a fourth embodiment of the conversion circuit.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. Before describing the embodiments of the present disclosure, comparative examples will be described for comparison. By describing the comparative examples, the problems will become clearer.

[0008] <Comparative Example 1> Figure 1 shows a first comparative example of the conversion circuit. The microcontroller 100 includes switches 101, 102, and 103, an ADC 104, PIOs 105 to 108, and terminals T1 to T7. The ADC 104 is the first comparative example of the conversion circuit. Here, the ADC 104 has a 12-bit resolution, which is the mainstream for microcontrollers.

[0009] Switch 101 is connected between terminal T1 and the input terminal of ADC104. Switch 102 is connected between terminal T2 and the input terminal of ADC104. Switch 103 is connected between terminal T3 and the input terminal of ADC104.

[0010] The microcontroller 100 can selectively select which switch to turn on from among switches 101 to 103, thereby selectively selecting which terminal to receive the analog signal input to the ADC 104 from among terminals T1 to T3.

[0011] The ADC104 converts the analog signal input from the selected terminal into a digital signal with 12-bit resolution and outputs it.

[0012] <Second Comparative Example> FIG. 2 is a diagram showing a second comparative example of the conversion circuit. ADC200 is a second comparative example of the conversion circuit.

[0013] ADC200 includes an ADC201 having a resolution of 16 bits, which is higher than that of ADC104.

[0014] ADC200 is connected to terminals T4 to T7 of the microcomputer 100. ADC200 performs conversion processing using the reference voltage VREF output from the reference voltage source 300.

[0015] ADC200 converts the input analog signal into a digital signal with a resolution of 16 bits and outputs it to the microcomputer 100.

[0016] That is, the external ADC200 can supply the microcomputer 100 with a digital signal having a higher resolution than that of the ADC104 provided in the microcomputer 100.

[0017] However, when an external 16-bit ADC200 is provided, the cost increases. In addition, a reference voltage source 300 that outputs a reference voltage VREF for achieving 16-bit performance in addition to the 16-bit ADC200 is also a factor contributing to the high cost. Furthermore, there is also a problem that additional communication terminals for communicating with the 16-bit ADC200 are required for the microcomputer 100.

[0018] <First Embodiment> FIG. 3 is a diagram showing a first embodiment of the conversion circuit. The first embodiment of the conversion circuit includes a first signal processing circuit 1A and a second signal processing circuit 2A. The second signal processing circuit 2A is a part of the microcomputer. The first signal processing circuit 1A is provided outside the microcomputer. Here, the first signal processing circuit 1A is provided in front of the second signal processing circuit 2A.

[0019] The first signal processing circuit 1A includes amplifiers 11 and 13 and an extractor 12.

[0020] The analog signal Ain is input to the analog signal processing circuit 1A. More specifically, the analog signal Ain is input to the amplifier 11 and the extractor 12.

[0021] Amplifier 11 amplifies the analog signal Ain with a predetermined gain to generate analog signal A1, which is then output to the second signal processing circuit 2A.

[0022] The extractor 12 generates an analog signal A0 by extracting high-frequency components from the analog signal Ain and outputs it to the amplifier 13.

[0023] Amplifier 13 generates an analog signal A2 by amplifying the analog signal A0 and outputs it to the second signal processing circuit 2A. The gain of amplifier 13 is set higher than the gain of amplifier 11. For example, the gain of amplifier 11 is 1x and the gain of amplifier 13 is 16x.

[0024] The second signal processing circuit 2A includes ADCs 21 and 23, an extractor 22, an adjustment unit 24, and an adder 25.

[0025] Analog signal A1 is input to ADC21.

[0026] The ADC21 generates a digital signal D0 by performing an AD conversion of the analog signal A1 with 12-bit resolution and outputs it to the extractor 22.

[0027] The extractor 22 generates a digital signal D1_1 by extracting the low-frequency components from the digital signal D0 and outputs it to the adjustment unit 24. For example, the extractor 22 is an LPF (low-pass filter).

[0028] Analog signal A2 is input to ADC23.

[0029] The ADC23 generates a digital signal D2_1 by converting the analog signal A2 with 12-bit resolution and outputs it to the adjustment unit 24.

[0030] The adjustment unit 24 receives digital signals D1_1 and D2_1 and outputs digital signals D1_2 and D2_2 to the adder 25.

[0031] Here, the adjustment unit 24 has a multiplier ratio that matches the values ​​of digital signals D1_1 and D2_1. Specifically, the product of the multiplier of digital signal D1_2 relative to digital signal D1_1 and the multiplier of digital signal D2_1 relative to digital signal D2_2 is equal to the multiplier of the gain of amplifier 13 relative to the gain of amplifier 11.

[0032] Furthermore, amplifier 11 is not necessarily required. In that case, the adjustment unit 24 has a multiplier ratio equivalent to that of amplifier 13. Specifically, when the ADC 21 is configured to convert the analog input signal Ain to the digital signal D0, the product of the multiplier of digital signal D1_2 relative to digital signal D1_1 and the multiplier of digital signal D2_1 relative to digital signal D2_2 is equal to the multiplier of amplifier 13.

[0033] The adder 25 generates and outputs an output signal Dout by adding the digital signals D1_2 and D2_2.

[0034] By setting the gain of amplifier 13 higher than the gain of amplifier 11 and adjusting the gain of the digital signal with the adjustment unit 24, the digital signal D2_2 can be shifted to the lower bits relative to the digital signal D1_2, as shown in Figure 4. Here, since the ratio of the gain of amplifier 13 to the gain of amplifier 11 is 16, the digital signal D2_2 is shifted to the lower bits by 4 bits relative to the digital signal D1_2.

[0035] As described above, the analog signal A0 supplied to amplifier 13 is a signal obtained by extracting the high-frequency components from the analog input signal Ain. This makes the amplitude of analog signal A0 smaller than the amplitude of the analog input signal Ain, thereby preventing the amplitude of analog signal A0 from exceeding the input range of amplifier 13.

[0036] As shown in Figure 4, digital signals D1_2 and D2_2 have overlapping bits (digits). However, since the frequency characteristics F12 of extractor 12 and F22 of extractor 22 are complementary to each other, as shown in Figure 5, it is possible to suppress the deviation of the output signal Dout, which is the sum of digital signals D1_2 and D2_2, from the value obtained by directly converting the analog input signal Ain to digital using a 16-bit ADC.

[0037] From the perspective of reliably preventing the output signal Dout, obtained by adding digital signals D1_2 and D2_2, from deviating from the value obtained by directly converting the analog input signal Ain to digital using a 16-bit ADC, it is desirable that the cutoff frequencies of extractor 12 and extractor 22 be the same.

[0038] Figure 6 shows a first specific example of the extractor 12 and adjustment unit 24 in the first embodiment. The configuration is the same as in Figure 3, except for the extractor 12 and adjustment unit 24.

[0039] The extractor 12 includes an LPF 121 and a subtractor 122.

[0040] The LPF121 generates an analog signal A0_1 by extracting the low-frequency components from the analog signal Ain and outputs it to the subtractor 122. The LPF121 is a smoother configured to generate the analog signal A0_1 by smoothing the analog signal Ain.

[0041] The subtractor 122 generates analog signal A0_2 by subtracting analog signal A0_1 from analog signal Ain and outputs it to amplifier 13. As a result, the high-frequency component of analog signal Ain is output from subtractor 122 to amplifier 13. Analog signal A0_2 corresponds to analog signal A0 in Figure 3.

[0042] The adjustment unit 24 includes an amplifier 241.

[0043] Amplifier 241 generates a digital signal D1_2 by amplifying the digital signal D1_1 by a predetermined factor and outputs it to adder 25. Here, if the gain of amplifier 11 is 1x and the gain of amplifier 13 is 16x, amplifier 241 has a factor of 16x (the ratio of the gain of amplifier 13 to the gain of amplifier 11).

[0044] Digital signal D2 corresponds to digital signal D2_1 and digital signal D2_2 in Figure 3, respectively.

[0045] Figure 7 shows a second specific example of the extractor 12 and adjustment unit 24 in the first embodiment. The configuration is the same as in Figure 3, except for the extractor 12 and adjustment unit 24.

[0046] The extractor 12 is equipped with an HPF (high pass filter) 123.

[0047] HPF123 generates an analog signal A0 by extracting high-frequency components from the analog signal Ain and outputs it to amplifier 13.

[0048] The adjustment unit 24 includes an attenuator 242.

[0049] The attenuator 242 generates a digital signal D2_2 by attenuating the digital signal D2_1 by a predetermined factor and outputs it to the adder 25. Here, if the gain of amplifier 11 is 1x and the gain of amplifier 13 is 16x, the attenuator 242 has a factor of 1 / 16 (the ratio of the gain of amplifier 11 to the gain of amplifier 13).

[0050] Digital signal D1 corresponds to digital signal D1_1 and digital signal D1_2 in Figure 3, respectively.

[0051] In the first specific example of the adjustment unit 24, the adjustment unit 24 comprises only an amplifier 241. In the second specific example of the adjustment unit 24, the adjustment unit 24 comprises only an attenuator 242. However, the configuration of the adjustment unit 24 is not limited to the first and second specific examples. For example, the adjustment unit 24 may comprise both an amplifier 241 and an attenuator 242. Here, if the adjustment unit 24 comprises both an amplifier 241 and an attenuator 242, and the gain of amplifier 11 is 1x and the gain of amplifier 13 is 16x, then it is sufficient that amplifier 241 has a multiplier of Mx, attenuator 242 has a multiplier of 1 / Nx, and the product of M and N is the same as the ratio of the gain of amplifier 13 to the gain of amplifier 11.

[0052] <Second Embodiment> Figure 8 shows a second embodiment of the conversion circuit. The second embodiment of the conversion circuit comprises a first signal processing circuit 1A and a second signal processing circuit 2B. The second signal processing circuit 2B includes a detection circuit 26 and a selector 27 in addition to the configuration of the second signal processing circuit 2A. Note that if the adjustment unit 24 is configured as shown in Figure 6, that is, if the adjustment unit 24 is made into an amplifier 241, it is preferable to provide an amplifier with the same gain as the amplifier 241 between the output terminal of the ADC 21 and the selector 27.

[0053] The detection circuit 26 detects the digital signal D2 and generates a determination signal S1 indicating whether or not the digital signal D2 exceeds a certain range, and outputs it to the selector 27.

[0054] Selector 27 receives a decision signal S1 and, based on the value of the decision signal S1, selects and outputs either the digital signal D0 or the output signal Dout. Here, if the digital signal D2 is outside a certain range, selector 27 selects and outputs the digital signal D0. If the digital signal D2 is within a certain range, selector 27 selects and outputs the output signal Dout.

[0055] In the configuration of the first embodiment, when the high-frequency component of the analog input Ain is large, the analog signal A0_2 may exceed the input range of the ADC13, and the discrepancy between the output signal Dout actually output from the adder 25 and the expected value of the output signal Dout may become large. In other words, the output signal Dout output from the adder 25 may be a signal with a large error.

[0056] On the other hand, in the second embodiment, when the digital signal D2 is outside a certain range, the selector 27 selects and outputs the digital signal D0. This makes it possible to output a digital signal D0 that has a resolution of 12 bits but a small error.

[0057] As a variation, an extractor with a higher cutoff frequency than extractor 22 may be provided to pass the digital signal D0 through. In contrast to the configuration shown in Figure 8, if the adjustment unit 24 is configured as shown in Figure 6, that is, if the adjustment unit 24 is made into an amplifier 241, the extractor with a higher cutoff frequency than extractor 22 may be provided before an amplifier with the same gain as amplifier 241, or after an amplifier with the same gain as amplifier 241.

[0058] Here, the digital signal D0 selected and output by the selector 27 is 12 bits, and the output signal Dout is 16 bits. The detection circuit 26 outputs a determination signal S1 to the selector 27, and may also output the determination signal S1 to the circuit that receives the output of the selector 27. This allows the circuit that receives the output of the selector 27 to determine whether the output of the selector 27 is a 12-bit signal or a 16-bit signal based on the determination signal S1.

[0059] Figures 9A and 9B show examples of input and output signal waveforms of the amplifier 13 in the second embodiment.

[0060] Figure 9A shows the waveforms of analog signal A0_2 and analog signal A2 when the high-frequency component of analog signal Ain is small.

[0061] Analog signal A0_2 is a signal waveform obtained by extracting the high-frequency components from analog signal Ain.

[0062] Since analog signal A2 is analog signal A0_2 multiplied by 16, the output waveform has an amplitude amplified 16 times.

[0063] At this time, the amplified analog signal A2 does not exceed the input range of the ADC23 because the high-frequency components of the analog signal Ain are small, and an accurate value is input to the amplifier 23.

[0064] Figure 9B shows the waveforms of analog signal A0_2 and analog signal A2 when the high-frequency component of analog signal Ain is large.

[0065] Analog signal A0_2 is a signal waveform obtained by extracting the high-frequency components from analog signal Ain.

[0066] Since analog signal A2 is analog signal A0_2 multiplied by 16, the output waveform has an amplitude amplified 16 times.

[0067] At this time, the amplified analog signal A2 exceeds the input range of the ADC23 due to the large high-frequency component of the analog signal Ain. As a result, the dotted line portion becomes overrange, and the correct value is not input to the amplifier 23.

[0068] <Third Embodiment> Figure 10 shows a third embodiment of the conversion circuit. The third embodiment of the conversion circuit comprises a first signal processing circuit 1B and a second signal processing circuit 2B. In addition to the configuration of the first signal processing circuit 1A, the first signal processing circuit 1B includes a detection circuit 14, a dither generation circuit 15, and an adder 16.

[0069] The detection circuit 14 detects the analog signal A2 and generates a determination signal S2 indicating whether or not the analog signal A2 exceeds a certain range, and outputs it to the dither generation circuit 15.

[0070] The dither generation circuit 15 outputs a dither signal A3 to the adder 16 to reduce quantization errors.

[0071] The adder 16 generates and outputs analog signal A4 by adding analog signal A1 and dither signal A3. Analog signal A4 is supplied to ADC 21.

[0072] With the configuration of the third embodiment of the conversion circuit, the dither signal A3 is added to the analog signal A1, thereby reducing quantization errors.

[0073] Furthermore, if the analog signal A0_2 exceeds the input range of the amplifier 13, the selector 27 selects and outputs the digital signal D0. Therefore, even if the analog signal A0_2 exceeds the input range of the amplifier 13, if the dither generation circuit 15 is operating, the digital signal D0, which is obtained by AD conversion of the analog signal A4 including the dither signal A3, will be output as is. In the third embodiment of the conversion circuit, the detection circuit 14 detects the analog signal A2, and if the analog signal A0_2 exceeds the input range of the amplifier 13, the operation of the dither generation circuit 15 is turned OFF.

[0074] <Fourth Embodiment> Figure 11 shows a fourth embodiment of the conversion circuit. The fourth embodiment of the conversion circuit comprises a first signal processing circuit 1A and a second signal processing circuit 2C. The second signal processing circuit 2C is configured by integrating ADC21 and ADC23 into a single ADC20 from the configuration of the second signal processing circuit 2A, and adding switches SW1 and SW2 and a processing circuit 28.

[0075] Switch SW1 is connected between amplifier 11 and ADC20 and switches whether or not to supply analog signal A1 to ADC20.

[0076] Switch SW2 is connected between amplifier 13 and ADC20 and switches whether or not to supply analog signal A2 to ADC20.

[0077] Here, switches SW1 and SW2 switch ON / OFF complementaryly using time-division multiplexing.

[0078] The processing circuit 28 receives the digital signal output from the ADC 20 and switches between digital signal D0 and digital signal D2 in a time-division manner before outputting them.

[0079] When switch SW1 is turned ON, analog signal A1 is input to ADC20. Therefore, when switch SW1 is ON, ADC20 generates a digital signal by A / D conversion of analog signal A1. The digital signal generated by ADC20 is input to processing circuit 28 and is output to extractor 22 as digital signal D0 while switch SW1 is ON. Digital signal D0 is converted to digital signal D1_2 via extractor 22 and amplifier 241. Digital signal D1_2 is supplied to adder 25.

[0080] When switch SW2 is turned ON, analog signal A2 is input to ADC20. Therefore, when switch SW2 is ON, ADC20 generates a signal obtained by A / D conversion of analog signal A2. The digital signal generated by ADC20 is input to processing circuit 28 and is output to adder 25 as digital signal D2 while switch SW2 is ON.

[0081] The adder 25 serially adds the digital signals D1_2 and D2 in a time-division multiplexer to generate a 16-bit digital signal Dout.

[0082] Therefore, with the fourth embodiment of the conversion circuit, it becomes possible to perform AD conversion with 16-bit high resolution using only one ADC, without needing to prepare multiple ADCs.

[0083] <Note> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.

[0084] (Note 1) A first AD converter (21) is configured to convert a signal based on an analog input signal (Ain) or a signal based on a first amplified signal (A1) obtained by amplified the analog input signal (Ain) with a first gain by a first amplifier (11) into a first digital signal (D0), A first extractor (12) is configured to generate a first extracted signal (A0) obtained by extracting the high-frequency components of the analog input signal (Ain), A second amplifier (13) is configured to generate a second amplified signal (A2) obtained by amplifying the first extracted signal (A0) with a second gain greater than the first gain, A second AD converter (23) configured to convert the aforementioned second amplified signal (A2) into a second digital signal (D2_1), A second extractor (22) is configured to generate a second extracted signal (D1_1) obtained by extracting the low-frequency component of the first digital signal (D0), An adjustment unit (24) is configured to receive the second extraction signal (D1_1) and the second digital signal (D2_1) and generate a third digital signal (D1_2) and a fourth digital signal (D2_2), An adder (25) configured to generate a digital output signal (Dout) obtained by adding the third digital signal (D1_2) and the fourth digital signal (D2_2), Equipped with, The third digital signal (D1_2) is either the second extracted signal (D1_1) itself or a signal obtained by adjusting the magnification of the second extracted signal (D1_1). The fourth digital signal (D2_2) is either the second digital signal (D2_1) itself or a signal obtained by adjusting the magnification of the second digital signal (D2_1). Conversion circuit.

[0085] (Note 2) If the first AD converter (21) is configured to convert a signal based on the analog input signal (Ain) into the first digital signal (D0), If the first AD converter (21) is configured to convert a signal based on the first amplified signal (A1) into a first digital signal (D0), then the product of the multiplier of the third digital signal (D1_2) relative to the second extracted signal (D1_1) and the multiplier of the second digital signal (D2_1) relative to the fourth digital signal (D2_2) is equal to the second gain, and the first AD converter (21) is configured to convert a signal based on the first amplified signal (A1) into a first digital signal (D0), then the product of the multiplier of the third digital signal (D1_2) relative to the second extracted signal (D1_1) and the multiplier of the second digital signal (D2_1) relative to the fourth digital signal (D2_2) is equal to the multiplier of the second gain relative to the first gain. The conversion circuit described in Appendix 1.

[0086] (Note 3) Further comprising the aforementioned first amplifier (11), The conversion circuit according to Appendix 1 or 2, wherein the first AD converter (21) is configured to convert the first amplified signal (A1) into the first digital signal (D0).

[0087] (Note 4) The first extractor (12) includes a first smoother (121) configured to generate a first smoothed signal (A0_1) obtained by smoothing the analog input signal (Ain), A subtractor (122) is configured to generate the first extracted signal (A0) obtained by subtracting the first smoothed signal (A0_1) from the analog input signal (Ain), A conversion circuit as described in any of the appendices 1 to 3, comprising the features described herein.

[0088] (Note 5) The conversion circuit according to any one of the appendices 1 to 4, wherein the adjustment unit (24) comprises an attenuator (242) configured to generate the fourth digital signal (D2_2) obtained by multiplying the second digital signal (D2_1) by a predetermined attenuation ratio.

[0089] (Note 6) The conversion circuit according to any one of the appendices 1 to 5, wherein the adjustment unit (24) comprises an amplifier (241) configured to generate the third digital signal (D1_2) obtained by multiplying the first digital signal (D0) by a predetermined amplification ratio.

[0090] (Note 7) A first determination circuit (26) configured to determine whether the fourth digital signal (D2_2) is within a first predetermined range, Based on the determination result of the first determination circuit (26), If the fourth digital signal (D2_2) is within the first predetermined range, the digital output signal (Dout) is selected and output. A selector configured to select and output one of the following if the fourth digital signal (D2_2) is outside the first predetermined range: the first digital signal (D0), the third extracted signal obtained by extracting the first digital signal (D0) with a third extractor that has a higher cutoff frequency than the second extractor (22) and extracts low-frequency components, the amplified signal of the first digital signal, the amplified signal of the third extracted signal, or the signal obtained by extracting the amplified signal of the first digital signal with the third extractor, A conversion circuit as described in any of the appendices 1 to 6, comprising the features described herein.

[0091] (Note 8) The conversion circuit according to any one of the appendices 1 to 7, further comprising an add-on circuit (15) configured to supply an added signal (A4) obtained by adding a dither signal (A3) to the analog input signal (Ain) or the first amplified signal (A1) to the first AD converter (21).

[0092] (Note 9) The system includes a second determination circuit (14) configured to determine whether the second amplified signal (A2) is within a second predetermined range, The additional circuit (15) is determined based on the determination result of the second determination circuit (14). If the second amplified signal (A2) is within the second predetermined range, the summation signal is supplied to the first AD converter (21). The conversion circuit described in Appendix 8, configured to supply the analog input signal (Ain) or the first amplified signal (A1) to the first AD converter (21) if the second amplified signal (A2) is outside the second predetermined range.

[0093] (Note 10) Third AD converter (20), A conversion circuit according to any one of the appendices 1 to 9, wherein a switching circuit (SW1,2) configured to time-division switch between a signal based on the analog input signal (Ain) or a signal based on the first amplified signal (A1) and the second amplified signal (A2) and supply them to the third AD converter (20), functions as the first AD converter (21) and the second AD converter.

[0094] (Note 11) A first output unit configured to receive an analog input signal (Ain) and output a signal based on the analog input signal (Ain) or a signal based on a first amplified signal (A1) obtained by amplified the analog input signal (Ain) with a first gain by a first amplifier (11), A first extractor (12) is configured to generate a first extracted signal (A0) obtained by extracting the analog input signal (Ain), The system includes a second amplifier (13) configured to generate a second amplified signal (A2) obtained by amplifying the first extracted signal (A0) with a second gain greater than the first gain, and a second output section configured to output the second amplified signal (A2), An analog signal processing circuit equipped with the following features. [Explanation of Symbols]

[0095] 1A, 1B First signal processing circuit 2A, 2B, 2C Second signal processing circuit 11,13 Amplifier 12,22 extractor 121 LPF 122 Subtractor 123 HPF 14,26 Detection circuit 15 Dither generation circuit 20,21,23,104,200,201 ADC 24 Adjustment section 241 Amplifier 242 Attenuator 25 Adder 27 Selector 28 Processing Circuit 100 microcontrollers 101, 102, 103, SW1, SW2 switches 105, 106, 107, 108 PIO 300 Reference voltage source

Claims

1. A first AD converter configured to convert a signal based on an analog input signal or a signal based on a first amplified signal obtained by amplified the analog input signal with a first gain in a first amplifier into a first digital signal, A first extractor configured to generate a first extracted signal obtained by extracting the high-frequency components of the analog input signal, A second amplifier configured to generate a second amplified signal obtained by amplifying the first extracted signal with a second gain greater than the first gain, A second AD converter configured to convert the second amplified signal into a second digital signal, A second extractor configured to generate a second extracted signal obtained by extracting the low-frequency components of the first digital signal, An adjustment unit configured to generate a third digital signal and a fourth digital signal upon receiving the second extraction signal and the second digital signal, An adder configured to generate a digital output signal obtained by adding the third digital signal and the fourth digital signal, Equipped with, The third digital signal is the second extracted signal itself or a signal obtained by adjusting the magnification of the second extracted signal. The fourth digital signal is either the second digital signal itself or a signal obtained by adjusting the magnification of the second digital signal. Conversion circuit.

2. If the first AD converter is configured to convert a signal based on the analog input signal into the first digital signal, The product of the multiplier of the third digital signal relative to the second extracted signal and the multiplier of the second digital signal relative to the fourth digital signal is equal to the second gain. If the first AD converter is configured to convert a signal based on the first amplified signal into a first digital signal, The conversion circuit according to claim 1, wherein the product of the multiplier of the third digital signal with respect to the second extracted signal and the multiplier of the second digital signal with respect to the fourth digital signal is equal to the multiplier of the second gain with respect to the first gain.

3. Further comprising the first amplifier, The conversion circuit according to claim 1, wherein the first AD converter is configured to convert the first amplified signal into a first digital signal.

4. The first extractor includes a first smoother configured to generate a first smoothed signal obtained by smoothing the analog input signal, A subtractor configured to generate the first extracted signal obtained by subtracting the first smoothing signal from the analog input signal, The conversion circuit according to claim 1, comprising:

5. The conversion circuit according to claim 1, wherein the adjustment unit comprises an attenuator configured to generate the fourth digital signal obtained by multiplying the second digital signal by a predetermined attenuation ratio.

6. The conversion circuit according to claim 1, wherein the adjustment unit comprises an amplifier configured to generate the third digital signal obtained by multiplying the first digital signal by a predetermined amplification ratio.

7. A first determination circuit configured to determine whether the fourth digital signal is within a first predetermined range, Based on the determination result of the first determination circuit, If the fourth digital signal is within the first predetermined range, the digital output signal is selected and output. A selector configured to select and output one of the following if the fourth digital signal is outside the first predetermined range: the first digital signal, a third extracted signal obtained by extracting the first digital signal with a third extractor that has a higher cutoff frequency than the second extractor and extracts low-frequency components, an amplified signal of the first digital signal, an amplified signal of the third extracted signal, or a signal obtained by extracting the amplified signal of the first digital signal with the third extractor, A conversion circuit according to any one of claims 1 to 6, comprising:

8. The conversion circuit according to any one of claims 1 to 6, further comprising an additional circuit configured to supply to the first AD converter an added signal obtained by adding a dither signal to the analog input signal or the first amplified signal.

9. The system includes a second determination circuit configured to determine whether the second amplified signal is within a second predetermined range, The additional circuit is determined based on the determination result of the second determination circuit. If the second amplified signal is within the second predetermined range, the summed signal is supplied to the first AD converter. The conversion circuit according to claim 8, wherein if the second amplified signal is outside the second predetermined range, the analog input signal or the first amplified signal is supplied to the first AD converter.

10. The third AD converter, The conversion circuit according to claim 1, wherein a switching circuit configured to time-division switch between a signal based on the analog input signal or a signal based on the first amplified signal and the second amplified signal and supply them to the third AD converter, functions as the first AD converter and the second AD converter.

11. A first output unit configured to receive an analog input signal and output a signal based on the analog input signal or a signal based on a first amplified signal obtained by amplified the analog input signal with a first gain by a first amplifier, A first extractor configured to generate a first extracted signal obtained by extracting the analog input signal, A second amplifier is configured to generate a second amplified signal obtained by amplifying the first extracted signal with a second gain greater than the first gain, and a second output unit is configured to output the second amplified signal, An analog signal processing circuit equipped with the following features.

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