Printed circuit board

Abstract

One of the objectives of the present invention is to provide a printed circuit board that can realize circuits with fine line widths and spacing. [Solution] One embodiment of the present invention provides a printed circuit board comprising: a first insulating layer having a first surface and a second surface facing each other in the thickness direction; a second insulating layer disposed on the first surface side of the first insulating layer; a conductive via disposed in a through hole formed in the thickness direction in the first insulating layer; an internal conductor layer disposed between the inner wall of the through hole and the conductive via; and a first pad disposed on the first surface side of the first insulating layer, further away from the first insulating layer than the second insulating layer, and including a first conductor layer and a second conductor layer disposed on the first conductor layer, wherein the internal conductor layer forms an interface with the first conductor layer and makes contact with it.

Description

Technical Field

[0001] The present invention relates to a printed circuit board.

Background Art

[0002] Recently, in order to meet the trend of weight reduction and miniaturization of mobile devices, there is an increasingly high need to achieve thinner, lighter, shorter, and smaller printed circuit boards implemented therein. On the other hand, as mobile devices become thinner, lighter, shorter, and smaller, an undercut phenomenon occurs during the process of realizing a fine circuit, which may cause defects in the fine circuit. In response to the technical requirements for this, research has continued to improve reliability while realizing a circuit with a fine line width and interval.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One object of the present invention is to provide a printed circuit board capable of realizing a circuit with a fine line width and interval.

Means for Solving the Problems

[0004] As a method for solving the above problems, a novel structure of a printed circuit board will be proposed through an example. Specifically, a first insulating layer having a first surface and a second surface facing each other in the thickness direction, a second insulating layer disposed on the first surface side of the first insulating layer, a conductive via disposed in a through hole formed in the first insulating layer in the thickness direction, an internal conductor layer disposed between the inner wall of the through hole and the conductive via, and a first pad disposed on the first surface side of the first insulating layer, separated from the first insulating layer farther than the second insulating layer, and including a first conductor layer and a second conductor layer disposed on the first conductor layer, wherein the internal conductor layer forms an interface and contacts the first conductor layer.

[0005] In one embodiment, the upper surface of the internal conductor layer can contact the lower surface of the first conductor layer.

[0006] In one embodiment, the upper surface of the inner conductor layer and the upper surface of the second insulating layer can be coplane.

[0007] In one embodiment, the internal conductor layer does not need to cover the upper surface of the second insulating layer.

[0008] In one embodiment, the inner conductor layer does not need to be in contact with the second conductor layer.

[0009] In one embodiment, the internal conductor layer includes the first internal conductor layer and the second internal conductor layer, and the first internal conductor layer can be positioned closer to the inner wall of the through hole than the second internal conductor layer.

[0010] In one embodiment, the upper surfaces of the first internal conductor layer and the second internal conductor layer can come into contact with the lower surface of the first conductor layer.

[0011] In one embodiment, the upper surfaces of the first internal conductor layer and the second internal conductor layer can be on the same plane as the upper surface of the second insulating layer.

[0012] In one embodiment, the first internal conductor layer and the second internal conductor layer do not need to cover the upper surface of the second insulating layer.

[0013] In one embodiment, the first internal conductor layer and the second internal conductor layer do not need to be in contact with the second conductor layer.

[0014] In one embodiment, the conductive via may be configured to protrude beyond the first surface to the outside of the first insulating layer, beyond the internal conductor layer.

[0015] In one embodiment, the second conductor layer may have a shape in which the region corresponding to the conductive via protrudes.

[0016] In one embodiment, the conductive via may protrude outward from the first surface of the first insulating layer.

[0017] In one embodiment, the thickness of the first conductor layer may be 0.5 μm or more and 2 μm or less.

[0018] In one embodiment, the distance protruding laterally from the through hole of the first insulating layer in the first pad may be 25 μm or less.

Advantages of the Invention

[0019] In the case of the printed circuit board according to an example of the present invention, a circuit with a fine line width and interval can be provided.

Brief Description of the Drawings

[0020] [Figure 1] It is a block diagram schematically showing an example of an electronic device system. [Figure 2] It is a perspective view schematically showing an example of an electronic device. [Figure 3] It is a cross-sectional view schematically showing an example of a printed circuit board. [Figure 4] It shows an enlarged view of a partial area of FIG. 3. [Figure 5] It is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 6] It is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 7] It shows an example of a method for manufacturing a printed circuit board. [Figure 8] It shows an example of a method for manufacturing a printed circuit board. [Figure 9] It shows an example of a method for manufacturing a printed circuit board. [Figure 10] It shows an example of a method for manufacturing a printed circuit board. [Figure 11] It shows an example of a method for manufacturing a printed circuit board. [Figure 12] It shows an example of a method for manufacturing a printed circuit board. [Figure 13] An example of a printed circuit board manufacturing method is shown. [Figure 14] An example of a printed circuit board manufacturing method is shown. [Figure 15] An example of a printed circuit board manufacturing method is shown. [Modes for carrying out the invention]

[0021] Embodiments of the present invention will be described below with reference to specific embodiments and accompanying drawings. However, embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to give a more complete explanation of the present invention to a person of ordinary skill. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0022] [Electronic equipment] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0023] Referring to the drawing, the electronic device 1000 houses the main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0024] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). It goes without saying that other different forms of chip-related electronic components may also be included. Furthermore, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may also be in the form of a package that includes the chips and electronic components mentioned above.

[0025] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It also includes any other diverse wireless or wired standards and protocols. Furthermore, it goes without saying that network-related component 1030 may be combined with chip-related component 1020.

[0026] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCCs (multi-layer ceramic condensers), etc. However, they are not limited to these, and may also include other passive elements in chip component form used for various other applications. It goes without saying that other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0027] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the main board 1010 or not. Examples of other electronic components include, but are not limited to, audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. Needless to say, other electronic components used for various purposes may also be included, depending on the type of electronic device 1000.

[0028] The electronic device 1000 may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, or automobile. However, it is not limited to these, and it goes without saying that it may be any other electronic device that processes data.

[0029] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0030] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. Inside the smartphone 1100 is a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Other components, such as a camera module 1130 and / or a speaker 1140, may or may not be physically and / or electrically connected to the motherboard 1110. Some of the components 1120 may be the chip-related components described above, and may, for example, be a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board with the active and / or passive components built-in. On the other hand, it goes without saying that the electronic device is not necessarily limited to a smartphone 1100, but may be other electronic devices as described above.

[0031] [Printed circuit board] Figure 3 is a schematic cross-sectional view showing an example of a printed circuit board, and Figure 4 is an enlarged view of a part of Figure 3. Referring to Figures 3 and 4, the printed circuit board 100 according to this embodiment includes a first insulating layer 101, a second insulating layer 102, conductive vias 130, an internal conductor layer 140, and a first pad 110 including a first conductor layer 111 and a second conductor layer 112. Here, the internal conductor layer 140, which is placed in a through-hole of the first insulating layer 101, forms an interface with the first conductor layer 111 and makes contact. In other words, the internal conductor layer 140 and the first conductor layer 111 are not an integral structure but form an interface as separate components. With such a structure, the conductive vias 130, the first pad 110, etc. can be miniaturized and the pitch can be effectively reduced. The main components of the printed circuit board will be described in detail below.

[0032] The first insulating layer 101 may be a core insulating layer. The first insulating layer 101 may contain an insulating material. As the insulating material, insulating resins such as thermosetting resins such as epoxy resin or thermoplastic resins such as polyimide, or materials in which these resins are mixed with an inorganic filler such as silica, or resins impregnated with an inorganic filler into a core material such as glass fiber (glass cloth, glass fabric), for example, an insulating layer of CCL (copper clad laminate) may be used, but is not limited thereto. The first insulating layer 101 has a first surface S1 and a second surface S2 that face each other in the thickness direction (up and down direction with respect to the illustrated form). The first insulating layer 101 also has through holes (H in Figure 6) formed in the thickness direction. The first insulating layer 101 may be thicker than the second and third insulating layers 102 and 103 which are arranged on the first surface S1 and second surface S2 sides, respectively. In this case, the thickness of each layer can be measured using a scanning microscope or optical microscope, based on the polished or cut surface of the printed circuit board in the vertical direction. If the thickness is not constant, the relative thicknesses can be compared using the average value of the thickness of each object measured at any five points.

[0033] A second insulating layer 102 is arranged on the first surface S1 side of the first insulating layer 101. A third insulating layer 103 can be arranged on the second surface S2 side of the first insulating layer 101. Examples of insulating materials that may be included in the second and third insulating layers 102 and 103 include insulating resins such as thermosetting resins like epoxy resins or thermoplastic resins like polyimide, or materials in which these resins are mixed with inorganic fillers such as silica, or resins impregnated with inorganic fillers into a core material such as glass fiber, such as ABF (Ajinomoto Build-up Film) or prepreg, but are not limited to these. In addition, as further insulating layers, a fourth insulating layer 104 and a fifth insulating layer 105 may be arranged on the first surface S1 and second surface S2 sides of the first insulating layer 101, respectively, and the fourth insulating layer 104 and the fifth insulating layer 105 may be build-up insulating layers.

[0034] The conductive via 130 is positioned in the through-hole formed in the thickness direction of the first insulating layer 101, and the first pad 110 and the second pad 120 can be connected to each other by the conductive via 130. An internal conductor layer 140 is positioned between the inner wall of the through-hole in the first insulating layer 101 and the conductive via 130. In this case, the internal conductor layer 140 may include a plurality of conductor layers, for example, a first internal conductor layer 141 and a second internal conductor layer 142. Here, the first internal conductor layer 141 can be positioned closer to the inner wall of the through-hole in the first insulating layer 101 than the second internal conductor layer 142.

[0035] The conductive via 130 can contain metals such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof, and can perform various functions depending on the design. For example, the conductive via 130 can include ground vias, power vias, signal vias, etc. In one example, after the internal conductor layer 140 is formed by plating, the conductive via 130 can be formed by filling the through-hole with a plug. The conductive via 130 can have a substantially circular or elliptical shape based on its planar shape viewed from above. In addition, from the viewpoint of ensuring adhesion by increasing the specific surface area, the conductive via 130 may have a polygonal shape on a plane, or it may have a so-called flower shape in which multiple circles or ellipses overlap.

[0036] The first pad 110 is positioned on the first surface S1 side of the first insulating layer 101, further away from the first insulating layer 101 than the second insulating layer 102, and includes a first conductor layer 111 and a second conductor layer 112. A second pad 120 can be positioned on the second surface S2 side of the first insulating layer 101, and the second pad 120 may include a third conductor layer 121 and a fourth conductor layer 122. The second pad 120 can be implemented in the same form as the first pad 110, and although the structure of the first pad 110 and conductive via 130 on the first surface S1 side of the first insulating layer 101 will be described below, this description can also be applied to the second pad 120 and conductive via 130 positioned on the second surface S2 side of the first insulating layer 101.

[0037] In this embodiment, the internal conductor layer 140 forms an interface with the first conductor layer 111 and makes contact with it. More specifically, the upper surface of the internal conductor layer 140 can be in contact with the lower surface of the first conductor layer 111. Also, as shown in the illustrated form, the upper surface of the internal conductor layer 140 and the upper surface of the second insulating layer 102 can be coplane. Such a coplane structure can be obtained by performing a process such as polishing the portion of the internal conductor layer 140 that is located above the second insulating layer 102, as will be described later. More specifically, the internal conductor layer 140 does not have to cover the upper surface of the second insulating layer 102. Also, the internal conductor layer 140 does not have to be in contact with the second conductor layer 112.

[0038] If the internal conductor layer 140 includes first and second internal conductor layers 141 and 142, the upper surfaces of the first and second internal conductor layers 141 and 142 can be in contact with the lower surface of the first conductor layer 111. The upper surfaces of the first and second internal conductor layers 141 and 142 can be coplane with the upper surface of the second insulating layer 102. The first and second internal conductor layers 141 and 142 do not have to cover the upper surface of the second insulating layer 102. Furthermore, the first and second internal conductor layers 141 and 142 do not have to be in contact with the second conductor layer 112.

[0039] Thus, in this embodiment, the internal conductor layer 140 is formed in a separate process, for example, a separate plating process, rather than being formed integrally with the first conductor layer 111, thereby forming an interface and enabling contact between them. If the internal conductor layer 140 and the first conductor layer 111 were plated at the same time to achieve an integral structure, it may become difficult to realize a miniaturized circuit in the subsequent etching process. In this embodiment, after etching the region of the internal conductor layer 140 formed on the second insulating layer 102, a relatively thin first conductor layer 111 is formed, thereby enabling miniaturization of the first pad 110. In other words, by forming the internal conductor layer 140 separately from the first conductor layer 111, the first pad 110 can be formed to be thin and narrow even after etching, thereby allowing more conductive vias 130 to be placed in the same size space. Specifically, the thickness t of the first conductor layer 111 may be between 0.5 μm and 2 μm, and the distance d protruding laterally from the through-hole of the first insulating layer 101 in the first pad 110 can be reduced to a level of 25 μm or less. This makes it possible to reduce the size of the first pad 110 and improve the alignment with the conductive vias 130. Furthermore, the spacing between the conductive vias 130 can also be miniaturized; for example, the spacing between adjacent conductive vias 130 can be reduced to a level of 300 μm or less.

[0040] On the other hand, as shown in the modified example in Figure 5, the conductive via 130 may protrude further from the first surface S1 to the outside of the first insulating layer 101 than the internal conductor layer 140. In this case, as shown in the modified example in Figure 6, the second conductor layer 112 may have a protruding region corresponding to the conductive via 130. Also, the conductive via 130 may protrude outward from the first surface S1 of the first insulating layer 101. When the conductive via 130 has a protruding structure as in the modified example, the electrical and physical contact with the first pad 110 can be improved.

[0041] Furthermore, to describe the further configuration of the printed circuit board 100, conductor patterns 151 and 161 can be placed on the first pad 110 and the second pad 120, respectively, and conductor patterns can also be placed at the same level as the first pad 110 and the second pad 120. In this case, vias 152 and 162 can be provided to connect the first and second pads 110 and 120 to the conductor patterns 151 and 161, respectively.

[0042] The following describes an example of a method for manufacturing a printed circuit board, with reference to Figures 7 to 15. First, referring to Figures 7 and 8, a first insulating layer 101 is provided, and a second insulating layer 102 and a third insulating layer 103 are placed on the first surface S1 and second surface S2 of the first insulating layer 101, respectively. Then, through holes H are formed that penetrate through this in the thickness direction. As an example, the second insulating layer 102 and the third insulating layer 103 can be formed by removing copper foil from both sides of a CCL (Copper Clad Laminate) and then laminating ABF on both sides of the remaining first insulating layer 101. The through holes H in the first insulating layer 101 can be formed by an appropriate processing method, for example, laser processing, and then a desmear process can be performed.

[0043] Next, as shown in Figure 9, an internal conductor layer 140 is formed in the through-hole H of the first insulating layer 101. The internal conductor layer 140 can also be formed on the first surface S1 and the second surface S2 of the first insulating layer 101, in addition to the through-hole H. The internal conductor layer 140 may include a first internal conductor layer 141 and a second internal conductor layer 142. In this case, the first internal conductor layer 141 can be formed by electroless plating, and the second internal conductor layer 142 can be formed by electrolytic plating. Then, referring to Figure 10, a conductive via 130 is formed by a process such as filling the through-hole H of the first insulating layer 101 with a plug. Other plating processes that can be used in the art can also be used. After that, if necessary, the portion of the conductive via 130 that protrudes outward can be removed by a polishing process, as shown in the form in Figure 11.

[0044] Next, as shown in Figure 12, at least a portion of the area covering the first surface S1 and the second surface S2 of the first insulating layer 101 in the internal conductor layer 140 is removed. In this process, the upper surface of the second insulating layer 102 and the upper surface of the internal conductor layer 140 can be made coplane. Alternatively, the conductive via 130 can be further polished to remove the area protruding in the vertical direction. Alternatively, the area protruding in the vertical direction from the conductive via 130 can be left as is, in which case the structure of Figure 5 can be obtained. Referring to Figures 13 and 14, the first and second conductor layers 111, 112 and the third and fourth conductor layers 121, 122 are then formed. Here, as an example of the process, the second conductor layer 112 and the fourth conductor layer 122 may be formed by forming a mask layer 250 and then performing pattern plating on the open area. Subsequently, as shown in Figure 15, the mask layer 250 is removed, and parts of the first, second, third, and fourth conductor layers 111, 112, 121, and 122 are removed by etching to obtain the first pad 110 and the second pad 120 having the structure described above. After that, a printed circuit board of the above configuration can be obtained through an appropriate build-up process.

[0045] In this invention, "on a cross-section" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. Furthermore, "on a plane" can mean the shape when the object is cut horizontally, or the planar shape when the object is viewed from above or below.

[0046] In this invention, terms such as "upper side," "upper part," and "upper surface" are used for convenience to mean the direction toward the surface on which electronic components can be mounted, based on the cross-section of the drawing, while terms such as "lower side," "lower part," and "lower surface" are used to mean the opposite direction. However, this is merely a definition of direction for the sake of explanation, and it goes without saying that the scope of rights in the patent claims is not particularly limited by such descriptions of direction.

[0047] In this invention, "connected" is a concept that includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept that includes both cases where they are physically connected and cases where they are not connected. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, within the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0048] The expression "example" as used in this invention does not mean that each embodiment is the same as another, but is provided to highlight and illustrate the unique and distinct features of each. However, the examples presented above do not preclude their realization in combination with features of other examples. For example, even if a matter described in a particular example is not described in another example, it can be understood as a description related to that other example, unless there is a description in the other example that contradicts or is contrary to that description.

[0049] The terms used in this invention are used merely to illustrate an example and are not intended to limit the invention. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0050] 1000:Electronic equipment 1010: Mainboard 1020: Chip-related components 1030: Network-related components 1040: Other parts 1050: Camera 1060: Antenna 1070: Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts Package 1130: Camera module 1140: Speaker 101: First insulating layer 102: Second insulating layer 103: Third insulating layer 110, 120: Pad 111, 112, 121, 122: Conductor layer 130: Conductive via 140: Inner conductor layer 141: First inner conductor layer 142: Second inner conductor layer 151, 161: Conductor patterns 152, 162: Beer

Claims

1. A first insulating layer having a first surface and a second surface facing each other in the thickness direction, A second insulating layer is disposed on the first surface side of the first insulating layer, A conductive via is disposed in a through-hole formed in the thickness direction in the first insulating layer, An internal conductor layer is disposed between the inner wall of the through hole and the conductive via, The first insulating layer includes a first pad, which is positioned on the first surface side of the first insulating layer, at a distance from the first insulating layer than from the second insulating layer, and includes a first conductor layer and a second conductor layer positioned on the first conductor layer, A printed circuit board in which the internal conductor layer forms an interface with and contacts the first conductor layer.

2. The printed circuit board according to claim 1, wherein the upper surface of the internal conductor layer is in contact with the lower surface of the first conductor layer.

3. The printed circuit board according to claim 2, wherein the upper surface of the internal conductor layer and the upper surface of the second insulating layer are coplane.

4. The printed circuit board according to claim 2, wherein the internal conductor layer does not cover the upper surface of the second insulating layer.

5. The printed circuit board according to claim 1, wherein the internal conductor layer does not come into contact with the second conductor layer.

6. The printed circuit board according to claim 1, wherein the internal conductor layer includes a first internal conductor layer and a second internal conductor layer, and the first internal conductor layer is positioned closer to the inner wall of the through hole than the second internal conductor layer.

7. The printed circuit board according to claim 6, wherein the upper surfaces of the first internal conductor layer and the second internal conductor layer are in contact with the lower surface of the first conductor layer.

8. The printed circuit board according to claim 7, wherein the upper surfaces of the first internal conductor layer and the second internal conductor layer and the upper surface of the second insulating layer are coplane.

9. The printed circuit board according to claim 7, wherein the first internal conductor layer and the second internal conductor layer do not cover the upper surface of the second insulating layer.

10. The printed circuit board according to claim 7, wherein the first internal conductor layer and the second internal conductor layer do not come into contact with the second conductor layer.

11. The printed circuit board according to claim 1, wherein the conductive vias protrude from the first surface to the outside of the first insulating layer more than the internal conductor layer.

12. The printed circuit board according to claim 11, wherein the second conductor layer has a shape in which the region corresponding to the conductive via protrudes.

13. The printed circuit board according to claim 12, wherein the conductive vias protrude outward from the first surface of the first insulating layer.

14. The printed circuit board according to claim 1, wherein the thickness of the first conductor layer is 0.5 μm or more and 2 μm or less.

15. The printed circuit board according to claim 1, wherein the distance of the first pad protruding laterally from the through-hole of the first insulating layer is 25 μm or less.

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