Full Nanosheet Air Gap Spacer

Abstract

We provide nanosheet transistors that reduce parasitic capacitance. [Solution] The nanosheet transistor includes a spacer region 156 between a high-k metal gate stack 142 and an epitaxial layer 136. The spacer region includes a first nanosheet stack having a plurality of nanosheets 102. The spacer region includes an internal spacer region 158 positioned between nanosheets, and a lateral subway region 160 located along the edge of a nanosheet, the internal spacer region, and another nanosheet.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor device manufacturing, and more particularly to manufacturing nanosheet transistors having stacked air gaps between stacked sheets and side sub-way air gaps along the edges.

Background Art

[0002] As semiconductor microchips and integrated circuits become smaller, vertically stacked semiconductor nanosheets are increasingly being used. A nanosheet is a two-dimensional nanostructure whose vertical thickness is substantially smaller than its width. Semiconductor nanosheets are considered a viable option for reducing the size of semiconductor devices. By vertically stacking semiconductor nanosheets, the area efficiency can be improved and the drive current can be increased within a given layout.

[0003] A general process flow for forming semiconductor nanosheets includes forming a material stack that includes a sacrificial layer of silicon germanium between silicon nanosheets. After removing the sacrificial layer, vertically stacked, suspended silicon nanosheets are obtained. Functional gate structures can be formed above and below each silicon nanosheet.

Summary of the Invention

[0004] Aspects of one embodiment of the present invention include a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor can include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region can include a first nanosheet stack having a first nanosheet and a second nanosheet. The spacer region can include an internal spacer region disposed between the first nanosheet and the second nanosheet, and a side sub-way region located along the edges of the first nanosheet, the internal spacer region, and the second nanosheet.

[0005] An embodiment of one invention includes a method for manufacturing a nanosheet transistor. This method may include forming a nanosheet stack comprising a sacrificial internal spacer and a nanosheet; forming an epitaxial layer adjacent to the nanosheet stack; recessing the epitaxial layer to expose the sacrificial internal spacer at the corner etched portion; and removing the sacrificial internal spacer to form an air gap around the nanosheet.

[0006] An embodiment of one invention includes a nanosheet transistor for reducing parasitic capacitance. The nanosheet transistor may include a spacer region between a high-k metal gate and an epitaxial layer. The spacer region may include a first nanosheet stack comprising a first nanosheet and a second nanosheet, and an internal spacer region between the first nanosheet and the second nanosheet. The internal spacer region may include an air gap across the width of the first nanosheet and the second nanosheet. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows a nanosheet transistor in the manufacturing stage of a processing method according to one embodiment of the present invention. [Figure 2] Figure 1 is a cross-sectional side view of a nanosheet transistor, where similar reference numbers refer to similar features in subsequent manufacturing stages of the processing method. [Figure 3] Figure 1 is a cross-sectional side view of a nanosheet transistor, where similar reference numbers in the previous figure refer to similar features in subsequent manufacturing stages of the processing method. [Figure 4] Figure 7 is a schematic top view of a nanosheet transistor during the manufacturing process, where similar reference numbers in the previous figure refer to similar features. [Figure 5] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 6] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 7] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 8] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 9] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 10] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 11] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 12] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 13] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 14]Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 15] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 16] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 17] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 18] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 19] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Figure 20] Figure 4 shows four cross-sectional side views of the nanosheet transistor at each position, where similar reference numbers in the previous figure refer to the same features and represent the manufacturing stage of the processing method following the immediately preceding figure. [Modes for carrying out the invention]

[0008] The following detailed description refers to the accompanying drawings illustrating specific examples of embodiments of the present invention. These embodiments are described in sufficient detail so that those skilled in the art can implement them, and it should be understood that other embodiments may be utilized, and structural, logical, and electrical modifications may be made without departing from the described embodiments. Therefore, the following detailed description should not be construed as restrictive, and the embodiments included are defined by the appended claims.

[0009] In relation to the manufacture of transistors and integrated circuits, the primary surface refers to the surface of a semiconductor layer on which multiple transistors are manufactured, for example, by a planar process, within and around that layer. As used herein, the term “perpendicular” means substantially orthogonal to the primary surface. Typically, the primary surface is aligned with the plane of the single-crystal silicon layer on which the transistor device is manufactured.

[0010] Improvements in transistor device design have made it possible to move feature sizes into the deep submicron and nanometer regions. However, these smaller feature sizes can have detrimental effects on the operation of transistor devices, even on issues that are normally minor. For example, parasitic capacitance, particularly fringe parasitic capacitance between the gate and source / drain, can account for a larger proportion of the total capacitance in smaller transistor devices. A high proportion of parasitic capacitance can have a serious impact on the transient response of the device.

[0011] To reduce parasitic capacitance, transistor devices may include spacers made of a low dielectric constant material in designated areas. In some embodiments, since air has a very low dielectric constant, the spacers may be formed using an air gap. However, if the air gap is not properly formed, any benefits that air offers may not be realized. For example, if the epitaxially grown source / drain region grows within an air gap region, the performance of the transistor device will degrade. Therefore, the embodiments described below include a spacer region having an air gap formed after the epitaxial region has been grown.

[0012] Figure 1 shows a nanosheet transistor 100 in the manufacturing stage of a processing method according to one embodiment of the present invention. The nanosheet transistor 100 includes nanosheets 102 and a sacrificial semiconductor layer 104 formed alternately in a vertical layer stack 105 on a substrate 106. The substrate 106 includes shallow trench isolation 108, which may be an embedded oxide (BOX) layer of a semiconductor-on-insulator (SOI) substrate or a dielectric isolation of a bulk substrate. The nanosheets 102 (i.e., nanosheets or nanowires) may be made of a semiconductor material such as silicon (Si). The sacrificial semiconductor layer 104 may be made of a semiconductor material such as silicon-germanium (SiGe). The nanosheets 102 and the sacrificial semiconductor layer 104 may be formed by an epitaxial growth process, and at least the sacrificial semiconductor layer 104 may not be doped. The semiconductor material of the sacrificial semiconductor layer 104 is selected so as to be cleanly removed from the semiconductor material of the nanosheets 102. As used herein, the term “clean” in relation to a material removal process (e.g., etching) indicates that, with the appropriate selection of an etching solution, the material removal rate (i.e., etching rate) of the material in question exceeds the removal rate of at least one other material exposed to the material removal process. The sacrificial semiconductor layer 104 may include a bottom sacrificial semiconductor layer 104a with a different silicon-germanium ratio, thereby allowing the manufacturing operator to cleanly remove the bottom sacrificial layer 104a without removing other sacrificial semiconductor layers 104 or nanosheets 102. The number of nanosheets 102 and sacrificial semiconductor layers 104 may differ from the number shown in the typical embodiment (more or fewer layers).

[0013] The hard mask 110 is formed on the top surface of the layer stack 105 including the nanosheet 102 and the sacrificial semiconductor layer 104. The hard mask 110 may be composed of a hard mask material such as silicon nitride, which is deposited (e.g., by chemical vapor deposition (CVD)) and patterned using a litho-patterning process. By this patterning, the nanosheet transistor 100 can be formed as the fin 112, and the nanosheet 102 and the sacrificial semiconductor layer 104 are the trimmed layer stack 105 where the portions of the nanosheet 102 and the sacrificial semiconductor layer 104 alternate. The fin 112 protrudes in a direction perpendicular to the main surface 114 of the shallow trench isolation 108. The hard mask 110 functions as an etching mask during the etching process for forming the fin 112.

[0014] FIG. 2 shows a cross-sectional side view of the nanosheet transistor 100 of FIG. 1, with like reference numerals referring to like features and being in a subsequent manufacturing stage of the processing method. In FIG. 2, the nanosheet transistor 100 has side sacrificial bodies 116 formed on both sides of the fin 112. The side sacrificial bodies 116 can be formed using atomic layer deposition (ALD) and anisotropic etching. Additionally or alternatively, the side sacrificial bodies 116 may be formed epitaxially. The side sacrificial bodies 116 can be formed using the same material as the sacrificial layer 104. For example, the side sacrificial bodies 116 and the sacrificial layer 104 may be formed of silicon-germanium having the same proportion of germanium (e.g., 25%, 30%, 35%, 40%, or 45%). The bottom sacrificial semiconductor layer 104a can also include silicon-germanium, but can include a different proportion (e.g., 50 percent, 55 percent, 60 percent, 65 percent, or 70 percent). The side sacrificial bodies 116 may be formed using a material different from the sacrificial layer 104.

[0015] FIG. 3 shows a cross-sectional side view of the nanosheet transistor 100 of FIG. 1, with the same reference numbers as in the previous figure referring to the same features and being at a subsequent manufacturing stage of the processing method. In FIG. 3, the nanosheet transistor 100 has a blocking mask 118 that protects the other side sacrificial body 116 while the one side sacrificial body 116 is etched for each fin 112. By etching the one side sacrificial body 116, the nanosheet 102 and the sacrificial semiconductor layer 104 on the first edge 120a are exposed. The material of 118 can be a conventional organic thin film used in a lithography process such as OPL.

[0016] FIG. 4 shows a schematic top view of the nanosheet transistor 100 at the manufacturing stage of FIG. 7, with the same reference numbers as in the previous figure referring to the same features. FIG. 4 also shows the cross-sectional lines, namely X, X', Y, and Y', for the cross-sectional views of the subsequent figures described in this application. Line X and line X' show cross-sectional views along the x-axis, and line Y and line Y' show cross-sectional views along the y-axis. The X cross-sectional view is along the longitudinal direction of the stack 105 of the nanosheet 102 and the sacrificial layer 104. The X' cross-sectional view is along the longitudinal direction of the side sacrificial body 116 that will ultimately become the side sub-channel region. The Y cross-sectional view crosses the stack 105 of the nanosheet 102 and the sacrificial layer 104 under the gate spacer region in the width direction (the cross-sectional views of FIGS. 1-3). The Y' cross-sectional view is also in the width direction but is at a position that will ultimately become the source / drain region of the device, as shown in detail below.

[0017] Figure 5 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figures refer to similar features in the manufacturing stage of the processing method following Figure 3. Figure 5 also includes cross-sectional lines in Figure X' showing the locations of cross-sections Y and Y', and cross-sectional lines in Figure Y showing the locations of cross-sections X and X'. In Figure 5, the blocking mask 118 and nanosheet hard mask 110 have been removed. Here, the nanosheet transistor 100 includes a dummy gate structure 122 having a top hard mask 122a and a bottom dummy gate structure 122b (i.e., shown only in partial Figures X and X'). Since the dummy gate structure 122 is removed before the manufacturing of the nanosheet transistor 100 is complete, the dummy gate structure 122 can be formed from any type of hard mask material. The bottom dummy gate structure 122b may include a thin silicon oxide layer and amorphous silicon subsequently patterned by conventional lithography and etching processes.

[0018] Figure 6 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figures refer to similar features and represent the manufacturing stage of the processing method following Figure 5. Figure 6 also shows that the bottom sacrificial semiconductor layer 104a includes a gap 124 that is cleanly etched from the substrate 106, the side sacrificial body 116, and the remaining sacrificial semiconductor layer 104. The nanosheet 102 and the sacrificial semiconductor layer 104 are held in place at the second edge 120b by the side sacrificial body 116, which is attached to a shallow trench isolation 108.

[0019] Figure 7 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figures refer to similar features and represent the manufacturing stage of the processing method following Figure 6. Figure 7 also includes spacer dielectrics 126 (e.g., silicon oxide, silicon nitride) formed around the dummy gate structure 122, as well as around the stack 105 of nanosheets 102 and sacrificial semiconductor layer 104. The spacer dielectrics 126 are also formed beneath the sacrificial semiconductor layer 104, in the position where the bottom sacrificial layer 104a was before it was removed. As shown in partial Figure Y', the spacer dielectrics 126 do not fill all of the interlayer dielectric region 128 between the first stack 105-1 and the second stack 105-2. However, in the region immediately surrounding the dummy gate structure 122, the space between the stacks 105 is filled with spacer dielectrics 126.

[0020] Figure 8 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figures refer to similar features and represent the manufacturing stage of the processing method following Figure 7. Figure 8 shows the segmentation of the fin 112 and the depression of the sacrificial semiconductor layer 104. As shown in partial Figure Y', when the entire stack 105 (nanosheet 102, sacrificial semiconductor layer 104, and lateral sacrificial 116) is etched down to the main surface 114 and shallow trench isolation 108 of the substrate 106 in the region between the dummy gate structure 122, the fin 112 is segmented. This segmentation creates a separation 130 between the first stack 105a and the second stack 105b (see partial Figure X). The nanosheet 102 under the spacer dielectric 126 between stacks 105a / 105b is not etched, but the sacrificial semiconductor layer 104 is depressed by a depression distance 132 corresponding to the thickness of the spacer dielectric 126 covering the dummy gate structure 122. As shown in partial figure X', the lateral sacrificial body 116 beneath the dummy gate structure 122 is etched only by a recess distance 132, but not completely.

[0021] Figure 9 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figures refer to similar features and represent the manufacturing stages of the processing method following Figure 8. Figure 9 shows the formation of the sacrificial internal spacer 134 and the growth of the epitaxial layer 136. The sacrificial internal spacer 134 may contain titanium oxide, titanium nitride, or other materials and is formed around the recessed area of ​​the sacrificial semiconductor layer 104. After the sacrificial internal spacer 134 is formed, the epitaxial layer 136 is formed between stack 105a and stack 105b.

[0022] Figure 10 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figures refer to similar features and represent the manufacturing stage of the processing method following Figure 9. Figure 10 shows the deposition of an interlayer dielectric (ILD) 138 (e.g., silicon oxide, or other dielectric material). The ILD 138 is deposited between dummy gate structures 122 in a portion of the epitaxial layer 136 (see parts X and X') and in a portion of the main surface 114 (see part Y'). The nanosheet transistor 100 is then planarized onto a poly surface 140. The poly surface 140 is positioned at a level that exposes the bottom dummy gate structure 122b.

[0023] Figure 11 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 10. Figure 11 shows the stage where the dummy gate structure 122 (i.e., the bottom dummy gate structure 122b) has been completely removed, the sacrificial semiconductor layer 104 and the side sacrificial bodies 116 have been released, and the high-k metal gate (HKMG) stack 142 has replaced the sacrificial semiconductor layer 104, the side sacrificial bodies 116, and a portion of the bottom dummy gate structure 122b. After the replacement of the HKMG stack 142, the top of the HKMG stack 142, including the spacer dielectric 126, is recessed and refilled with dielectric capping material 144 (i.e., self-aligned contact (SAC) cap or sacrificial cap).

[0024] Figure 12 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 11. Figure 12 shows a contact cut 148 defining a region in the ILD 138 above the epitaxial layer 136 where no S / D contacts exist. The contact cut 148 may be completed using reactive ion etching (RIE). The contact cut 148 etches the ILD 138 without etching the spacer dielectric 126 or the epitaxial layer 136. Figure 12 intentionally shows that the placement of the contact cut 148 cannot be ideal (i.e., some misalignment may occur during the lithography process), with the left edge of the contact cut resting on the epitaxial layer 136 and the right edge of the contact cut resting on the epi-spacer dielectric 126. Embodiments disclosed herein can form an air gap even under an ideal or misaligned contact cut.

[0025] Figure 13 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 12. Figure 13 shows the spacer dielectric 126 etched within the contact cut 148. The spacer pull-down area 150 is indicated. The spacer pull-down area 150 is the contact area. The epitaxial layer 136 is exposed at both the left and right edges of the cut area.

[0026] Figure 14 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers from the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 13. Figure 14 shows a corner etched area 152 on the epitaxial layer 136. The corner etched area 152 is located in the region exposed by the contact cut 148 and the spacer pull-down region 150. The corner etched area 152 exposes the sacrificial internal spacer 134, as shown in partial Figure X', and the spacer dielectric 126 is above the top nanosheet 102a, as shown in partial Figure Y.

[0027] Figure 15 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 14. Figure 15 shows the air gap 154 ​​in the spacer region 156 between the HKMG stack 142 and the epitaxial layer 136. The air gap 154 ​​is formed when the sacrificial internal spacer 134 is cleanly etched from the nanosheet transistor 100. The sacrificial internal spacer 134 is made of a material that can be etched with minimal impact on the rest of the nanosheet transistor 100. As described with respect to Figure 14, etching of the sacrificial internal spacer 134 is made possible and completed through the corner etch area 152 of the epitaxial layer 136. For example, a reactive chemical etching of the sacrificial internal spacer 134 can come into contact with the sacrificial internal spacer 134 through the corner etch area 152 and continue etching until the entire sacrificial internal spacer 134 is removed. Therefore, the air gap 154 ​​includes an internal spacer region 158 between the nanosheets 102, and the internal spacer region 158 may include the entire width from the first edge 120a to the second edge 120b of the nanosheet 102, such that the internal spacer region consists only of the air gap 154. The air gap 154 ​​may also include a lateral subway region 160 along the second edge 120b of the nanosheet 102 and the internal spacer region 158.

[0028] Figure 16 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 15. Figure 16 shows a non-formal dielectric deposit 162, such as silicon nitride filler, that closes the corner etched area 152 and the spacer pull-down region 150 so that the air gap 154 ​​is no longer exposed. As shown, the non-formal dielectric deposit 162 does not flow into the air gap 154, but only fills the corner etched area 152 and the spacer pull-down region 150. Therefore, the air gap 154 ​​is completed after the growth of the epitaxial layer 136, making it less likely that the epitaxial growth will adversely affect the parasitic capacitance of the nanosheet transistor 100. An example of the formation of the non-formal dielectric deposit 162 may be using high-density plasma (HDP) deposition.

[0029] Figure 17 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 16. Figure 17 shows a dielectric deposit overfill 164 in which the contact cuts 148 are filled up to the surface 140 of the SAC cap. The nanosheet transistor 100 may then be planarized up to the surface 140 of the SAC cap. The contact cuts 148 may be filled using, for example, chemical vapor deposition (QV) technology.

[0030] Figure 18 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 17. Figure 18 shows the etch-back of ILD 138 from trench region 166. ILD 138 is cleanly etched back without etching the spacer dielectric 126, sacrificial cap 144, epitaxial layer 136, or dielectric deposit overfill 164.

[0031] Figure 19 shows four cross-sectional side views of the nanosheet transistor 100 at the locations shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 18. Figure 19 shows metal liner deposition 168 for silicide formation. An example of a metal liner may be titanium deposited by radiofrequency physical vapor deposition (RFPVD).

[0032] Figure 20 shows four cross-sectional side views of the nanosheet transistor 100 at the positions shown in Figure 4, where similar reference numbers in the previous figure refer to similar features and represent the manufacturing stage of the processing method following Figure 19. Figure 20 shows a trench region 166 filled with trench contacts 170 around a dielectric deposit overfill 164, enabling the nanosheet transistor 100 to operate. In operation, the nanosheet transistor 100 exhibits reduced parasitic capacitance due to a spacer region 156 located between the HKMG stack 142 and the epitaxial layer 136. The spacer region 156 includes a nanosheet stack 105 consisting of nanosheets 102. Between the nanosheets 102, the stack 105 includes an internal spacer region 158 and a lateral subway region 160. The lateral subway region 160 is located along the second edge 120b of the nanosheet 102 and the internal spacer region 158.

[0033] The methods described above are used for manufacturing integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer either as bare dies in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with either surface-mounted or embedded-mounted wiring, or both). In either case, the chips may be integrated with other chips, individual circuit elements, or other signal processing devices, or combinations thereof, as part of either an intermediate or final product.

[0034] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention. The terms used herein have been selected to best describe the principles of the embodiments, their practical applications or technical improvements to the art available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing nanosheet transistors. Forming a nanosheet stack comprising sacrificial internal spacers and nanosheets, and forming an epitaxial layer adjacent to the nanosheet stack, The epitaxial layer is recessed to expose the sacrificial internal spacer at the corner etch portion, and the sacrificial internal spacer is removed to form an air gap around the nanosheet. Methods that include...

2. The interlayer dielectric layer is penetrated to open the contact cut, the spacer within the contact cut is etched, and the epitaxial layer is exposed. The method according to claim 1, including the method described in claim 1.

3. The method according to claim 1, comprising forming a spacer between the nanosheet stack and the substrate.

4. The method according to claim 1, wherein the air gap includes a lateral subway region along the edge of the nanosheet.

5. The method according to claim 1, comprising filling the corner etched portion with a non-conformal dielectric deposit.

6. The method according to claim 5, comprising forming trench contacts around the non-conformal dielectric deposit.

7. The method according to claim 1, wherein removing the sacrificial internal spacer includes etching the sacrificial internal spacer through the corner etch portion.

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