Nitride semiconductor equipment

Abstract

It suppresses voltage surges and voltage noise during switching. [Solution] The nitride semiconductor device 10 includes a conductive substrate 11, a nitride semiconductor layer 15 located on the conductive substrate 11, a transistor 100 that includes a part of the nitride semiconductor layer 15 and has a gate electrode 24, a source electrode 28, and a drain electrode 30 located on the nitride semiconductor layer 15, and a snubber circuit 200 connected in parallel to the source electrode 28 and the drain electrode 30. The conductive substrate 11 is electrically connected to the source electrode 28. The snubber circuit 200 includes a snubber resistor 201 located on the nitride semiconductor layer 15 and electrically connected to the drain electrode 30, and a snubber capacitor 210 electrically connected to the snubber resistor 201 and the conductive substrate 11 and including parasitic capacitance formed by the nitride semiconductor layer 15.

Description

[Technical Field]

[0001] This invention relates to nitride semiconductor devices. [Background technology]

[0002] Currently, the commercialization of high-electron-mobility transistors (HEMTs) using group III nitride semiconductors such as gallium nitride (GaN) (hereinafter sometimes simply referred to as "nitride semiconductors") is progressing. HEMTs use a two-dimensional electron gas formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices utilizing HEMTs are recognized as devices that enable lower on-resistance and higher frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transport layer composed of a gallium nitride (GaN) layer, and an electron supply layer composed of an aluminum gallium nitride (AlGaN) layer. In the electron transport layer, a two-dimensional electron gas is formed near the interface of the heterojunction between the electron transport layer and the electron supply layer. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2017-73506

[0005] [overview] High-speed switching elements such as nitride semiconductors (HEMTs) offer high conversion efficiency due to low switching losses. However, as switching speeds increase and switching transition times shorten, voltage surges and voltage noise are more likely to occur during switching.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a conductive substrate, a nitride semiconductor layer located on the conductive substrate, a transistor including a portion of the nitride semiconductor layer and having a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer, and a snubber circuit connected in parallel to the source electrode and the drain electrode, wherein the conductive substrate is electrically connected to the source electrode, and the snubber circuit includes a snubber resistor located on the nitride semiconductor layer and electrically connected to the drain electrode, and a snubber capacitor electrically connected to the snubber resistor and the conductive substrate and including a parasitic capacitance formed by the nitride semiconductor layer. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] Figure 2 is an enlarged plan view of the nitride semiconductor device shown in Figure 1. [Figure 3] Figure 3 is a cross-sectional view taken along the line F3-F3 in Figure 2. [Figure 4] Figure 4 is a circuit diagram of a transistor and snubber circuit. [Figure 5] Figure 5 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device shown in Figure 2. [Figure 6] Figure 6 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 6. [Figure 8] Figure 8 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 7. [Figure 9] Figure 9 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 8. [Figure 10] Figure 10 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 9. [Figure 11] Figure 11 is a schematic cross-sectional view showing an exemplary manufacturing process following Figure 10. [Figure 12]FIG. 12 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 11. [Figure 13] FIG. 13 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 12. [Figure 14] FIG. 14 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 13. [Figure 15] FIG. 15 is a schematic cross-sectional view showing an exemplary manufacturing process following FIG. 14. [Figure 16] FIG. 16 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a schematic plan view of an exemplary nitride semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view taken along line F18-F18 of FIG. 17.

[0008] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to a fixed scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0009] In the present disclosure, terms such as "first", "second", "third", etc. are used to clearly distinguish the components of an object and do not rank the object. Also, the expression "at least one" used in the present disclosure means one or more of a plurality of desired options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0010] The following detailed description includes devices, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0011] [First Embodiment] [Schematic Structure of Nitride Semiconductor Device] Referring to FIGS. 1 to 3, a nitride semiconductor device 10 according to the first embodiment will be described.

[0012] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to the first embodiment. FIG. 2 shows a schematic planar structure in which a part of the internal structure of the nitride semiconductor device 10 in FIG. 1 is enlarged. FIG. 3 shows a schematic cross-sectional structure obtained by cutting the nitride semiconductor device 10 along the F3-F3 line in FIG. 2.

[0013] The nitride semiconductor device 10 is used, for example, as a switching element with an RC snubber circuit. As shown in FIG. 1, the nitride semiconductor device 10 is, for example, a chip formed in a rectangular flat plate shape. The nitride semiconductor device 10 includes a chip upper surface 10A and a chip lower surface 10B (see FIG. 3). Further, the nitride semiconductor device 10 includes four chip side surfaces 10C that connect the chip upper surface 10A and the chip lower surface 10B.

[0014] In a plan view, the nitride semiconductor device 10 includes an active region A1 in which a transistor 100 described later is formed, and an inactive region A2 in which the transistor 100 is not formed. In one example, the active region A1 is the region inside the broken line in FIG. 1 and is located at the central portion of the chip upper surface 10A. The inactive region A2 is the region outside the broken line in FIG. 1, is located on the outer peripheral side of the chip upper surface 10A, and has a frame shape surrounding the active region A1.

[0015] The nitride semiconductor device 10 includes at least one gate pad 102, at least one source pad 103, and at least one drain pad 104. The gate pad 102, source pad 103, and drain pad 104 are electrically connected to the transistor 100. The gate pad 102, source pad 103, and drain pad 104 are formed on the top surface 10A of the nitride semiconductor device 10. The gate pad 102, source pad 103, and drain pad 104 can be used as external connection terminals of the nitride semiconductor device 10.

[0016] Each of the gate pad 102, source pad 103, and drain pad 104 is formed in a rectangular shape, for example, in a plan view. In one example, the gate pad 102 is located at one corner of the top surface 10A of the chip, for example. Also, the gate pad 102 is positioned in the inactive region A2 in a plan view. The source pad 103 and drain pad 104 are arranged alternately. Note that the shapes of each of the gate pad 102, source pad 103, and drain pad 104 in a plan view can be arbitrarily changed. Also, the arrangement of the gate pad 102, source pad 103, and drain pad 104 can be arbitrarily changed.

[0017] As shown in Figures 2 and 3, the nitride semiconductor device 10 includes a conductive substrate 11 and a nitride semiconductor layer 15 located on the conductive substrate 11. The conductive substrate 11 forms the lower surface 10B of the nitride semiconductor device 10. An example of the conductive substrate 11 includes a substrate body 12 and an electrode layer 13.

[0018] The substrate body 12 can be formed from Si, silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the substrate body 12 is a Si substrate. The substrate body 12 may have a thickness of, for example, 100 μm or more and 1500 μm or less. In one example, the thickness of the substrate body 12 is 250 μm.

[0019] The substrate body 12 has an upper surface 12A and a lower surface 12B located on the opposite side of the upper surface 12A. The upper surface 12A of the substrate body 12 constitutes the upper surface of the conductive substrate 11.

[0020] The electrode layer 13 is formed on the lower surface 12B of the substrate body 12. The electrode layer 13 has an electrode upper surface 13A and an electrode lower surface 13B located on the opposite side of the electrode upper surface 13A. The electrode upper surface 13A of the electrode layer 13 is the surface facing the substrate body 12 and is fixed to the lower surface 12B of the substrate body 12. The electrode lower surface 13B of the electrode layer 13 constitutes the lower surface of the conductive substrate 11 and the chip lower surface 10B. Although not shown in the figure, the electrode layer 13 is electrically connected to the source electrode 28 of the transistor 100.

[0021] Furthermore, if the substrate body 12 is a low-resistance substrate, the electrode layer 13 can be omitted. In this case, the substrate body 12 is electrically connected to the source electrode 28 of the transistor 100. The resistance value of the low-resistance substrate is, for example, 2 × 10⁻⁶. -2 The resistance is less than or equal to Ωcm. For example, a low-resistance substrate is a SiC substrate. To achieve low resistance, the low-resistance substrate may be doped with impurities. An example of an impurity is nitrogen (N).

[0022] The nitride semiconductor layer 15 includes a first nitride semiconductor layer 15A located on the conductive substrate 11 via a buffer layer 14, and a second nitride semiconductor layer 15B located on the first nitride semiconductor layer 15A. The buffer layer 14 may be made of any material that facilitates the epitaxial growth of the first nitride semiconductor layer 15A.

[0023] For example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having a different Al composition. For example, the buffer layer 14 may consist of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In order to suppress leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make it semi-insulating. In that case, the impurities may be, for example, carbon (C) or iron (Fe), and the concentration of the impurities may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0024] The first nitride semiconductor layer 15A may be, for example, a GaN layer. The first nitride semiconductor layer 15A may have a thickness of, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the first nitride semiconductor layer 15A, an impurity may be introduced into a part of the first nitride semiconductor layer 15A to make the region other than the surface region of the first nitride semiconductor layer 15A semi-insulating. In this case, the impurity may be, for example, C, and the concentration of the impurity in the first nitride semiconductor layer 15A may be, for example, 4 × 10⁻⁶. 16 cm -3 This can be done.

[0025] The second nitride semiconductor layer 15B has a larger band gap than the first nitride semiconductor layer 15A. The second nitride semiconductor layer 15B may be, for example, an AlGaN layer. Since the band gap increases with increasing Al composition, the second nitride semiconductor layer 15B, which is an AlGaN layer, has a larger band gap than the first nitride semiconductor layer 15A, which is a GaN layer. For example, the second nitride semiconductor layer 15B is an Al with an Al composition ratio of X. X Ga (1-X)It is composed of N. The Al composition ratio X may be 0.1 < X < 0.4, preferably 0.1 < X < 0.3. The second nitride semiconductor layer 15B may have a thickness of, for example, 5 nm or more and 20 nm or less. In one example, the thickness of the second nitride semiconductor layer 15B is 8 nm or more.

[0026] The first nitride semiconductor layer 15A and the second nitride semiconductor layer 15B are composed of nitride semiconductors having different lattice constants from each other. Therefore, the nitride semiconductor (for example, GaN) constituting the first nitride semiconductor layer 15A and the nitride semiconductor (for example, AlGaN) constituting the second nitride semiconductor layer 15B form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the first nitride semiconductor layer 15A and the second nitride semiconductor layer 15B and the piezo-polarization caused by the crystal strain near the hetero-junction interface, the energy level of the conduction band of the first nitride semiconductor layer 15A near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the first nitride semiconductor layer 15A at a position close to the hetero-junction interface between the first nitride semiconductor layer 15A and the second nitride semiconductor layer 15B (for example, within a range of about several nm from the interface).

[0027] [Schematic Structure of Transistor] The nitride semiconductor device 10 includes a transistor 100 configured to include a nitride semiconductor layer 15. Hereinafter, first, referring to FIG. 3, the cross-sectional structure of the transistor 100 will be described, and then referring to FIG. 2, the planar layout of the transistor 100 will be described. In FIGS. 2 and 3, two transistors 100 arranged in the X-axis direction are shown.

[0028] Here, the Z-axis direction of the XYZ axes shown in the drawings after FIG. 2 is the thickness direction of the conductive substrate 11, and the X-axis direction and the Y-axis direction are two mutually orthogonal directions on a plane orthogonal to the Z-axis direction. The term "plan view" used in the present disclosure means viewing the nitride semiconductor device 10 from above in the Z-axis direction unless otherwise explicitly stated. Also, unless otherwise stated, the thickness means the thickness in the Z-axis direction.

[0029] The transistor 100 is configured as a HEMT using a nitride semiconductor. FIGS. 2 and 3 show the structure of a HEMT using GaN as an example of the transistor 100.

[0030] As shown in FIG. 3, the transistor 100 includes a conductive substrate 11 and a buffer layer 14 located on the conductive substrate 11. The transistor 100 further includes an electron traveling layer 16 located on the buffer layer 14 and an electron supply layer 18 located on the electron traveling layer 16. The electron traveling layer 16 is composed of a first nitride semiconductor layer 15A in the active region A1. The electron supply layer 18 is composed of a second nitride semiconductor layer 15B in the active region A1. A 2DEG 20 spreads at a position in the electron traveling layer 16 close to the hetero-junction interface between the electron traveling layer 16 and the electron supply layer 18.

[0031] The transistor 100 further includes a gate layer 22 located on the electron supply layer 18 and a gate electrode 24 located on the gate layer 22. The gate layer 22 is partially provided on the electron supply layer 18.

[0032] The gate layer 22 is composed of a nitride semiconductor containing acceptor-type impurities. For example, the gate layer 22 may be a gallium nitride layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may include at least one of zinc (Zn), magnesium (Mg), and carbon (C). The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 18 cm -3 or more 1×10 20 cm-3 The following are possible. In one example, the gate layer 22 is GaN containing at least one of Mg and Zn as an impurity.

[0033] The gate electrode 24 comprises one or more metal layers. In one example, the gate electrode 24 is a titanium nitride (TiN) layer. In another example, the gate electrode 24 comprises a first metal layer formed of Ti and a second metal layer located on the first metal layer and formed of TiN. The gate electrode 24 forms a Schottky junction with the gate layer 22. The gate electrode 24 is partially provided on the gate layer 22. The gate electrode 24 may have a thickness of, for example, 50 nm to 200 nm.

[0034] The transistor 100 further includes a passivation layer 26. The passivation layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24. The passivation layer 26 is formed from at least one of the following materials: silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 26 is formed from a material containing SiN. The passivation layer 26 may have a thickness of, for example, 50 nm to 150 nm.

[0035] The passivation layer 26 includes a source opening 26A and a drain opening 26B that are spaced apart from each other in the X-axis direction. The gate layer 22 is located between the source opening 26A and the drain opening 26B. The gate layer 22 is located closer to the source opening 26A than to the drain opening 26B.

[0036] The transistor 100 includes a source electrode 28 that contacts the electron supply layer 18 through a source opening 26A, and a drain electrode 30 that contacts the electron supply layer 18 through a drain opening 26B. The source electrode 28 and the drain electrode 30 may include one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the source electrode 28 and the drain electrode 30 have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including a Ti layer, AlCu layer, Ti layer, and TiN layer in that order from the top.

[0037] The source electrode 28 includes a source contact portion 28A filled within the source opening 26A and an extension portion 28B formed integrally with the source contact portion 28A and located on the passivation layer 26. The source contact portion 28A is in ohmic contact with the 2DEG20 directly beneath the electron supply layer 18 via the source opening 26A. The extension portion 28B functions as a source field plate electrode.

[0038] In the example shown in Figure 3, the extension portion 28B (source field plate electrode) covers the gate electrode 24 and the entire gate layer 22. The extension portion 28B includes an end portion 28BE facing the drain electrode 30 as the source field plate electrode end portion. The extension portion 28B (source field plate electrode) plays a role in mitigating electric field concentration near the end of the gate layer 22 when a high voltage is applied between the source and drain in the off state, when 2DEG20 in the region of the electron transport layer 16 directly below the gate layer 22 has disappeared.

[0039] The drain electrode 30 includes a drain contact portion 30A filled within the drain opening 26B. The drain contact portion 30A is in ohmic contact with the 2DEG20 directly beneath the electron supply layer 18 via the drain opening 26B.

[0040] In the transistor 100 configured as described above, the inclusion of acceptor-type impurities in the gate layer 22 raises the energy levels of the electron transport layer 16 and the electron supply layer 18. As a result, in the region directly beneath the gate layer 22, the energy level of the conduction band of the electron transport layer 16 near the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Consequently, when a gate control voltage that turns off the transistor 100 is applied to the gate electrode 24 (for example, when the gate-source voltage is 0V or lower), 2DEG20 is not formed in the region of the electron transport layer 16 directly beneath the gate layer 22. On the other hand, 2DEG20 is formed in the regions of the electron transport layer 16 other than the region directly beneath the gate layer 22.

[0041] Thus, the presence of the acceptor-type impurity-doped gate layer 22 causes 2DEG20 to disappear in the region of the electron transport layer 16 directly beneath the gate layer 22, thereby realizing the normally-off operation of the transistor. When an appropriate gate control voltage (on voltage) is applied to the gate electrode 24, a channel formed by 2DEG20 is created in the region of the electron transport layer 16 directly beneath the gate layer 22, and the source-drain junction becomes conductive.

[0042] Although not shown in the diagram, the transistor 100 includes a source electrode 28, a drain electrode 30, and an interlayer insulating film covering the passivation layer 26. The interlayer insulating film is formed from at least one of the following materials: silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the interlayer insulating film is formed from SiO2.

[0043] The gate electrode 24 is electrically connected to the gate pad 102 located on the interlayer insulating film by vias and gate wiring that penetrate the interlayer insulating film. The source electrode 28 is electrically connected to the source pad 103 located on the interlayer insulating film by vias and source wiring that penetrate the interlayer insulating film. The drain electrode 30 is electrically connected to the drain pad 104 located on the interlayer insulating film by vias and drain wiring that penetrate the interlayer insulating film. The source electrode 28 is also electrically connected to the conductive substrate 11. In one example, the source electrode 28 is electrically connected to the conductive substrate 11 by vias that penetrate the buffer layer 14, the electron transport layer 16 (first nitride semiconductor layer 15A), and the electron supply layer 18 (second nitride semiconductor layer 15B).

[0044] Next, with reference to Figure 2, the planar layout of transistor 100 in the active region A1 will be described. Note that the passivation layer 26 is not shown in Figure 2. Also, for clarity, the end portion 28BE of the extension portion 28B (source field plate electrode) shown in Figure 3 is shown with a dashed line in Figure 2.

[0045] As shown in Figure 3, the source contact portion 28A, the gate electrode 24 (gate layer 22), and the drain contact portion 30A are arranged side by side in the X-axis direction. The combination of the source contact portion 28A, gate electrode 24 (gate layer 22), and drain contact portion 30A arranged side by side in the X-axis direction constitutes one HEMT cell HC. Although the example in Figure 2 shows two HEMT cell HCs arranged side by side in the X-axis direction, in reality, more HEMT cell HCs may be arranged. The number of HEMT cell HCs is not particularly limited, and the transistor 100 may contain one or more HEMT cell HCs.

[0046] [Synthetic structure of a snubber circuit] As shown in Figures 2 and 3, the nitride semiconductor device 10 includes a snubber circuit 200 connected in parallel to the source electrode 28 and drain electrode 30 of the transistor 100.

[0047] As shown in Figures 2 and 3, the nitride semiconductor device 10 includes a transistor pair consisting of two specific transistors 100 (HEMT cells HC) arranged side by side in the X-axis direction. The two transistors 100 constituting the transistor pair are arranged on the nitride semiconductor layer 15 such that their drain electrodes 30 face each other.

[0048] In the following, one of the two transistors 100 constituting a transistor pair may be referred to as the first transistor 100A, and the other as the second transistor 100B. Furthermore, the electron transport layer 16, electron supply layer 18, gate electrode 24, source electrode 28, and drain electrode 30 of the first transistor 100A may be referred to as the first electron transport layer 16, first electron supply layer 18, first gate electrode 24, first source electrode 28, and first drain electrode 30, respectively. Similarly, the electron transport layer 16, electron supply layer 18, gate electrode 24, source electrode 28, and drain electrode 30 of the second transistor 100B may be referred to as the second electron transport layer 16, second electron supply layer 18, second gate electrode 24, second source electrode 28, and second drain electrode 30, respectively.

[0049] The snubber circuit 200 is positioned between the first transistor 100A and the second transistor 100B in the X-axis direction. Alternatively, the snubber circuit 200 can be positioned between the first drain electrode 30 of the first transistor 100A and the second drain electrode 30 of the second transistor 100B in the X-axis direction.

[0050] As shown in Figure 3, the snubber circuit 200 includes a snubber resistor 201 located on the nitride semiconductor layer 15 and electrically connected to the drain electrode 30, and a snubber capacitor 210 electrically connected to the snubber resistor 201 and the conductive substrate 11, and including parasitic capacitance formed by the nitride semiconductor layer 15.

[0051] The snubber resistor 201 is located between the first drain electrode 30 of the first transistor 100A and the second drain electrode 30 of the second transistor 100B. More specifically, a resistive opening 202 is provided in the second nitride semiconductor layer 15B between the first drain electrode 30 and the second drain electrode 30, exposing the first nitride semiconductor layer 15A. The resistive opening 202 is located in a different position from the first transistor 100A and the second transistor 100B in the second nitride semiconductor layer 15B.

[0052] The resistive opening 202 is formed by partially removing the second nitride semiconductor layer 15B and, if necessary, partially removing the surface layer of the first nitride semiconductor layer 15A (for example, about 100 nm from the top surface). The resistive opening 202 is also continuously provided in the passivation layer 26 located on the first nitride semiconductor layer 15A. Therefore, the resistive opening 202 is a recess that penetrates the passivation layer 26 and the second nitride semiconductor layer 15B, with the first nitride semiconductor layer 15A exposed at its bottom. In the region of the nitride semiconductor layer 15 where the resistive opening 202 is formed, the second nitride semiconductor layer 15B is absent, and therefore 2DEG20 is partially lost.

[0053] The snubber resistor 201 is located within the resistance opening 202. The snubber resistor 201 is formed from a high-resistivity material such as polysilicon. In one example, the snubber resistor 201 is composed of polysilicon. Polysilicon has an electrical resistivity of, for example, 1 × 10⁻⁶. 3 This is a high-resistance polysilicon with a resistance of Ωcm or more.

[0054] The snubber resistor 201 includes a resistor body 201A located within the resistor opening 202 and filling the resistor opening 202. The resistor body 201A is in contact with the first nitride semiconductor layer 15A at the bottom surface of the resistor opening 202. Therefore, the snubber resistor 201 is in contact with the first nitride semiconductor layer 15A through the resistor opening 202.

[0055] The snubber resistor 201 is formed integrally with the resistor body 201A and includes a resistive contact portion 201B that is exposed on the passivation layer 26. The resistive contact portion 201B is in ohmic contact with the first drain electrode 30 of the first transistor 100A and the second drain electrode 30 of the second transistor 100B. Therefore, the snubber resistor 201 is electrically connected to both the first drain electrode 30 and the second drain electrode 30.

[0056] In one example, the resistive contact portion 201B includes a first resistive extension portion 201B1 and a second resistive extension portion 201B2 extending in the X-axis direction on the passivation layer 26. The first resistive extension portion 201B1 extends toward the first drain electrode 30 of the first transistor 100A. The second resistive extension portion 201B2 extends toward the second drain electrode 30 of the second transistor 100B. The first drain electrode 30 of the first transistor 100A is in contact with one or both of the top and side surfaces of the first resistive extension portion 201B1. The second drain electrode 30 of the second transistor 100B is in contact with one or both of the top and side surfaces of the second resistive extension portion 201B2.

[0057] The resistance value of the snubber resistor 201 in the snubber circuit 200, described later, depends on the length L1 of the snubber resistor 201 in the X-axis direction. Therefore, the length L1 of the snubber resistor 201 is set according to the required resistance value of the snubber resistor 201.

[0058] The length L1 of the snubber resistor 201 is, for example, 1 μm or more, preferably 5 μm or more. By increasing the length L1 of the snubber resistor 201, the resistance value of the snubber resistor 201 can be increased. The length L1 of the snubber resistor 201 is, for example, 20 μm or less, preferably 10 μm or less. By shortening the length L1 of the snubber resistor 201, the increase in size of the nitride semiconductor device 10 caused by providing the snubber circuit 200 can be suppressed. Note that the length L1 of the snubber resistor 201 is the length in the X-axis direction of the portion (resistor body portion 201A) that is filled in the resistance opening 202.

[0059] The thickness T1 of the snubber resistor 201 is, for example, 0.05 μm or more and 0.3 μm or less. The thickness T1 of the snubber resistor 201 is the thickness of the snubber resistor 201 in the portion where the resistive contact portion 201B is located. In one example, the thickness T1 of the snubber resistor 201 is shorter than the length L1 of the snubber resistor 201. In other words, the length L1 of the snubber resistor 201 is longer than the thickness T1 of the snubber resistor 201. Also, the length L1 of the snubber resistor 201 may be the same as the thickness T1 of the snubber resistor 201, or it may be shorter than the thickness T1 of the snubber resistor 201.

[0060] Although not shown in the diagram, the snubber resistor 201 is covered by an interlayer insulating film that covers the source electrode 28, drain electrode 30, and passivation layer 26 in the transistor 100.

[0061] As shown in Figure 2, in a plan view, the snubber resistor 201 and the resistor opening 202 extend in the Y-axis direction. In one example, the Y-axis length of the snubber resistor 201 is longer than the Y-axis length of the drain electrodes 30 (first drain electrode 30 and second drain electrode 30). In other words, one end of the snubber resistor 201 in the Y-axis direction protrudes further to the left in the Y-axis direction than one end of the drain electrode 30 in the Y-axis direction. The other end of the snubber resistor 201 in the Y-axis direction protrudes further to the left in the Y-axis direction than the other end of the drain electrode 30 in the Y-axis direction.

[0062] As shown in Figure 3, the snubber capacitor 210 includes parasitic capacitance formed by the nitride semiconductor layer 15. The conductive substrate 11 is set to source potential by being electrically connected to the source electrode 28. The snubber resistor 201 is positioned opposite the conductive substrate 11 with the first nitride semiconductor layer 15A in between. The snubber resistor 201 is electrically connected to the first drain electrode 30 of the first transistor 100A and the second drain electrode 30 of the second transistor 100B. The snubber capacitor 210 is a capacitor formed using the parasitic capacitance generated in the first nitride semiconductor layer 15A located between the conductive substrate 11 and the snubber resistor 201.

[0063] The snubber capacitor 210 forms a parasitic capacitance C based on the following equation (1). C = ε × (S / d) ... (1) Here, in equation (1), S is the area of ​​contact between the conductive substrate 11 and the snubber resistor 201. d is the distance between the conductive substrate 11 and the snubber resistor 201. ε is the dielectric constant of the dielectric layer interposed between the conductive substrate 11 and the snubber resistor 201. In the example shown in Figure 3, the distance d is the distance between the electrode layer 13 of the conductive substrate 11 and the snubber resistor 201, and the dielectric layer consists of the substrate body 12, buffer layer 14, and first nitride semiconductor layer 15A of the conductive substrate 11. The parasitic capacitance C can be changed by changing one or more of the contact area S, distance d, and dielectric constant ε of the dielectric layer.

[0064] The snubber capacitor 210 is electrically connected to the source electrode 28 of the transistor 100 via the conductive substrate 11. The snubber capacitor 210 is also electrically connected to the first drain electrode 30 of the first transistor 100A and the second drain electrode 30 of the second transistor 100B via the snubber resistor 201.

[0065] Therefore, as shown in the circuit diagram of Figure 4, a snubber resistor 201 and a snubber capacitor 210 are connected in series between the drain electrode 30 and the source electrode 28 of transistor 100. The snubber resistor 201 and snubber capacitor 210 form a snubber circuit 200 connected in parallel to the source electrode 28 and the drain electrode 30 of transistor 100. The snubber circuit 200 is an RC snubber. Note that the second transistor 100B is omitted in Figure 4. In this way, the snubber circuit 200 is fabricated within the same chip that forms transistor 100 by utilizing the nitride semiconductor layer 15 used in transistor 100.

[0066] The resistance value of the snubber resistor 201 that constitutes the snubber circuit 200 is, for example, between 10kΩ and 100kΩ. The capacitance value of the snubber capacitor 210 that constitutes the snubber circuit 200 is, for example, between 0.01pF and 0.1pF.

[0067] [Manufacturing method for nitride semiconductor devices] Next, an example of a manufacturing method for the nitride semiconductor device 10 shown in Figure 2 will be described. Figures 5 to 15 are schematic cross-sectional views illustrating an exemplary manufacturing process of the nitride semiconductor device 10. Figures 5 to 15 correspond to the cross-sectional structure shown in Figure 3. For ease of understanding, components similar to those in Figure 3 are denoted by the same reference numerals in Figures 5 to 15.

[0068] As shown in Figure 5, the manufacturing method for the nitride semiconductor device 10 includes sequentially forming a buffer layer 14, a first nitride semiconductor layer 15A, a second nitride semiconductor layer 15B, a third nitride semiconductor layer 301, and a first metal layer 302 on a substrate body 12. The buffer layer 14, the first nitride semiconductor layer 15A, the second nitride semiconductor layer 15B, and the third nitride semiconductor layer 301 can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD).

[0069] Although detailed illustrations are omitted, in one example, the buffer layer 14 may be a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the conductive substrate 11 and a grated AlGaN layer (second buffer layer) formed on the AlN layer. The grated AlGaN layer can be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0070] The first nitride semiconductor layer 15A formed on the buffer layer 14 may be a GaN layer. The second nitride semiconductor layer 15B formed on the first nitride semiconductor layer 15A may be an AlGaN layer. Therefore, the second nitride semiconductor layer 15B is composed of a nitride semiconductor having a larger band gap than the first nitride semiconductor layer 15A.

[0071] The third nitride semiconductor layer 301 is a layer for forming the gate layer 22, and is, for example, a GaN layer containing Mg as an acceptor-type impurity. The third nitride semiconductor layer 301 is formed by doping GaN with Mg while growing GaN on the second nitride semiconductor layer 15B. The first metal layer 302 is a layer for forming the gate electrode 24, and is, for example, a TiN layer. The first metal layer 302 is formed, for example, by sputtering.

[0072] As shown in Figure 6, the manufacturing method of the nitride semiconductor device 10 includes a step of forming a gate electrode 24. The gate electrode 24 is formed by selectively removing the first metal layer 302. In one example, a mask layer is formed on the first metal layer 302 to cover the region where the gate electrode 24 is to be formed. In one example, the mask layer is formed of a resist film. The gate electrode 24 is formed by selectively removing the first metal layer 302 using the mask layer.

[0073] As shown in Figure 7, the manufacturing method of the nitride semiconductor device 10 includes a step of forming a gate layer 22. The gate layer 22 is formed by selectively removing the third nitride semiconductor layer 301. In one example, a mask layer is formed on the third nitride semiconductor layer 301 to cover the region where the gate layer 22 is to be formed. The mask layer is formed, for example, from a resist film. The gate layer 22 is formed by selectively removing the third nitride semiconductor layer 301 using the mask layer.

[0074] As shown in Figure 8, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a passivation layer 26 on the first nitride semiconductor layer 15A. The passivation layer 26 can be formed, in one example, by low-pressure chemical vapor deposition (LPCVD).

[0075] As shown in Figure 9, the manufacturing method of the nitride semiconductor device 10 includes a step of forming a resistive opening 202. The resistive opening 202 can be formed by selectively removing the passivation layer 26 and the second nitride semiconductor layer 15B. In one example, a mask layer is formed on the passivation layer 26 that exposes the region to be formed as the resistive opening 202. In one example, the mask layer is formed of a resist film. The passivation layer 26 and the second nitride semiconductor layer 15B are selectively removed using the mask layer. At this time, a portion of the surface layer of the first nitride semiconductor layer 15A may also be removed.

[0076] As shown in Figure 10, the manufacturing method of the nitride semiconductor device 10 includes the step of forming a resistive layer 303 on a passivation layer 26. The resistive layer 303 is a layer that becomes the snubber resistor 201 of the snubber circuit 200. As shown in Figure 10, the resistive layer 303 is in contact with the first nitride semiconductor layer 15A at the resistive opening 202.

[0077] As shown in Figure 11, the manufacturing method of the nitride semiconductor device 10 includes a step of forming a snubber resistor 201. The snubber resistor 201 is formed by selectively removing the resistor layer 303. In one example, a mask layer is formed on the resistor layer 303 to cover the area on which the snubber resistor 201 is to be formed. The mask layer is formed, for example, from a resist film. The snubber resistor 201 is formed by selectively removing the resistor layer 303 using the mask layer.

[0078] As shown in Figure 12, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a source opening 26A and a drain opening 26B. The source opening 26A and the drain opening 26B can be formed by selectively removing the passivation layer 26.

[0079] As shown in Figure 13, the manufacturing method of the nitride semiconductor device 10 includes the step of forming a second metal layer 304 on the passivation layer 26. The second metal layer 304 is a layer that will become the source electrode 28 and the drain electrode 30. The second metal layer 304 is formed, for example, by sputtering. As shown in Figure 13, the second metal layer 304 is in contact with the second nitride semiconductor layer 15B (electron supply layer 18) at the source opening 26A and the drain opening 26B.

[0080] As shown in Figure 14, the manufacturing method for the nitride semiconductor device 10 includes the step of forming a source electrode 28 and a drain electrode 30. The source electrode 28 and the drain electrode 30 are formed by selectively removing the second metal layer 304. In one example, a mask layer is formed on the second metal layer 304, covering the area where the source electrode 28 and the drain electrode 30 are to be formed. In one example, the mask layer is formed of a resist film. The electrodes are formed by selectively removing the second metal layer 304 using the mask layer.

[0081] As shown in Figure 15, the manufacturing method of the nitride semiconductor device 10 includes a step of forming an electrode layer 13. The electrode layer 13 is formed on the lower surface 12B of the substrate body 12, for example, by sputtering. Although not shown in the figure, the manufacturing method of the nitride semiconductor device 10 also includes a step of forming a connection structure such as a via for electrically connecting the electrode layer 13 and the source electrode 28. The step of forming the connection structure is performed before or after the step of forming the electrode layer 13. By going through the above steps, the nitride semiconductor device 10 can be obtained.

[0082] [Effect] Next, the operation of the nitride semiconductor device 10 of the first embodiment will be described. The nitride semiconductor device 10 has a snubber circuit 200 integrated into the chip that makes up the transistor 100, between the drain and source of the transistor 100. In other words, the snubber circuit 200 is built into the chip of the nitride semiconductor device 10, including the transistor 100. The snubber circuit 200 absorbs the surge voltage oscillations that occur between the drain and source of the transistor 100 during switching and attenuates them with a snubber resistor 201. This suppresses the voltage surge and voltage noise generated in the transistor 100 during switching.

[0083] [effect] The nitride semiconductor device 10 of the first embodiment provides the following advantages. (1-1) The nitride semiconductor device 10 includes a conductive substrate 11, a nitride semiconductor layer 15 located on the conductive substrate 11, a transistor 100 which includes a part of the nitride semiconductor layer 15 and has a gate electrode 24, a source electrode 28, and a drain electrode 30 located on the nitride semiconductor layer 15, and a snubber circuit 200 connected in parallel to the source electrode 28 and the drain electrode 30. The conductive substrate 11 is electrically connected to the source electrode 28. The snubber circuit 200 includes a snubber resistor 201 located on the nitride semiconductor layer 15 and electrically connected to the drain electrode 30, and a snubber capacitor 210 which is electrically connected to the snubber resistor 201 and the conductive substrate 11 and includes parasitic capacitance formed by the nitride semiconductor layer 15.

[0084] In this case, the snubber circuit 200 is integrated into the chip that makes up the transistor 100. This suppresses voltage surges and voltage noise during switching, especially during high-speed switching. Furthermore, compared to a configuration in which the snubber circuit is externally configured as a separate element, the configuration with the snubber circuit 200 built-in requires less wiring for the formation and connection of the snubber circuit. As a result, the parasitic inductance component in the snubber circuit 200 can be reduced. As a result, the transistor 100 can be effectively protected from element failure caused by voltage surges and malfunctions due to high-frequency noise.

[0085] (1-2) The nitride semiconductor layer 15 includes a first nitride semiconductor layer 15A and a second nitride semiconductor layer 15B located on the first nitride semiconductor layer 15A and having a larger band gap than the first nitride semiconductor layer 15A. A resistive opening 202 is provided in the second nitride semiconductor layer 15B at a location different from the transistor 100, exposing the first nitride semiconductor layer 15A. The snubber resistor 201 is in contact with the first nitride semiconductor layer 15A via the resistive opening 202.

[0086] In this case, the resistive opening 202 exposes a portion of the nitride semiconductor layer 15A, creating a region where 2DEG20 does not occur. A snubber resistor 201 is then placed in the resistive opening 202. This allows for easy placement of the snubber resistor 201 while eliminating 2DEG20 in the nitride semiconductor layer 15. Furthermore, by filling the resistive opening 202 with a high-resistance material such as polysilicon, a snubber resistor 201 with a high resistance value can be easily formed.

[0087] (1-3) The transistor 100 includes a first transistor 100A and a second transistor 100B. The first transistor 100A and the second transistor 100B are arranged side by side on the nitride semiconductor layer 15 such that their drain electrodes 30 face each other. The snubber resistor 201 is located between the drain electrode 30 of the first transistor 100A and the drain electrode 30 of the second transistor 100B and is electrically connected to both of those drain electrodes 30.

[0088] In this case, the snubber circuit 200 can be placed between the first transistor 100A and the second transistor 100B, which are arranged in the X-axis direction within the active region A1. Furthermore, by making the snubber circuit 200 connected to both the first transistor 100A and the second transistor 100B, the increase in the chip area of ​​the nitride semiconductor device 40 due to the addition of the snubber circuit 200 can be suppressed.

[0089] (1-4) The length L1 of the snubber resistor 201 is longer than the thickness T1 of the snubber resistor 201. In this case, the increase in the Z-axis dimension of the nitride semiconductor device 10 due to the addition of the snubber circuit 200, i.e., the increase in chip thickness, can be suppressed.

[0090] [Second Embodiment] The nitride semiconductor device 40 of the second embodiment differs from that of the first embodiment in the configuration of the drain electrode 30 and the snubber resistor 201. The other configurations are the same as those of the first embodiment. In the following, the components that are the same as those of the first embodiment will not be described, and the components that differ from those of the first embodiment will be described.

[0091] As shown in Figure 16, the nitride semiconductor device 40 includes a first transistor 100A and a second transistor 100B. The nitride semiconductor device 40 includes one drain electrode 31 shared by the first transistor 100A and the second transistor 100B.

[0092] The drain electrode 31 includes a first drain contact portion 31A filled in the drain opening 26B of the first transistor 100A, and a second drain contact portion 31B filled in the drain opening 26B of the second transistor 100B. The first drain contact portion 31A and the second drain contact portion 31B are in ohmic contact with the 2DEG20 directly beneath the electron supply layer 18 via the drain opening 26B.

[0093] The drain electrode 31 further includes a drain connection portion 31C. The drain connection portion 31C is integrally formed with the first drain contact portion 31A and the second drain contact portion 31B, and connects the first drain contact portion 31A and the second drain contact portion 31B. The drain connection portion 31C is located on the snubber resistor 201 and is in contact with the upper surface of the snubber resistor 201. The drain electrode 31 covers the upper surface of the snubber resistor 201.

[0094] In the case of a nitride semiconductor device 40 including the drain electrode 31 of the above structure, the resistance value of the snubber resistor 201 depends on the thickness T1 of the snubber resistor 201. Therefore, the thickness T1 of the snubber resistor 201 is set according to the required resistance value of the snubber resistor 201. Methods for adjusting the thickness T1 of the snubber resistor 201 include, for example, changing the thickness of the passivation layer 26 or forming the resistance opening 202 deep within the first nitride semiconductor layer 15A.

[0095] The thickness T1 of the snubber resistor 201 is, for example, 0.05 μm or more, preferably 0.1 μm or more. By increasing the thickness T1 of the snubber resistor 201, the resistance value of the snubber resistor 201 can be increased. The thickness T1 of the snubber resistor 201 is, for example, 0.5 μm or less, preferably 0.3 μm or less. By shortening the thickness T1 of the snubber resistor 201, the increase in size of the nitride semiconductor device 10 caused by providing the snubber circuit 200 can be suppressed.

[0096] The length L1 of the snubber resistor 201 is, for example, between 1 μm and 20 μm. In one example, the length L1 of the snubber resistor 201 is shorter than the thickness T1 of the snubber resistor 201. In other words, the thickness T1 of the snubber resistor 201 is thicker than the length L1 of the snubber resistor 201. Alternatively, the thickness T1 of the snubber resistor 201 may be the same as the length L1 of the snubber resistor 201, or it may be thinner than the length L1 of the snubber resistor 201.

[0097] [Mechanism of Action and Effects] The operation of the nitride semiconductor device 40 in the second embodiment is the same as the operation of the nitride semiconductor device 10 in the first embodiment.

[0098] The nitride semiconductor device 40 of the second embodiment provides the same effects as described above in (1-1) to (1-4). Furthermore, the nitride semiconductor device 40 of the second embodiment provides the following effects.

[0099] (2-1) The thickness T1 of the snubber resistor 201 is greater than the length L1 of the snubber resistor 201. In this case, the increase in the dimensions of the nitride semiconductor device 40 in the X-axis direction due to the addition of the snubber circuit 200, i.e., the increase in chip area, can be suppressed.

[0100] [Third Embodiment] The nitride semiconductor device 50 of the third embodiment differs from that of the first embodiment in the location where the snubber circuit 200 is provided. The other configurations are the same as those of the first embodiment. Below, the same components as in the first embodiment will not be described, and the components that differ from those of the first embodiment will be described.

[0101] A nitride semiconductor device 50 according to the third embodiment will be described with reference to Figures 17 and 18. Figure 17 shows a schematic planar structure of a portion of the internal structure of the nitride semiconductor device 50, and represents the area corresponding to the area around where the gate pad 102 is located in the planar view of the nitride semiconductor device 10 shown in Figure 1. Figure 18 shows a schematic cross-sectional structure of the nitride semiconductor device 50 cut along the line F18-F18 in Figure 17. Figure 18 also illustrates the source electrode 28 of the transistor 100, the drain electrode 30, the interlayer insulating film 32 covering the passivation layer 26, and the gate pad 102 located on the interlayer insulating film 32.

[0102] As shown in Figures 17 and 18, the nitride semiconductor device 50 includes a snubber circuit 200A. The snubber circuit 200A includes a portion located directly below the gate pad 102 and is positioned to span between the active region A1 and the inactive region A2. Also, as shown in Figure 17, in a plan view, the snubber circuit 200A is positioned between the drain electrode 30C of transistor 100C, which is transistor 100 located next to the gate pad 102 in the X-axis direction, and the chip side surface 10C.

[0103] As shown in Figure 18, the snubber circuit 200A includes a snubber resistor 201 and a first electrode 204 and a second electrode 205 electrically connected to the snubber resistor 201. The first electrode 204 and the second electrode 205 may include one or more metal layers. For example, the first electrode 204 and the second electrode 205 may be formed by a combination of two or more metal layers selected from the group including Ti layers, TiN layers, Al layers, AlSiCu layers, and AlCu layers. In one example, the first electrode 204 and the second electrode 205 have a four-layer structure (Ti layer / AlCu layer / Ti layer / TiN layer) including a Ti layer, AlCu layer, Ti layer, and TiN layer in that order from the top.

[0104] The snubber resistor 201 is located in the inactive region A2. The shape, dimensions, and other configurations of the snubber resistor 201 are the same as in the first embodiment. In one example, the length L1 of the snubber resistor 201 is longer than the thickness of the snubber resistor 201.

[0105] The first electrode 204 is located between the drain electrode 30C and the snubber resistor 201 in the active region A1 and is electrically connected to the drain electrode 30C. More specifically, in the active region A1, a first electrode opening 26C is provided in the passivation layer 26 between the drain electrode 30C and the snubber resistor 201, exposing the second nitride semiconductor layer 15B. Furthermore, the first electrode 204 may be located across the active region A1 and the inactive region A2, or its entirety may be located in the inactive region A2.

[0106] The first electrode 204 includes a first electrode contact portion 204A filled within the first electrode opening 26C. The first electrode contact portion 204A is in ohmic contact with 2DEG20 directly beneath the electron supply layer 18 (second nitride semiconductor layer 15B) via the first electrode opening 26C. Thus, the first electrode 204 is electrically connected to the drain electrode 30C via 2DEG20. The first electrode 204 is also electrically connected to the snubber resistor 201. In one example, the first electrode 204 is in contact with one or both of the top and side surfaces of the first resistance extension portion 201B1 of the snubber resistor 201.

[0107] The second electrode 205 is located in the inactive region A2 between the snubber resistor 201 and the chip side surface 10C, and is in contact with the second nitride semiconductor layer 15B. More specifically, in the inactive region A2, a second electrode opening 26D is provided in the passivation layer 26 between the snubber resistor 201 and the chip side surface 10C, exposing the second nitride semiconductor layer 15B.

[0108] The second electrode 205 includes a second electrode contact portion 205A filled within the second electrode opening 26D. The second electrode contact portion 205A is in ohmic contact with 2DEG20 directly beneath the second nitride semiconductor layer 15B via the second electrode opening 26D. The second electrode 205 is also electrically connected to the snubber resistor 201. In one example, the second electrode 205 is in contact with one or both of the upper and side surfaces of the second resistance extension portion 201B2 of the snubber resistor 201.

[0109] The snubber circuit 200A includes a first snubber capacitor 210A and a second snubber capacitor 210B. The first snubber capacitor 210A and the second snubber capacitor 210B are connected in parallel between the conductive substrate 11 and the snubber resistor 201. The first snubber capacitor 210A is formed using parasitic capacitance generated in the first nitride semiconductor layer 15A located between the conductive substrate 11 and the snubber resistor 201, similar to the snubber capacitor 210 of the first embodiment.

[0110] The second snubber capacitor 210B utilizes 2DEG20 generated in the first nitride semiconductor layer 15A located in the inactive region A2. Within the first nitride semiconductor layer 15A located in the inactive region A2, 2DEG20 extends in the planar direction along the heterojunction interface with the second nitride semiconductor layer 15B. The 2DEG20 located in the inactive region A2 is electrically connected to the snubber resistor 201 via the second electrode 205. The 2DEG20 extending in the planar direction in the inactive region A2 faces the conductive substrate 11 across the first nitride semiconductor layer 15A. The second snubber capacitor 210B is formed using the parasitic capacitance generated in the first nitride semiconductor layer 15A located between the conductive substrate 11 and the 2DEG20 extending in the planar direction in the inactive region A2.

[0111] As shown in Figures 17 and 18, an element isolation region A3 is provided between the active region A1 and the inactive region A2 to electrically separate the 2DEG20 generated in the first nitride semiconductor layer 15A located in the active region A1 from the 2DEG20 generated in the first nitride semiconductor layer 15A located in the inactive region A2. In a plan view, the element isolation region A3 is formed to surround the active region A1 and the inactive region A2, respectively.

[0112] The element isolation region A3 is, for example, a region on the first nitride semiconductor layer 15A where the second nitride semiconductor layer 15B is partially absent. In the example shown in Figure 18, the element isolation region A3 is formed by removing a portion of the first nitride semiconductor layer 15A. The second nitride semiconductor layer 15B can be removed by etching or the like. The element isolation region A3 is filled, for example, by filling it with an interlayer insulating film 32.

[0113] Furthermore, the element isolation region A3 may be a region in the second nitride semiconductor layer 15B that contains inert atoms. For example, in a plan view, inert atoms that cause 2DEG20 to disappear are implanted into the portion of the second nitride semiconductor layer 15B that becomes the element isolation region A3. The inert atoms are, for example, argon (Ar). Due to the implantation of inert atoms, the second nitride semiconductor layer 15B, although existing on the first nitride semiconductor layer 15A, loses its ability to form 2DEG20 in the first nitride semiconductor layer 15A. As a result, the 2DEG20 directly beneath the ion-implanted second nitride semiconductor layer 15B in the first nitride semiconductor layer 15A partially disappears.

[0114] [Mechanism of Action and Effects] The operation of the nitride semiconductor device 50 in the third embodiment is the same as the operation of the nitride semiconductor device 10 in the first embodiment.

[0115] The nitride semiconductor device 50 of the third embodiment provides the same effects as described in (1-1), (1-2), and (1-4). Furthermore, the nitride semiconductor device 50 of the third embodiment provides the following effects.

[0116] (3-1) The nitride semiconductor device 50 includes an active region A1 on which a transistor 100 is formed and an inactive region A2 on which a transistor 100 is not formed. A gate pad 102 is located on the nitride semiconductor layer 15 in the inactive region A2 and is electrically connected to the gate electrode 24. The nitride semiconductor layer 15 includes a first nitride semiconductor layer 15A and a second nitride semiconductor layer 15B located on the first nitride semiconductor layer 15A and having a larger band gap than the first nitride semiconductor layer 15A. The snubber circuit 200A includes a first electrode 204 and a second electrode 205 electrically connected to a snubber resistor 201. The first electrode 204 is located between the snubber resistor 201 and the drain electrode 30 and is electrically connected to the drain electrode 30. The second electrode 205 is electrically connected to a 2DEG20 that occurs in the first nitride semiconductor layer 15A located directly beneath the gate pad 102 in the inactive region A2.

[0117] In this case, a snubber circuit 200A is provided using the nitride semiconductor layer 15 located in the inactive region A2. Since the inactive region A2 is a region where transistors 100 are not formed, the snubber circuit 200A can be provided without changing the arrangement of transistors 100. Furthermore, the increase in the chip area of ​​the nitride semiconductor device 40 due to the addition of the snubber circuit 200 can be suppressed.

[0118] (3-2) The snubber circuit 200A includes a first snubber capacitor 210A and a second snubber capacitor 210B connected in parallel between the conductive substrate 11 and the snubber resistor 201. The first snubber capacitor 210A is a capacitor that includes parasitic capacitance generated in the first nitride semiconductor layer 15A located between the conductive substrate 11 and the snubber resistor 201. The second snubber capacitor 210B is a capacitor that includes parasitic capacitance generated in the first nitride semiconductor layer 15A located between the conductive substrate 11 and 2DEG20 generated in the first nitride semiconductor layer 15A located directly beneath the gate pad 102.

[0119] By providing the first snubber capacitor 210A and the second snubber capacitor 210B connected in parallel, the capacitance value of the snubber capacitors constituting the snubber circuit 200A can be increased. By increasing the capacitance value of the snubber capacitors, voltage surges during switching can be effectively suppressed. In particular, the second snubber capacitor 210B uses 2DEG20, which is generated in the inactive region A2, as the capacitor electrode. In this case, it is easy to increase the capacitance value of the capacitor by securing a large opposing area for the capacitor.

[0120] [Example of changes] Transistor 100 is not limited to HEMTs using GaN, but may also be transistors using other nitride semiconductors.

[0121] In the nitride semiconductor device 10 of the first embodiment, the snubber circuit 200 may be electrically connected to only one of the first drain electrode 30 of the first transistor 100A and the second drain electrode 30 of the second transistor 100B.

[0122] In the nitride semiconductor device 50 of the third embodiment, the second electrode 205 only needs to have a second electrode contact portion 205A positioned so that it can make ohmic contact with 2DEG generated in the first nitride semiconductor layer 15A located in the inactive region A2. Therefore, the second electrode 205 and the second electrode contact portion 205A may be located in a part not directly beneath the gate pad 102.

[0123] One or more of the various examples described herein can be combined to the extent that they do not conflict with the technical specifications. As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, for example, the expression “the first element is positioned on the second element” is intended to mean that in one embodiment the first element may be in contact with and directly positioned on the second element, while in other embodiments the first element may be positioned above the second element without contact. In other words, the term “on” does not preclude structures in which other elements are formed between the first and second elements.

[0124] The Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the Z-axis direction "up" and "down" being vertical. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0125] [Note] The technical concepts that can be grasped from this disclosure are described below. Note that, not as an attempt to limit the scope but to aid understanding, the components described in the appendices are denoted by the corresponding reference numerals of the components in the embodiments described above. The reference numerals are provided as examples to aid understanding, and the components described in each appendice should not be limited to those indicated by the reference numerals.

[0126] [Note 1] A conductive substrate (11) and A nitride semiconductor layer (15) located on the conductive substrate (11), A transistor (100) that includes a portion of the nitride semiconductor layer (15) and has a gate electrode (24), a source electrode (28), and a drain electrode (30) located on the nitride semiconductor layer (15), The system includes a snubber circuit (200, 200A) connected in parallel to the source electrode (28) and the drain electrode (30), The conductive substrate (11) is electrically connected to the source electrode (28), The aforementioned snubber circuit (200, 200A) is, A snubber resistor (201) is located on the nitride semiconductor layer (15) and is electrically connected to the drain electrode (30), A nitride semiconductor device (10, 40, 50) comprising: a snubber capacitor (210, 210A, 210B) electrically connected to the snubber resistor (201) and the conductive substrate (11), and including parasitic capacitance formed by the nitride semiconductor layer (15).

[0127] [Note 2] The nitride semiconductor layer (15) is First nitride semiconductor layer (15A), The first nitride semiconductor layer (15A) is located on the second nitride semiconductor layer (15B) which has a larger band gap than the first nitride semiconductor layer (15A), and the second nitride semiconductor layer (15B) is located on the first nitride semiconductor layer (15A). A resistive opening (202) is provided in the second nitride semiconductor layer (15B) at a position different from the transistor (100) to expose the first nitride semiconductor layer (15A). The nitride semiconductor device (10, 40, 50) described in Appendix 1, wherein the snubber resistor (201) is in contact with the first nitride semiconductor layer (15A) via the resistor opening (202).

[0128] [Note 3] The nitride semiconductor device (10, 40, 50) described in Appendix 2, wherein the snubber resistor (201) is composed of polysilicon disposed within the resistive opening (202).

[0129] [Note 4] The nitride semiconductor layer (15) is First nitride semiconductor layer (15A), The first nitride semiconductor layer (15A) is located on the second nitride semiconductor layer (15B) which has a larger band gap than the first nitride semiconductor layer (15A), and the second nitride semiconductor layer (15B) is located on the first nitride semiconductor layer (15A). The transistor (100) includes a first transistor (100A) and a second transistor (100B), The first transistor (100A) is, A first electron transport layer (16) composed of the first nitride semiconductor layer (15A), The first electron supply layer (18) is composed of the second nitride semiconductor layer (15B), It includes a first gate electrode (24), a first source electrode (28), and a first drain electrode (30) located on a first electron supply layer (18), The second transistor (100B) is, A second electron transport layer (16) composed of the first nitride semiconductor layer (15A), A second electron supply layer (18) composed of the second nitride semiconductor layer (15B), It includes a second gate electrode (24), a second source electrode (28), and a second drain electrode (30) located on a second electron supply layer (18), The first transistor (100A) and the second transistor (100B) are arranged side by side on the nitride semiconductor layer (15) such that the first drain electrode (30) and the second drain electrode (30) face each other. The nitride semiconductor device (10) according to any one of the appendices 1 to 3, wherein the snubber resistor (201) is located between the first drain electrode (30) and the second drain electrode (30) and is electrically connected to both the first drain electrode (30) and the second drain electrode (30).

[0130] [Note 5] The first drain electrode (30) and the second drain electrode (30) are arranged side by side facing each other in the first direction. The nitride semiconductor device (10) described in Appendix 4, wherein the length (L1) of the snubber resistor (201) in the first direction is longer than the thickness (T1) of the snubber resistor (201).

[0131] [Note 6] The device includes an active region (A1) on which the transistor (100) is formed, and an inactive region (A2) on which the transistor (100) is not formed. A gate pad (102) electrically connected to the gate electrode (24) is located on the nitride semiconductor layer (15) in the inactive region (A2). The nitride semiconductor layer (15) is First nitride semiconductor layer (15A), The first nitride semiconductor layer (15A) is located on the second nitride semiconductor layer (15B) which has a larger band gap than the first nitride semiconductor layer (15A), and the second nitride semiconductor layer (15B) is located on the first nitride semiconductor layer (15A). The snubber circuit (200A) includes a first electrode (204) and a second electrode (205) electrically connected to the snubber resistor (201), The first electrode (204) is located between the snubber resistor (201) and the drain electrode (30), and is electrically connected to the drain electrode (30). The nitride semiconductor device (50) according to any one of the appendices 1 to 3, wherein the second electrode (205) is electrically connected to a two-dimensional electron gas (20) generated in the first nitride semiconductor layer (15A) located directly beneath the gate pad (102) in the inactive region (A2).

[0132] [Note 7] The first electrode (204) and the second electrode (205) are arranged side by side in the first direction. The nitride semiconductor device (50) described in Appendix 6, wherein the length (L1) of the snubber resistor (201) in the first direction is longer than the thickness (T1) of the snubber resistor (201).

[0133] [Note 8] The nitride semiconductor layer (15) is First nitride semiconductor layer (15A), The first nitride semiconductor layer (15A) is located on the second nitride semiconductor layer (15B) which has a larger band gap than the first nitride semiconductor layer (15A), and the second nitride semiconductor layer (15B) is located on the first nitride semiconductor layer (15A). The transistor (100) is The electron transport layer (16) is composed of the first nitride semiconductor layer (15A), The electron supply layer (18) is composed of the second nitride semiconductor layer (15B), Located on the electron supply layer (18), the gate layer (22) contains acceptor-type impurities, The gate electrode (24) located on the gate layer (22), A passivation layer (26) covers the electron supply layer (18), the gate layer (22), and the gate electrode (24), and has a source opening (26A) and a drain opening (26B) that are spaced apart from each other with the gate layer (22) in between, The source electrode (28) is in contact with the electron supply layer (18) through the source opening (26A), A nitride semiconductor device (10, 40, 50) according to any one of appendices 1 to 7, comprising the drain electrode (30) in contact with the electron supply layer (18) through the drain opening (26B). [Explanation of Symbols]

[0134] A1...active area A2…Inactive area A3...Element isolation region HC...HEMT cell L1...Length T1...thickness 10, 40, 50… Nitride semiconductor equipment 10A…Top surface of the chip 10B...Bottom of the chip 10C…Chip side 11... Conductive substrate 12…Main board 12A…Top surface of main body 12B…Bottom surface of main body 13...electrode layer 13A…Top surface of electrode 13B…Bottom surface of electrode 14…Buffer layer 15… Nitride semiconductor layer 15A...First nitride semiconductor layer 15B...Second nitride semiconductor layer 16…Electron transport layer, first electron transport layer, second electron transport layer 18...electron supply layer, first electron supply layer, second electron supply layer 20... Two-dimensional electron gas (2DEG) 22...Gate layer 24...Gate electrode, 1st gate electrode, 2nd gate electrode 26… Passivation layer 26A... Source opening 26B...Drain opening 26C...First electrode opening 26D…Second electrode opening 28…Source electrode, first source electrode, second source electrode 28A…Source contact section 28B...Extension part 28BE…End 30... Drain electrode, first drain electrode, second drain electrode 30A...Drain contact section 30C…Drain electrode 31…Drain electrode 31A...First drain contact section 31B...Second drain contact section 31C...Drain connection 32...Interlayer insulating film 100,100C…transistor 100A...1st transistor 100B...2nd transistor 102... Gate pad 103…Sourcepad 104...Drain pad 200... Snubber circuit 200A... Snubber circuit 201... Snubber resistor 201A... Resistor body 201B... Resistive contact section 201B1…1st resistance extension part 201B2…Second resistance extension part 202...Resistance opening 204...1st electrode 204A...First electrode contact section 205…Second electrode 205A...Second electrode contact section 210... Snubber capacitor 210A…First snubber capacitor 210B...Second snubber capacitor 301...Third nitride semiconductor layer 302...first metal layer 303...Resistor layer 304…Second metal layer

Claims

1. A conductive substrate and A nitride semiconductor layer located on the conductive substrate, A transistor comprising a portion of the nitride semiconductor layer and having a gate electrode, a source electrode, and a drain electrode located on the nitride semiconductor layer, It includes a snubber circuit connected in parallel to the source electrode and the drain electrode, The conductive substrate is electrically connected to the source electrode, The aforementioned snubber circuit is A snubber resistor located on the nitride semiconductor layer and electrically connected to the drain electrode, A nitride semiconductor device comprising: a snubber resistor and a snubber capacitor electrically connected to the conductive substrate and including a parasitic capacitance formed by the nitride semiconductor layer.

2. The nitride semiconductor layer is First nitride semiconductor layer, The present invention includes a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, A resistive opening is provided in the second nitride semiconductor layer at a position different from the transistor, exposing the first nitride semiconductor layer. The nitride semiconductor device according to claim 1, wherein the snubber resistor is in contact with the first nitride semiconductor layer through the resistive opening.

3. The nitride semiconductor device according to claim 2, wherein the snubber resistor is composed of polysilicon disposed within the resistive opening.

4. The nitride semiconductor layer is First nitride semiconductor layer, The present invention includes a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, The transistor includes a first transistor and a second transistor, The first transistor is, A first electron transport layer composed of the first nitride semiconductor layer, The first electron supply layer is composed of the second nitride semiconductor layer, It includes a first gate electrode, a first source electrode, and a first drain electrode located on the first electron supply layer, The aforementioned second transistor is A second electron transport layer composed of the first nitride semiconductor layer, A second electron supply layer composed of the second nitride semiconductor layer, It includes a second gate electrode, a second source electrode, and a second drain electrode located on the second electron supply layer, The first transistor and the second transistor are arranged side by side on the nitride semiconductor layer such that the first drain electrode and the second drain electrode face each other. The nitride semiconductor device according to any one of claims 1 to 3, wherein the snubber resistor is located between the first drain electrode and the second drain electrode and is electrically connected to both the first drain electrode and the second drain electrode.

5. The first drain electrode and the second drain electrode are arranged side by side facing each other in the first direction. The nitride semiconductor device according to claim 4, wherein the length of the snubber resistor in the first direction is longer than the thickness of the snubber resistor.

6. The region includes an active region on which the transistor is formed and an inactive region on which the transistor is not formed. A gate pad electrically connected to the gate electrode is located on the nitride semiconductor layer in the inactive region. The nitride semiconductor layer is First nitride semiconductor layer, The present invention includes a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, The snubber circuit includes a first electrode and a second electrode electrically connected to the snubber resistor, The first electrode is located between the snubber resistor and the drain electrode and is electrically connected to the drain electrode. The nitride semiconductor device according to any one of claims 1 to 3, wherein the second electrode is electrically connected to a two-dimensional electron gas generated in the first nitride semiconductor layer located directly beneath the gate pad in the inactive region.

7. The first electrode and the second electrode are arranged side by side in a first direction. The nitride semiconductor device according to claim 6, wherein the length of the snubber resistor in the first direction is longer than the thickness of the snubber resistor.

8. The nitride semiconductor layer is First nitride semiconductor layer, The present invention includes a second nitride semiconductor layer located on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, The aforementioned transistor is An electron transport layer composed of the first nitride semiconductor layer, An electron supply layer composed of the second nitride semiconductor layer, A gate layer located on the electron supply layer and containing acceptor-type impurities, The gate electrode located on the gate layer, A passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having source and drain openings arranged apart from each other with the gate layer in between, The source electrode, which is in contact with the electron supply layer through the source opening, A nitride semiconductor device according to any one of claims 1 to 3, comprising the drain electrode in contact with the electron supply layer through the drain opening.

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