Resistive random-access memory structure and method for manufacturing the same

Abstract

This invention provides an improved resistive random-access memory structure and a method for manufacturing the same. [Solution] The resistive random-access memory structure includes a substrate and a memory stack structure disposed on the substrate. The memory stack structure includes a lower electrode layer, a switching layer disposed on the lower electrode layer, an upper electrode layer disposed on the switching layer, and an oxidation protection layer disposed on the sidewall of the memory stack structure. Spacers are disposed around the memory stack structure. The spacers cover the oxidation protection layer. A dielectric buffer layer is disposed on the spacers.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and more particularly to an improved resistive random-access memory structure and a method for manufacturing the same. [Background technology]

[0002] A resistive random-access memory (RRAM) cell typically consists of two conductive electrodes flanked by a switching layer, allowing the memory cell to switch between a high-resistance state (HRS) representing a logical "0" and a low-resistance state (LRS) representing a logical "1".

[0003] RRAM operation relies on the formation and breakdown of conductive filaments within the switching layer. These filaments form low-resistance paths between electrodes, driving the cell to LRS. However, the unpredictable number and distribution of these filaments result in unstable electrical characteristics, such as voltage fluctuations required to set (switch to LRS) or reset (switch to HRS) the cell.

[0004] Furthermore, when depositing ultra-low k dielectric layers (ULKs), arc phenomena occurring in the plasma chemical vapor deposition process damage the RRAM memory structure. Therefore, further efforts are needed to overcome this problem. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent No. 9847481 [Patent Document 2] U.S. Patent No. 9431604 [Patent Document 3] U.S. Patent No. 9431603 [Patent Document 4] U.S. Patent No. 9214628 [Patent Document 5] U.S. Patent No. 9209392 [Patent Document 6] U.S. Patent No. 8963114 [Patent Document 7] U.S. Patent No. 8686387 [Patent Document 8] U.S. Patent No. 7026174 [Patent Document 9] U.S. Patent No. 11844291 [Patent Document 10] U.S. Patent No. 11793091 [Patent Document 11] U.S. Patent No. 11239419 [Patent Document 12] U.S. Patent No. 10573811 [Patent Document 13] U.S. Patent No. 10153432 [Patent Document 14] Specification of Chinese Patent No. 102683173 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The object of the present invention is to provide an improved resistive random-access memory structure and a method for manufacturing the same in order to solve the shortcomings or deficiencies of existing technologies. [Means for solving the problem]

[0007] One aspect of the present invention provides a resistive random-access memory structure comprising a substrate, a memory stack structure disposed on the substrate, the memory stack structure including a lower electrode layer, a switching layer disposed on the lower electrode layer, an upper electrode layer disposed on the switching layer, and an oxidation protection layer disposed on the side wall of the memory stack structure, and a spacer located around the memory stack structure and covering the oxidation protection layer, and a dielectric buffer layer disposed on the spacer.

[0008] According to some embodiments, the resistive change memory structure further includes an inter-metal dielectric (IMD) layer covering the dielectric buffer layer.

[0009] According to some embodiments, the resistive change memory structure further includes a conductive via disposed on the memory stack structure within the IMD layer, and the conductive via is in direct contact with the upper electrode layer, the spacer, and the dielectric buffer layer.

[0010] According to some embodiments, the upper electrode layer includes a TaN layer and a TaNO x layer, and the TaNO x layer is in direct contact with the conductive via.

[0011] According to some embodiments, the conductive via includes a barrier layer and a copper layer.

[0012] According to some embodiments, the spacer is a silicon nitride spacer.

[0013] According to some embodiments, the dielectric buffer layer is a silicon oxide layer.

[0014] According to some embodiments, the silicon oxide layer is a PECVD oxide layer or a TEOS-based silicon oxide layer.

[0015] According to some embodiments, the switching layer includes a TaO x layer and a Ta2O5 layer, and the lower electrode layer includes a TaN layer.

[0016] According to some embodiments, the memory stack structure further includes an iridium layer between the switching layer and the upper electrode layer.

[0017] Another aspect of the present invention provides a method for forming a resistive random-access memory structure. A substrate is provided. A memory stack structure is formed on the substrate. The memory stack structure includes a lower electrode layer, a switching layer disposed on the lower electrode layer, an upper electrode layer disposed on the switching layer, and an oxidation protection layer disposed on the sidewall of the memory stack structure. Spacers are formed around the memory stack structure. The spacers cover the oxidation protection layer. A dielectric buffer layer is formed on the spacers.

[0018] According to some embodiments, the method further includes the step of forming an intermetallic dielectric (IMD) layer covering a dielectric buffer layer.

[0019] According to some embodiments, the method further includes the step of forming conductive vias on a memory stack structure within an IMD layer. The conductive vias are in direct contact with the upper electrode layer, spacers, and dielectric buffer layer.

[0020] According to some embodiments, the upper electrode layer is a TaN layer and a TaNO x Including layers, TaNO x The layer is in direct contact with the conductive via.

[0021] According to some embodiments, the conductive via includes a barrier layer and a copper layer.

[0022] According to some embodiments, the spacer is a silicon nitride spacer.

[0023] According to some embodiments, the dielectric buffer layer is a silicon oxide layer.

[0024] According to some embodiments, the silicon oxide layer is a PECVD oxide layer or a TEOS-based silicon oxide layer.

[0025] According to some embodiments, the switching layer is TaO x The electrode layer includes a Ta2O5 layer, and the lower electrode layer includes a TaN layer.

[0026] According to some embodiments, the memory stack structure further includes an iridium layer between the switching layer and the upper electrode layer. [Brief explanation of the drawing]

[0027] These and other objectives of the present invention will become undeniably clear to those skilled in the art after reading the following detailed description of preferred embodiments shown in various figures and drawings.

[0028] [Figure 1] This is a schematic diagram illustrating a method for forming a resistive random-access memory structure according to an embodiment of the present invention. [Figure 2] This is a schematic diagram illustrating a method for forming a resistive random-access memory structure according to an embodiment of the present invention. [Figure 3] This is a schematic diagram illustrating a method for forming a resistive random-access memory structure according to an embodiment of the present invention. [Figure 4] This is a schematic diagram illustrating a method for forming a resistive random-access memory structure according to an embodiment of the present invention. [Figure 5] This is a schematic diagram illustrating a method for forming a resistive random-access memory structure according to an embodiment of the present invention. [Modes for carrying out the invention]

[0029] The following detailed description of this disclosure refers to the accompanying drawings, which form part of this specification and illustrate specific embodiments in which the invention may be carried out. These embodiments are described in sufficient detail to enable those skilled in the art to carry out the invention.

[0030] Other embodiments may be utilized, and structural, logical, and electrical modifications may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be considered limiting, and the embodiments included herein are defined by the appended claims.

[0031] Figures 1 to 5 are schematic diagrams showing a method for forming a resistive switching memory structure 1 according to an embodiment of the present invention. As shown in Figure 1, first, a substrate 100 is provided. For example, the substrate 100 may be a silicon substrate, but is not limited thereto. An intermetallic dielectric (IMD) layer 110, a capping layer 120, and a silicon oxide layer 130 are deposited on the substrate 100. According to one embodiment of the present invention, for example, the IMD layer 110 may include a low dielectric constant material or an ultra-low dielectric constant material. According to one embodiment of the present invention, for example, the capping layer 120 may include nitrogen-doped silicon carbide having a thickness of, for example, 300 to 400 angstroms. According to an embodiment of the present invention, for example, the silicon oxide layer 130 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process (also called a PECVD oxide layer), and its thickness is, for example, 400 to 800 angstroms.

[0032] According to embodiments of the present invention, a lower metal conductor layer 210 is formed within the IMD layer 110. According to one embodiment of the present invention, the lower metal conductor layer 210 may include, but is not limited to, copper, titanium nitride, titanium, tantalum nitride, or tantalum. According to one embodiment of the present invention, for example, the lower metal conductor layer 210 is formed using a copper damascene process. According to one embodiment of the present invention, short vias 220 are formed in the capping layer 120 and the silicon oxide layer 130. According to one embodiment of the present invention, the short vias 220 may include, for example, tungsten.

[0033] According to embodiments of the present invention, a deposition process, a photolithography process, and an etching process are then performed to form a memory stack structure MS on the short vias 220 and the silicon oxide layer 130. According to one embodiment of the present invention, the memory stack structure MS includes, for example, a lower electrode layer 310, a switching layer 320 disposed on the lower electrode layer 310, an iridium layer 330 having a thickness of about 50 angstroms disposed on the switching layer 320, an upper electrode layer 340 disposed on the iridium layer 330, and a mask layer 350 disposed on the upper electrode layer 340.

[0034] According to one embodiment of the present invention, for example, the lower electrode layer 310 may include, but is not limited to, a TaN layer having a thickness of about 100 to 200 angstroms. According to one embodiment of the present invention, the switching layer 320 may include, for example, a TaO layer having a thickness of about 150 to 250 angstroms. x The layer 321 may include, but is not limited to, a Ta2O5 layer 322 having a thickness of approximately 30 to 50 angstroms. According to one embodiment of the present invention, for example, the upper electrode layer 340 may include, but is not limited to, a TaN layer having a thickness of approximately 500 to 700 angstroms. According to one embodiment of the present invention, for example, the mask layer 350 may include a PECVD oxide layer.

[0035] As shown in Figure 2, an oxidation process such as an oxygen plasma oxidation process is then performed to form an oxidation protective layer PL on the sidewall of the memory stack structure MS. According to one embodiment of the present invention, the oxidation protective layer PL is TaNO x This includes, but is not limited to, layers.

[0036] Next, as shown in FIG. 3, a deposition process and an anisotropic dry etching process are performed to form a spacer SP around the memory stack MS. According to an embodiment of the present invention, the spacer SP covers the oxidized protective layer PL. According to an embodiment of the present invention, the spacer SP contains silicon nitride, but is not limited thereto. During the above-described anisotropic dry etching process, the mask layer 350 is also etched and shrunk, whereby a part of the upper surface 340a of the upper electrode layer 340 is exposed. According to an embodiment of the present invention, the upper electrode layer 340 may include a TaNO x layer 340s on the upper surface 340a. According to an embodiment of the present invention, the upper electrode layer 340 includes a TaN layer 340t and TaNO x layer 340s.

[0037] As shown in FIG. 4, a dielectric buffer layer 410 is deposited on the substrate 100 in a blanket manner. According to an embodiment of the present invention, the dielectric buffer layer 410 may be a silicon oxide layer. According to an embodiment of the present invention, for example, the silicon oxide layer may be a PECVD oxide layer or a TEOS-based silicon oxide layer. According to an embodiment of the present invention, for example, the thickness of the dielectric buffer layer 410 may be 200 to 600 angstroms, but is not limited thereto. According to an embodiment of the present invention, the dielectric buffer layer 410 conformally covers the mask layer 350, the upper surface 340a of the upper electrode layer 340, the spacer SP, and the silicon oxide layer 130.

[0038] As shown in Figure 5, an intermetallic dielectric (IMD) layer 140 is then deposited on the substrate 100 in a blanket manner so as to cover the dielectric buffer layer 410. According to one embodiment of the present invention, for example, the IMD layer 140 may include a low dielectric constant material or an ultra-low dielectric constant material having a thickness of, for example, about 1800 to 2200 angstroms. According to one embodiment of the present invention, conductive vias MV are formed within the IMD layer 140 on the memory stack structure MS so as to be in direct contact with the upper electrode layer 340, the spacer SP, and the dielectric buffer layer 410. Protection of the spacer SP and the dielectric buffer layer 410 can protect the memory stack structure MS from arc damage during the plasma etching process.

[0039] According to one embodiment of the present invention, the upper electrode layer 340 is TaNO x Layer 340s is in direct contact with the conductive via MV. According to one embodiment of the present invention, the conductive via MV includes, for example, a barrier layer BL and a copper layer CL.

[0040] Structurally, as shown in Figure 5, the resistive random-access memory structure 1 includes a substrate 100 and a memory stack structure MS disposed on the substrate 100. The memory stack structure MS includes a lower electrode layer 310, a switching layer 320 on the lower electrode layer 310, an upper electrode layer 340 on the switching layer 320, and an oxidation protection layer PL on the sidewall of the memory stack structure MS. Spacers SP are arranged around the memory stack structure MS. The spacers SP cover the oxidation protection layer PL. A dielectric buffer layer 410 is arranged on the spacers SP.

[0041] According to one embodiment of the present invention, the spacer SP is a silicon nitride spacer. According to one embodiment of the present invention, the switching layer 320 is TaO x It includes layer 321 and Ta2O5 layer 322. The lower electrode layer 310 includes a TaN layer. According to one embodiment of the present invention, the memory stack structure MS may further include an iridium layer 330 located between the switching layer 320 and the upper electrode layer 340.

[0042] According to one embodiment of the present invention, the resistive random-access memory structure 1 further includes an IMD layer 140 covering a dielectric buffer layer 410. According to one embodiment of the present invention, the resistive random-access memory structure 1 further includes conductive vias MV disposed within the IMD layer 140 on a memory stack structure MS, the conductive vias MV being in direct contact with the upper electrode layer 340, the spacer SP, and the dielectric buffer layer 410. According to one embodiment of the present invention, the dielectric buffer layer 410 is a silicon oxide layer, for example, a PECVD oxide layer or a TEOS-based silicon oxide layer.

[0043] According to one embodiment of the present invention, the upper electrode layer 340 is made up of a TaN layer 340t and a TaNO x It can include layer 340s, TaNO x Layer 340s is in direct contact with the conductive via MV. According to one embodiment of the present invention, the conductive via MV includes a barrier layer BL and a copper layer CL.

[0044] Those skilled in the art will readily recognize that numerous modifications and changes to the apparatus and method can be made while retaining the teachings of the present invention. Therefore, the above disclosure should be construed as being limited only by the boundaries of the appended claims.

Claims

1. A resistive random-access memory structure, circuit board and A memory stack structure disposed on the substrate, wherein the memory stack structure includes a lower electrode layer, a switching layer disposed on the lower electrode layer, an upper electrode layer disposed on the switching layer, and an oxidation protection layer disposed on the side wall of the memory stack structure. A spacer located around the memory stack structure, wherein the spacer covers the oxidation protection layer, A resistive random-access memory structure comprising a dielectric buffer layer disposed on the spacer.

2. The resistive random-access memory structure according to claim 1, further comprising an intermetallic dielectric (IMD) layer covering the dielectric buffer layer.

3. The resistive switching memory structure according to claim 2, further comprising conductive vias disposed on the memory stack structure within the IMD layer, wherein the conductive vias are in direct contact with the upper electrode layer, the spacer, and the dielectric buffer layer.

4. The upper electrode layer consists of a TaN layer and a TaNO ｘ Including a layer, the TaNO ｘ The resistive random-access memory structure according to claim 3, wherein the layer is in direct contact with the conductive via.

5. The resistive random-access memory structure according to claim 3, wherein the conductive via includes a barrier layer and a copper layer.

6. The resistive switching memory structure according to claim 1, wherein the spacer is a silicon nitride spacer.

7. The resistive switching memory structure according to claim 1, wherein the dielectric buffer layer is a silicon oxide layer.

8. The resistive random-access memory structure according to claim 7, wherein the silicon oxide layer is a PECVD oxide layer or a TEOS-based silicon oxide layer.

9. The switching layer is TaO ｘ Layer and Ta ２ O ５ The resistive random-access memory structure according to claim 1, comprising a layer, wherein the lower electrode layer comprises a TaN layer.

10. The resistive random-access memory structure according to claim 1, wherein the memory stack structure further includes an iridium layer between the switching layer and the upper electrode layer.

11. A method for forming a resistive random-access memory structure, The steps include providing a substrate and A step of forming a memory stack structure on the substrate, wherein the memory stack structure includes a lower electrode layer, a switching layer disposed on the lower electrode layer, an upper electrode layer disposed on the switching layer, and an oxidation protection layer disposed on the side wall of the memory stack structure. A step of forming a spacer around the memory stack structure, wherein the spacer covers the oxidation protection layer, A method comprising the step of forming a dielectric buffer layer on the spacer.

12. The method according to claim 11, further comprising the step of forming an intermetallic dielectric (IMD) layer covering the dielectric buffer layer.

13. The method according to claim 12, further comprising the step of forming a conductive via on the memory stack structure within the IMD layer, wherein the conductive via is in direct contact with the upper electrode layer, the spacer, and the dielectric buffer layer.

14. The upper electrode layer consists of a TaN layer and a TaNO ｘ Including a layer, the TaNO ｘ The method according to claim 13, wherein the layer is in direct contact with the conductive via.

15. The method according to claim 13, wherein the conductive via includes a barrier layer and a copper layer.

16. The method according to claim 11, wherein the spacer is a silicon nitride spacer.

17. The method according to claim 11, wherein the dielectric buffer layer is a silicon oxide layer.

18. The method according to claim 17, wherein the silicon oxide layer is a PECVD oxide layer or a TEOS-based silicon oxide layer.

19. The switching layer is TaO ｘ layer and Ta ２ O ５ layer, and the lower electrode layer includes a TaN layer. The method according to claim 11

20. The method according to claim 11, wherein the memory stack structure further includes an iridium layer between the switching layer and the upper electrode layer.

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