Semiconductor equipment and electronic control systems

Abstract

To provide semiconductor devices that can reduce manufacturing costs, and electronic control systems that incorporate them. [Solution] The detection transistor 15 is configured to turn on when a back electromotive force is generated at the power output terminal 2, and the source voltage changes in conjunction with the back electromotive force. The clamp element 16 limits the gate voltage of the detection transistor 15 to a predetermined clamp voltage based on the voltage at the power output terminal 2. The gate connection circuit 42 includes a resistor element 18 that connects the power output terminal 2 to the gate of the detection transistor 15, and an nMOS transistor 19 that applies the ground power supply voltage SGND to the gate of the detection transistor 15 and blocks the current flowing from the gate of the detection transistor 15 toward the ground power supply voltage SGND.

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices and electronic control systems, and more particularly to a semiconductor device that supplies power to an externally connected load, and an electronic control system equipped with the semiconductor device. [Background technology]

[0002] Patent Document 1 describes a semiconductor device capable of preventing the failure of an output transistor due to secondary breakdown. This semiconductor device comprises a detection transistor, a control transistor, and an output transistor. The detection transistor supplies a detection current during the period when the output voltage at the load terminal is lower than the ground voltage. The control transistor is controlled to be ON during the period when the detection current flows. The output transistor is controlled to be OFF during the period when the control transistor is ON, i.e., during the period when the output voltage is lower than the ground voltage.

[0003] Patent Document 2 describes an overvoltage protection circuit that can prevent circuit malfunction caused by a set value of dynamic clamp voltage. This overvoltage protection circuit comprises an output transistor, a load, a dynamic clamp circuit, and a clamp changeover switch. The output transistor is connected between the power supply and the output terminal. The load is connected to the output terminal. The dynamic clamp circuit limits the voltage difference between the power supply and the output terminal. The clamp changeover switch is connected between the dynamic clamp circuit and the output terminal, and its conduction state is determined based on a comparison between a reference voltage and the voltage at the output terminal. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-47804 [Patent Document 2] Japanese Patent Publication No. 2007-28747 [Overview of the project] [Problems that the invention aims to solve]

[0005] For example, as shown in Patent Documents 1 and 2, a configuration is known in which power is supplied from an output transistor to a load via the output terminal. For example, if the load is inductive, a back electromotive force, such as a negative voltage, may be generated at the output terminal when the output transistor is turned off. Even if the load is not inductive, a back electromotive force may be generated at the output terminal due to, for example, the parasitic inductance component of the wire harness. Using the configuration shown in Patent Document 1, such a negative voltage can be clamped by the body diode of the output transistor, which is fixed to the off position. Alternatively, using the configuration shown in Patent Document 2, such a negative voltage can be clamped by a dynamic clamp circuit.

[0006] However, in the configurations shown in Patent Documents 1 and 2, high voltages may be applied to the detection transistor and clamp switch that detect the voltage at the output terminal. For this reason, the detection transistor and the clamp switch, and in fact the transistor, need to be composed of, for example, a high-voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a thick gate oxide film. Consequently, additional manufacturing processes are required, which could lead to increased manufacturing costs.

[0007] The embodiments described later were made in view of these considerations, and other issues and novel features will become clear from the description and accompanying drawings of this specification. [Means for solving the problem]

[0008] A semiconductor device according to one embodiment includes an output transistor, a detection transistor, a first clamp element, and a gate connection circuit. The output transistor is connected between a first power supply terminal to which a first power supply voltage is supplied and a power output terminal, and when controlled to be ON, it supplies power to a load to which a second power supply voltage is supplied at one end via the power output terminal. The detection transistor is inserted in the path between the first power supply terminal and the power output terminal, and is configured to turn ON when a back electromotive force is generated at the power output terminal, by changing its source voltage in conjunction with the back electromotive force. The first clamp element limits the gate voltage of the detection transistor to a predetermined clamp voltage with reference to the voltage at the power output terminal. The gate connection circuit is connected to the gate of the detection transistor. The gate connection circuit includes a first resistive element that connects the power output terminal to the gate of the detection transistor, and a rectifier element that applies a second power supply voltage to the gate of the detection transistor and interrupts the current in the direction from the gate of the detection transistor toward the second power supply voltage. [Effects of the Invention]

[0009] According to the above embodiment, manufacturing costs can be reduced in a semiconductor device that supplies power to a load, and in an electronic control system equipped therewith. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a circuit diagram showing an example of the configuration of the main parts of a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a timing chart showing an example of the operation of the semiconductor device in Figure 1. [Figure 3] Figure 3 shows an example of the current-voltage characteristics of a Zener diode, which is one of the clamping elements in Figure 1. [Figure 4] Figure 4 shows an example of a detailed power supply voltage waveform associated with a load dump in Figure 2. [Figure 5] Figure 5 is a cross-sectional view showing an example of the device structure in the semiconductor device shown in Figure 1. [Figure 6]FIG. 6 is a circuit block diagram showing a configuration example of an electronic control system (ECU) to which the semiconductor device shown in FIG. 1 is applied. [Figure 7] FIG. 7 is a schematic diagram showing a configuration example of a vehicle equipped with the electronic control system (ECU) shown in FIG. 6. [Figure 8] FIG. 8 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a timing chart showing an operation example of the semiconductor device in FIG. 9. [Figure 11] FIG. 11 is a circuit diagram showing a configuration example obtained by modifying FIG. 9 in the semiconductor device according to the third embodiment. [Figure 12] FIG. 12 is a circuit diagram showing a configuration example of a main part of a semiconductor device according to the fourth embodiment. [Figure 13] FIG. 13 is a timing chart showing an operation example of the semiconductor device in FIG. 12. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a main part of a semiconductor device which is a first comparative example with respect to FIG. 1. [Figure 15] FIG. 15 is a cross-sectional view showing an example of a device structure in the semiconductor device shown in FIG. 14. [Figure 16] FIG. 16 is a circuit diagram showing a configuration example of a main part of a semiconductor device which is a second comparative example with respect to FIG. 9.

Embodiments for Carrying Out the Invention

[0011] In the following embodiments, the description will be divided into multiple sections or embodiments where necessary for convenience. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, in the following embodiments, when referring to the number of elements (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number.

[0012] Furthermore, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless specifically stated or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of constituent elements, etc., it shall include those that substantially approximate or resemble such shapes, etc., unless specifically stated or considered to be not in principle. The same applies to the numerical values ​​and ranges mentioned above.

[0013] Furthermore, in the following embodiments, p-channel MOSFETs and n-channel MOSFETs are referred to as pMOS transistors and nMOS transistors, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all figures used to explain the embodiments, the same reference numerals are generally used for identical components, and repeated explanations are omitted.

[0014] (First Embodiment) <Circuit configuration of semiconductor device> Figure 1 is a circuit diagram showing an example of the main configuration of a semiconductor device 105 according to the first embodiment. The semiconductor device 105 shown in Figure 1 includes a power terminal 1, a power output terminal 2, a ground power terminal 3, a control input terminal 4, a power transistor (PT) 7, and various control circuits for controlling the power transistor (PT) 7. The various control circuits include an on / off control circuit (CTL) 9, a charge pump circuit (CP) 10, a clamp element 11, a gate resistor element 12, a control switch 13, and a protection circuit 41A. Details of the protection circuit 41A will be described later.

[0015] Power terminal 1 receives a battery voltage Vbat, such as 12V, from an external battery 6 via power wiring. This supplies a power supply voltage (first power supply voltage) VCC to power terminal 1, i.e., power node N6. A load 8 is connected to power output terminal 2. Load 8 is, for example, an inductive load. One end of load 8 is supplied with a ground power supply voltage (second power supply voltage) PGND. In addition, an output voltage VOUT and an output current IOUT are generated at power output terminal 2.

[0016] The power transistor (PT) 7 is also an output transistor connected between the power supply terminal 1 and the power output terminal 2. When controlled to be ON, the power transistor (PT) 7 supplies power to the load 8 connected to the power output terminal 2 via the power output terminal 2. In this example, the power transistor (PT) 7 is an nMOS transistor. The source and drain of the power transistor (PT) 7 are connected to the power output terminal 2 and the power supply terminal 1, respectively.

[0017] The power transistor (PT) 7 has a body diode 30 with a commonly connected source and back gate as the anode and drain as the cathode. A clamping element 11, specifically a Zener diode, clamps the gate-source voltage VGSo of the power transistor (PT) 7. This limits the gate voltage of the power transistor (PT) 7 so that it does not become excessively high by the charge pump circuit 10.

[0018] The control input terminal 4 receives an external on / off control signal IN. The on / off control circuit 9 exclusively controls the charge pump circuit 10 and the control switch 13 in response to the on / off control signal IN. The control switch 13 is, for example, an nMOS transistor. When the control switch 13 is controlled to ON, it short-circuits the output node N3 of the charge pump circuit 10 with the power output terminal 2, i.e., the power output node N7.

[0019] For example, when the on / off control signal IN is at the on level, the on / off control circuit 9 activates the charge pump circuit 10. This causes the charge pump circuit 10 to generate a boosted voltage Vcp that is higher than the power supply voltage VCC. The boosted voltage Vcp is applied to the gate node N4 of the power transistor (PT) 7 via the gate resistor element 12. On the other hand, when the on / off control signal IN is at the off level, the on / off control circuit 9 controls the control switch 13 to the on level. This controls the power transistor (PT) 7 to be turned off by short-circuiting the gate-source connection via the gate resistor element 12 and the control switch 13.

[0020] Here, we will explain the operation when the protection circuit 41A is not provided. When the on / off control signal IN transitions from the on level to the off level, the power transistor (PT) 7 turns off. At this time, a back electromotive force is generated at the power output terminal 2, for example due to the load 8, in this case a negative voltage lower than the 0V ground power supply voltage PGND. On the other hand, the power transistor (PT) 7 can remain off because its gate-source is short-circuited via the gate resistor element 12 and the control switch 13.

[0021] As a result, the power transistor (PT) 7 can clamp the drain-source voltage, and consequently the back electromotive force generated at the power output terminal 2, based on the clamp voltage of the body diode 30, in other words, the Zener voltage. Furthermore, the power transistor (PT) 7 can dissipate the flyback energy associated with the back electromotive force via the body diode 30. This type of clamping operation is sometimes called avalanche clamping.

[0022] However, a problem may arise if the on / off control signal IN transitions from the off level to the on level during a period when a back electromotive force is generated at the power output terminal 2. In this case, the control switch 13 is turned off and the charge pump circuit 10 is activated, resulting in the power transistor (PT) 7 turning on with a high drain-source voltage applied. As a result, the power transistor (PT) 7 may be destroyed by deviating from the safe operating area (SOA). Therefore, a protection circuit 41A is provided to maintain the off state of the power transistor (PT) 7 even in such cases.

[0023] <Regarding the protective circuit used as a comparative example> Here, before describing the protection circuit 41A, we will describe a protection circuit that serves as a first comparative example. Figure 14 is a circuit diagram showing an example of the main components of a semiconductor device 300 that serves as a first comparative example with respect to Figure 1. The semiconductor device 300 shown in Figure 14 differs from the semiconductor device 105 shown in Figure 1 in the configuration of the protection circuit 41C. The protection circuit 41C shown in Figure 14 comprises a detection transistor 15, a Zener diode 14, pMOS transistors 31 and 32, an nMOS transistor 33, and a control switch 34.

[0024] The detection transistor 15 is inserted in the path between the power supply terminal (first power supply terminal) 1 and the power output terminal 2. The detection transistor 15 is generally configured to turn on when a back electromotive force is generated at the power output terminal 2, by changing its source voltage in conjunction with the back electromotive force.

[0025] Specifically, the detection transistor 15 is composed of, for example, an nMOS transistor. The source and back gate of the detection transistor 15 are connected to the power output terminal 2. The gate of the detection transistor 15 is connected to the ground power supply terminal 3. A ground power supply voltage (second power supply voltage) SGND, which is 0V, is applied to the ground power supply terminal 3. As a result, the detection transistor 15 turns on when a negative voltage occurs at the power output terminal 2, more specifically, when the negative voltage causes a gate-source voltage VGSd to exceed the threshold voltage. When the detection transistor 15 is turned on, it flows a detection current Idet.

[0026] The Zener diode 14 is inserted in the path between the power supply terminal 1, i.e., the power supply node N6, and the drain of the detection transistor 15. The Zener diode 14 sets the upper limit of the output voltage VOUT required to activate the protection circuit 41C. That is, the protection circuit 41C is activated when the output voltage VOUT drops below the Zener voltage of the Zener diode 14 with respect to the power supply voltage VCC. This allows the protection circuit 41C to remain deactivated, for example, when a negative voltage of noise level that is not a back electromotive force occurs, preventing the protection circuit 41C from being unnecessarily activated.

[0027] As a specific example, the clamp voltage of the body diode 30 is 40V, etc. On the other hand, the Zener voltage of the Zener diode 14 is set to 18V, etc. When the power supply voltage VCC is 12V, the protection circuit 41C becomes active when the output voltage VOUT drops below -6V. Also, when it becomes active, the detection transistor 15 is on because a gate-source voltage of 6V VGSd is applied to it. Note that the protection circuit 41C must be activated at least before the avalanche clamp operation by the body diode 30 begins. For this reason, the Zener voltage of the Zener diode 14 is set to be lower than the clamp voltage of the body diode 30.

[0028] The pMOS transistors 31 and 32 constitute a current mirror circuit. The source pMOS transistor 31 transfers the detection current Idet flowing through the detection transistor 15 to the destination pMOS transistor 32. The nMOS transistor 33 is connected between node N10, which is the drain of the pMOS transistor 32, and the power output node N7. The nMOS transistor 33 is, for example, a depletion-type transistor with its gate-source short-circuited, and functions as a current source or a high-resistance element. The nMOS transistor 33 is also a voltage conversion element that converts the current transferred to node N10 into a voltage.

[0029] The control switch (first control switch) 34 is controlled to be on or off by a voltage converted by the nMOS transistor 33. When the control switch 34 is controlled to be on, that is, when a detection current Idet flows through the detection transistor 15 in response to a negative voltage, it short-circuits the gate-source of the power transistor (PT) 7. The control switch 34 consists of an nMOS transistor whose source and drain are connected to the power output node N7 and gate node N4.

[0030] By providing such a protection circuit 41C, as described above, even if the on / off control signal IN transitions from the off level to the on level during the period when a back electromotive force is generated at the power output terminal 2, the control switch 34 can be kept in the on state as long as the back electromotive force is generated. As a result, the power transistor (PT) 7 can be kept in the off state, thus preventing damage to the power transistor (PT) 7.

[0031] However, in the configuration example shown in Figure 14, a high gate-source voltage VGSd may be applied to the detection transistor 15. For example, if the power supply voltage VCC is 12V and the clamp voltage of the body diode 30 is 40V, the output voltage VOUT will be -28V during the period when the avalanche clamp operation is performed. In this case, the gate-source voltage VGSd will be +28V. For this reason, the detection transistor 15 needed to be a high-voltage MOS transistor.

[0032] <Regarding the device structure used as a comparative example> Figure 15 is a cross-sectional view showing an example of the device structure in the semiconductor device 300 shown in Figure 14. Figure 15 shows a unit output transistor PTu, low-voltage pMOS transistors MP-L and nMOS transistors MN-L, and high-voltage pMOS transistors MP-H2 and nMOS transistors MN-H2. The power transistor (PT) 7 is, in detail, composed of multiple unit output transistors PTu connected in parallel with each other. Figure 15 shows one of these unit output transistors PTu. Furthermore, the various control circuits described in Figure 1 are constructed using pMOS transistors MP-L, MP-H2 and nMOS transistors MN-L, MN-H2.

[0033] In Figure 15, an N-type epitaxial layer 502 is formed on an N-type semiconductor substrate 501. The unit output transistor PTu, pMOS transistors MP-L, MP-H2, and nMOS transistors MN-L, MN-H2 are formed using a diffusion layer or the like placed on the surface of the epitaxial layer 502. Furthermore, the unit output transistor PTu, pMOS transistors MP-L, MP-H2, and nMOS transistors MN-L, MN-H2 are separated from each other by a thick oxide film 503 (LOCOS).

[0034] The unit output transistor PTu is composed of a vertical nMOS transistor with the back surface of the semiconductor substrate 501 as the drain. Specifically, a Pbase diffusion layer 505, which serves as the back gate (BG), is formed on the surface of the epitaxial layer 502. Within the Pbase diffusion layer 505, N + A source (S) diffusion layer 510 and a P for supplying power to the back gate (BG) + A power supply diffusion layer 511 of the type is formed. The epitaxial layer 502 and the semiconductor substrate 501 become drains (D). The power supply voltage VCC is supplied to the drains (D), i.e., the back surface of the semiconductor substrate 501.

[0035] In addition, a trench 509 extending in the depth direction is formed in the epitaxial layer 502. A thin gate oxide film 506 and polysilicon 508 serving as a gate (G) are embedded in the trench 509. The source (S) diffusion layer 510 is formed at a position contacting the sidewall of the trench 509. When a predetermined voltage is applied between the gate (G) and the source (S), a channel is formed at a location on the sidewall of the trench 509 in the Pbase diffusion layer 505. As a result, a drive current flows from the back surface of the semiconductor substrate 501 toward the source (S) diffusion layer 510.

[0036] In the pMOS transistor MP-L with a low-voltage specification, on the surface of the epitaxial layer 502, P + -type source (S) diffusion layer 511 and drain (D) diffusion layer 511, and an N + -type power supply diffusion layer 510 for the back gate are formed. On the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, polysilicon 508 serving as a gate (G) is formed via a thin gate oxide film 506.

[0037] In the nMOS transistor MN-L with a low-voltage specification, from the surface of the epitaxial layer 502, a P - -type deep diffusion layer 504, that is, a p-well is formed. In the P - -type diffusion layer 504, an N + -type source (S) diffusion layer 510 and drain (D) diffusion layer 510, and a P + -type power supply diffusion layer 511 for the back gate are formed. On the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, polysilicon 508 serving as a gate (G) is formed via a thin gate oxide film 506. Note that the pMOS transistor MP-L and the nMOS transistor MN-L with a low-voltage specification have a breakdown voltage of about 6V, for example.

[0038] In the pMOS transistor MP-H2 with a high-voltage specification, on the surface of the epitaxial layer 502, P +The source (S) diffusion layer 511 of type and N for the back gate + A power supply diffusion layer 510 of the type is formed. On the other hand, on the drain (D) side, P is released from the surface of the epitaxial layer 502. - A deep diffusion layer 512 of the type is formed. - In the type diffusion layer 512, P + A drain (D) diffusion layer 511 of type 511 is formed.

[0039] Furthermore, polysilicon 508, which forms the gate (G), is formed on the epitaxial layer 502 located between the source (S) diffusion layer 511 and the drain (D) diffusion layer 511, via a thick gate oxide film 507. Thus, the film thickness TH2 of the gate oxide film 507 used in the high-pressure specification is greater than the film thickness TH1 of the gate oxide film 506 used in the low-pressure specification. Moreover, unlike the low-pressure specification, the gate oxide film 507 and polysilicon 508 near the drain (D) are layered on top of a thick oxide film 503 to achieve high pressure resistance.

[0040] In the high-voltage nMOS transistor MN-H2, P is present on the surface of the epitaxial layer 502. - A deep diffusion layer 504 of the type, i.e., a p-well, is formed. - In the diffuse layer 504 of type N + A source (S) diffusion layer 510 of type and P for the back gate + A power supply diffusion layer 511 of the type is formed. On the other hand, on the drain (D) side, N is emitted from the surface of the epitaxial layer 502. - A deep diffusion layer 513 of the N type is formed. - In the diffuse layer 513 of type N + A drain (D) diffusion layer 510 of type 510 is formed.

[0041] Furthermore, polysilicon 508, which forms the gate (G), is formed on the epitaxial layer 502 located between the source (S) diffusion layer 510 and the drain (D) diffusion layer 510, via a thick gate oxide film 507. Similar to the pMOS transistor MP-H2, the thickness TH2 of the gate oxide film 507 is greater than the thickness TH1 used in low-voltage specifications. In addition, the gate oxide film 507 and polysilicon 508 near the drain (D) overlap a thick oxide film 503 to achieve high breakdown voltage.

[0042] Furthermore, as shown in Figure 15, an NPN-type parasitic bipolar transistor 50 may be formed on the nMOS transistor MN-H2. The parasitic bipolar transistor 50 is N + Type drain (D) diffusion layer 510 and N - A deep diffusion layer 513 of the type is emitted, P + Type power supply diffusion layer 511 and P - The deep diffusion layer 504 of the N-type semiconductor substrate 501 and the epitaxial layer 502 operate as the base and collector, respectively. Although not shown in the figure, the parasitic bipolar transistor can also be formed on an nMOS transistor MN-L.

[0043] In the device structure described above, the detection transistor 15 needs to be composed of, for example, a high-voltage nMOS transistor MN-H2. Furthermore, most of the other transistors can be composed of low-voltage pMOS transistors MP-L and nMOS transistors MN-L. This necessitates separate manufacturing processes for forming a thin gate oxide film 506 with thickness TH1 and a thick gate oxide film 507 with thickness TH2. As a result, manufacturing costs could increase.

[0044] <Regarding the protection circuit according to the embodiment> Therefore, the protection circuit 41A shown in Figure 1 is provided. In addition to the same components as the protection circuit 41C shown in Figure 14, the protection circuit 41A includes a clamp element 16, a gate connection circuit 42, and a clamp element 35. The clamp element (first clamp element) 16, specifically the Zener diode, limits the gate voltage of the detection transistor 15 to a predetermined clamp voltage with respect to the output voltage VOUT. That is, the clamp element 16 clamps the gate-source voltage VGSd and the gate-back gate voltage of the detection transistor 15.

[0045] The clamp element (second clamp element) 35, specifically the Zener diode, limits the gate-source voltage VGSc2 of the control switch (first control switch) 34 to a predetermined clamp voltage. That is, when a back electromotive force is generated at the power output terminal 2, a high voltage can be generated not only at the detection transistor 15 but also at the gate-source of the control switch 34. Therefore, the clamp element 35 is provided. The clamp voltage of the clamp elements 16 and 35, i.e., the Zener voltage, is, for example, 6V.

[0046] The gate connection circuit 42 is connected to the gate of the detection transistor 15. The gate connection circuit 42 comprises two resistors 17 and 18 and an nMOS transistor 19 which is a rectifier element. The resistor (first resistor) 18 connects the power output terminal 2 to the gate of the detection transistor 15. The nMOS transistor 19 applies the ground power supply voltage (second power supply voltage) SGND to the gate of the detection transistor 15, blocking the current flowing from the gate of the detection transistor 15 toward the ground power supply voltage SGND.

[0047] In this example, the gate-source of the nMOS transistor 19 is short-circuited. Additionally, the source and back gate of the nMOS transistor 19 are connected in common. As a result, the nMOS transistor 19 functions as a diode with the source and back gate as anodes and the drain as the cathode.

[0048] Specifically, the nMOS transistor 19 is a diode element using a body diode between the back gate and drain, and is also a transistor that is diode-connected with the source and drain reversed. The nMOS transistor 19, functioning as a diode, applies the ground power supply voltage SGND input to the anode to the gate of the detection transistor 15 from its cathode. The nMOS transistor 19, also functioning as a diode, blocks current flowing from the cathode to the anode.

[0049] The resistive element (second resistive element) 17 is connected in series with the nMOS transistor 19. More specifically, the resistive element 17 is connected between the drain of the nMOS transistor 19 and node N8, which is the gate of the detection transistor 15. The resistive element 17 is provided to limit the current flowing from the ground power supply voltage SGND through the gate of the detection transistor 15 to the clamp element 16, although this will be described in detail later.

[0050] In the configuration described above, first, by providing the clamp element 16, the upper limits of the gate-source voltage VGSd and the gate-back gate voltage of the detection transistor 15 can be limited to 6V, etc. As a result, the detection transistor 15 can be made of an nMOS transistor having a thin gate oxide film. However, for example, simply adding the clamp element 16 to the configuration example shown in Figure 14 may cause problems in normal operation rather than avalanche clamp operation.

[0051] In other words, during normal operation, when the power transistor (PT) 7 is controlled to be ON, a shoot-through current flows from the power output terminal 2, to which approximately the power supply voltage VCC is applied, to the ground power supply terminal 3, to which the ground power supply voltage SGND is applied, via the forward clamping element 16. Therefore, in Figure 1, an nMOS transistor 19 that functions as a diode is provided. This prevents such shoot-through current. Note that a normal diode element may be provided instead of the nMOS transistor 19.

[0052] On the other hand, the nMOS transistor 19, which functions as a diode, is reverse-biased during periods when no negative voltage is generated at the power output terminal 2. During this period, node N8, which is the gate of the detection transistor 15, can maintain a voltage higher than the ground power supply voltage SGND, for example, approximately the power supply voltage VCC, via the forward clamping element 16. As a result, the detection transistor 15 can remain on even during periods when no negative voltage is generated at the power output terminal 2, for example, during periods when the power transistor (PT) 7 is ON.

[0053] Therefore, in Figure 1, a resistor 18 is provided to connect the power output terminal 2 and node N8. This allows the power output terminal 2 and node N8 to be short-circuited during periods when no negative voltage is generated at the power output terminal 2, i.e., during periods when the nMOS transistor 19, which functions as a diode, is reverse-biased. As a result, the detection transistor 15 can be kept off.

[0054] <Semiconductor device operation> Figure 2 is a timing chart showing an example of the operation of the semiconductor device 105 in Figure 1. For comparison, Figure 2 also shows the gate-source voltages VGSd and VGSc2 when using the configuration example shown in Figure 14. Figure 2 also shows four periods T1-T4. Period T1 is the period when the power transistor (PT) 7 is off. Period T2 is the period after the power transistor (PT) 7 has been turned on. Period T3 is the period after the power transistor (PT) 7 has been turned off. Period T4 is the period during which a load dump occurs.

[0055] [Regarding Period T1 (PT: Off)] The control input terminal 4 receives an ON / OFF control signal IN at the "L" level, i.e., the off level. In response, the ON / OFF control circuit 9 controls the control switch 13 to ON by outputting an "H" level to node N5, i.e., the gate-source voltage VGSc1. The ON / OFF control circuit 9 also controls the charge pump circuit 10 to an inactive state by outputting an "L" level to node N2. The power transistor (PT) 7 turns OFF when the gate-source voltage VGSo becomes 0V in response to the ON state of the control switch 13.

[0056] On the other hand, the output voltage VOUT generated at the power output node N7 becomes the ground power supply voltage PGND when the power transistor (PT) 7 is turned off. At this time, the gate voltage of the detection transistor 15, i.e., the voltage at node N8, becomes equal to the voltage at the power output node N7 via the resistor element 18. As a result, the detection transistor 15 turns off when its gate-source voltage VGSd becomes 0V.

[0057] [Regarding Period T2 (PT: Turn-On & On)] The control input terminal 4 receives an "H" level, i.e., an on-level on / off control signal IN. In response, the on / off control circuit 9 outputs an "L" level to node N5, i.e., the gate-source voltage VGSc1, thereby turning off the control switch 13. The on / off control circuit 9 also outputs an "H" level to node N2, thereby activating the charge pump circuit 10. As a result, a boosted voltage Vcp is applied to the gate node N4 of the power transistor (PT) 7. The power transistor (PT) 7 turns on when the on-level gate-source voltage VGSo is applied.

[0058] The output voltage VOUT is approximately the same level as the power supply voltage VCC due to the power transistor (PT) 7 being in the ON state. At this time, the gate voltage of the detection transistor 15, i.e., the voltage at node N8, becomes equal to the voltage at power output node N7 via the resistor element 18. As a result, the detection transistor 15 turns OFF when the gate-source voltage VGSd becomes 0V. On the other hand, when using the configuration example shown in Figure 14, the gate-source voltage VGSd becomes an OFF voltage with a magnitude equivalent to the output voltage VOUT, i.e., the power supply voltage VCC.

[0059] Furthermore, as shown in Figure 1, by providing the nMOS transistor 19 which functions as a diode, no particular problems arise even when the output voltage VOUT becomes approximately the same level as the power supply voltage VCC. In other words, the nMOS transistor 19 which functions as a diode can interrupt the current flowing from the power output terminal 2 to the ground power supply terminal 3 via the clamp element 16 or the resistor elements 18, 17.

[0060] [Regarding Period T3 (PT: Turn-off & Off)] The control input terminal 4 receives an on / off control signal IN at the "L" level again. In response, as in the case of period T1, the control switch 13 turns on and the charge pump circuit 10 becomes inactive, causing the power transistor (PT) 7 to turn off. At this time, the flyback energy stored in the load 8 is released. The resulting back electromotive force causes the output voltage VOUT to become a negative voltage. As a result, an avalanche clamp operation is performed.

[0061] The output voltage VOUT is clamped to prevent it from falling below a predetermined negative voltage Vn, based on the clamp voltage Vclp, i.e., the Zener voltage Vz30, of the body diode 30 of the power transistor (PT) 7. The avalanche clamp operation is maintained as long as the power transistor (PT) 7 is in the off state. In the avalanche clamp operation, the flyback energy is released through the body diode 30. Once the flyback energy is completely released, the output voltage VOUT becomes the ground power supply voltage PGND.

[0062] However, as shown in Figure 2, if the on / off control signal IN reaches the "H" level during the avalanche clamp operation, the control switch 13 turns off and the charge pump circuit 10 becomes active. As a result, if the power transistor (PT) 7 is turned on, the avalanche clamp operation cannot be maintained. Furthermore, since the power transistor (PT) 7 is turned on with a high drain-source voltage applied, its operating point will be outside the safe operating area (SOA). In this case, the power transistor (PT) 7 may be destroyed by thermal runaway.

[0063] On the other hand, if a protection circuit 41A is provided, even in such a case, the avalanche clamp operation, that is, the off state of the power transistor (PT) 7 can be maintained. Specifically, when the output voltage VOUT becomes a negative voltage, current flows from the ground power supply terminal 3 through the power output node N7 and the load 8. As a result, the gate voltage of the detection transistor 15, i.e., the voltage at node N8, drops from the ground power supply voltage SGND, which is 0V, by the forward voltage of the body diode of the nMOS transistor 19, for example, 0.6V.

[0064] As a result, the detection transistor 15 turns on because the gate-source voltage VGSd becomes on level. At this time, the gate-source voltage VGSd of the detection transistor 15 is limited by the clamp voltage of the clamp element 16, i.e., the Zener voltage Vz16 such as 6V. On the other hand, when using the configuration example shown in Figure 14, the gate-source voltage VGSd becomes an on voltage with a magnitude of the negative voltage Vn generated at the power output node N7, for example, 28V.

[0065] When the detection transistor 15 is turned on, node N10, which is the transfer destination of the current mirror circuit, becomes "H" level. As a result, the gate-source voltage VGSc2 of the control switch 34 becomes ON level. At this time, the gate-source voltage VGSc2 is limited by the clamp voltage of the clamp element 35, i.e., the Zener voltage Vz35 such as 6V. On the other hand, when using the configuration example shown in Figure 14, the gate-source voltage VGSc2 can become an ON voltage greater than the magnitude of the negative voltage Vn.

[0066] The control switch 34 turns on when the gate-source voltage VGSc2 becomes ON. The control switch 34 remains ON as long as the detection transistor 15 is ON, and consequently, the output voltage VOUT is a negative voltage. The gate-source voltage VGSo of the power transistor (PT) 7 is 0V as long as the control switch 34 is ON. As a result, the power transistor (PT) 7 remains OFF as long as the output voltage VOUT is a negative voltage, regardless of the ON / OFF control signal IN, and maintains the avalanche clamp operation.

[0067] Here, when the output voltage VOUT becomes a negative voltage, the current path from the ground power supply terminal 3 to the power output terminal 2 includes a path through the resistor element 18 and a path through the clamp element 16. In this case, if the current flowing through the clamp element 16 becomes large, the clamp voltage may increase due to its operating resistance.

[0068] Figure 3 shows an example of the current-voltage characteristics of a Zener diode, which is one of the clamping elements in Figure 1. As shown in Figure 3, when the Zener current Iz flowing through the Zener diode increases from "IzA" to "IzB", the Zener voltage Vz also rises from "VzA" to "VzB". In this way, when the clamping voltage of the clamping element 16 becomes high, the gate-source voltage VGSd of the detection transistor 15 may exceed its breakdown voltage. Therefore, in Figure 1, a resistor element 17 is provided. This limits the Zener current Iz flowing through the clamping element 16 and suppresses fluctuations in the clamping voltage.

[0069] [Regarding Period T4 (Road Dump)] During period T4, the power transistor (PT) 7 is in the off state, and a high-voltage surge occurs at power supply terminal 1, i.e., power supply node N6. One type of power supply surge is a high-energy surge called a load dump. Figure 4 shows an example of a detailed power supply voltage waveform associated with a load dump in Figure 2. As shown in Figure 4, the power supply voltage VCC rises from 12V to a predetermined load dump voltage VLD due to the load dump, and then returns to the original 12V after a time constant τ of, for example, 400ms.

[0070] When a load dump occurs, a high voltage is applied between the drain and source of the power transistor (PT) 7, similar to when a back electromotive force is generated. However, if the power transistor (PT) 7 performs avalanche clamping even in response to a load dump, the high energy may cause the power transistor (PT) 7 to be destroyed. Therefore, countermeasures against load dumps are taken by a circuit not shown in Figure 1. In parallel with this, the detection transistor 15 needs to remain in the off state in response to a load dump. The detection transistor 15 shown in Figure 1 is configured to remain in the off state when a positive voltage fluctuation occurs at the power supply node N6.

[0071] <About the device structure according to the embodiment> Figure 5 is a cross-sectional view showing an example of the device structure in the semiconductor device 105 shown in Figure 1. The structure of the high-voltage pMOS transistor MP-H1 and nMOS transistor MN-H1 differs between the structure shown in Figure 5 and the structure shown in Figure 15. Specifically, the high-voltage pMOS transistor MP-H1 and nMOS transistor MN-H1 are equipped with a thin gate oxide film 506 having a film thickness TH1 instead of the thick gate oxide film 507 having a film thickness TH2 shown in Figure 15.

[0072] In other words, by providing the clamp element 16, the gate-source voltage VGSd and gate-back gate voltage of the detection transistor 15 can be limited, as shown in Figure 2. Similarly, by providing the clamp element 35, the gate-source voltage VGSc2 and gate-back gate voltage of the control switch 34 can be limited. For this reason, the detection transistor 15 and the control switch 34 can be realized using nMOS transistors MN-H1 having a thin gate oxide film 506. As a result, unlike in the case of Figure 15, the manufacturing process does not require the step of forming a thick gate oxide film 507 with a thickness TH2, thus reducing manufacturing costs.

[0073] <Examples of application to electronic control units (ECUs)> Figure 6 is a circuit block diagram showing an example configuration of an electronic control unit (ECU) 401 to which the semiconductor device 105 shown in Figure 1 is applied. The electronic control unit (ECU) 401 shown in Figure 6 includes, in addition to the semiconductor device 105 shown in Figure 1, a power regulator 404 and a diode 403, and an ECU control device 402, in this case a microcontroller unit (MCU). The electronic control unit (ECU) 401 may be composed of a wiring board or the like on which these components are mounted.

[0074] The electronic control unit (ECU) 401 also has a power terminal 1A, a ground power terminal 3A, and a power output terminal 2A. A battery 6 is connected between power terminal 1A and ground power terminal 3A. A load is connected to power output terminal 2A. In this example, the load is a vehicle lamp load 8a-8c. The other end of the lamp load 8a-8c is supplied with ground power voltage PGND.

[0075] Power terminal 1A receives the battery voltage Vbat. Power regulator 404 receives the power voltage VCC obtained from power terminal 1A and generates a low-voltage power supply voltage for the ECU control device 402. The generated power supply voltage is supplied to the ECU control device 402 via diode 403. In addition, the ground power supply voltage SGND of the battery 6 is supplied to one end of the ECU control device 402 via ground power terminal 3A. Diode 403 is responsible for protecting the ECU control device 402 and prevents reverse current from flowing to the ECU control device 402 in the event of reverse connection of the battery 6, etc.

[0076] The power supply terminal 1 of the semiconductor device 105 is supplied with a power supply voltage VCC from the power supply terminal 1A of the electronic control unit (ECU) 401. The power output terminal 2 of the semiconductor device 105 is connected to the power output terminal 2A of the electronic control unit (ECU) 401. In addition, the ground power supply terminal 3 of the semiconductor device 105 is supplied with a ground power supply voltage SGND via the ground power supply terminal 3A of the electronic control unit (ECU) 401.

[0077] The output port of the ECU control device 402 is connected to the control input terminal 4 of the semiconductor device 105. The ECU control device 402 outputs an on / off control signal IN to the semiconductor device 105 to instruct the power transistor (PT) 7 to be turned on or off. Based on the on / off control signal IN from the control input terminal 4, the semiconductor device 105 controls the power supply to the lamp loads 8a-8c. Here, for example, if a back electromotive force is generated at the power output terminal 2A at the moment the power supply to the lamp loads 8a-8c is stopped, the semiconductor device 105 performs an avalanche clamp operation.

[0078] Furthermore, the semiconductor device 105 can maintain the avalanche clamp operation, i.e., the off state of the power transistor (PT) 7, even if the on / off control signal IN becomes high during the avalanche clamp operation. As a result, the power transistor (PT) 7 can be properly protected within the safe operating area (SOA). This makes it possible to improve the reliability of the electronic control unit (ECU) 401.

[0079] Figure 7 is a schematic diagram showing an example configuration of a vehicle 109 equipped with the electronic control unit (ECU) 401 shown in Figure 6. The vehicle 109 is, for example, an automobile. The vehicle 109 shown in Figure 7 is equipped with a battery 6, an electronic control unit 401, and lamp loads 8a-8c, as shown in Figure 6. For example, the rated power of the lamp loads 8a, 8b, and 8c are 21W, 5W, and 21W, respectively.

[0080] The electronic control system 401 and the ramp loads 8a-8c are connected by a wire harness. More specifically, the ramp loads 8a-8c are provided in two sets, one for right turns and one for left turns. Accordingly, the electronic control system (ECU) 401 may be configured such that one ECU control device 402 controls two semiconductor devices 105. Also, the ground power supply voltage PGND shown in Figure 6 is connected, for example, to the housing of the vehicle 109.

[0081] <Main effects of the first embodiment> As described above, the semiconductor device 105 according to the first embodiment includes a detection transistor 15 that detects the back electromotive force from the load 8, a clamping element 16 that clamps its gate-source voltage VGSd, and a gate connection circuit 42 connected to the gate of the detection transistor 15. This makes it possible to perform avalanche clamping without damaging the output transistor, and the detection transistor 15 can be formed using a thin gate oxide film 506. As a result, manufacturing costs can be reduced.

[0082] (Second Embodiment) <Circuit configuration of semiconductor device> Figure 8 is a circuit diagram showing an example of the main configuration of the semiconductor device 106 according to the second embodiment. The semiconductor device 106 shown in Figure 8 differs from the configuration example shown in Figure 1 in the configuration of the protection circuit 41B, and more specifically, the gate connection circuit 43. In the gate connection circuit 43, the nMOS transistor 19 has, more specifically, a vertically structured NPN parasitic bipolar transistor 50, as described in Figure 15. As shown in Figure 8, the parasitic bipolar transistor 50 operates with the drain of the nMOS transistor 19 as the emitter and the source and back gate as the base. The collector of the parasitic bipolar transistor 50 is connected to the power supply node N6.

[0083] Here, for example, let's assume that a parasitic bipolar transistor 50 exists in the configuration example shown in Figure 1, and that operation is performed during the period T3 shown in Figure 2, i.e., the negative voltage period. In this case, a forward current flows through the body diode of the nMOS transistor 19, with the source and back gate as anodes and the drain as the cathode. As a result, the parasitic bipolar transistor 50 can turn on. When this happens, the drain voltage of the nMOS transistor 19 rises toward the power supply voltage VCC. Consequently, the current flowing through the clamp element 16 increases, and the gate-source voltage VGSd of the detection transistor 15 may become excessively high.

[0084] In Figure 8, a resistor (third resistor) 21 and a clamp element 20 are connected to the nMOS transistor 19. As in Figure 1, the gate of the nMOS transistor 19 is supplied with a ground-level voltage SGND. However, unlike in Figure 1, the source of the nMOS transistor 19 is supplied with a ground-level voltage SGND via the resistor 21. The resistor 21 may be made of, for example, polysilicon. The clamp element 20, more specifically a Zener diode, limits the gate-source voltage of the nMOS transistor 19 to a predetermined clamp voltage.

[0085] In this configuration, when the output voltage VOUT becomes negative due to the back electromotive force, current flows sequentially from the ground power supply terminal 3 to the power output node N7 through the resistor 21, the body diode of the nMOS transistor 19, and the resistors 17 and 18. At this time, a voltage drop occurs across the resistor 21. When this voltage drop exceeds the threshold voltage of the nMOS transistor 19, the nMOS transistor 19 turns on. The drain-source voltage of the nMOS transistor decreases upon turning on. As a result, the parasitic bipolar transistor 50 can maintain its off state because its base-emitter voltage becomes smaller.

[0086] <Main effects of the second embodiment> As described above, the semiconductor device 106 according to the second embodiment can be used to obtain the same effects as those described in the first embodiment. Furthermore, when a back electromotive force is generated at the power output terminal 2, the parasitic bipolar transistor 50 of the nMOS transistor 19 can be kept in the off state. As a result, malfunctions associated with the turning on of the parasitic bipolar transistor 50 can be prevented. Specifically, it is possible to prevent situations in which the clamp voltage of the clamp element 16 rises, causing a breakdown voltage violation of the detection transistor 15.

[0087] (Third embodiment) <Circuit configuration of semiconductor device> Figure 9 is a circuit diagram showing an example of the main components of a semiconductor device 205 according to a third embodiment. Figure 16 is a circuit diagram showing an example of the main components of a semiconductor device 305, which is a second comparative example with respect to Figure 9. First, in order to facilitate understanding of the invention, Figure 16 will be described before describing Figure 9. The semiconductor device 305, which is a second comparative example shown in Figure 16, is equipped with a dynamic clamp circuit 40D instead of the protection circuit 41A shown in Figure 1. The other components are the same as in Figure 1, so a detailed explanation will be omitted.

[0088] Here, the protection circuit 41A shown in Figure 1 is a circuit designed to prevent malfunctions when the semiconductor device 105 performs avalanche clamp operation, specifically, malfunctions that occur when the on / off control signal IN becomes "H" level during a negative voltage period, as shown in Figure 2. On the other hand, the dynamic clamp circuit 40D is a circuit designed to cause the semiconductor device 305 to perform a dynamic clamp operation that is different from avalanche clamp operation.

[0089] The dynamic clamp circuit 40D comprises a clamp element 64 and a detection transistor 65. As in Figure 1, the detection transistor 65 is inserted in the path between the power supply terminal 1, i.e., the power supply node N6, and the power output terminal 2, i.e., the power output node N7. The detection transistor 65 is configured to turn on when a back electromotive force is generated at the power output terminal 2, by changing its source voltage in conjunction with the back electromotive force. Specifically, the detection transistor 65 is an nMOS transistor to which the ground power supply voltage SGND is applied to the gate.

[0090] However, unlike in Figure 1, the source of the detection transistor 65 is connected to the gate node N4 of the power transistor (PT) 7. The back gate of the detection transistor 65 is connected to the power output terminal 2, i.e., the power output node N7, as in Figure 1. Meanwhile, the clamp element (third clamp element) 64 is inserted in the path between the power supply node N6 and the drain of the detection transistor 65. The clamp element 64, specifically the Zener diode, is provided to limit the back electromotive force generated at the power output terminal 2 to a predetermined clamp voltage.

[0091] In dynamic clamp operation, the back electromotive force is clamped not by the body diode of the power transistor (PT) 7, but by the clamp voltage of the clamping element 64 and the gate-source voltage VGSo of the power transistor (PT) 7 in a weakly ON state. The flyback energy associated with the back electromotive force is dissipated by the on-resistance of the power transistor (PT) 7 in a weakly ON state.

[0092] Here, the gate-source voltage VGSo of the power transistor (PT) 7 is determined by the gate resistor element 12 and the control switch (second control switch) 13. That is, when the control switch 13 is controlled to turn ON in response to the transition of the ON / OFF control signal IN to the OFF level, it connects the gate node N4 of the power transistor (PT) 7 to the power output node N7 via the gate resistor element 12. In this state, when current flows through the gate resistor element 12, a voltage drop occurs. The gate-source voltage VGSo is determined by this voltage drop.

[0093] As a specific example, let's assume that the power supply voltage VCC is 12V and the clamp voltage of the clamp element 64, i.e., the Zener voltage Vz64, is 33.5V. First, when the power transistor (PT) 7 is turned off, a back electromotive force, i.e., a negative voltage, is generated at the power output terminal 2. At this time, the gate voltage of the power transistor (PT) 7 decreases in conjunction with the decrease in output voltage VOUT due to the gate resistor element 12 and the ON control switch 13.

[0094] Here, when the gate voltage of the power transistor (PT) 7 drops by a Zener voltage Vz64 of 33.5V relative to the 12V power supply voltage VCC, the gate voltage is clamped to -21.5V by the clamp element 64 and the ON-state detection transistor 65. At this time, a voltage drop of about 1.5V occurs across the gate resistor element 12 due to the current flowing through the detection transistor 65. As a result, the output voltage VOUT is clamped to -23V. The power transistor (PT) 7 enters a weak ON state because, for example, a gate-source voltage VGSo of about 1.5V is applied to a threshold voltage of about 1.0V.

[0095] In the configuration and operation described above, a high voltage may be applied between the gate and back gate of the detection transistor 65, as in the first embodiment. Accordingly, a high voltage may also be applied between the gate and source of the detection transistor 65. For example, the gate-back gate voltage VGBd may be 23V. The gate-source voltage VGSd may be 21.5V. As a result, as in the first embodiment, a process to form a thick gate oxide film is required in the manufacturing process, which may increase manufacturing costs.

[0096] Therefore, a dynamic clamp circuit 40A, shown in Figure 9, is provided. This dynamic clamp circuit 40A includes a clamp element 64 and a detection transistor 65, similar to those in Figure 16, as well as a clamp element 16 and a gate connection circuit 42, similar to those in Figure 1. Briefly, the clamp element 16 limits the gate voltage of the detection transistor 65 to a predetermined clamp voltage, such as 6V, based on the output voltage VOUT of the power output terminal 2. As a result, the gate-back gate voltage VGBd of the detection transistor 65 is clamped, and consequently, the gate-source voltage VGSd is also clamped.

[0097] The gate connection circuit 42 comprises resistive elements 17 and 18 and an nMOS transistor 19 which is a rectifier element. The nMOS transistor 19 applies the ground power supply voltage SGND to the gate of the detection transistor 65, blocking the current flowing from the gate of the detection transistor 65 toward the ground power supply voltage SGND. This blocks the current path from the power output terminal 2 to the ground power supply terminal 3 via the clamp element 16 when the power transistor (PT) 7 is ON.

[0098] The resistor 18 connects the power output terminal 2 to the gate of the detection transistor 65. This keeps the detection transistor 65 in the off state during periods when no back electromotive force is generated. The resistor 17 is connected in series with the nMOS transistor 19. The resistor 17 limits the current flowing from the ground power supply terminal 3 to the clamp element 16 via node N8 of the gate of the detection transistor 65 during periods when a back electromotive force is generated. This suppresses the rise in the clamp voltage at the clamp element 16, and consequently, the rise in the gate-back gate voltage VGBd and gate-source voltage VGSd of the detection transistor 65.

[0099] By providing such a dynamic clamp circuit 40A, particularly the clamp element 16, the process of forming a thick gate oxide film in the manufacturing process becomes unnecessary, as in the first embodiment. That is, the semiconductor device 205 can be realized with the device structure shown in Figure 5. As a result, manufacturing costs can be reduced. Furthermore, the semiconductor device 205 can be applied to an electronic control system (ECU) 401, for example, as shown in Figure 6, as in the first embodiment. In this case, the power transistor (PT) 7 can be appropriately protected by performing a dynamic clamp operation against the back electromotive force from the ramp load 8a-8c. As a result, the reliability of the electronic control system (ECU) 401 can be improved.

[0100] <Semiconductor device operation> Figure 10 is a timing chart showing an example of the operation of the semiconductor device 205 in Figure 9. Similar to Figure 2, Figure 10 shows the operation during the period T1-T4. For comparison, Figure 10 also shows the gate-source voltage VGSd and gate-back gate voltage VGBd when using the configuration example shown in Figure 16. Here, we will mainly focus on the differences from the case in Figure 2.

[0101] During period T2, the output voltage VOUT becomes approximately equal to the power supply voltage VCC in response to the turn-on of the power transistor (PT) 7. At this time, the gate voltage of the detection transistor 65 becomes equal to the output voltage VOUT via the resistor element 18. The back gate voltage of the detection transistor 65 is equal to the output voltage VOUT. A boosted voltage Vcp is applied to the source of the detection transistor 65. As a result, the detection transistor 65 is turned off. In addition, any current that may occur from the power output terminal 2 to the ground power supply terminal 3 during period T2 is blocked by the nMOS transistor 19, which functions as a diode.

[0102] During period T2, more specifically, the gate-back gate voltage VGBd of the detection transistor 65 becomes 0V. The gate-source voltage VGSd of the detection transistor 65 becomes an off-voltage based on the difference voltage between the boosted voltage Vcp and the output voltage VOUT. The magnitude of this off-voltage is limited by the clamp voltage of the clamp element 11. On the other hand, when using the configuration example shown in Figure 16, the magnitude of the gate-back gate voltage VGBd is equal to the magnitude of the output voltage VOUT, i.e., approximately the magnitude of the power supply voltage VCC. Also, the gate-source voltage VGSd becomes an off-voltage with the magnitude of the boosted voltage Vcp.

[0103] During period T3, a back electromotive force is generated in response to the turn-off of the power transistor (PT) 7, causing the output voltage VOUT to become a negative voltage. Here, the dynamic clamp circuit 40A shown in Figure 9 and the protection circuit 41A shown in Figure 1 have different functions, as described above. Therefore, Figure 10 shows an example of operation in which, unlike in Figure 2, no transition to the on-level of the on / off control signal IN occurs during period T3.

[0104] When the output voltage VOUT becomes a negative voltage, dynamic clamping operation is performed using the dynamic clamp circuit 40A. As a result, the ground power supply voltage SGND is applied to the gate of the detection transistor 65 via the nMOS transistor 19 and the resistor element 17. The source voltage of the detection transistor 65 also changes in conjunction with the output voltage VOUT, which becomes a negative voltage. Consequently, the detection transistor 65 turns ON. The clamp element 64 also becomes conductive when the negative voltage reaches a predetermined voltage.

[0105] The clamp voltage Vclp relative to the output voltage VOUT is determined by the sum of the Zener voltage Vz64 of the clamp element 64 and the gate-source voltage VGSo of the power transistor (PT) 7. As a result, the output voltage VOUT is clamped so that it does not fall below a predetermined negative voltage Vn. The gate-source voltage VGSo of the power transistor (PT) 7 is the on-voltage with a weak on-state magnitude. In addition, the gate voltage of the gate node N4 of the power transistor (PT) 7 is higher than the negative voltage Vn generated at the power output node N7 by the amount of the gate-source voltage VGSo of the power transistor (PT) 7.

[0106] The gate-back gate voltage VGBd of the detection transistor 65 is limited by the Zener voltage Vz16 of the clamp element 16. The gate-source voltage VGSd of the detection transistor 65 is the on-voltage based on the difference voltage between the Zener voltage Vz16 and the gate-source voltage VGSo of the power transistor (PT) 7. On the other hand, when using the configuration example shown in Figure 16, the magnitude of the gate-back gate voltage VGBd is the magnitude of the negative voltage Vn. Also, the gate-source voltage VGSd is the on-voltage based on the difference voltage between the negative voltage Vn and the gate-source voltage VGSo of the power transistor (PT) 7.

[0107] During period T3, current flows from the ground power supply terminal 3 to the power output terminal 2 via the clamp element 16. The resistive element 17 limits the current flowing through the clamp element 16 at this time. In dynamic clamp operation, the flyback energy associated with the back electromotive force is released by the on-resistance of the power transistor (PT). Once the flyback energy is completely released, the output voltage VOUT becomes the ground power supply voltage PGND.

[0108] During period T4, a load dump occurs at power node N6. The detection transistor 65 is configured to remain in the off state in response to the load dump, as in Figure 2. As a result, dynamic clamping is not performed in response to the load dump.

[0109] <Circuit configuration of a semiconductor device (modified example)> Figure 11 is a circuit diagram showing a modified configuration of the semiconductor device 206 according to the third embodiment, which is a modified version of the configuration shown in Figure 9. The semiconductor device 206 shown in Figure 11 includes a gate connection circuit 43 that is different from the one in Figure 9. As described in the second embodiment, the nMOS transistor 19 in the gate connection circuit 42 shown in Figure 9 has, more specifically, a parasitic bipolar transistor 50. In this case, during period T3, the parasitic bipolar transistor 50 turns on, which may cause the drain voltage of the nMOS transistor 19 to rise and the current flowing through the clamp element 16 to increase.

[0110] Therefore, to prevent such malfunctions, in the gate connection circuit 43 shown in Figure 11, a resistor 21 and a clamp element 20 are connected to the nMOS transistor 19, similar to the case in Figure 8. The ground power supply voltage SGND is applied to the source of the nMOS transistor 19 via the resistor 21. The clamp element 20 limits the gate-source voltage of the nMOS transistor 19 to a predetermined clamp voltage.

[0111] <Main effects of the third embodiment> As described above, by using the semiconductor devices 205 and 206 according to the third embodiment, the same effects as those described in the first and second embodiments can be obtained. Specifically, dynamic clamping operation can be realized, and the detection transistor 65 can be formed using a thin gate oxide film 506. As a result, manufacturing costs can be reduced. In addition, malfunctions associated with the turning on of the parasitic bipolar transistor 50 can be prevented.

[0112] (Fourth embodiment) <Configuration of semiconductor device> Figure 12 is a circuit diagram showing an example of the main configuration of a semiconductor device 207 according to the fourth embodiment. The semiconductor device 207 shown in Figure 12 includes a dynamic clamp circuit 40C that is different from the one in Figure 9. In addition to the clamp elements 16, 64 and gate connection circuit 42 which perform the same roles as in Figure 9, the dynamic clamp circuit 40C includes two detection transistors 65A, 65B, a resistor element 22, an nMOS transistor 23 for clamping, a clamp element 24, and a resistor element 25.

[0113] Two detection transistors 65A and 65B have their gates connected in common, and their back gates are both connected to the power output terminal 2. A clamp element (first clamp element) 16 limits the gate voltages of detection transistors 65A and 65B to a predetermined clamp voltage, with reference to the output voltage VOUT of the power output terminal 2. The source of the detection transistor (first detection transistor) 65B is connected to the power output terminal 2, and its drain is connected to the power supply terminal 1 via a clamp element (third clamp element) 64. However, in this example, a resistor 22 is connected between the drain of detection transistor 65B and the clamp element 64.

[0114] The detection transistor (second detection transistor) 65A has its source connected to the gate node N4 of the power transistor (PT) 7, and its drain connected to the power supply terminal 1 via the clamping nMOS transistor 23. The clamping element (fourth clamping element) 24, specifically a Zener diode, and the resistive element (fourth resistive element) 25 are connected in parallel between the gate and source of the clamping nMOS transistor 23. The gate of the clamping nMOS transistor 23 is also connected to the power supply terminal 1 via the clamping element 64. The back gate of the clamping nMOS transistor 23 is connected to the power output terminal 2.

[0115] Here, both detection transistors 65A and 65B are responsible for detecting negative voltages generated at the power output terminal 2, and turn ON when a negative voltage is detected. When the negative voltage reaches a predetermined value, the clamp element 64 becomes conductive via the ON detection transistor 65B. As a result, a voltage is applied to the gate of the clamping nMOS transistor 23 that is lowered from the power supply voltage VCC by the Zener voltage Vz64 of the clamping element 64. The clamping nMOS transistor 23 receives this gate voltage and clamps the source voltage of node N12 with its own gate-source voltage VGSm.

[0116] As a result, the gate voltage of the power transistor (PT) 7 is also clamped from node N12 via the ON-state detection transistor 65A. The clamp voltage in this case is determined by the sum of the Zener voltage Vz64 of the clamping element 64 and the gate-source voltage VGSm of the clamping nMOS transistor 23. In addition, the output voltage VOUT of the power output terminal 2 is also clamped by dynamic clamping. The clamp voltage in this case is determined by the sum of the Zener voltage Vz64, the gate-source voltage VGSm, and the gate-source voltage VGSo of the power transistor (PT) 7.

[0117] The clamp element 24 limits the gate-source voltage VGSm of the clamping nMOS transistor 23 to a clamp voltage such as 6V. The resistor element 25 keeps the nMOS transistor 23 in the off state during the non-conductive period of the clamp element 64. The resistor element 22 is provided to limit the current flowing through the clamp element 64, that is, to suppress variations in the clamp voltage. However, the resistor element 22 may be omitted. Also, the resistor element 22 may be a depletion-type MOS transistor with its gate-source short-circuited, for example, to reduce the circuit area.

[0118] <Semiconductor device operation> Figure 13 is a timing chart showing an example of the operation of the semiconductor device 207 in Figure 12. In Figure 12, as in Figure 10, the operation during period T1-T4 is shown. Here, we will mainly focus on the differences from the case in Figure 10.

[0119] During period T1, depending on the off state of the power transistor (PT) 7, the output voltage VOUT is the ground power supply voltage PGND, i.e., 0V. In this state, the gate-source voltage VGSd2 of the detection transistor 65B is 0V due to the resistor 18. The gate-source voltage VGSd1 of the detection transistor 65A is 0V due to the resistor 18 and the ON state of the control switch 13. Also, the gate-source voltage VGSm of the clamping nMOS transistor 23 is 0V due to the resistor 25.

[0120] During period T2, the output voltage VOUT becomes approximately the same level as the power supply voltage VCC as the power transistor (PT) 7 turns on. At this time, the gate-source voltage VGSd2 of the detection transistor 65B becomes 0V due to the resistor 18. Meanwhile, a boosted voltage Vcp is applied to the source of the detection transistor 65A. As a result, the gate-source voltage VGSd1 of the detection transistor 65A becomes the off voltage based on the difference voltage between the boosted voltage Vcp and the output voltage VOUT, i.e., approximately the power supply voltage VCC. Also, the gate-source voltage VGSm of the clamping nMOS transistor 23 is 0V due to the resistor 25.

[0121] During period T3, a back electromotive force is generated in response to the turn-off of the power transistor (PT) 7, causing the output voltage VOUT to become a negative voltage. This triggers dynamic clamp operation using the dynamic clamp circuit 40C. The ground power supply voltage SGND is applied to the gates of the detection transistors 65A and 65B via the nMOS transistor 19 and the resistor element 17. The source voltage of the detection transistor 65A also changes in conjunction with the negative output voltage VOUT. As a result, both detection transistors 65A and 65B are turned on. The clamp element 64 also becomes conductive when the negative voltage reaches a predetermined voltage.

[0122] The clamp voltage Vclp relative to the output voltage VOUT is determined by the sum of the Zener voltage Vz64 of the clamping element 64, the gate-source voltage VGSm of the clamping nMOS transistor 23, and the gate-source voltage VGSo of the power transistor (PT) 7. As a result, the output voltage VOUT is clamped so that it does not fall below a predetermined negative voltage Vn.

[0123] The gate-source voltage VGSd2 of the detection transistor 65B is the on-voltage limited by the Zener voltage Vz16 of the clamping element 16. The gate-back gate voltages of detection transistors 65A and 65B are also limited by the Zener voltage Vz16. On the other hand, the gate-source voltage VGSd1 of the detection transistor 65A is the on-voltage based on the difference voltage between the Zener voltage Vz16 and the gate-source voltage VGSo of the power transistor (PT) 7. Furthermore, the gate-source voltage VGSm of the clamping nMOS transistor 23 is the on-voltage limited by the Zener voltage Vz24 of the clamping element 24.

[0124] <About semiconductor devices (variant examples)> The dynamic clamp circuit 40C shown in Figure 12 includes a gate connection circuit 42. However, instead of the gate connection circuit 42, a gate connection circuit 43 as shown in Figure 11 may be provided. This prevents malfunctions in the nMOS transistor 19 that occur when the parasitic bipolar transistor 50 is turned on.

[0125] <Main effects of the fourth embodiment> As described above, the same effects as those described in the third embodiment can be obtained by using the semiconductor device 207 according to the fourth embodiment. Furthermore, dynamic clamp operation can be realized by using the same detection transistor as in the first embodiment, i.e., the detection transistor 65B whose gate and source are connected to the power output terminal 2. However, from the viewpoint of circuit area, the third embodiment is preferable.

[0126] (Other embodiments) In the first to fourth embodiments described above, a semiconductor device that supplies a power supply voltage VCC to a load 8 supplied with a ground power supply voltage PGND at one end, i.e., a high-side semiconductor device, was described as an example. However, the methods of the first to fourth embodiments are also applicable to a semiconductor device that supplies a ground power supply voltage PGND to a load 8 supplied with a power supply voltage VCC at one end, i.e., a low-side semiconductor device.

[0127] In this case, the back electromotive force generated at the power output terminal 2 will be a positive voltage, not a negative voltage. Accordingly, for example, in Figure 1, the detection transistor 15 may be composed of a pMOS transistor. Also, the nMOS transistor 19 in the gate connection circuit 42 may be replaced with a pMOS transistor to which the power supply voltage VCC is applied to both the gate and source.

[0128] The present invention has been described in detail above based on embodiments, but the present invention is not limited to the embodiments described above and can be modified in various ways without departing from its essence. For example, the embodiments described above are described in detail in order to explain the present invention in an easy-to-understand manner and are not necessarily limited to those having all the described configurations. Furthermore, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add a configuration from another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace a part of the configuration of each embodiment with a configuration from another embodiment. [Explanation of Symbols]

[0129] 1,1A power terminal 2,2A power output terminal 7. Power Transistors (Output Transistors) 8 loads 12 Gate Resistors 13,34 Control switches 14 Zener diode 15, 65, 65A, 65B detection transistors 16, 24, 35, 64 clamp elements 17, 18, 21, 25 Resistor elements 19,33 nMOS transistors 30 Body Diodes 31,32 pMOS transistors 40A, 40B, 40C Dynamic Clamp Circuit 41A,41B protection circuit 42,43 Gate connection circuit 105,106,205,206,207 Semiconductor equipment 401 Electronic Control Unit (ECU) 402 ECU Control Unit IN On / Off Control Signal SGND, PGND Ground Power Supply Voltage VCC power supply voltage

Claims

1. An output transistor is connected between a first power supply terminal to which a first power supply voltage is supplied and a power output terminal, and when controlled to be ON, it supplies power to a load to which a second power supply voltage is supplied at one end via the power output terminal. A detection transistor is inserted in the path between the first power supply terminal and the power output terminal, and is configured to turn on when a back electromotive force is generated at the power output terminal, by changing the source voltage in conjunction with the back electromotive force; A first clamping element that limits the gate voltage of the detection transistor to a predetermined clamping voltage based on the voltage of the power output terminal, A gate connection circuit connected to the gate of the detection transistor, Equipped with, The aforementioned gate connection circuit is A first resistor element that connects the power output terminal to the gate of the detection transistor, A rectifier element that applies the second power supply voltage to the gate of the detection transistor and interrupts the current flowing from the gate of the detection transistor toward the second power supply voltage, Having, Semiconductor equipment.

2. In the semiconductor device described in claim 1, Furthermore, it has a second resistive element connected in series with the rectifier element, which limits the current flowing from the second power supply voltage to the first clamp element via the gate of the detection transistor. Semiconductor equipment.

3. In the semiconductor device described in claim 1, The rectifier element is composed of a transistor with its gate and source short-circuited. Semiconductor equipment.

4. In the semiconductor device described in claim 1, The rectifier element comprises a transistor and a third resistive element. The transistor has the second power supply voltage applied to its gate and the second power supply voltage applied to its source via the third resistor. Semiconductor equipment.

5. In the semiconductor device described in claim 1, Furthermore, the system includes a first control switch that controls the output transistor to turn off during the period when the detection transistor is ON. The detection transistor has a source connected to the power output terminal. Semiconductor equipment.

6. In the semiconductor device described in claim 5, Furthermore, the system includes a Zener diode inserted in the path between the first power supply terminal and the drain of the detection transistor, The Zener voltage of the Zener diode is lower than the clamping voltage of the body diode of the output transistor. Semiconductor equipment.

7. In the semiconductor device according to claim 5, further, A current mirror circuit that transfers the current flowing through the detection transistor, A voltage conversion element that converts the current flowing to the destination of the current mirror circuit into a voltage, Equipped with, The first control switch is controlled to be on or off by the voltage converted by the voltage conversion element, and when controlled to be on, it short-circuits the gate-source of the output transistor. Semiconductor equipment.

8. In the semiconductor device according to claim 7, Furthermore, it is equipped with a second clamping element, The first control switch is composed of a MOS transistor whose source and gate are connected to the power output terminal and the voltage conversion element, respectively. The second clamping element limits the gate-source voltage of the MOS transistor to a predetermined clamping voltage. Semiconductor equipment.

9. In the semiconductor device according to claim 1, further, A third clamping element is inserted in the path between the first power supply terminal and the drain of the detection transistor to limit the back electromotive force to a predetermined clamping voltage, Gate resistor element, A second control switch, when controlled to be ON, connects the gate of the output transistor to the power output terminal via the gate resistor element, Equipped with, The detection transistor has its source connected to the gate of the output transistor. Semiconductor equipment.

10. In the semiconductor device described in claim 9, The back gate of the detection transistor is connected to the power output terminal. Semiconductor equipment.

11. In the semiconductor device described in claim 9, further, A transistor for clamping, A fourth clamping element and a fourth resistive element are connected in parallel between the gate and source of the clamping transistor, Equipped with, The detection transistor comprises a first detection transistor and a second detection transistor whose gates are connected in common. The first detection transistor has its source connected to the power output terminal and its drain connected to the first power supply terminal via the third clamping element. The second detection transistor has its source connected to the gate of the output transistor and its drain connected to the first power supply terminal via the clamping transistor. The gate of the clamping transistor is connected to the first power supply terminal via the third clamping element. Semiconductor equipment.

12. A first power supply terminal to which a first power supply voltage is supplied, The power output terminal to which the load is connected, A semiconductor device that supplies power to the aforementioned load, A control device for controlling the aforementioned semiconductor device, An electronic control system having, A second power supply voltage is supplied to one end of the aforementioned load. The aforementioned semiconductor device is An output transistor is connected between the first power supply terminal and the power output terminal, and when controlled to be ON, it supplies power to the load via the power output terminal. A detection transistor is inserted in the path between the first power supply terminal and the power output terminal, and is configured to turn on when a back electromotive force is generated at the power output terminal, by changing the source voltage in conjunction with the back electromotive force; A first clamping element that limits the gate voltage of the detection transistor to a predetermined clamping voltage based on the voltage of the power output terminal, A gate connection circuit connected to the gate of the detection transistor, Equipped with, The aforementioned gate connection circuit is A first resistor element that connects the power output terminal to the gate of the detection transistor, A rectifier element that applies the second power supply voltage to the gate of the detection transistor and interrupts the current flowing from the gate of the detection transistor toward the second power supply voltage, It has, The control device outputs an on / off control signal to the semiconductor device for instructing the output transistor to be turned on or off. Electronic control system.

13. In the electronic control system according to claim 12, The semiconductor device further includes a second resistive element connected in series with the rectifier element, which limits the current flowing from the second power supply voltage to the first clamp element via the gate of the detection transistor. Electronic control system.

14. In the electronic control system according to claim 12, The rectifier element is composed of a transistor with its gate and source short-circuited. Electronic control system.

15. In the electronic control system according to claim 12, The rectifier element comprises a transistor and a third resistive element. The transistor has the second power supply voltage applied to its gate and the second power supply voltage applied to its source via the third resistor. Electronic control system.

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