Nitride semiconductor devices

Abstract

This achieves both a reduction in parasitic capacity and an improvement in pressure resistance. [Solution] The nitride semiconductor device 1 comprises a substrate 10, a semiconductor laminate 20 provided above the substrate 10 and including a channel, a source electrode 34 and a drain electrode 36 provided in contact with the semiconductor laminate 20, a p-type gate layer 30 provided between the source electrode 34 and the drain electrode 36, and a gate electrode 32 provided above the p-type gate layer 30. The semiconductor laminate 20 includes an electron transport layer 22 and an electron supply layer 24 provided above the electron transport layer 22. The electron supply layer 24 includes a thin film portion 24A located between the gate electrode 32 and the source electrode 34 in a plan view, and a thick film portion 24B located between the gate electrode 32 and the drain electrode 36 in a plan view and being thicker than the thin film portion 24A. The p-type gate layer 30 spans the thin film portion 24A and the thick film portion 24B. The end of the p-type gate layer 30 on the source electrode 34 side is located on the thin film portion 24A.

Description

Technical Field

[0001] The present disclosure relates to nitride semiconductor devices.

Background Art

[0002] Patent Document 1 discloses a nitride semiconductor device including a two-dimensional electron gas (2DEG) as a channel. In the nitride semiconductor device disclosed in Patent Document 1, a p-type nitride semiconductor layer is provided so as to cover a side surface on the source electrode side of a gate recess portion, and a gate electrode is further provided on an upper surface of the p-type nitride semiconductor layer. It is described that the parasitic capacitance generated between the gate electrode and the 2DEG can be reduced thereby.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above conventional nitride semiconductor device, when a high drain voltage is applied at the off state, an electric field tends to concentrate at an end portion on the drain electrode side of the gate recess portion. For this reason, there is a problem that the leakage current increases and the breakdown voltage between the gate and the drain decreases.

[0005] Therefore, the present disclosure provides a nitride semiconductor device capable of achieving both reduction of parasitic capacitance and improvement of breakdown voltage.

Means for Solving the Problems

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a substrate, a semiconductor laminate provided above the substrate and including a channel, a source electrode and a drain electrode provided in contact with the semiconductor laminate, a threshold adjustment layer provided between the source electrode and the drain electrode, and a gate electrode provided above the threshold adjustment layer. The semiconductor laminate includes a first nitride semiconductor layer and a second nitride semiconductor layer provided above the first nitride semiconductor layer. The second nitride semiconductor layer includes a first thin film portion located between the gate electrode and the source electrode in a plan view of the substrate, and a first thick film portion located between the gate electrode and the drain electrode in the plan view of the substrate and thicker than the first thin film portion. The threshold adjustment layer extends across the first thin film portion and the first thick film portion in a plan view of the substrate, and an end portion of the threshold adjustment layer on the source electrode side is located on the first thin film portion.

[0007] A nitride semiconductor device according to another aspect of the present disclosure comprises a substrate, a semiconductor stack provided above the substrate and including a channel, a first electrode and a second electrode provided in contact with the semiconductor stack, a first threshold adjustment layer provided between the first electrode and the second electrode, a second threshold adjustment layer provided between the first threshold adjustment layer and the second electrode, a first gate electrode provided above the first threshold adjustment layer, and a second gate electrode provided above the second threshold adjustment layer, wherein the semiconductor stack includes a first nitride semiconductor layer and a second nitride semiconductor layer provided above the first nitride semiconductor layer, the second nitride semiconductor layer being provided above the first gate electrode and the The first threshold adjustment layer includes a first thin film portion located between the first electrode and the substrate, a second thin film portion located between the second gate electrode and the second electrode in a plan view of the substrate, and a first thick film portion located between the first thin film portion and the second thin film portion in a plan view of the substrate, and being thicker than either the first thin film portion or the second thin film portion, wherein the first threshold adjustment layer spans the first thin film portion and the first thick film portion in a plan view of the substrate, the second threshold adjustment layer spans the second thin film portion and the first thick film portion in a plan view of the substrate, the first electrode-side end of the first threshold adjustment layer is located on the first thin film portion, and the second electrode-side end of the second threshold adjustment layer is located on the second thin film portion.

[0008] A nitride semiconductor device according to another aspect of the present disclosure comprises a substrate, an n-type third nitride semiconductor layer provided above the substrate, a p-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer, a semiconductor laminate including a channel provided to cover the inner surface of an opening that penetrates the fourth nitride semiconductor layer and reaches the third nitride semiconductor layer and the area above the fourth nitride semiconductor layer, a first electrode and a second electrode provided in contact with the semiconductor laminate, a threshold adjustment layer provided between the first electrode and the second electrode, a gate electrode provided above the threshold adjustment layer, and a drain electrode provided below the substrate, wherein the opening is provided between the first electrode and the second electrode in a plan view of the substrate, and both the first electrode and the second electrode are source electrodes electrically connected to each other, and the semiconductor The substrate laminate includes a first nitride semiconductor layer and a second nitride semiconductor layer provided above the first nitride semiconductor layer, wherein the second nitride semiconductor layer includes a first thin film portion located between the gate electrode and the first electrode in a plan view of the substrate, a second thin film portion located between the gate electrode and the second electrode in a plan view of the substrate, and a first thick film portion located between the first thin film portion and the second thin film portion in a plan view of the substrate and being thicker than either the first thin film portion or the second thin film portion, wherein the threshold adjustment layer spans the first thin film portion and the first thick film portion, and spans the second thin film portion and the first thick film portion in a plan view of the substrate, the end of the threshold adjustment layer on the first electrode side is located on the first thin film portion, and the end of the threshold adjustment layer on the second electrode side is located on the second thin film portion. [Effects of the Invention]

[0009] According to this disclosure, it is possible to achieve both a reduction in parasitic capacity and an improvement in pressure resistance. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a cross-sectional view of a nitride semiconductor device according to a modified example of Embodiment 1. [Figure 3] Figure 3 is a cross-sectional view of a nitride semiconductor device according to Embodiment 2. [Figure 4A] Figure 4A is a cross-sectional view of a nitride semiconductor device according to a comparative example. [Figure 4B] Figure 4B shows the capacitance characteristics of nitride semiconductor devices in comparative examples and examples. [Figure 5] Figure 5 is a cross-sectional view of a nitride semiconductor device according to a modified example 1 of Embodiment 2. [Figure 6] Figure 6 is a cross-sectional view of a nitride semiconductor device according to a modified example 2 of Embodiment 2. [Figure 7] Figure 7 is a cross-sectional view of a nitride semiconductor device according to a modified example 3 of Embodiment 2. [Figure 8] Figure 8 is a cross-sectional view of a nitride semiconductor device according to a modified example 4 of Embodiment 2. [Figure 9] Figure 9 is a cross-sectional view of a nitride semiconductor device according to a modified example 5 of Embodiment 2. [Figure 10A] Figure 10A is a plan view of a nitride semiconductor device according to Embodiment 2. [Figure 10B] Figure 10B is a cross-sectional view of the nitride semiconductor device in the XB-XB plane shown in Figure 10A. [Figure 11] Figure 11 is a cross-sectional view of a nitride semiconductor device according to Embodiment 3. [Figure 12] Figure 12 is a cross-sectional view of a nitride semiconductor device according to a modified example 1 of Embodiment 3. [Figure 13A] Figure 13A is a plan view of a nitride semiconductor device according to a modified example 1 of Embodiment 3. [Figure 13B] Figure 13B is a cross-sectional view of a nitride semiconductor device along the line XIIIB-XIIIB in Figure 13A. [Figure 13C] Figure 13C is a cross-sectional view of a nitride semiconductor device along the line XIIIC-XIIIC in Figure 13A. [Figure 14] Figure 14 is a cross-sectional view of a nitride semiconductor device according to a modified example 2 of Embodiment 3. [Figure 15] Figure 15 is a cross-sectional view of a nitride semiconductor device according to Embodiment 4. [Figure 16] Figure 16 is a cross-sectional view of a nitride semiconductor device according to a modified example 1 of Embodiment 4. [Figure 17] Figure 17 is a cross-sectional view of a nitride semiconductor device according to a modified example 2 of Embodiment 4. [Figure 18] Figure 18 is a cross-sectional view of a nitride semiconductor device according to Embodiment 5. [Figure 19] Figure 19 is a cross-sectional view of a nitride semiconductor device according to a modified example 1 of Embodiment 5. [Figure 20] Figure 20 is a cross-sectional view of a nitride semiconductor device according to a modified example 2 of Embodiment 5. [Modes for carrying out the invention]

[0011] (Summary of this disclosure) A nitride semiconductor device according to a first aspect of the present disclosure comprises a substrate, a semiconductor laminate provided above the substrate and including a channel, a source electrode and a drain electrode provided in contact with the semiconductor laminate, a threshold adjustment layer provided between the source electrode and the drain electrode, and a gate electrode provided above the threshold adjustment layer, wherein the semiconductor laminate includes a first nitride semiconductor layer and a second nitride semiconductor layer provided above the first nitride semiconductor layer, the second nitride semiconductor layer includes a first thin film portion located between the gate electrode and the source electrode in a plan view of the substrate, and a first thick film portion located between the gate electrode and the drain electrode in a plan view of the substrate and being thicker than the first thin film portion, the threshold adjustment layer straddles the first thin film portion and the first thick film portion in a plan view of the substrate, and the end of the threshold adjustment layer on the source electrode side is located on the first thin film portion.

[0012] When the nitride semiconductor device is turned off, the generation of 2DEG near the interface between the first thin film and the first nitride semiconductor layer is suppressed. Since the source electrode side end of the threshold adjustment layer is located on the first thin film, the area in which the threshold adjustment layer and 2DEG face each other is reduced. Therefore, the parasitic capacitance between the gate and source can be reduced. In addition, since the threshold adjustment layer spans both the first thin film and the thick film, the electric field caused by the high drain voltage when the device is turned off is distributed between the drain electrode side end of the threshold adjustment layer and the drain electrode side end of the first thin film in contact with the threshold adjustment layer. Since electric field concentration is suppressed, the leakage current is reduced and the breakdown voltage between the gate and drain can be increased. Thus, the nitride semiconductor device according to this embodiment can achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0013] A nitride semiconductor device according to a second aspect of the present disclosure is a nitride semiconductor device according to a first aspect, wherein the source electrode is provided on the first thin film portion and the drain electrode is provided on the first thick film portion.

[0014] This suppresses the generation of 2DEG on the source electrode side when the device is off, further reducing parasitic capacitance between the gate and source. Additionally, the distance between the source electrode and 2DEG can be reduced, thereby lowering the contact resistance to the channel.

[0015] A nitride semiconductor device according to a third aspect of the present disclosure is a nitride semiconductor device according to a first aspect, wherein the second nitride semiconductor layer further includes a second thick film portion located between the first thin film portion and the source electrode in a plan view of the substrate.

[0016] This allows for an increase in the concentration of 2DEG generated near the interface between the second thick film and the first nitride semiconductor layer, thereby reducing on-resistance.

[0017] A nitride semiconductor device according to a fourth aspect of the present disclosure is a nitride semiconductor device according to a third aspect, wherein the source electrode is provided on the second thick film portion and the drain electrode is provided on the first thick film portion.

[0018] This increases the concentration of 2DEG generated directly below both the source and drain electrodes, thereby reducing the on-resistance.

[0019] A nitride semiconductor device according to a fifth aspect of the present disclosure is a nitride semiconductor device according to a first aspect, wherein the second nitride semiconductor layer further includes a second thin film portion that is located between the first thick film portion and the drain electrode in a plan view of the substrate and is thinner than the first thick film portion, the source electrode is provided on the first thin film portion and the drain electrode is provided on the second thin film portion.

[0020] This allows the distance between each of the source and drain electrodes and 2DEG to be reduced, thereby reducing the contact resistance to the channel.

[0021] A nitride semiconductor device according to a sixth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to fifth aspects, wherein the second nitride semiconductor layer further includes a first inclined portion located between the first thin film portion and the first thick film portion in a plan view of the substrate, and having an inclined upper surface.

[0022] This makes it easier for the electric field caused by the high drain voltage when the device is off to disperse along the upper surface of the first inclined section, thereby further increasing the breakdown voltage.

[0023] A nitride semiconductor device according to a seventh aspect of the present disclosure is a nitride semiconductor device according to a third or fourth aspect, wherein the second nitride semiconductor layer further includes a first inclined portion located between the first thin film portion and the first thick film portion in a plan view of the substrate and having an inclined upper surface, and a second inclined portion located between the first thin film portion and the second thick film portion in a plan view of the substrate and having an inclined upper surface, wherein the inclination of the upper surface of the first inclined portion is gentler than the inclination of the upper surface of the second inclined portion.

[0024] This makes it easier for the electric field caused by the high drain voltage when the device is off to disperse along the upper surface of the first inclined section, thereby further increasing the breakdown voltage. In addition, the steeper slope of the upper surface of the second inclined section allows for a shorter gate-source distance, enabling miniaturization of nitride semiconductor devices.

[0025] A nitride semiconductor device according to the eighth aspect of this disclosure is a nitride semiconductor device according to any one of the first to seventh aspects, wherein the threshold adjustment layer is a p-type nitride semiconductor layer.

[0026] This raises the potential at the conduction band edge of the channel directly beneath the p-type nitride semiconductor layer. This reduces the carrier concentration directly beneath the p-type nitride semiconductor layer, shifting the transistor threshold to the positive side. As a result, the nitride semiconductor device can be operated as a normally-off field-effect transistor (FET).

[0027] A nitride semiconductor device according to a ninth aspect of the present disclosure is a nitride semiconductor device according to any one of the first to eighth aspects, wherein the nitride semiconductor device is divisible into an active region and an inactive region in a plan view of the substrate, the source electrode and the drain electrode are provided in the active region, the nitride semiconductor device further comprises a drain pad provided in the inactive region and electrically connected to the drain electrode, the first thick film portion, the first thin film portion and the threshold adjustment layer are all further located between the source electrode and the drain pad in a plan view of the substrate, and the threshold adjustment layer spans the first thin film portion and the first thick film portion between the source electrode and the drain pad in a plan view of the substrate.

[0028] This allows for the dispersion of the electric field caused by the high drain voltage applied to the drain pad, thereby further increasing the breakdown voltage.

[0029] A nitride semiconductor device according to a tenth aspect of the present disclosure comprises a substrate, a semiconductor laminate provided above the substrate and including a channel, a first electrode and a second electrode provided in contact with the semiconductor laminate, a first threshold adjustment layer provided between the first electrode and the second electrode, a second threshold adjustment layer provided between the first threshold adjustment layer and the second electrode, a first gate electrode provided above the first threshold adjustment layer, and a second gate electrode provided above the second threshold adjustment layer, wherein the semiconductor laminate includes a first nitride semiconductor layer and a second nitride semiconductor layer provided above the first nitride semiconductor layer, the second nitride semiconductor layer being provided above the first gate electrode and the The first threshold adjustment layer includes a first thin film portion located between the first electrode and the substrate, a second thin film portion located between the second gate electrode and the second electrode in a plan view of the substrate, and a first thick film portion located between the first thin film portion and the second thin film portion in a plan view of the substrate, and being thicker than either the first thin film portion or the second thin film portion, wherein the first threshold adjustment layer spans the first thin film portion and the first thick film portion in a plan view of the substrate, the second threshold adjustment layer spans the second thin film portion and the first thick film portion in a plan view of the substrate, the first electrode-side end of the first threshold adjustment layer is located on the first thin film portion, and the second electrode-side end of the second threshold adjustment layer is located on the second thin film portion.

[0030] When the nitride semiconductor device is turned off, the generation of 2DEG near the interface between the first thin film and the first nitride semiconductor layer is suppressed. Since the first electrode-side end of the first threshold adjustment layer is located on the first thin film, the area in which the first threshold adjustment layer and 2DEG face each other is reduced. Therefore, the parasitic capacitance between the first gate electrode and the first electrode can be reduced. Similarly, the parasitic capacitance between the second gate electrode and the second electrode can also be reduced. Furthermore, since the first threshold adjustment layer spans both the first thin film and the first thick film, even if a high voltage is applied to the second electrode when the device is turned off, the electric field caused by this voltage is dispersed between the second electrode-side end of the first threshold adjustment layer and the second electrode-side end of the first thin film that the first threshold adjustment layer is in contact with. Similarly, since the second threshold adjustment layer spans both the second thin film portion and the first thick film portion, even if a high voltage is applied to the first electrode when the device is off, the electric field caused by this voltage is distributed between the first electrode side end of the second threshold adjustment layer and the first electrode side end of the second thin film portion to which the second threshold adjustment layer is in contact. In this way, electric field concentration is suppressed regardless of whether a high voltage is applied to the first or second electrode when the device is off, thus reducing leakage current and increasing breakdown voltage. Thus, the nitride semiconductor device according to this embodiment makes it possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0031] A nitride semiconductor device according to an eleventh aspect of the present disclosure is a nitride semiconductor device according to a tenth aspect, wherein the first electrode is provided on the first thin film portion, and the second electrode is provided on the second thin film portion.

[0032] As a result, when the device is off, the generation of 2DEG between the first electrode and the first threshold adjustment layer, and between the second electrode and the second threshold adjustment layer, is suppressed, thereby further reducing parasitic capacitance. In addition, the distance between each of the first and second electrodes and 2DEG can be reduced, thereby reducing the contact resistance to the channel.

[0033] A nitride semiconductor device according to a twelfth aspect of the present disclosure is a nitride semiconductor device according to a tenth aspect, wherein the second nitride semiconductor layer further includes a second thick film portion located between the first thin film portion and the first electrode in a plan view of the substrate, and a third thick film portion located between the second thin film portion and the second electrode in a plan view of the substrate.

[0034] This makes it possible to increase the concentration of 2DEG generated near the interface between each of the second and third thick film portions and the first nitride semiconductor layer, thereby reducing the on-resistance.

[0035] A nitride semiconductor device according to a thirteenth aspect of the present disclosure is a nitride semiconductor device according to a twelfth aspect, wherein the first electrode is provided on the second thick film portion, and the second electrode is provided on the third thick film portion.

[0036] This allows for an increase in the concentration of 2DEG generated directly below the first and second electrodes, thereby reducing the on-resistance.

[0037] A nitride semiconductor device according to a fourteenth aspect of the present disclosure is a nitride semiconductor device according to any one of the tenth to thirteenth aspects, wherein the second nitride semiconductor layer further includes a first inclined portion located between the first thin film portion and the first thick film portion in a plan view of the substrate and having an inclined upper surface, and a third inclined portion located between the second thin film portion and the first thick film portion in a plan view of the substrate and having an inclined upper surface.

[0038] This makes it easier for the electric field caused by the high voltage when the device is off to disperse along the upper surface of the first or second inclined section, thereby further increasing the withstand voltage.

[0039] A nitride semiconductor device according to a 15th aspect of the present disclosure is a nitride semiconductor device according to any one of the 10th to 14th aspects, further comprising: an n-type third nitride semiconductor layer provided above the substrate; a p-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer; and a drain electrode provided below the substrate, wherein the semiconductor laminate is provided to cover the inner surface of an opening that penetrates the fourth nitride semiconductor layer and reaches the third nitride semiconductor layer, and the area above the fourth nitride semiconductor layer, the opening being provided between a first electrode and a second electrode in a plan view of the substrate, the first electrode and the second electrode both being source electrodes electrically connected to each other, the first gate electrode and the first threshold adjustment layer being provided between the bottom surface of the opening and the first electrode in a plan view of the substrate, and the second gate electrode and the second threshold adjustment layer being provided between the bottom surface of the opening and the second electrode in a plan view of the substrate.

[0040] This makes it possible to realize nitride semiconductor devices as so-called vertical devices. It also enables higher voltage resistance and higher current capacity for nitride semiconductor devices.

[0041] A nitride semiconductor device according to a sixteenth aspect of the present disclosure is a nitride semiconductor device according to a fifteenth aspect, further comprising: a p-type fifth nitride semiconductor layer provided above the semiconductor laminate at a position overlapping with the bottom surface of the opening in a plan view of the substrate; and a third electrode provided above the fifth nitride semiconductor layer and set to the same potential as the source electrode.

[0042] This allows the electric field lines extending from the drain electrode to be terminated in the p-type fifth nitride semiconductor layer, thereby reducing the gate-drain parasitic capacitance. Therefore, according to this embodiment, the rise and fall times of voltage and current can be shortened, enabling the realization of a nitride semiconductor device capable of high-speed operation. Furthermore, since switching losses can be reduced, total losses are suppressed even during high-speed operation, resulting in a low-loss power device.

[0043] A nitride semiconductor device according to the 17th aspect of this disclosure is a nitride semiconductor device according to any one of the 10th to 16th aspects, wherein both the first threshold adjustment layer and the second threshold adjustment layer are p-type nitride semiconductor layers.

[0044] This reduces the carrier concentration directly beneath the p-type nitride semiconductor layer, shifting the transistor threshold to the positive side. As a result, the nitride semiconductor device can be operated as a normally-off FET.

[0045] A nitride semiconductor device according to the 18th aspect of the present disclosure is a nitride semiconductor device according to any one of the 10th to 17th aspects, wherein the nitride semiconductor device is divisible into an active region and an inactive region in a plan view of the substrate, the first electrode and the second electrode are provided in the active region, and the nitride semiconductor device further comprises a first pad provided in the inactive region and electrically connected to the first electrode, and a second pad provided in the inactive region and electrically connected to the second electrode, and a first thick film portion, a first thin film portion and a first threshold tone Each of the leveling layers is located further between the first electrode and the first pad in a plan view of the substrate, and the first threshold adjustment layer spans the first thin film portion and the first thick film portion between the first electrode and the first pad in a plan view of the substrate, and the first thick film portion, the second thin film portion and the second threshold adjustment layer are all located further between the second electrode and the second pad in a plan view of the substrate, and the second threshold adjustment layer spans the second thin film portion and the first thick film portion between the second electrode and the second pad in a plan view of the substrate.

[0046] This allows for the dispersion of the electric field caused by the high voltage applied to the first or second pad, thereby further increasing the withstand voltage.

[0047] A nitride semiconductor device according to a 19th aspect of the present disclosure comprises a substrate, an n-type third nitride semiconductor layer provided above the substrate, a p-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer, a semiconductor laminate including a channel provided to cover the inner surface of an opening that penetrates the fourth nitride semiconductor layer and reaches the third nitride semiconductor layer and the area above the fourth nitride semiconductor layer, a first electrode and a second electrode provided in contact with the semiconductor laminate, a threshold adjustment layer provided between the first electrode and the second electrode, a gate electrode provided above the threshold adjustment layer, and a drain electrode provided below the substrate, wherein the opening is provided between the first electrode and the second electrode in a plan view of the substrate, and both the first electrode and the second electrode are source electrodes electrically connected to each other, and the semiconductor The substrate laminate includes a first nitride semiconductor layer and a second nitride semiconductor layer provided above the first nitride semiconductor layer, wherein the second nitride semiconductor layer includes a first thin film portion located between the gate electrode and the first electrode in a plan view of the substrate, a second thin film portion located between the gate electrode and the second electrode in a plan view of the substrate, and a first thick film portion located between the first thin film portion and the second thin film portion in a plan view of the substrate and being thicker than either the first thin film portion or the second thin film portion, wherein the threshold adjustment layer spans the first thin film portion and the first thick film portion, and spans the second thin film portion and the first thick film portion in a plan view of the substrate, the end of the threshold adjustment layer on the first electrode side is located on the first thin film portion, and the end of the threshold adjustment layer on the second electrode side is located on the second thin film portion.

[0048] When the nitride semiconductor device is turned off, the generation of 2DEG near the interface between each of the first and second thin film portions and the first nitride semiconductor layer is suppressed. Since the end of the threshold adjustment layer on the first electrode side is located on the first thin film portion, and the end of the threshold adjustment layer on the second electrode side is located on the second thin film portion, the area in which the threshold adjustment layer and 2DEG face each other is reduced. Therefore, parasitic capacitance between the gate electrode and each of the first and second electrodes can be reduced. Furthermore, the nitride semiconductor device according to this embodiment is a so-called vertical device and has excellent breakdown voltage. Thus, the nitride semiconductor device according to this embodiment can achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0049] A nitride semiconductor device according to a 20th aspect of the present disclosure is a nitride semiconductor device according to a 19th aspect, wherein the first electrode is provided on the first thin film portion, and the second electrode is provided on the second thin film portion.

[0050] As a result, the generation of 2DEG between each of the first and second electrodes and the threshold adjustment layer is suppressed when the device is off, further reducing parasitic capacitance. In addition, the distance between each of the first and second electrodes and 2DEG can be reduced, thereby reducing the contact resistance to the channel.

[0051] A nitride semiconductor device according to a 21st aspect of the present disclosure is a nitride semiconductor device according to a 19th aspect, wherein the second nitride semiconductor layer further includes a second thick film portion located between the first thin film portion and the first electrode in a plan view of the substrate, and a third thick film portion located between the second thin film portion and the second electrode in a plan view of the substrate.

[0052] This makes it possible to increase the concentration of 2DEG generated near the interface between each of the second and third thick film portions and the first nitride semiconductor layer, thereby reducing the on-resistance.

[0053] A nitride semiconductor device according to a 22nd aspect of the present disclosure is a nitride semiconductor device according to a 21st aspect, wherein the first electrode is provided on the second thick film portion, and the second electrode is provided on the third thick film portion.

[0054] This allows for an increase in the concentration of 2DEG generated directly below the first and second electrodes, thereby reducing the on-resistance.

[0055] A nitride semiconductor device according to a 23rd aspect of the present disclosure is a nitride semiconductor device according to any one of the 19th to 22nd aspects, wherein the second nitride semiconductor layer further includes a first inclined portion located between the first thin film portion and the first thick film portion in a plan view of the substrate and having an inclined upper surface, and a third inclined portion located between the second thin film portion and the first thick film portion in a plan view of the substrate and having an inclined upper surface.

[0056] This makes it easier for the electric field caused by the high voltage when the device is off to disperse along the upper surface of the first or second inclined section, thereby further increasing the withstand voltage.

[0057] The embodiments will be described in detail below with reference to the drawings.

[0058] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, manufacturing processes, and the sequence of manufacturing processes shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0059] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0060] Furthermore, in this specification, terms indicating relationships between elements such as parallel and orthogonal, terms indicating the shape of elements such as rectangles, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0061] Furthermore, in this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layer and is also referred to as the "vertical direction." In addition, the direction parallel to the main surface of the substrate may be referred to as the "horizontal direction." A "vertical" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the vertical direction, that is, a device in which the main current passes through the substrate in the vertical direction. A "horizontal" semiconductor device means a device in which the main path of current, such as drain current or forward current, is in the horizontal direction, that is, a device in which the main current does not pass through the substrate.

[0062] Furthermore, the side of the substrate on which the heterostructure is provided is considered the "upper" or "upper side," and the opposite side is considered the "lower" or "lower side." In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact with each other and are touching.

[0063] Furthermore, in this specification, unless otherwise specified, "plan view" refers to a view of the semiconductor device substrate from a direction perpendicular to the main surface, that is, a view of the main surface of the substrate from the front.

[0064] In this specification, "A and B overlap in a plan view" means that at least a part of A and at least a part of B overlap. That is, it includes cases where only a part of A and only a part of B overlap, cases where all of A overlaps with B, cases where all of B overlaps with A, and cases where A and B completely overlap with each other.

[0065] In addition, n-type and p-type indicate the conductivity type of a semiconductor and are conductivity types with opposite polarities to each other. n y -type represents a state in which an n-type dopant is added to a semiconductor at a high concentration, so-called heavy doping. Also, n - -type represents a state in which an n-type dopant is added to a semiconductor at a low concentration, so-called light doping. n + -type and n - -type are both examples of n-type, and may be described as n-type without distinguishing them from each other. Also, for p-type, p + -type and p - -type, the same applies.

[0066] In this specification, the "main component" means the component with the highest content rate among all the components constituting a member. For example, a component with a content rate of 50% or more is the main component. A component is a material, an element, a compound, etc. Also, "member A is made of component B" or "member A is composed of component B" means that member A substantially contains only component B. However, member A may contain impurities that are inevitably mixed in during manufacturing in addition to component B.

[0067] In this specification, AlGaN represents ternary mixed crystal Al x Ga 1-x N (0 < x < 1). Hereinafter, a multi-component mixed crystal is abbreviated with the arrangement of the respective constituent element symbols, for example, AlInN, GaInN, etc. For example, Al x Ga 1-x-y In[[ID=N(0 < x < 1, 0 < y < 1, and 0 < x + y < 1) is abbreviated as AlGaInN. x, 1 - x - y, and y represent the composition ratios of Al, Ga, and In, respectively.

[0068] Also, in this specification, ordinal numbers such as "first" and "second" do not mean the number or order of components, unless otherwise specified, and are used for the purpose of avoiding confusion and distinguishing between components of the same kind.

[0069] (Embodiment 1) First, the configuration of the nitride semiconductor device according to Embodiment 1 will be described using FIG. 1.

[0070] FIG. 1 is a cross-sectional view of the nitride semiconductor device 1 according to this embodiment. In FIG. 1, each component such as the semiconductor layer, insulating layer, and electrode included in the nitride semiconductor device 1 is shaded to represent a cross-section. Note that for the electron traveling layer 22, the shading representing the cross-section is omitted. The same applies to other cross-sectional views after FIG. 2.

[0071] The nitride semiconductor device 1 shown in FIG. 1 is a normally-off type lateral FET. That is, the threshold value of the nitride semiconductor device 1 is greater than 0V. In the nitride semiconductor device 1, for example, the source electrode 34 is grounded, and a positive potential is applied to the drain electrode 36. When a potential less than the threshold value, such as 0V or a negative potential, is applied to the gate electrode 32, the nitride semiconductor device 1 is in a non-conductive state, that is, off, and no current flows between the source electrode 34 and the drain electrode 36. When a positive potential exceeding the threshold voltage is applied to the gate electrode 32, the nitride semiconductor device 1 is in a conductive state, that is, on, and current flows from the drain electrode 36 toward the source electrode 34. The current flowing from the drain electrode 36 toward the source electrode 34 when on is also called the drain current. The drain current flows in a direction parallel to the main surface of the substrate 10, that is, in the lateral direction.

[0072] <0000The nitride semiconductor device 1 according to this embodiment is a nitride semiconductor device in which the semiconductor layer including the channel mainly contains nitride semiconductor. Specifically, the buffer layer 12, back barrier layer 14, electron transport layer 22, electron supply layer 24, and p-type gate layer 30 each mainly contain nitride semiconductor.

[0073] Nitride semiconductor device 1 is a device having an AlGaN / GaN heterostructure. Due to spontaneous polarization and piezoelectric polarization occurring on the (0001) plane of GaN, a high concentration of 2DEG26 is generated near the heterointerface. Therefore, even in the undoped state, 1 × 10¹⁶ 2DEG26 is generated near the heterointerface. 13 cm -2 The above sheet carrier concentrations can be obtained. Nitride semiconductor device 1 is a high electron mobility transistor (HEMT) containing 2DEG26 as the channel.

[0074] As shown in Figure 1, the nitride semiconductor device 1 comprises a substrate 10, a buffer layer 12, a back barrier layer 14, a semiconductor laminate 20, a p-type gate layer 30, a gate electrode 32, a source electrode 34, a drain electrode 36, an interlayer insulating layer 40, and a source field plate 50.

[0075] The substrate 10 is a substrate made of a nitride semiconductor. The planar shape of the substrate 10 is, for example, rectangular, but is not limited to this. The substrate 10 has, for example, a thickness of 300 μm and a carrier concentration of 5 × 10⁻¹⁴ 18 cm -3 n + The substrate is made of GaN of type n. The substrate 10 may also be a Si substrate, SiC substrate, or ZnO substrate. Furthermore, the substrate 10 may be an insulating substrate such as sapphire or diamond. Alternatively, the substrate 10 may be a semiconductor substrate that has conductivity due to the addition of n-type impurities, and may be a conductive substrate such as a graphite substrate containing graphene.

[0076] The buffer layer 12 is provided above the substrate 10. The buffer layer 12 is, for example, a film made of undoped GaN with a thickness of 7 μm. The buffer layer 12 may be provided in contact with the upper surface of the substrate 10, or another nitride semiconductor layer may be provided between the buffer layer 12 and the substrate 10. Note that "undoped" means that the nitride semiconductor is not doped with a dopant that changes the polarity to n-type or p-type.

[0077] The buffer layer 12 may be an insulating layer or a semi-insulating layer. For example, the buffer layer 12 may be a film made of carbon-doped GaN (C-GaN). The carbon concentration of the buffer layer 12 may be, for example, 3 × 10⁻¹⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 The values ​​may be greater than or equal to the above. The buffer layer 12 may contain n-type impurities such as Si. The concentration of n-type impurities in the buffer layer 12 is lower than the carbon concentration and oxygen concentration of the buffer layer 12, for example, 5 × 10⁻⁶. 16 cm -3 The following, or 2 × 10 16 cm -3 The following is also acceptable.

[0078] The back barrier layer 14 is provided above the buffer layer 12. The back barrier layer 14 is made of, for example, an undoped AlGaN layer. The back barrier layer 14 may be an insulating layer or a semi-insulating layer. For example, the back barrier layer 14 may be a film made of carbon-doped AlGaN (C-AlGaN). The carbon concentration of the back barrier layer 14 is, for example, 3 × 10⁻¹⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 The above is also acceptable. Furthermore, the back barrier layer 14 may consist of two layers: an undoped layer that is not intentionally doped with impurities and a carbon-doped layer.

[0079] The presence of the buffer layer 12 and the back barrier layer 14 suppresses so-called punch-through, where electrons leak from 2DEG26 to the substrate 10. This increases the breakdown voltage of the nitride semiconductor device 1. Note that at least one of the buffer layer 12 and the back barrier layer 14 may be omitted.

[0080] The semiconductor stack 20 is provided above the substrate 10 and includes channels. The semiconductor stack 20 is provided on the upper surface of the back barrier layer 14. In this embodiment, the semiconductor stack 20 includes an electron transport layer 22 and an electron supply layer 24. The semiconductor stack 20 also includes 2DEG26 as channels.

[0081] The electron transport layer 22 is an example of the first nitride semiconductor layer. Specifically, the electron transport layer 22 is provided on the upper surface of the back barrier layer 14. The electron transport layer 22 is, for example, a film made of undoped GaN with a thickness of 150 nm. Although the electron transport layer 22 is assumed to be undoped, it may be partially Si-doped or otherwise made n-type.

[0082] The electron transport layer 22 includes a channel 2DEG26. Specifically, a channel 2DEG26 is generated near the interface between the electron transport layer 22 and the electron supply layer 24. The 2DEG26 extends along the interface between the electron transport layer 22 and the electron supply layer 24, parallel to the main surface of the substrate 10.

[0083] Although not shown in Figure 1, an AlN layer with a thickness of approximately 1 nm is provided between the electron transport layer 22 and the electron supply layer 24. The AlN layer is an example of a nitride semiconductor layer included in the semiconductor stack 20. This suppresses alloy scattering, improves the electron mobility of the channel, and makes it possible to reduce on-resistance. Note that the AlN layer is not necessarily required.

[0084] The electron supply layer 24 is an example of a second nitride semiconductor layer provided above the electron transport layer 22. Specifically, the electron supply layer 24 is provided so as to cover the upper surface of the electron transport layer 22. The electron supply layer 24 is, for example, a film made of undoped AlGaN. The electron supply layer 24 has a larger band gap than the electron transport layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 24 and the electron transport layer 22. The electron supply layer 24 supplies electrons to the channel (2DEG26) formed in the electron transport layer 22.

[0085] As shown in Figure 1, the electron supply layer 24 includes a thin film portion 24A and a thick film portion 24B that is thicker than the thin film portion 24A. The thin film portion 24A and the thick film portion 24B are integrally formed and have the same composition. That is, the Al composition ratios of the thin film portion 24A and the thick film portion 24B are the same, for example, 10% to 50%, but may be 15% to 25%.

[0086] The thin film portion 24A is an example of the first thin film portion and is located between the gate electrode 32 and the source electrode 34 in a plan view of the substrate 10. In this embodiment, the thin film portion 24A is further provided in a position overlapping with the p-type gate layer 30 and in a position overlapping with the source electrode 34 in a plan view. The thin film portion 24A is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 30 to the position overlapping with the source electrode 34.

[0087] The thick film portion 24B is an example of the first thick film portion and is located between the gate electrode 32 and the drain electrode 36 in a plan view of the substrate 10. In this embodiment, the thick film portion 24B is further provided in a position overlapping with the p-type gate layer 30 and in a position overlapping with the drain electrode 36 in a plan view. The thick film portion 24B is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 30 to the position overlapping with the drain electrode 36.

[0088] The film thickness of the thin film portion 24A is, for example, less than half the film thickness of the thick film portion 24B, but may also be less than or equal to one-third. The lower limit of the film thickness of the thin film portion 24A is, for example, 10 nm, but may also be 6 nm. As an example, the film thickness of the thin film portion 24A can be 20 nm.

[0089] The thickness of the thick film portion 24B depends on the composition of the electron supply layer 24. For example, if the Al composition ratio is 20%, the upper limit of the thickness of the thick film portion 24B is 70 nm. This suppresses the occurrence of misfit dislocations and cracks. Note that the upper limit of the thickness of the thick film portion 24B tends to decrease as the Al composition ratio increases. For example, if the Al composition ratio is 25%, the upper limit of the thickness of the thick film portion 24B is 45 nm, and if the Al composition ratio is 30%, the upper limit of the thickness of the thick film portion 24B is 22 nm.

[0090] The boundary between the thin film portion 24A and the thick film portion 24B overlaps the p-type gate layer 30 in a plan view of the substrate 10. The thin film portion 24A and the thick film portion 24B form a step, and the p-type gate layer 30 is provided so as to cover this step. The side wall of the thick film portion 24B located at the boundary is, for example, perpendicular to the main surface of the substrate 10.

[0091] The p-type gate layer 30 is an example of a threshold adjustment layer and is a p-type nitride semiconductor layer provided between the source electrode 34 and the drain electrode 36. In a plan view of the substrate 10, the p-type gate layer 30 spans both the thin film portion 24A and the thick film portion 24B. Specifically, the p-type gate layer 30 continuously covers the upper surface of the thin film portion 24A, the side wall of the thick film portion 24B located at the boundary between the thin film portion 24A and the thick film portion 24B, and the upper surface of the thick film portion 24B. The end of the p-type gate layer 30 on the source electrode 34 side is located on the thin film portion 24A. In this embodiment, the thin film portion 24A is provided between the end of the p-type gate layer 30 on the source electrode 34 side and the source electrode 34, and also extends to the portion directly below the source electrode 34. The end of the p-type gate layer 30 on the drain electrode 36 side is located on the thick film portion 24B. The p-type gate layer 30 is positioned at a distance from the source electrode 34 and the drain electrode 36, and is electrically isolated from them. The upper surface of the p-type gate layer 30 is flat, but a step may be provided corresponding to the step difference between the thin film portion 24A and the thick film portion 24B.

[0092] The p-type gate layer 30 has, for example, a thickness of 200 nm and a carrier concentration of 5 × 10⁻¹⁶ 17 cm -3 This is a film made of p-type GaN. Note that the thickness and carrier concentration of the p-type gate layer 30 are merely examples and can be changed as appropriate. The p-type gate layer 30 may also be a film made of p-type AlGaN.

[0093] The presence of the p-type gate layer 30 raises the potential at the conduction band edge of the channel. This reduces the carrier concentration directly below the gate electrode 32, allowing the threshold voltage of the FET to be shifted to the positive side. Therefore, the nitride semiconductor device 1 can be easily realized as a normally-off type FET.

[0094] The gate electrode 32 is provided above the p-type gate layer 30. The gate electrode 32 is electrically connected to the p-type gate layer 30. Specifically, the gate electrode 32 is provided in contact with the upper surface of the p-type gate layer 30. In this embodiment, the gate electrode 32 straddles the thin film portion 24A and the thick film portion 24B in a plan view of the substrate 10. The end of the gate electrode 32 on the source electrode 34 side overlaps the thin film portion 24A in a plan view, and the end of the gate electrode 32 on the drain electrode 36 side overlaps the thick film portion 24B in a plan view.

[0095] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 can be made of a material that is ohmic-connected to a p-type nitride semiconductor layer such as p-type GaN, but is not limited to this, and may also be made of a material that is Schottky-contacted to a p-type nitride semiconductor layer. For example, Pd, Ni-based materials, WSi, Au, etc. can be used.

[0096] The source electrode 34 and the drain electrode 36 are provided above the substrate 10 in contact with the semiconductor laminate 20. The source electrode 34 and the drain electrode 36 are provided with the p-type gate layer 30 and the gate electrode 32 sandwiched between them. Specifically, the source electrode 34 is electrically connected to the electron transport layer 22 and is provided away from the p-type gate layer 30 and the gate electrode 32. The source electrode 34 is provided on the thin film portion 24A. The drain electrode 36 is electrically connected to the electron transport layer 22 and is provided away from the p-type gate layer 30 and the gate electrode 32. The drain electrode 36 is provided on the thick film portion 24B.

[0097] The source electrode 34 and the drain electrode 36 are each formed using a conductive material such as a metal. As the materials for the source electrode 34 and the drain electrode 36, for example, materials that can be ohmic-connected to an n-type nitride semiconductor layer such as n-type GaN by heat treatment can be used, such as Ti / Al (a stacked structure of a Ti layer and an Al layer). The source electrode 34 and the drain electrode 36 are formed, for example, using the same material and the same process.

[0098] Furthermore, at least one of the source electrode 34 and the drain electrode 36 may be provided so as to be in contact with the electron transport layer 22. Specifically, source openings and drain openings may be provided that penetrate the electron supply layer 24 and expose the electron transport layer 22. The source electrode 34 may be provided so as to cover the inner surface of the source opening, and the drain electrode 36 may be provided so as to cover the inner surface of the drain opening, and the source electrode 34 and the drain electrode 36 may each be in contact with the 2DEG26 exposed on the inner surface of each opening. This can reduce contact resistance, and therefore can reduce on-resistance.

[0099] The interlayer insulating layer 40 is provided above the gate electrode 32. Specifically, the interlayer insulating layer 40 is provided so as to cover the gate electrode 32, the p-type gate layer 30, the electron supply layer 24, the source electrode 34, and the drain electrode 36. The interlayer insulating layer 40 has a single-layer or multi-layer structure of an insulating film such as SiN, SiO2, SiON, or Al2O3.

[0100] The source field plate 50 is located above the interlayer insulating layer 40 and is connected to the source electrode 34 through an opening in the interlayer insulating layer 40. The source field plate 50 is formed using a conductive material such as metal. For example, the source field plate 50 may be a plated film made of, for example, gold (Au).

[0101] In this embodiment, the source field plate 50 overlaps with the gate electrode 32 in a plan view of the substrate 10. The source field plate 50 extends beyond the gate electrode 32 towards the drain electrode 36 from a position overlapping the source electrode 34 in a plan view of the substrate 10. The source field plate 50 can mitigate the electric field between the gate and drain. The source field plate 50 does not overlap the drain electrode 36 in a plan view.

[0102] The source field plate 50 also functions as source wiring that electrically connects a source pad (not shown) and a source electrode 34. Although not shown in Figure 1, drain wiring and a drain pad electrically connected to the drain electrode 36, and gate wiring and a gate pad electrically connected to the gate electrode 32 may be provided above the interlayer insulating layer 40.

[0103] [Effects, etc.] As described above, in the nitride semiconductor device 1 according to this embodiment, the electron supply layer 24 includes a thin film portion 24A and a thick film portion 24B. This makes it possible to make the concentration of 2DEG26 generated near the interface between the electron supply layer 24 and the electron transport layer 22 differ depending on the location.

[0104] The polarization that generates 2DEG26 includes spontaneous polarization due to the atomic arrangement of GaN and piezoelectric polarization due to the difference in lattice constants between the electron supply layer 24 made of AlGaN and the electron transport layer 22 made of GaN. Piezoelectric polarization changes depending on the composition and film thickness of the electron supply layer 24 made of AlGaN. Therefore, the concentration of 2DEG26 can be changed by adjusting at least one of the composition and film thickness of the electron supply layer 24 made of AlGaN. For example, reducing the film thickness of the electron supply layer 24 will lower the concentration of 2DEG26, and increasing the film thickness of the electron supply layer 24 will increase the concentration of 2DEG26.

[0105] In this embodiment, the concentration of 2DEG26 generated near the interface between the thick film portion 24B and the electron transport layer 22 can be increased, thereby reducing the on-resistance. On the other hand, the generation of 2DEG26 near the interface between the thin film portion 24A and the electron transport layer 22 can be suppressed. For example, when the gate electrode 32 is not subjected to a voltage above the threshold voltage, the generation of 2DEG26 near the interface between the thin film portion 24A and the electron transport layer 22 can be prevented, or its concentration can be kept sufficiently low. This reduces the parasitic capacitance that occurs between the gate electrode 32 and the source electrode 34 when the device is off.

[0106] Furthermore, in the nitride semiconductor device 1, the p-type gate layer 30 is provided spanning both the thin film portion 24A and the thick film portion 24B in a plan view. The electric field caused by the high drain voltage when the device is off is distributed between the end of the p-type gate layer 30 on the drain electrode 36 side and the end of the thin film portion 24A on the drain electrode 36 side with which the p-type gate layer 30 is in contact. Since electric field concentration is suppressed, leakage current is reduced and the breakdown voltage between the gate and drain can be increased. Thus, according to the nitride semiconductor device 1 of this embodiment, it is possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0107] Furthermore, since the source electrode 34 is provided on the thin film portion 24A, the distance between the heterointerface of the electron transport layer 22 and the electron supply layer 24 and the source electrode 34 is shortened. This reduces the contact resistance between the source electrode 34 and 2DEG26. Therefore, according to the nitride semiconductor device 1 of this embodiment, the on-resistance can be reduced.

[0108] [Manufacturing method] The nitride semiconductor device 1 configured as described above can be manufactured, for example, by the method shown below.

[0109] First, a nitride semiconductor is grown on the main surface of the substrate 10 by epitaxial growth, such as metal oxide vapor phase epitaxy (MOVPE) or hydride vapor phase epitaxy (HVPE). For example, a buffer layer 12, a back barrier layer 14, an electron transport layer 22, and an electron supply layer 24 are formed in this order in succession on the main surface of the substrate 10. Then, a portion of the electron supply layer 24 is removed by dry etching or the like to partially thin the film thickness of the electron supply layer 24. This forms a thin film portion 24A. Subsequently, a p-type gate layer 30 is formed by epitaxial growth, such as MOVPE or HVPE, so as to cover at least the boundary between the thin film portion 24A and the thick film portion 24B. The p-type gate layer 30 is formed to cover the upper surfaces of both the thin film portion 24A and the thick film portion 24B in contact with each other. Then, the p-type gate layer 30 is patterned into a predetermined shape by dry etching or the like.

[0110] Next, a metal film is formed to cover the p-type gate layer 30 by electron beam deposition or sputtering, and the gate electrode 32 is formed by removing unwanted portions by etching or lift-off. Furthermore, a metal film is formed to cover the upper surfaces of the thin film portion 24A and the thick film portion 24B, and the source electrode 34 and drain electrode 36 are formed by removing unwanted portions by etching or lift-off. Note that the formation of the gate electrode 32 and the formation of the source electrode 34 and drain electrode 36 may be performed in either order. Also, the source electrode 34 and drain electrode 36 may be formed in different processes.

[0111] Next, after forming the gate electrode 32, source electrode 34, and drain electrode 36, an interlayer insulating layer 40 is formed. The interlayer insulating layer 40 is formed by, for example, plasma CVD or atomic layer deposition. After forming the interlayer insulating layer 40, an opening is formed in the interlayer insulating layer 40 by dry etching or the like, exposing at least a portion of the source electrode 34 and drain electrode 36. Then, a source field plate 50 and drain wiring (not shown) are formed to fill the opening. The source field plate 50 and drain wiring are formed by, for example, sequentially depositing Ti, Al, Ni, etc. by sputtering or electron beam deposition, followed by Au plating.

[0112] In this way, the nitride semiconductor device 1 shown in Figure 1 can be manufactured. Note that the above-described method for manufacturing the nitride semiconductor device 1 is merely an example and is not particularly limited.

[0113] [Differentiation] Next, a modified example of Embodiment 1 will be described. In the following, the differences from Embodiment 1 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0114] Figure 2 is a cross-sectional view of the nitride semiconductor device 2 according to this modified example. As shown in Figure 2, the nitride semiconductor device 2 differs from the nitride semiconductor device 1 shown in Figure 1 in that the electron supply layer 24 further includes a thin film portion 24C.

[0115] The thin film portion 24C is an example of a second thin film portion and is located between the thick film portion 24B and the drain electrode 36 in a plan view of the substrate 10. In this embodiment, the thin film portion 24C is further provided in a position that overlaps with the drain electrode 36 in a plan view. The thin film portion 24C is provided with a substantially uniform film thickness continuously from the edge of the thick film portion 24B to the position that overlaps with the drain electrode 36. The film thickness of the thin film portion 24C may be the same as the film thickness of the thin film portion 24A, but may be different. For example, the film thickness of the thin film portion 24A may be greater than the film thickness of the thin film portion 24C.

[0116] In this modified example, the drain electrode 36 is provided on the thin film portion 24C. This shortens the distance between the heterointerface of the electron transport layer 22 and the electron supply layer 24 and the drain electrode 36. Therefore, the contact resistance between 2DEG26 and the drain electrode 36 can be reduced. According to the nitride semiconductor device 2 of this modified example, the on-resistance can be further reduced.

[0117] (Embodiment 2) Next, Embodiment 2 will be described.

[0118] Embodiment 2 differs from Embodiment 1 in that the electron supply layer includes a second thick film portion. Below, we will focus on explaining the differences from Embodiment 1, and omit or simplify the explanation of the common points.

[0119] [composition] Figure 3 is a cross-sectional view of the nitride semiconductor device 101 according to this embodiment. As shown in Figure 3, the nitride semiconductor device 101 differs from the nitride semiconductor device 1 shown in Figure 1 in that it includes a semiconductor stack 120 instead of a semiconductor stack 20. The semiconductor stack 120 differs from the semiconductor stack 20 in that it includes an electron supply layer 124 instead of an electron supply layer 24.

[0120] The electron supply layer 124 has a different cross-sectional shape compared to the electron supply layer 24. Specifically, the electron supply layer 124 includes a thin film portion 124A and thick film portions 24B and 124C. In other words, the electron supply layer 124 has a gate recess 128, which is a recess provided on its upper surface. The thin film portion 124A corresponds to the bottom of the gate recess 128, and the side walls of the thick film portions 24B and 124C on the thin film portion 124A side correspond to the side walls of the gate recess 128.

[0121] The thin film portion 124A is an example of the first thin film portion and is located between the gate electrode 32 and the source electrode 34 in a plan view of the substrate 10. In this embodiment, the thin film portion 124A is further provided in a position that overlaps with the p-type gate layer 30 in a plan view. The thin film portion 124A does not overlap with the source electrode 34 in a plan view. In a plan view, the thin film portion 124A is provided with a substantially uniform film thickness continuously from the edge of the thick film portion 24B to the edge of the thick film portion 124C.

[0122] The thick film portion 124C is an example of a second thick film portion and is located between the gate electrode 32 and the source electrode 34 in a plan view of the substrate 10. In this embodiment, the thick film portion 124C is further provided in a position that overlaps with the source electrode 34 in a plan view. That is, the source electrode 34 is provided on the thick film portion 124C. The thick film portion 124C does not overlap with the p-type gate layer 30 in a plan view. In a plan view, the thick film portion 124C is provided with a substantially uniform film thickness continuously from the edge of the thin film portion 124A to the position that overlaps with the source electrode 34.

[0123] The film thickness of the thick film portion 124C may be the same as the film thickness of the thick film portion 24B, but may also be different. For example, the film thickness of the thick film portion 24B may be greater than the film thickness of the thick film portion 124C.

[0124] The boundary between the thin film portion 124A and the thick film portion 124C is located between the p-type gate layer 30 and the source electrode 34 in a plan view of the substrate 10. The thin film portion 124A and the thick film portion 124C form a step, and this step is not covered by the p-type gate layer 30. The side wall of the thick film portion 124C located at the boundary is, for example, perpendicular to the main surface of the substrate 10.

[0125] [Effects, etc.] Thus, in the nitride semiconductor device 101 according to this embodiment, the electron supply layer 124 includes a thick film portion 124C. This makes it possible to increase the concentration of 2DEG26 generated near the interface between the thick film portion 124C and the electron transport layer 22 in the region between the p-type gate layer 30 and the source electrode 34. Therefore, the on-resistance of the nitride semiconductor device 101 can be reduced.

[0126] Furthermore, the nitride semiconductor device 101, like the nitride semiconductor device 1 according to Embodiment 1, can achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage. Below, the reduction of parasitic capacitance will be explained based on the simulation results performed by the inventors.

[0127] Figure 4A is a cross-sectional view of the nitride semiconductor device 101x according to the comparative example. As shown in Figure 4A, the nitride semiconductor device 101x according to the comparative example differs from the nitride semiconductor device 101 shown in Figure 3 in that it includes a semiconductor stack 120x instead of a semiconductor stack 120. The semiconductor stack 120x differs from the semiconductor stack 120 in that it includes an electron supply layer 124x instead of an electron supply layer 124. The p-type gate layer 30 covers the upper surface of the thin film portion 124Ax, a part of the upper surface of the thick film portion 24B, and a part of the upper surface of the thick film portion 124Cx in contact with each other. In other words, the p-type gate layer 30 is provided so as to cover the entire bottom surface and side wall of the gate recess 128x.

[0128] In the comparative example shown in Figure 4A, the portion of the p-type gate layer 30 covering the thick film portion 24B and the portion covering the thick film portion 124Cx each face the 2DEG26. As a result, the parasitic capacitance between the gate electrode 32 and the 2DEG26 becomes large.

[0129] Figure 4B shows the capacitance characteristics of nitride semiconductor devices for the comparative example and the example. The comparative example shown in Figure 4B has the same configuration as the nitride semiconductor device 101x shown in Figure 4A. Example 1 has the same configuration as the nitride semiconductor device 101 shown in Figure 3. Example 2 has the same configuration as the nitride semiconductor device 102 shown in Figure 5, which will be described later. Example 2 will be described later.

[0130] Figure 4B shows the input capacitance Ciss, output capacitance Coss, and feedback capacitance Crss of the devices for the comparative example and each embodiment. The input capacitance Ciss is the sum of the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd. The output capacitance Coss is the sum of the drain-source parasitic capacitance Cds and the gate-drain parasitic capacitance Cgd. The feedback capacitance Crss is the gate-drain parasitic capacitance Cgd.

[0131] As shown in Figure 4B, the output capacitance Coss is almost the same in both the comparative example and Example 1. In contrast, the input capacitance Ciss is smaller in Example 1 than in the comparative example. On the other hand, the feedback capacitance Crss is smaller in the comparative example than in Example 1. However, the input capacitance Ciss is ordered by a larger number of orders of magnitude than the feedback capacitance Crss. In other words, the configuration of Example 1, which can reduce the input capacitance Ciss, has a greater effect in reducing parasitic capacitance.

[0132] In Example 1, i.e., the nitride semiconductor device 101 according to Embodiment 2, the input capacitance Ciss can be significantly reduced because, as described above, the parasitic capacitance Cgs between the p-type gate layer 30 and the source electrode 34 side 2DEG can be reduced. The same applies to the nitride semiconductor device 1 according to Embodiment 1.

[0133] [Differentiation] Next, several modifications of Embodiment 2 will be described. In the following, the differences from Embodiment 2 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0134] <Example 1> Figure 5 is a cross-sectional view of the nitride semiconductor device 102 according to Modification 1. As shown in Figure 5, the nitride semiconductor device 102 differs from the nitride semiconductor device 101 shown in Figure 3 in that it has an interlayer insulating layer 140 instead of the interlayer insulating layer 40.

[0135] The interlayer insulating layer 140 includes a SiN layer 142 and an SiO2 layer 144. The SiO2 layer 144 is provided above the SiN layer 142. The interlayer insulating layer 140 may further include other insulating layers such as SiN and Al2O3.

[0136] The SiN layer 142 covers the upper surface of the electron supply layer 124 and the upper and side surfaces of the p-type gate layer 30 in contact with each other. The thickness of the SiN layer 142 is, for example, 200 nm to 500 nm. Figure 5 shows an example where the thickness of the SiN layer 142 is the same as the thickness of the source electrode 34 and the drain electrode 36, but is not limited to this. The thickness of the SiN layer 142 may be smaller or larger than the thickness of the source electrode 34 and the drain electrode 36. The SiN layer 142 is formed, for example, by plasma CVD or ALD.

[0137] The SiO2 layer 144 covers the upper surface of the SiN layer 142 in contact with it. The thickness of the SiO2 layer 144 is greater than the thickness of the SiN layer 142. The thickness of the SiO2 layer 144 is, for example, between 100 nm and 800 nm. The thickness of the SiO2 layer 144 may be the same as the thickness of the SiN layer 142, or it may be less than the thickness of the SiN layer 142. The SiO2 layer 144 is formed, for example, by plasma CVD or ALD, but it may also be formed by coating.

[0138] Furthermore, the SiO2 layer 144 has through holes 145 between the p-type gate layer 30 and the drain electrode 36 in a plan view, and a portion of the source field plate 50 is provided within the through holes 145. This makes it possible to reduce the parasitic capacitance Cgd between the gate and drain.

[0139] The capacitance characteristics of the nitride semiconductor device 102 according to this modified example correspond to the capacitance characteristics of Example 2 shown in Figure 4B. The feedback capacitance Crss depends on the film thickness of the SiN layer 142 and SiO2 layer 144 under the source field plate 50, the length of the source field plate 50, the gate-drain distance, etc., and as shown in Figure 4B, it is higher in Example 2 than in Example 1. In contrast, since the SiO2 layer 144, which has a lower dielectric constant than the SiN layer 142, is provided, the parasitic capacitance Cgs between the gate and source can be reduced, and the input capacitance Ciss is lower in Example 2 than in Example 1. The increase in feedback capacitance Crss is only slight, and it can be seen that the configuration according to Example 2, which can reduce the input capacitance Ciss, has a large effect in reducing parasitic capacitance.

[0140] Thus, the nitride semiconductor device 102 according to this modified example can further reduce the input capacitance Ciss.

[0141] <Modification 2> Figure 6 is a cross-sectional view of the nitride semiconductor device 103 according to Modification 2. As shown in Figure 6, the nitride semiconductor device 103 has a different positional relationship between the gate recess 128 and the p-type gate layer 30 compared to the nitride semiconductor device 101 shown in Figure 3.

[0142] In this modified example, the p-type gate layer 30 is provided to fill the gate recess 128. Specifically, the end of the p-type gate layer 30 on the source electrode 34 side and the end of the gate recess 128 on the source electrode 34 side coincide in a plan view of the substrate 10. The p-type gate layer 30 continuously covers the upper surface of the thin film portion 124A from the side wall of the thick film portion 124C to the side wall of the thick film portion 24B. The p-type gate layer 30 is in contact with the respective side walls of the thick film portion 24B and the thick film portion 124C. The p-type gate layer 30 covers a portion of the upper surface of the thick film portion 24B, but does not cover the upper surface of the thick film portion 124C.

[0143] This allows for a larger range of high concentration of 2DEG26 between the gate and source, thereby reducing on-resistance. Furthermore, in this modified example, since the source electrode 34 side end of the p-type gate layer 30 is located on the thin film portion 124A, parasitic capacitance can be reduced. In addition, since the p-type gate layer 30 spans both the thin film portion 124A and the thick film portion 24B, electric field concentration can be mitigated and the breakdown voltage can be increased.

[0144] Furthermore, the nitride semiconductor device 103 according to this modified example may include an interlayer insulating layer 140 instead of the interlayer insulating layer 40, similar to the nitride semiconductor device 102 according to Modified Example 1.

[0145] <Variation 3> Figure 7 is a cross-sectional view of the nitride semiconductor device 104 according to the third modification. As shown in Figure 7, the nitride semiconductor device 104 has a different cross-sectional shape of the electron supply layer 124 compared to the nitride semiconductor device 101 shown in Figure 3.

[0146] In this modified example, as shown in Figure 7, the electron supply layer 124 includes a thin film portion 124A, thick film portions 24B and 124C, and inclined portions 124D and 124E.

[0147] The inclined portion 124D is an example of a first inclined portion with an inclined upper surface, and is located between the thin film portion 124A and the thick film portion 24B in a plan view of the substrate 10. The upper surface of the inclined portion 124D is a plane inclined at an inclination angle θ1. The inclination angle θ1 is the angle on the thick film portion 24B side of the angle formed between the upper surface of the inclined portion 124D and a plane parallel to the main surface of the substrate 10. The inclination angle θ1 is, for example, 20° or more and 80° or less.

[0148] The inclined portion 124E is an example of a second inclined portion with an inclined upper surface, and is located between the thin film portion 124A and the thick film portion 124C in a plan view of the substrate 10. The upper surface of the inclined portion 124E is a plane inclined at an inclination angle θ2. The inclination angle θ2 is the angle on the thick film portion 124C side of the angle formed between the upper surface of the inclined portion 124E and the plane parallel to the main surface of the substrate 10. The inclination angle θ2 is greater than the inclination angle θ1. The inclination angle θ2 is, for example, 30° or more and 90° or less. Note that if the inclination angle θ2 is 90°, it is essentially equivalent to not having an inclined portion 124E.

[0149] The inclined portions 124D and 124E are formed by adjusting the shape of the end of the opening in the resist mask during dry etching to form the gate recess 128. Specifically, the resist mask has an opening in the region corresponding to the gate recess 128, and an inclined surface is provided at the end of the opening. At this time, the inclined surface at the end on the drain electrode 36 side, i.e., the portion corresponding to inclined portion 124D, is made gentler than the inclined surface at the end on the source electrode 34 side, i.e., the portion corresponding to inclined portion 124E. As a result, each inclined surface formed at the end of the opening is transferred to the electron supply layer 124 by dry etching to form the inclined portions 124D and 124E. The inclination of the upper surface of inclined portion 124D is gentler than the inclination of the upper surface of inclined portion 124E.

[0150] Furthermore, the slope can be changed by adjusting the bake temperature of the resist mask. For example, baking at a high temperature will make the slope gentler, while baking at a low temperature will make the slope steeper or perpendicular. The bake temperature of the resist mask is not particularly limited, but for example, it is between 80°C and 160°C. In addition, by making the distance between the gate and drain longer than the distance between the gate and source, the slope of the end corresponding to the sloped portion 124D can be made gentler than the slope of the end corresponding to the sloped portion 124E.

[0151] In this modified example, the p-type gate layer 30 continuously contacts and covers the upper surface of the inclined portion 124D from the thin film portion 124A to the thick film portion 24B. As a result, the electric field caused by a high drain voltage is easily dispersed not only at the end of the thin film portion 124A on the drain electrode 36 side and the end of the p-type gate layer 30 on the drain electrode 36 side, but also on the upper surface of the inclined portion 124D. Therefore, electric field concentration can be mitigated and the breakdown voltage can be increased.

[0152] Furthermore, the nitride semiconductor device 104 according to this modified example may have an interlayer insulating layer 140 instead of the interlayer insulating layer 40, similar to the nitride semiconductor device 102 according to Modified Example 1. Also, the nitride semiconductor device 104 may have a p-type gate layer 30 provided so as to fill the gate recess 128, similar to the nitride semiconductor device 103 according to Modified Example 2. Specifically, the p-type gate layer 30 may be in contact with the upper surface of the inclined portion 124E.

[0153] <Modification 4> Figure 8 is a cross-sectional view of the nitride semiconductor device 105 according to Modification 4. As shown in Figure 8, the nitride semiconductor device 105 has a different stacking structure of the semiconductor stack 120 compared to the nitride semiconductor device 101 shown in Figure 3.

[0154] As shown in Figure 8, the semiconductor laminate 120 further includes an electron supply layer 127. The electron supply layer 127 corresponds to a second electron supply layer when the electron supply layer 124 is the first electron supply layer. The electron supply layer 127 is provided in contact with the upper surface of the electron supply layer 124. Specifically, the electron supply layer 127 is provided in contact with the upper surfaces of the thick film portion 24B and the thick film portion 124C, but not on the upper surface of the thin film portion 124A. In other words, the electron supply layer 127 is not provided within the gate recess 128.

[0155] The electron supply layer 127 is, for example, a layer made of InAlGaN. The layer made of InAlGaN is also called a cap layer. The stacked structure of electron supply layer 127 and electron supply layer 124 can increase the polarization amount of piezoelectric polarization and increase the concentration of 2DEG26. This can reduce the on-resistance. The thickness of electron supply layer 127 is, for example, between 20 nm and 80 nm.

[0156] The electron supply layer 127 may be, for example, an oxide layer mainly composed of gallium oxide. Gallium oxide is, for example, κ-Ga2O3 and has a band gap of approximately 4.9 eV. For example, if the electron supply layer 124 is Al 0.2 Ga 0.8 When N is present, the band gap of electron supply layer 127 is larger than that of electron supply layer 124, and the polarization is also larger. In this case, 2DEG occurs near the interface between electron supply layer 127 and electron supply layer 124. That is, the nitride semiconductor device 105 becomes a multi-channel device consisting of 2DEG occurring in two layers. Therefore, the on-resistance can be further reduced.

[0157] Furthermore, gallium oxide has a refractive index of less than 2.0 at a wavelength of 365 nm, which is lower than the refractive index of GaN (2.7). Therefore, it has a light confinement effect within the electron supply layer 127. This increases the utilization efficiency of light generated at the interface between the p-type gate layer 30 and the electron supply layer 124, thereby increasing the carrier concentration of 2DEG26. Consequently, the on-resistance reduction effect can be further enhanced.

[0158] Furthermore, the nitride semiconductor device 105 according to this modified example may have an interlayer insulating layer 140 instead of the interlayer insulating layer 40, similar to the nitride semiconductor device 102 according to Modified Example 1. Also, the nitride semiconductor device 105 may have a p-type gate layer 30 that fills the gate recess 128, similar to the nitride semiconductor device 103 according to Modified Example 2. In addition, the nitride semiconductor device 105 may have an electron supply layer 124 that includes inclined portions 124D and 124E, similar to the nitride semiconductor device 104 according to Modified Example 3. In this case, the end of the electron supply layer 127 on the gate recess 128 side may also have an inclined portion whose upper surface is inclined so as to be continuous with the inclined portions 124D and 124E, respectively.

[0159] <Modification 5> Figure 9 is a cross-sectional view of the nitride semiconductor device 106 according to Modification 5. As shown in Figure 9, the nitride semiconductor device 106 differs from the nitride semiconductor device 101 shown in Figure 3 in that it has an oxide layer 130 instead of a p-type gate layer 30.

[0160] The oxide layer 130 is an example of a threshold adjustment layer and is an oxide layer provided between the source electrode 34 and the drain electrode 36. The oxide layer 130 is a layer mainly composed of, for example, gallium oxide (Ga2O3) or nickel oxide (NiO). The thickness of the oxide layer 130 is, for example, 50 nm to 200 nm.

[0161] The oxide layer 130, which mainly contains Ga2O3 or NiO, can raise the potential at the conduction band edge of the channel, similar to the p-type gate layer 30. Therefore, the carrier concentration directly below the oxide layer 130 can be reduced, and the transistor threshold can be shifted to the positive side. Thus, the nitride semiconductor device 106 can be operated normally-off.

[0162] The oxide layer 130 may be a layer made of SiO2, Al2O3, or the like. The nitride semiconductor device 106 according to this modified example can be operated as a so-called MOSFET (Metal Oxide Semiconductor FET). Alternatively, the nitride semiconductor device 106 may have an insulating layer such as SiN or SiON instead of the oxide layer 130. The nitride semiconductor device 106 can be operated as a MISFET (Metal Insulator Semiconductor FET).

[0163] Furthermore, the nitride semiconductor device 106 according to this modified example may have an interlayer insulating layer 140 instead of the interlayer insulating layer 40, similar to the nitride semiconductor device 102 according to Modified Example 1. Also, the nitride semiconductor device 106 may have an oxide layer 130 that fills the gate recess 128, similar to the nitride semiconductor device 103 according to Modified Example 2. Also, the nitride semiconductor device 106 may have an electron supply layer 124 that includes inclined portions 124D and 124E, similar to the nitride semiconductor device 104 according to Modified Example 3. Also, the nitride semiconductor device 106 may have a semiconductor laminate 120 that includes an electron supply layer 127, similar to the nitride semiconductor device 105 according to Modified Example 4.

[0164] [Flat layout] Next, the planar layout of the nitride semiconductor device 101 according to Embodiment 2 will be described. Note that the planar layouts of the nitride semiconductor devices 102 to 106 according to Modifications 1 to 5 are substantially the same.

[0165] Figure 10A is a plan view of the nitride semiconductor device 101 according to this embodiment. Figure 10B is a cross-sectional view of the nitride semiconductor device 101 along the XB-XB line in Figure 10A. The cross-section of the nitride semiconductor device 101 along the II-II line shown in Figure 10A is as shown in Figure 3.

[0166] As shown in Figure 10A, the nitride semiconductor device 101 can be divided into an active region 101A and an inactive region 101B in a plan view.

[0167] The active region 101A is the area enclosed by the dotted rectangle shown in Figure 10A. The active region 101A is the main operating region of the nitride semiconductor device 101. Specifically, the active region 101A is the region that becomes the main current path when the nitride semiconductor device 101 is turned on. The active region 101A is sometimes called the device region. The active region 101A is provided with a gate electrode 32, a source electrode 34, a drain electrode 36, a source field plate 50, and a gate recess 128. In Figure 10A, the source field plate 50 is shaded with dots to distinguish it from the others.

[0168] Both the source electrode 34 and the drain electrode 36 have, for example, an elongated shape in one direction, and are arranged so that their longitudinal directions are parallel to each other. Multiple source electrodes 34 and multiple drain electrodes 36 are arranged alternately, one at a time, with a gate electrode 32 and a p-type gate layer 30 in between. The gate electrode 32, the p-type gate layer 30, and the gate recess 128 are each provided in an annular shape surrounding one source electrode 34. In addition, in the active region 101A, as shown in Figures 3 and 10B, 2DEG26 is generated near the interface between the electron transport layer 22 and the electron supply layer 124.

[0169] The inactive region 101B is the region other than the active region 101A. The inactive region 101B is located around the active region 101A and may also be called the peripheral region or element isolation region. The inactive region 101B can be considered a region in which at least the electron transport layer 22 has been made highly resistive so that 2DEG26 does not occur. The resistance is increased by ion implantation, for example, Fe or boron B. In Figure 10B, the region in which the resistance has been increased by ion implantation is represented by dot shading. For example, ion implantation is performed on the electron transport layer 22 and the electron supply layer 24, but is not limited to these. Ion implantation may be performed only on the region of the electron transport layer 22 in which 2DEG26 may occur, or ion implantation may also be performed on the buffer layer 12, the back barrier layer 14 and the electron supply layer 24.

[0170] In this embodiment, as shown in Figure 10A, a drain pad 60 is provided in the inert region 101B. The drain pad 60 is provided at one end of the source electrode 34 in the longitudinal direction. The drain pad 60 is electrically connected to the drain electrode 36 via drain wiring 62. The drain wiring 62 is provided so as to straddle the inert region 101B and the active region 101A, and is connected to the drain electrode 36 provided in the active region 101A. The drain pad 60 is provided on the upper surface of the interlayer insulating layer 40, as shown in Figure 10B. The drain wiring 62 is connected to the drain electrode 36 via via holes or the like provided in the interlayer insulating layer 40.

[0171] Both the drain pad 60 and the drain wiring 62 are formed using a metallic material. Suitable metallic materials for the pad and wiring include metals with low resistivity and high thermal conductivity, such as Au or Cu. The pad and wiring are single-layer metal films made of one type of metal or an alloy of two or more metals, but they may also be laminated films of multiple metal films with different compositions.

[0172] Although not shown in Figure 10A, the inert region 101B may be provided with a gate pad and gate wiring electrically connected to the gate electrode 32, as well as a source pad and source wiring electrically connected to the source electrode 34. The inert region 101B is sometimes referred to as the pad region.

[0173] In this embodiment, as shown in Figures 10A and 10B, the gate electrode 32, the p-type gate layer 30, the gate recess 128, and the thin film portion 124A and thick film portion 24B of the electron supply layer 124 are located further between the source electrode 34 and the drain pad 60 in a plan view of the substrate 10. The p-type gate layer 30 spans the thin film portion 124A and the thick film portion 24B between the source electrode 34 and the drain pad 60. A portion of the boundary between the active region 101A and the inactive region 101B coincides with a portion of the inner circumference contour of the gate electrode 32 in a plan view. Both the gate recess 128 and the p-type gate layer 30 are provided so as to span the boundary between the active region 101A and the inactive region 101B. This makes it possible to suppress the increase of so-called buffer leak. The position of the boundary between the active region 101A and the inactive region 101B does not need to be a position that overlaps with the p-type gate layer 30 in a plan view. For example, the boundary between the active region 101A and the inactive region 101B may coincide with the boundary between the thin film portion 124A and the thick film portion 24B.

[0174] This allows the electric field caused by the high drain voltage applied to the drain pad 60 to be dispersed, thereby further increasing the breakdown voltage. In other words, not only the electric field generated within the active region 101A, but also the electric field generated between the active region 101A and the inactive region 101B can be dispersed, further increasing the breakdown voltage.

[0175] In the example shown in Figure 10A, the gate electrode 32 and the p-type gate layer 30 surround the source electrode 34 in a plan view, but the design is not limited to this. The gate electrode 32 and the p-type gate layer 30 may be provided in a rectangular shape parallel to the source electrode 34 and the drain electrode 36, respectively. For example, the gate electrode 32 may be a so-called finger electrode. In this case, the gate recess 128 and the p-type gate layer 30 located below the finger electrode are provided so as to straddle the boundary between the thin film portion 124A and the thick film portion 24B at the boundary between the active region 101A and the inactive region 101B near the drain pad 60, but the p-type gate layer 30 does not have to straddle the thin film portion 124A and the thick film portion 24B between the drain pad 60 and the source electrode 34.

[0176] (Embodiment 3) Next, Embodiment 3 will be described.

[0177] Embodiment 3 differs from Embodiments 1 and 2 in that the nitride semiconductor device has two electrodes instead of a source electrode and a drain electrode, and is a bidirectional device that allows current to flow bidirectionally between these two electrodes. Below, we will mainly explain the differences from Embodiments 1 and 2, and omit or simplify the explanation of the common points.

[0178] Figure 11 is a cross-sectional view of a nitride semiconductor device 201 according to this embodiment. As shown in Figure 11, the nitride semiconductor device 201 comprises a substrate 10, a buffer layer 12, a back barrier layer 14, a semiconductor laminate 220, p-type gate layers 230 and 231, gate electrodes 232 and 233, a first electrode 234, a second electrode 235, an interlayer insulating layer 40, a first field plate 250, and a second field plate 251.

[0179] The semiconductor laminate 220 includes an electron transport layer 22 and an electron supply layer 224. The electron supply layer 224 has a different cross-sectional shape compared to the electron supply layer 124. Specifically, the electron supply layer 224 includes thin film portions 224A and 224B and a thick film portion 224C.

[0180] The thin film portion 224A is an example of the first thin film portion and is located between the gate electrode 232 and the first electrode 234 in a plan view of the substrate 10. In this embodiment, the thin film portion 224A is further provided in a position overlapping with the p-type gate layer 230 and in a position overlapping with the first electrode 234 in a plan view. The thin film portion 224A is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 230 to the position overlapping with the first electrode 234.

[0181] The thin film portion 224B is an example of a second thin film portion and is located between the gate electrode 233 and the second electrode 235 in a plan view of the substrate 10. In this embodiment, the thin film portion 224B is further provided in a position overlapping with the p-type gate layer 231 and in a position overlapping with the second electrode 235 in a plan view. The thin film portion 224B is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 231 to the position overlapping with the second electrode 235.

[0182] The thick film portion 224C is an example of the first thick film portion and is located between the thin film portion 224A and the thin film portion 224B in a plan view of the substrate 10. In this embodiment, the thick film portion 224C is further provided in a position overlapping with the p-type gate layer 230 and a position overlapping with the p-type gate layer 231 in a plan view. The thick film portion 224C is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 230 to the position overlapping with the p-type gate layer 231.

[0183] The film thickness of the thin film portions 224A and 224B is, for example, the same as the film thickness of the thin film portion 24A according to Embodiment 1. Similarly, the film thickness of the thick film portion 224C is, for example, the same as the film thickness of the thick film portion 24B according to Embodiment 1. Note that the film thicknesses of the thin film portion 224A and the thin film portion 224B may be equal or different.

[0184] The boundary between the thin film portion 224A and the thick film portion 224C overlaps with the p-type gate layer 230 in a plan view of the substrate 10. The thin film portion 224A and the thick film portion 224C form a step, and the p-type gate layer 230 is provided so as to cover this step. The side wall of the thick film portion 224C located at the boundary is, for example, perpendicular to the main surface of the substrate 10.

[0185] The boundary between the thin film portion 224B and the thick film portion 224C overlaps with the p-type gate layer 231 in a plan view of the substrate 10. The thin film portion 224B and the thick film portion 224C form a step, and the p-type gate layer 231 is provided so as to cover this step. The side wall of the thick film portion 224C located at the boundary is, for example, perpendicular to the main surface of the substrate 10.

[0186] The p-type gate layer 230 is an example of a first threshold adjustment layer and is a p-type nitride semiconductor layer provided between the first electrode 234 and the second electrode 235. In a plan view of the substrate 10, the p-type gate layer 230 spans both the thin film portion 224A and the thick film portion 224C. Specifically, the p-type gate layer 230 continuously covers the upper surface of the thin film portion 224A, the side wall of the thick film portion 224C located at the boundary between the thin film portion 224A and the thick film portion 224C, and the upper surface of the thick film portion 224C. The end of the p-type gate layer 230 on the first electrode 234 side is located on the thin film portion 224A. The thin film portion 224A is provided between the end of the p-type gate layer 230 on the first electrode 234 side and the first electrode 234. The end of the p-type gate layer 230 on the second electrode 235 side is located on the thick film portion 224C. The p-type gate layer 230 is positioned at a distance from the gate electrode 233, the first electrode 234, and the second electrode 235, and is electrically isolated from them. The upper surface of the p-type gate layer 230 is flat, but a step may be provided corresponding to the step difference between the thin film portion 224A and the thick film portion 224C.

[0187] The p-type gate layer 231 is an example of a second threshold adjustment layer and is a p-type nitride semiconductor layer provided between the first electrode 234 and the second electrode 235. In a plan view of the substrate 10, the p-type gate layer 231 spans the thin film portion 224B and the thick film portion 224C. Specifically, the p-type gate layer 231 continuously covers the upper surface of the thin film portion 224B, the side wall of the thick film portion 224C located at the boundary between the thin film portion 224B and the thick film portion 224C, and the upper surface of the thick film portion 224C. The end of the p-type gate layer 231 on the second electrode 235 side is located on the thin film portion 224B. The thin film portion 224B is provided between the end of the p-type gate layer 231 on the second electrode 235 side and the second electrode 235. The end of the p-type gate layer 231 on the first electrode 234 side is located on the thick film portion 224C. The p-type gate layer 231 is positioned at a distance from the gate electrode 232, the first electrode 234, and the second electrode 235, and is electrically isolated from them. The upper surface of the p-type gate layer 231 is flat, but a step may be provided corresponding to the step difference between the thin film portion 224B and the thick film portion 224C.

[0188] The p-type gate layers 230 and 231 each have, for example, a thickness of 200 nm and a carrier concentration of 5 × 10⁻¹⁶. 17 cm -3 This is a film made of p-type GaN. Note that the thickness and carrier concentration of the p-type gate layers 230 and 231 are merely examples and can be changed as appropriate. The p-type gate layers 230 and 231 may also be films made of p-type AlGaN. The p-type gate layers 230 and 231 have the same structure as each other, but their shape and composition may differ.

[0189] The gate electrode 232 is an example of a first gate electrode and is provided above the p-type gate layer 230. The gate electrode 232 is electrically connected to the p-type gate layer 230. Specifically, the gate electrode 232 is provided in contact with the upper surface of the p-type gate layer 230. In this embodiment, the gate electrode 232 straddles the thin film portion 224A and the thick film portion 224C in a plan view of the substrate 10. The end of the gate electrode 232 on the first electrode 234 side overlaps the thin film portion 224A in a plan view, and the end of the gate electrode 232 on the second electrode 235 side overlaps the thick film portion 224C in a plan view.

[0190] The gate electrode 233 is an example of a second gate electrode and is provided above the p-type gate layer 231. The gate electrode 233 is electrically connected to the p-type gate layer 231. Specifically, the gate electrode 233 is provided in contact with the upper surface of the p-type gate layer 231. In this embodiment, the gate electrode 233 straddles the thin film portion 224B and the thick film portion 224C in a plan view of the substrate 10. The end of the gate electrode 233 on the second electrode 235 side overlaps the thin film portion 224B in a plan view, and the end of the gate electrode 233 on the first electrode 234 side overlaps the thick film portion 224C in a plan view.

[0191] The gate electrodes 232 and 233 are formed using a conductive material such as a metal. For example, the gate electrodes 232 and 233 can be made of a material that is ohmic-connected to a p-type nitride semiconductor layer such as p-type GaN, but are not limited to this, and may also be made of a material that is Schottky-contacted to a p-type nitride semiconductor layer such as p-type GaN. For example, Pd, Ni-based materials, WSi, Au, etc., can be used.

[0192] The first electrode 234 and the second electrode 235 are provided above the substrate 10 in contact with the semiconductor laminate 220. The first electrode 234 and the second electrode 235 are provided so as to sandwich the p-type gate layers 230 and 231 and the gate electrodes 232 and 233 between them. Specifically, the first electrode 234 is electrically connected to the electron transport layer 22 and is provided away from the p-type gate layer 230 and the gate electrode 232. The first electrode 234 is provided on the thin film portion 224A. The second electrode 235 is electrically connected to the electron transport layer 22 and is provided away from the p-type gate layer 231 and the gate electrode 233. The second electrode 235 is provided on the thin film portion 224B.

[0193] The first electrode 234 and the second electrode 235 are each formed using a conductive material such as a metal. As the materials for the first electrode 234 and the second electrode 235, for example, materials that can be ohmic connected to an n-type nitride semiconductor layer such as n-type GaN by heat treatment can be used, such as Ti / Al (a stacked structure of a Ti layer and an Al layer). The first electrode 234 and the second electrode 235 are formed, for example, using the same material and the same process.

[0194] Furthermore, at least one of the first electrode 234 and the second electrode 235 may be provided so as to be in contact with the electron transport layer 22. Specifically, two openings may be provided that penetrate the electron supply layer 224 and expose the electron transport layer 22. The first electrode 234 and the second electrode 235 are provided so as to cover the inner surface of each of the two openings. The first electrode 234 and the second electrode 235 are in contact with the 2DEG 26 exposed on the inner surface of the corresponding opening. This reduces contact resistance, and therefore reduces on-resistance.

[0195] The first field plate 250 is located above the interlayer insulating layer 40 and is connected to the first electrode 234 through an opening in the interlayer insulating layer 40. The first field plate 250 overlaps the gate electrode 232 in a plan view of the substrate 10. From the position where the first field plate 250 overlaps the first electrode 234 in a plan view of the substrate 10, it extends beyond the gate electrode 232 towards the second electrode 235.

[0196] The second field plate 251 is located above the interlayer insulating layer 40 and is connected to the second electrode 235 through an opening in the interlayer insulating layer 40. The second field plate 251 overlaps the gate electrode 233 in a plan view of the substrate 10. From the position where the second field plate 251 overlaps the second electrode 235 in a plan view of the substrate 10, the second field plate 251 extends beyond the gate electrode 233 towards the first electrode 234.

[0197] The first field plate 250 and the second field plate 251 are formed using a conductive material such as metal. For example, the first field plate 250 and the second field plate 251 are, for example, plated films made of Au. The first field plate 250 and the second field plate 251 are electrically isolated.

[0198] The first field plate 250 also functions as wiring to electrically connect a first pad (not shown) and a first electrode 234. The second field plate 251 also functions as wiring to electrically connect a second pad (not shown) and a second electrode 235. Although not shown in Figure 11, above the interlayer insulating layer 40, there may be a first gate wiring and a first gate pad electrically connected to the gate electrode 232, and a second gate wiring and a second gate pad electrically connected to the gate electrode 233, etc.

[0199] In the nitride semiconductor device 201 according to this embodiment, the gate electrode 232 and the gate electrode 233 can be set to different potentials from each other. The nitride semiconductor device 201 is a four-terminal drive device in which the potentials of the four electrodes—the gate electrode 232, the gate electrode 233, the first electrode 234, and the second electrode 235—can be set independently. By adjusting the potentials set for the four electrodes—the gate electrode 232, the gate electrode 233, the first electrode 234, and the second electrode 235—the nitride semiconductor device 201 can be operated as a bidirectional device such as a bidirectional switch. Furthermore, the nitride semiconductor device 201 can also function as a diode.

[0200] The method for manufacturing the nitride semiconductor device 201 according to this embodiment is the same as the method for manufacturing the nitride semiconductor device 1 according to Embodiment 1. In the method for manufacturing the nitride semiconductor device 1, the p-type gate layers 230 and 231, and the gate electrodes 232 and 233 can be formed by changing the shape of the etching mask in the step of forming the p-type gate layer 30 and the gate electrode 32.

[0201] [Effects, etc.] As described above, in the nitride semiconductor device 201 according to this embodiment, the electron supply layer 224 includes thin film portions 224A and 224B and a thick film portion 224C. This makes it possible to increase the concentration of 2DEG 26 generated near the interface between the thick film portion 224C and the electron transport layer 22, thereby reducing the on-resistance. On the other hand, it is possible to suppress the generation of 2DEG near the interface between each of the thin film portions 224A and 224B and the electron transport layer 22. For example, when the nitride semiconductor device 201 is off, it is possible to prevent the generation of 2DEG near the interface between each of the thin film portions 224A and 224B and the electron transport layer 22, or to keep the concentration sufficiently low. This makes it possible to reduce the parasitic capacitance generated between the gate electrode 232 and the first electrode 234, and between the gate electrode 233 and the second electrode 235, when the device is off.

[0202] Furthermore, since the p-type gate layer 230 spans both the thin film portion 224A and the thick film portion 224C, even if a high voltage is applied to the second electrode 235 when the device is off, the electric field caused by this voltage is dispersed between the end of the p-type gate layer 230 on the second electrode 235 side and the end of the thin film portion 224A on the second electrode 235 side with which the p-type gate layer 230 is in contact. Similarly, since the p-type gate layer 231 spans both the thin film portion 224B and the thick film portion 224C, even if a high voltage is applied to the first electrode 234 when the device is off, the electric field caused by this voltage is dispersed between the end of the p-type gate layer 231 on the first electrode 234 side and the end of the thin film portion 224B on the first electrode 234 side with which the p-type gate layer 231 is in contact. Thus, even if a high voltage is applied to either the first electrode 234 or the second electrode 235 when the device is off, electric field concentration is suppressed, reducing leakage current and increasing breakdown voltage. In this way, the nitride semiconductor device 201 according to this embodiment makes it possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage in a device that can carry current in both directions.

[0203] [Differentiation] Next, several modifications of Embodiment 3 will be described. In the following, the differences from Embodiment 3 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0204] <Example 1> Figure 12 is a cross-sectional view of the nitride semiconductor device 202 according to Modification 1. As shown in Figure 12, the nitride semiconductor device 202 has a different cross-sectional shape of the electron supply layer 224 compared to the nitride semiconductor device 201 shown in Figure 11.

[0205] Specifically, the electron supply layer 224 includes thin film portions 224A and 224B, and thick film portions 224C, 224D, and 224E. In other words, the electron supply layer 224 has gate recesses 228 and 229, which are recesses provided on its upper surface. Thin film portion 224A corresponds to the bottom of gate recess 228, and the side walls of each of the thick film portions 224C and 224D on the thin film portion 224A side correspond to the side walls of gate recess 228. Thin film portion 224B corresponds to the bottom of gate recess 229, and the side walls of each of the thick film portions 224C and 224E on the thin film portion 224B side correspond to the side walls of gate recess 229.

[0206] The thick film portion 224D is an example of a second thick film portion, and in a plan view of the substrate 10, it is located between the thin film portion 224A and the first electrode 234. In this embodiment, the thick film portion 224D is further provided in a position that overlaps with the first electrode 234 in a plan view. That is, the first electrode 234 is provided on the thick film portion 224D. In a plan view, the thick film portion 224D does not overlap with the p-type gate layer 230. In a plan view, the thick film portion 224D is provided with a substantially uniform film thickness, continuously from the edge of the thin film portion 224A to the position that overlaps with the first electrode 234.

[0207] The boundary between the thin film portion 224A and the thick film portion 224D is located between the p-type gate layer 230 and the first electrode 234 in a plan view of the substrate 10. The thin film portion 224A and the thick film portion 224D form a step, and this step is not covered by the p-type gate layer 230. The sidewall of the thick film portion 224D located at the boundary is, for example, perpendicular to the main surface of the substrate 10.

[0208] The thick film portion 224E is an example of a third thick film portion and is located between the thin film portion 224B and the second electrode 235 in a plan view of the substrate 10. In this embodiment, the thick film portion 224E is further provided in a position that overlaps with the second electrode 235 in a plan view. That is, the second electrode 235 is provided on the thick film portion 224E. In a plan view, the thick film portion 224E does not overlap with the p-type gate layer 231. In a plan view, the thick film portion 224E is provided with a substantially uniform film thickness continuously from the edge of the thin film portion 224B to the position that overlaps with the second electrode 235.

[0209] The boundary between the thin film portion 224B and the thick film portion 224E is located between the p-type gate layer 231 and the second electrode 235 in a plan view of the substrate 10. The thin film portion 224B and the thick film portion 224E form a step, and this step is not covered by the p-type gate layer 231. The sidewall of the thick film portion 224E located at the boundary is, for example, perpendicular to the main surface of the substrate 10.

[0210] The film thickness of the thick film portions 224D and 224E may be the same as the film thickness of the thick film portion 224C, but may also be different. For example, the film thickness of the thick film portion 224D or 224E may be greater than the film thickness of the thick film portion 224C.

[0211] Thus, in the nitride semiconductor device 202 according to this modified example, the electron supply layer 224 includes thick film portions 224D and 224E. This makes it possible to increase the concentration of 2DEG26 generated near the interface between the electron supply layer 224 and the electron transport layer 22 in the region between the p-type gate layer 230 and the first electrode 234, and in the region between the p-type gate layer 231 and the second electrode 235. Therefore, the on-resistance of the nitride semiconductor device 202 can be reduced. Furthermore, similar to the nitride semiconductor device 201 according to Embodiment 2, it is possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0212] Here, the planar layout of the nitride semiconductor device 202 according to this modified example will be described.

[0213] Figure 13A is a plan view of the nitride semiconductor device 202 according to this modified example. Figure 13B is a cross-sectional view of the nitride semiconductor device 202 along the line XIIIB-XIIIB in Figure 13A. Figure 13C is a cross-sectional view of the nitride semiconductor device 202 along the line XIIIC-XIIIC in Figure 13A. Furthermore, the cross-section of the nitride semiconductor device 202 along the line XII-XII shown in Figure 13A is as shown in Figure 12.

[0214] As shown in Figure 13A, the nitride semiconductor device 202 can be divided into an active region 202A and an inactive region 202B in a plan view. The active region 202A and the inactive region 202B are the same as the active region 101A and the inactive region 101B according to Embodiment 2, respectively.

[0215] The active region 202A is provided with gate electrodes 232 and 233, a first electrode 234 and a second electrode 235, a first field plate 250, a second field plate 251, and gate recesses 228 and 229. In Figure 13A, the first field plate 250 and the second field plate 251 are shaded with dots to distinguish them from the others.

[0216] Both the first electrode 234 and the second electrode 235 have, for example, an elongated shape in one direction, and are arranged so that their longitudinal directions are parallel to each other. Multiple first electrodes 234 and multiple second electrodes 235 are arranged alternately, one by one, with a gate electrode 232 and p-type gate layer 230 and a gate electrode 233 and p-type gate layer 231 in between. The gate electrode 232 and p-type gate layer 230, and the gate recess 228 are each provided in an annular shape surrounding one first electrode 234. The gate electrode 233 and p-type gate layer 231, and the gate recess 229 are each provided in an annular shape surrounding one second electrode 235. In addition, in the active region 202A, as shown in Figures 12, 13B, and 13C, 2DEG26 is generated near the interface between the electron transport layer 22 and the electron supply layer 224.

[0217] In this embodiment, as shown in Figure 13A, the inert region 202B is provided with a first pad 260 and a second pad 261. The first pad 260 is provided at one end of the first electrode 234 in the longitudinal direction. The first pad 260 is electrically connected to the first electrode 234 via a first wiring 262. The first wiring 262 is provided so as to straddle the inert region 202B and the active region 202A and is connected to the first electrode 234 provided in the active region 202A. The first pad 260 is provided on the upper surface of the interlayer insulating layer 40, as shown in Figure 13C. The first wiring 262 is connected to the first electrode 234 via via holes or the like provided in the interlayer insulating layer 40.

[0218] The second pad 261 is provided at the other end of the first electrode 234 in the longitudinal direction. The second pad 261 is provided so as to sandwich the active region 202A between it and the first pad 260. The second pad 261 is electrically connected to the second electrode 235 via the second wiring 263. The second wiring 263 is provided so as to straddle the inert region 202B and the active region 202A and is connected to the second electrode 235 provided in the active region 202A. The second pad 261 is provided on the upper surface of the interlayer insulating layer 40, as shown in Figure 13B. The second wiring 263 is connected to the second electrode 235 via via holes or the like provided in the interlayer insulating layer 40.

[0219] The first pad 260, the second pad 261, the first wiring 262, and the second wiring 263 are all formed using a metallic material. Suitable metallic materials for the pads and wiring include metals with low resistivity and high thermal conductivity, such as Au or Cu. The pads and wiring are single-layer metal films made of one type of metal or an alloy of two or more types of metals, but they may also be laminated films of multiple metal films with different compositions.

[0220] Although not shown in Figure 13A, the inert region 202B may be provided with a first gate pad and first gate wiring electrically connected to the gate electrode 232, and a second gate pad and second gate wiring electrically connected to the gate electrode 233.

[0221] In this embodiment, as shown in Figures 13A, 13B, and 13C, the gate electrode 232 and the p-type gate layer 230, the gate electrode 233 and the p-type gate layer 231, the gate recesses 228 and 229, and the thin film portion 224A, thin film portion 224B, and thick film portion 224C of the electron supply layer 224 are further located between the first electrode 234 and the second pad 261, and between the second electrode 235 and the first pad 260, respectively, in a plan view of the substrate 10. As shown in Figure 13B, the p-type gate layer 230 spans the thin film portion 224A and the thick film portion 224C between the first electrode 234 and the second pad 261. Also, as shown in Figure 13C, the p-type gate layer 231 spans the thin film portion 224B and the thick film portion 224C between the second electrode 235 and the first pad 260.

[0222] Furthermore, a portion of the boundary between the active region 202A and the inactive region 202B coincides with a portion of the inner circumferential contour of the gate electrode 232 or gate electrode 233. The p-type gate layer 230 or 231 is provided so as to straddle the boundary between the active region 202A and the inactive region 202B. This makes it possible to suppress the increase of so-called buffer leak. The position of the boundary between the active region 202A and the inactive region 202B does not need to be such that it overlaps with the p-type gate layer 230 or 231 in a plan view. For example, the boundary between the active region 202A and the inactive region 202B may coincide with the boundary between the thin film portion 224A or 224B and the thick film portion 224C.

[0223] This allows for the dispersion of the electric field caused by the high voltage applied to the first pad 260 or the second pad 261, thereby further increasing the breakdown voltage. In other words, it is possible to disperse not only the electric field generated within the active region 202A, but also the electric field generated between the active region 202A and the inactive region 202B, thereby further increasing the breakdown voltage.

[0224] <Modification 2> Figure 14 is a cross-sectional view of the nitride semiconductor device 203 according to the second modified example. As shown in Figure 14, the nitride semiconductor device 203 has a different cross-sectional shape of the electron supply layer 224 compared to the nitride semiconductor device 202 shown in Figure 12.

[0225] In this modified example, as shown in Figure 14, the electron supply layer 224 includes thin film portions 224A and 224B, thick film portions 224C, 224D and 224E, and inclined portions 224F, 224G, 224H and 224J.

[0226] The inclined portion 224F is an example of a first inclined portion with an inclined upper surface, and is located between the thin film portion 224A and the thick film portion 224C in a plan view of the substrate 10. The upper surface of the inclined portion 224F is a plane inclined at an inclination angle θ1. The inclination angle θ1 is the angle on the thick film portion 224C side of the angle formed by the upper surface of the inclined portion 224F and the plane parallel to the main surface of the substrate 10. The inclination angle θ1 is, for example, 20° or more and 80° or less.

[0227] The inclined portion 224G is an example of a second inclined portion with an inclined upper surface, and is located between the thin film portion 224A and the thick film portion 224D in a plan view of the substrate 10. The upper surface of the inclined portion 224G is a plane inclined at an inclination angle θ2. The inclination angle θ2 is the angle on the thick film portion 224D side of the angle formed between the upper surface of the inclined portion 224G and the plane parallel to the main surface of the substrate 10. The inclination angle θ2 is greater than the inclination angle θ1. The inclination angle θ2 is, for example, 30° or more and 90° or less. Note that if the inclination angle θ2 is 90°, it is essentially equivalent to not having an inclined portion 224G.

[0228] The inclined portion 224H is an example of a third inclined portion with an inclined upper surface, and is located between the thin film portion 224B and the thick film portion 224C in a plan view of the substrate 10. The upper surface of the inclined portion 224H is a plane inclined at an inclination angle θ3. The inclination angle θ3 is the angle on the thick film portion 224C side of the angle formed by the upper surface of the inclined portion 224H and the plane parallel to the main surface of the substrate 10. The inclination angle θ3 is, for example, 20° or more and 80° or less. The inclination angle θ3 is equal to the inclination angle θ1, but may be different.

[0229] The inclined portion 224J is an example of a fourth inclined portion with an inclined upper surface, and is located between the thin film portion 224B and the thick film portion 224E in a plan view of the substrate 10. The upper surface of the inclined portion 224J is a plane inclined at an inclination angle θ4. The inclination angle θ4 is the angle on the thick film portion 224E side of the angle formed by the upper surface of the inclined portion 224J and the plane parallel to the main surface of the substrate 10. The inclination angle θ4 is greater than the inclination angle θ3. The inclination angle θ4 is, for example, 30° or more and 90° or less. Note that if the inclination angle θ4 is 90°, it is essentially equivalent to not having an inclined portion 224J. The inclination angle θ4 is equal to the inclination angle θ2, but may be different.

[0230] In this modified configuration, the p-type gate layer 230 continuously contacts and covers the upper surface of the inclined portion 224F from the thin film portion 224A to the thick film portion 224C. As a result, even if a high voltage is applied to the second electrode 235 when the device is off, the electric field is easily dispersed over the upper surface of the inclined portion 224F. Furthermore, the p-type gate layer 231 continuously contacts and covers the upper surface of the inclined portion 224H from the thin film portion 224B to the thick film portion 224C. As a result, even if a high voltage is applied to the first electrode 234 when the device is off, the electric field is easily dispersed over the upper surface of the inclined portion 224H. In this way, regardless of whether a high voltage is applied to the first electrode 234 or the second electrode 235 when the device is off, electric field concentration is suppressed, thereby reducing leakage current and increasing withstand voltage.

[0231] (Embodiment 4) Next, Embodiment 4 will be described. Embodiment 4 describes a nitride semiconductor device including a vertical transistor. In the following, the differences between Embodiment 4 and Embodiments 1 to 3 and their respective modifications will be explained, and the explanation of common points will be omitted or simplified.

[0232] Figure 15 is a cross-sectional view of a nitride semiconductor device 301 according to Embodiment 4. The nitride semiconductor device 301 shown in Figure 15 is a normally-off vertical FET. In the nitride semiconductor device 301, source electrodes 334 and 335 are provided above the substrate 310, and a drain electrode 338 is provided below the substrate 310. Therefore, when the nitride semiconductor device 301 is turned on, the drain current flows in the thickness direction of the substrate 310, i.e., in the vertical direction.

[0233] As shown in Figure 15, the nitride semiconductor device 301 comprises a substrate 310, a drift layer 312, a block layer 314, a base layer 316, a semiconductor laminate 320, p-type gate layers 330 and 331, gate electrodes 332 and 333, source electrodes 334 and 335, a p-type semiconductor layer 336, a shielding electrode 337, and a drain electrode 338. The semiconductor laminate 320 includes an electron transport layer 322 and an electron supply layer 324. Note that the substrate 310, electron transport layer 322, electron supply layer 324, p-type gate layers 330 and 331, and gate electrodes 332 and 333 correspond to the substrate 10, electron transport layer 22, electron supply layer 224, p-type gate layers 230 and 231, and gate electrodes 232 and 233 of the nitride semiconductor device 201 according to Embodiment 3, respectively. For corresponding components, we will explain the differences in particular.

[0234] The substrate 310 is a substrate made of a nitride semiconductor. The substrate 310 is a conductive substrate. For example, the substrate 310 has a thickness of 300 μm and a carrier concentration of 1 × 10⁻¹⁶ 18 cm -3 n +The substrate is made of GaN of type 1. The substrate 310 does not have to be a nitride semiconductor substrate. For example, the substrate 310 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0235] The drift layer 312 is an example of an n-type third nitride semiconductor layer provided above the substrate 310. The drift layer 312 is, for example, an n-type semiconductor with a thickness of 8 μm. - It is a film made of type GaN. The donor concentration of the drift layer 312 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 1 x 10 17 cm -3 The following is an example: 1 × 10 16 cm -3 Furthermore, the carbon concentration (C concentration) of the drift layer 312 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 17 cm -3 The drift layer 312 is provided, for example, in contact with the upper surface (main surface) of the substrate 310.

[0236] The block layer 314 is an example of a p-type fourth nitride semiconductor layer provided above the drift layer 312. The block layer 314 has, for example, a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶ 17 cm -3 The film is made of p-type GaN. The block layer 314 is provided in contact with the upper surface of the drift layer 312.

[0237] The block layer 314 is formed by crystal growth, but it may also be formed, for example, by implanting Mg into the deposited i-GaN film. Furthermore, the block layer 314 may not be a p-type nitride semiconductor layer, but rather an insulating layer obtained by implanting Fe or B.

[0238] Furthermore, a high-resistance layer with higher resistance than the block layer 314 and the drift layer 312 may be provided between the block layer 314 and the drift layer 312. The high-resistance layer may be, for example, a carbon-doped GaN layer. By providing a high-resistance layer, punch-through can be suppressed and the breakdown voltage of the nitride semiconductor device 301 can be increased.

[0239] In this embodiment, as shown in Figure 15, the block layer 314 is in contact with the source electrodes 334 and 335. Therefore, the block layer 314 is fixed to the source potential applied to the source electrodes 334 and 335. This enables high breakdown voltage of the nitride semiconductor device 301. For example, when a reverse voltage is applied to the pn junction formed by the block layer 314 and the drift layer 312, specifically when the drain electrode 338 becomes higher in potential than the source electrodes 334 and 335, a depletion layer extends in the drift layer 312, making it possible to increase the breakdown voltage of the nitride semiconductor device 301.

[0240] The base layer 316 is an example of a semiconductor layer provided between the block layer 314 and the electron transport layer 322. The base layer 316 is a high-resistance layer with higher resistance than the block layer 314. The base layer 316 is, for example, a film made of undoped GaN (i-GaN) with a thickness of 200 nm. The base layer 316 is provided in contact with both the block layer 314 and the electron transport layer 322.

[0241] The base layer 316 may be an insulating layer or a semi-insulating layer. For example, the base layer 316 may be a film made of carbon-doped GaN (C-GaN). The carbon concentration of the base layer 316 may be, for example, 3 × 10⁻¹⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 The above is also acceptable. The base layer 316 may contain n-type impurities such as Si. The concentration of n-type impurities contained in the base layer 316 is lower than the carbon concentration and oxygen concentration of the base layer 316, for example, 5 × 10⁻⁶. 16 cm -3 The following, or 2 × 10 16 cm-3 The following is also acceptable. Furthermore, the base layer 316 does not necessarily have to be provided.

[0242] In the nitride semiconductor device 301, an opening 340 is provided that penetrates the block layer 314 and reaches the drift layer 312. The opening 340 is formed such that the opening area increases as it moves away from the substrate 310. Specifically, the bottom surface 340a of the opening 340 is parallel to the main surface of the substrate 310, and the side wall 340b of the opening 340 is inclined at an angle. The side wall 340b may also be perpendicular to the bottom surface 340a.

[0243] The semiconductor laminate 320 is provided so as to cover the inner surface of the opening 340 and the upper part of the block layer 314. Specifically, the electron transport layer 322 contacts and covers the bottom surface 340a and side wall 340b of the opening 340, as well as the upper surface of the base layer 316. Both the electron transport layer 322 and the electron supply layer 324 have a curved shape along the inner surface of the opening 340. The 2DEG 326 that forms near the interface between the electron transport layer 322 and the electron supply layer 324 also has a curved shape along the inner surface of the opening 340.

[0244] The electron supply layer 324 includes thin film portions 324A and 324B and a thick film portion 324C.

[0245] The thin film portion 324A is an example of the first thin film portion and is located between the gate electrode 332 and the source electrode 334 in a plan view of the substrate 310. In this embodiment, the thin film portion 324A is further provided in a position that overlaps with the p-type gate layer 330 in a plan view. The thin film portion 324A is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 330 to the position in contact with the source electrode 334.

[0246] The thin film portion 324B is an example of a second thin film portion and is located between the gate electrode 333 and the source electrode 335 in a plan view of the substrate 310. In this embodiment, the thin film portion 324B is further provided in a position that overlaps with the p-type gate layer 331 in a plan view. The thin film portion 324B is provided with a substantially uniform film thickness continuously from the position overlapping with the p-type gate layer 331 to the position in contact with the source electrode 335.

[0247] The thick film portion 324C is an example of the first thick film portion and is located between the thin film portion 324A and the thin film portion 324B in a plan view of the substrate 310. In this embodiment, the thick film portion 324C is further provided in a position overlapping with the p-type gate layer 330 and a position overlapping with the p-type gate layer 331 in a plan view. The thick film portion 324C has a shape that follows the inner surface of the opening 340. The film thickness of the thick film portion 324C differs between the inclined portion which is parallel to the side wall 340b of the opening 340, the bottom portion which is parallel to the bottom surface 340a of the opening 340, and the top portion which is the outer portion of the opening 340, but may be the same. Note that the film thickness of the thick film portion 324C is greater than the film thickness of each of the thin film portions 324A and 324B, at least in the top portion.

[0248] The p-type gate layer 330 is an example of a first threshold adjustment layer and is a p-type nitride semiconductor layer provided between the source electrode 334 and the source electrode 335. Specifically, in a plan view of the substrate 310, the p-type gate layer 330 is provided between the bottom surface 340a of the opening 340 and the source electrode 334.

[0249] The p-type gate layer 331 is an example of a second threshold adjustment layer and is a p-type nitride semiconductor layer provided between the p-type gate layer 330 and the source electrode 335. Specifically, the p-type gate layer 331 is provided between the bottom surface 340a of the opening 340 and the source electrode 335 in a plan view of the substrate 310. The p-type gate layer 331 is provided so as to sandwich the opening 340 between the p-type gate layer 330. For example, neither the p-type gate layers 330 and 331 overlap with either the bottom surface 340a or the side wall 340b of the opening 340 in a plan view, and they overlap with the upper surface of the underlayer 316.

[0250] The gate electrode 332 is an example of a first gate electrode and is provided above the p-type gate layer 330. The gate electrode 332 is electrically connected to the p-type gate layer 330. Specifically, the gate electrode 332 is provided in contact with the upper surface of the p-type gate layer 330.

[0251] The gate electrode 333 is an example of a second gate electrode and is provided above the p-type gate layer 331. The gate electrode 333 is electrically connected to the p-type gate layer 331. Specifically, the gate electrode 333 is provided in contact with the upper surface of the p-type gate layer 331.

[0252] In the present embodiment, the gate electrodes 332 and 333 are electrically connected to each other. Specifically, a gate pad (not shown) or the like is electrically connected to the gate electrodes 332 and 333, and the same gate potential is supplied.

[0253] In this embodiment, as in other embodiments, the p-type gate layer 330 and gate electrode 332 straddle the thin film portion 324A and the thick film portion 324C in a plan view of the substrate 310. The end of the p-type gate layer 330 on the source electrode 334 side is located on the thin film portion 324A. Also, the p-type gate layer 331 and gate electrode 333 straddle the thin film portion 324B and the thick film portion 324C in a plan view of the substrate 310. The end of the p-type gate layer 331 on the source electrode 335 side is located on the thin film portion 324B. As a result, as in other embodiments, it is possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage in the nitride semiconductor device 301.

[0254] The source electrode 334 is an example of a first electrode and is in contact with the semiconductor laminate 320. In this embodiment, the source electrode 334 is located away from the opening 340 in a plan view of the substrate 310.

[0255] The source electrode 335 is an example of a second electrode and is in contact with the semiconductor laminate 320. In this embodiment, the source electrode 335 is located away from the opening 340 in a plan view of the substrate 310. Specifically, the source electrode 335 is positioned so as to sandwich the opening 340 between it and the source electrode 334. Between the source electrode 335 and the source electrode 334 are the opening 340, p-type gate layers 330 and 331, gate electrodes 332 and 333, p-type semiconductor layer 336, and shielding electrode 337. Furthermore, the source electrodes 334 and 335 are electrically connected to each other. Specifically, source pads (not shown) are electrically connected to the source electrodes 334 and 335, and the same source potential is supplied to them.

[0256] In this embodiment, the source electrode 334 is provided so as to cover the source opening 342. The source electrode 335 is provided so as to cover the source opening 343. When the source electrode 334 is ON, it can be made to directly contact the 2DEG 326 exposed on the side wall 342b of the source opening 342. Similarly, the source electrode 335 is provided so as to cover the source opening 343. When the source electrode 335 is ON, it can be made to directly contact the 2DEG 326 exposed on the side wall 343b of the source opening 343. This reduces the contact resistance of each channel of the source electrodes 334 and 335.

[0257] The source openings 342 and 343 penetrate the semiconductor laminate 320 and the underlying layer 316 to reach the block layer 314. The bottom surfaces 342a and 343a of the source openings 342 and 343, respectively, are the upper surfaces of the block layer 314, but are not limited to this. The bottom surfaces 342a and 343a may be located below the interface between the block layer 314 and the underlying layer 316, that is, closer to the substrate 310.

[0258] The p-type semiconductor layer 336 is an example of a fifth p-type nitride semiconductor layer and is provided above the semiconductor laminate 320 in a position that overlaps with the bottom surface 340a of the opening 340 in a plan view of the substrate 310. Specifically, the p-type semiconductor layer 336 is provided in contact with the upper surface of the thick film portion 324C of the electron supply layer 324 and the lower surface of the shielding electrode 337. In a plan view of the substrate 310, the p-type semiconductor layer 336 overlaps with both the bottom surface 340a and the side wall 340b of the opening 340. However, in a plan view of the substrate 310, the p-type semiconductor layer 336 may overlap only with the bottom surface 340a of the opening 340 and not with the side wall 340b. Alternatively, in a plan view of the substrate 310, the p-type semiconductor layer 336 may overlap not only with the opening 340 but also with the upper surface of the block layer 314.

[0259] The p-type semiconductor layer 336 is electrically isolated from both the p-type gate layers 330 and 331. A source potential is supplied to the p-type semiconductor layer 336 via a shielding electrode 337. The p-type semiconductor layer 336 has, for example, a thickness of 200 nm and a carrier concentration of 1 × 10⁻¹⁶. 19 cm -3 This is a film made of p-type GaN or AlGaN. Note that the thickness and carrier concentration of the p-type semiconductor layer 336 are merely examples and can be changed as appropriate.

[0260] The shielding electrode 337 is an example of a third electrode and is provided above the p-type semiconductor layer 336. Specifically, the shielding electrode 337 is provided in contact with the upper surface of the p-type semiconductor layer 336. The shielding electrode 337 is set to the same potential as the source electrodes 334 and 335.

[0261] The shielding electrode 337 is formed using a conductive material such as a metal. For example, the shielding electrode 337 can be made of a material that is ohmic connected to a p-type nitride semiconductor such as p-type GaN. For example, Pd, Ni-based materials, WSi, Au, etc. can be used as the material for forming the shielding electrode 337.

[0262] In this way, by providing the p-type semiconductor layer 336, the electric field lines extending from the drain electrode 338 can be terminated to the p-type semiconductor layer 336 and the block layer 314, thereby reducing the gate-drain parasitic capacitance Cgd. Therefore, it becomes possible to increase the speed of FET switching with low loss.

[0263] The drain electrode 338 is located below the substrate 310. Specifically, the drain electrode 338 is located in contact with the lower surface of the substrate 310.

[0264] Thus, in the nitride semiconductor device 301 including a vertical transistor, p-type gate layers 330 and 331 are provided so as to span the thin film portions 324A and 324B and the thick film portion 324C of the electron supply layer 324, respectively. This makes it possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage, similar to the nitride semiconductor device 201 according to Embodiment 3.

[0265] An example of a method for manufacturing the nitride semiconductor device 301 is as follows. First, a semiconductor film that will form the basis for the drift layer 312, block layer 314, and underlayer 316 is formed on the substrate 310 by crystal growth using an epitaxial growth method such as MOCVD or HVPE. By adjusting the growth conditions such as raw materials, growth temperature, and growth time, the composition, film thickness, and impurity concentration can be set to values ​​suitable for each layer. The formation of the underlayer 316 may be omitted. Next, an opening 340 is formed that penetrates the underlayer 316 and block layer 314 and reaches the drift layer 312. The opening 340 is formed by, for example, dry etching.

[0266] Next, semiconductor films that will form the basis of the electron transport layer 322 and the electron supply layer 324 are sequentially formed by crystal growth methods such as MOCVD or HVPE, so as to cover the inner surface of the opening 340 and the upper surface of the base layer 316. By adjusting the growth conditions such as raw materials, growth temperature, and growth time, the composition, film thickness, and impurity concentration can be set to values ​​suitable for each layer. The electron transport layer 322 and the electron supply layer 324 are formed continuously in the same growth furnace without exposure to the atmosphere in between. Thin film portions 324A and 324B are formed by removing a portion of the semiconductor film that will form the electron supply layer 324 by dry etching or the like.

[0267] Next, the p-type gate layers 330 and 331 and the p-type semiconductor film that becomes the p-type semiconductor layer 336 are formed by crystal growth such as an epitaxial growth method such as the MOCVD method or the HVPE method so as to straddle each of the thin film portions 324A and 324B and the thick film portion 324C. Then, by patterning the formed p-type semiconductor film into a predetermined shape, the p-type gate layers 330 and 331 and the p-type semiconductor layer 336 are formed. The patterning is performed by dry etching or the like.

[0268] Next, after forming the source openings 342 and 343 by dry etching or the like, the source electrodes 334 and 335, the gate electrodes 332 and 333, the shielding electrode 337, and the drain electrode 338 are formed. The formation order of the source electrodes 334 and 335, the gate electrodes 332 and 333, the shielding electrode 337, and the drain electrode 338 is not particularly limited.

[0269] In the above manner, the nitride semiconductor device 301 shown in FIG. 15 can be manufactured. Note that the manufacturing method of the nitride semiconductor device 301 described above is merely an example and can be appropriately changed.

[0270] <� [Modification Example] Subsequently, a plurality of modification examples of Embodiment 4 will be described. Hereinafter, the description will focus on the differences from Embodiment 4, and the description of the common points will be omitted or simplified.

[0271] <Modification Example 1> FIG. 16 is a cross-sectional view of a nitride semiconductor device 302 according to Modification Example 1. As shown in FIG. 16, in the nitride semiconductor device 302, the cross-sectional shape of the electron supply layer 324 is different from that of the nitride semiconductor device 301 shown in FIG. 15.

[0272] Specifically, the electron supply layer 324 includes thin film portions 324A and 324B, and thick film portions 324C, 324D, and 324E. In other words, the electron supply layer 324 has gate recesses 328 and 329, which are recesses provided on its upper surface. Thin film portion 324A corresponds to the bottom of gate recess 328, and the side walls of each of the thick film portions 324C and 324D on the thin film portion 324A side correspond to the side walls of gate recess 328. Thin film portion 324B corresponds to the bottom of gate recess 329, and the side walls of each of the thick film portions 324C and 324E on the thin film portion 324B side correspond to the side walls of gate recess 329.

[0273] The thick film portions 324D and 324E are the same as the thick film portions 224D and 224E in the modified example 1 of Embodiment 2, respectively. Also, the gate recesses 328 and 329 are the same as the gate recesses 228 and 229 in the modified example 1 of Embodiment 2, respectively.

[0274] Thus, in the nitride semiconductor device 302 according to this modified example, the electron supply layer 324 includes thick film portions 324D and 324E. This makes it possible to increase the concentration of 2DEG326 generated near the interface between each of the thick film portions 324D and 324E and the electron transport layer 322 in the region between the p-type gate layer 330 and the source electrode 334, and in the region between the p-type gate layer 331 and the source electrode 335. Therefore, the on-resistance of the nitride semiconductor device 302 can be reduced. Furthermore, similar to the nitride semiconductor device 301 according to Embodiment 4, it is possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0275] <Modification 2> Figure 17 is a cross-sectional view of the nitride semiconductor device 303 according to the second modified example. As shown in Figure 17, the nitride semiconductor device 303 has a different cross-sectional shape of the electron supply layer 324 compared to the nitride semiconductor device 302 shown in Figure 16.

[0276] In this modified example, as shown in Figure 17, the electron supply layer 324 includes thin film portions 324A and 324B, thick film portions 324C, 324D and 324E, and inclined portions 324F, 324G, 324H and 324J. The inclined portions 324F, 324G, 324H and 324J are the same as the inclined portions 224F, 224G, 224H and 224J in Modified Example 2 of Embodiment 2, respectively.

[0277] In this modified example, the p-type gate layer 330 continuously contacts and covers the upper surface of the inclined portion 324F from the thin film portion 324A to the thick film portion 324C. Furthermore, the p-type gate layer 331 continuously contacts and covers the upper surface of the inclined portion 324H from the thin film portion 324B to the thick film portion 324C. This makes it possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage, similar to the nitride semiconductor device 301 according to Embodiment 4.

[0278] (Embodiment 5) Next, Embodiment 5 will be described. In Embodiment 5, the position of the gate electrode of the vertical transistor is different from that of Embodiment 4. In the following, the differences from Embodiment 4 will be explained in detail, and the explanation of the common points will be omitted or simplified.

[0279] Figure 18 is a cross-sectional view of a nitride semiconductor device 401 according to Embodiment 5. The nitride semiconductor device 401 shown in Figure 18 differs from the nitride semiconductor device 301 shown in Figure 15 in that it includes a p-type gate layer 430 and a gate electrode 432 instead of p-type gate layers 330 and 331, gate electrodes 332 and 333, p-type semiconductor layer 336, and shielding electrode 337.

[0280] The p-type gate layer 430 is an example of a threshold adjustment layer and is provided above the semiconductor laminate 320 in a position that overlaps with the bottom surface 340a of the opening 340 in a plan view of the substrate 310. Specifically, the p-type gate layer 430 is provided in contact with the upper surface of the thick film portion 324C of the electron supply layer 324 and the lower surface of the gate electrode 432. In a plan view of the substrate 310, the p-type gate layer 430 overlaps with the bottom surface 340a and the side wall 340b of the opening 340, and with the upper surface of the block layer 314.

[0281] The p-type gate layer 430 spans both the thin film portion 324A and the thick film portion 324C, and also spans both the thin film portion 324B and the thick film portion 324C, in a plan view of the substrate 310. Specifically, the p-type gate layer 430 is provided with a substantially uniform film thickness, continuously covering the thick film portion 324C from the thin film portion 324A to the thin film portion 324B. The end of the p-type gate layer 430 on the source electrode 334 side is located on the thin film portion 324A. The end of the p-type gate layer 430 on the source electrode 335 side is located on the thin film portion 324B.

[0282] The p-type gate layer 430 is provided between the source electrode 334 and the source electrode 335, and is electrically isolated from both the source electrodes 334 and 335. The gate potential is supplied to the p-type gate layer 430 via the gate electrode 432. The p-type gate layer 430 has, for example, a thickness of 200 nm and a carrier concentration of 1 × 10⁻¹⁶. 19 cm -3 This film is made of p-type GaN or AlGaN. Note that the thickness of the p-type gate layer 430 and the carrier concentration are merely examples and can be changed as appropriate.

[0283] The gate electrode 432 is provided above the p-type gate layer 430. Specifically, the gate electrode 432 is electrically connected to the p-type gate layer 430. The gate electrode 432 is provided in contact with the upper surface of the p-type gate layer 430. In this embodiment, the gate electrode 432 is provided in a position that overlaps the bottom surface 340a of the opening 340 in a plan view of the substrate 310.

[0284] The gate electrode 432 is formed using a conductive material such as a metal. For example, the gate electrode 432 can be made of a material that is ohmic connected to a p-type nitride semiconductor such as p-type GaN. For example, Pd, Ni-based materials, WSi, Au, etc. can be used as the material for forming the gate electrode 432.

[0285] In this embodiment, as in other embodiments, when the nitride semiconductor device 401 is off, the generation of 2DEG326 near the interface between each of the thin film portions 324A and 324B and the electron transport layer 322 is suppressed. Since the end of the p-type gate layer 430 on the source electrode 334 side is located on the thin film portion 324A, and the end of the p-type gate layer 430 on the source electrode 335 side is located on the thin film portion 324B, the area in which the p-type gate layer 430 and 2DEG326 face each other is reduced. Therefore, parasitic capacitance between the gate electrode 432 and each of the source electrodes 334 and 335 can be reduced. Furthermore, the nitride semiconductor device 401 according to this embodiment is a so-called vertical device and has excellent breakdown voltage. Thus, the nitride semiconductor device 401 according to this embodiment makes it possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0286] [Differentiation] Next, several modifications of Embodiment 5 will be described. In the following, the differences from Embodiment 5 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0287] <Example 1> Figure 19 is a cross-sectional view of a nitride semiconductor device 402 according to Modification 1. As shown in Figure 19, the nitride semiconductor device 402 has a different cross-sectional shape of the electron supply layer 324 compared to the nitride semiconductor device 401 shown in Figure 18. The cross-sectional shape of the electron supply layer 324 in the nitride semiconductor device 402 is the same as the cross-sectional shape of the electron supply layer 324 in the nitride semiconductor device 302 shown in Figure 16.

[0288] In the nitride semiconductor device 402 according to this modified example, the electron supply layer 324 includes thick film portions 324D and 324E. This makes it possible to increase the concentration of 2DEG326 generated near the interface between each of the thick film portions 324D and 324E and the electron transport layer 322 in the region between the p-type gate layer 430 and each of the source electrodes 334 and 335. Therefore, the on-resistance of the nitride semiconductor device 402 can be reduced. Furthermore, similar to the nitride semiconductor device 401 according to Embodiment 5, it is possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage.

[0289] <Modification 2> Figure 20 is a cross-sectional view of the nitride semiconductor device 403 according to Modification 2. As shown in Figure 20, the nitride semiconductor device 403 has a different cross-sectional shape of the electron supply layer 324 compared to the nitride semiconductor device 402 shown in Figure 19. The cross-sectional shape of the electron supply layer 324 in the nitride semiconductor device 403 is the same as the cross-sectional shape of the electron supply layer 324 in the nitride semiconductor device 303 shown in Figure 17.

[0290] In this modified example, the p-type gate layer 430 extends continuously from the thin film portion 324A to the thin film portion 324B, contacting and covering the upper surfaces of the inclined portion 324F, the thick film portion 324C, and the inclined portion 324H. This makes it possible to achieve both a reduction in parasitic capacitance and an improvement in breakdown voltage, similar to the nitride semiconductor device 401 according to Embodiment 5.

[0291] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as forms constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0292] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalents thereof. [Industrial applicability]

[0293] The nitride semiconductor devices relating to this disclosure are useful, for example, as power devices used in power supply circuits, inverter circuits, and the like for electrical equipment. [Explanation of Symbols]

[0294] 1, 2, 101, 102, 103, 104, 105, 106, 201, 202, 203, 301, 302, 303, 401, 402, 403 Nitride semiconductor devices 10,310 boards 12 buffer layers 14. Back barrier layer 20, 120, 220, 320 semiconductor laminates 22,322 electron transport layer 24, 124, 127, 224, 324 electron supply layer 24A, 24C, 124A, 224A, 224B, 324A, 324B Thin film part 24B, 124C, 224C, 224D, 224E, 324C, 324D, 324E Thick film part 26,326 2DEG 30, 230, 231, 330, 331, 430 p-type gate layers 32, 232, 233, 332, 333, 432 Ibaraki 34, 334, 335 Source electrodes 36, 338 Drain electrodes 40, 140 interlayer insulating layer 50 Source Field Plates 60 Drain Pads 62 Drain wiring 101A, 202A active area 101B, 202B Inactive area 124D, 124E, 224F, 224G, 224H, 224J, 324F, 324G, 324H, 324J Slope 128, 228, 229, 328, 329 gate recesses 130 Oxide layer 142 SiN layer 144 SiO2 layer 145 Through hole 234 First electrode 235 Second electrode 250 First Field Plate 251 Second Field Plate 260 First pad 261 Second pad 262 First Wiring 263 Second Wiring 312 Drift Layers 314 block layers 316 Base layer 336 p-type semiconductor layer 337 Shielding electrode 340 opening 342, 343 Source opening 340a, 342a, 343a bottom 340b, 342b, 343b side wall

Claims

1. circuit board and A semiconductor laminate including a channel is provided above the aforementioned substrate, Source electrode and drain electrode provided in contact with the semiconductor laminate, A threshold adjustment layer is provided between the source electrode and the drain electrode, A gate electrode provided above the threshold adjustment layer, The semiconductor laminate is A first nitride semiconductor layer, The present invention includes a second nitride semiconductor layer provided above the first nitride semiconductor layer, The second nitride semiconductor layer is A first thin film portion located between the gate electrode and the source electrode in a plan view of the substrate, The substrate includes a first thick film portion located between the gate electrode and the drain electrode in a plan view, and which is thicker than the first thin film portion. The threshold adjustment layer spans the first thin film portion and the first thick film portion in a plan view of the substrate. The end of the threshold adjustment layer on the source electrode side is located on the first thin film portion. Nitride semiconductor devices.

2. The source electrode is provided on the first thin film portion, The drain electrode is provided on the first thick film portion. The nitride semiconductor device according to claim 1.

3. The second nitride semiconductor layer further includes a second thick film portion located between the first thin film portion and the source electrode in a plan view of the substrate. The nitride semiconductor device according to claim 1.

4. The source electrode is provided on the second thick film portion, The drain electrode is provided on the first thick film portion. The nitride semiconductor device according to claim 3.

5. The second nitride semiconductor layer is located between the first thick film portion and the drain electrode in a plan view of the substrate, and further includes a second thin film portion that is thinner than the first thick film portion. The source electrode is provided on the first thin film portion, The drain electrode is provided on the second thin film portion. The nitride semiconductor device according to claim 1.

6. The second nitride semiconductor layer is located between the first thin film portion and the first thick film portion in a plan view of the substrate and further includes a first inclined portion whose upper surface is inclined. A nitride semiconductor device according to any one of claims 1 to 5.

7. The second nitride semiconductor layer is In a plan view of the substrate, a first inclined portion is located between the first thin film portion and the first thick film portion, and its upper surface is inclined, The substrate further includes a second inclined portion located between the first thin film portion and the second thick film portion in a plan view of the substrate, with an inclined upper surface. The inclination of the upper surface of the first inclined portion is gentler than the inclination of the upper surface of the second inclined portion. The nitride semiconductor device according to claim 3 or 4.

8. The threshold adjustment layer is a p-type nitride semiconductor layer. A nitride semiconductor device according to any one of claims 1 to 5.

9. The nitride semiconductor device can be divided into an active region and an inactive region in a plan view of the substrate. The source electrode and the drain electrode are provided in the active region. The nitride semiconductor device is The inert region is further provided with a drain pad that is electrically connected to the drain electrode, The first thick film portion, the first thin film portion, and the threshold adjustment layer are all located between the source electrode and the drain pad in a plan view of the substrate. The threshold adjustment layer, in a plan view of the substrate, spans the first thin film portion and the first thick film portion between the source electrode and the drain pad. A nitride semiconductor device according to any one of claims 1 to 5.

10. circuit board and A semiconductor laminate including a channel is provided above the aforementioned substrate, A first electrode and a second electrode are provided in contact with the semiconductor laminate, A first threshold adjustment layer is provided between the first electrode and the second electrode, A second threshold adjustment layer is provided between the first threshold adjustment layer and the second electrode, A first gate electrode provided above the first threshold adjustment layer, The device comprises a second gate electrode provided above the second threshold adjustment layer, The semiconductor laminate is A first nitride semiconductor layer, The present invention includes a second nitride semiconductor layer provided above the first nitride semiconductor layer, The second nitride semiconductor layer is A first thin film portion located between the first gate electrode and the first electrode in a plan view of the substrate, A second thin film portion located between the second gate electrode and the second electrode in a plan view of the substrate, The substrate includes a first thick film portion located between the first thin film portion and the second thin film portion in a plan view, and which is thicker than either the first thin film portion or the second thin film portion. The first threshold adjustment layer spans the first thin film portion and the first thick film portion in a plan view of the substrate. The second threshold adjustment layer spans the second thin film portion and the first thick film portion in a plan view of the substrate. The end of the first threshold adjustment layer on the first electrode side is located on the first thin film portion, The end of the second threshold adjustment layer on the second electrode side is located on the second thin film portion. Nitride semiconductor devices.

11. The first electrode is provided on the first thin film portion, The second electrode is provided on the second thin film portion. The nitride semiconductor device according to claim 10.

12. The second nitride semiconductor layer is A second thick film portion is located between the first thin film portion and the first electrode in a plan view of the substrate, The substrate further includes a third thick film portion located between the second thin film portion and the second electrode in a plan view of the substrate, The nitride semiconductor device according to claim 10.

13. The first electrode is provided on the second thick film portion, The second electrode is provided on the third thick film portion. The nitride semiconductor device according to claim 12.

14. The second nitride semiconductor layer is In a plan view of the substrate, a first inclined portion is located between the first thin film portion and the first thick film portion, and its upper surface is inclined, The substrate further includes a third inclined portion located between the second thin film portion and the first thick film portion in a plan view, with an inclined upper surface. A nitride semiconductor device according to any one of claims 10 to 13.

15. An n-type third nitride semiconductor layer is provided above the aforementioned substrate, A p-type fourth nitride semiconductor layer is provided above the third nitride semiconductor layer, The substrate further comprises a drain electrode provided below the substrate, The semiconductor laminate is provided so as to cover the inner surface of an opening that penetrates the fourth nitride semiconductor layer and reaches the third nitride semiconductor layer, and the area above the fourth nitride semiconductor layer. The opening is provided between the first electrode and the second electrode in a plan view of the substrate. Both the first electrode and the second electrode are source electrodes that are electrically connected to each other. The first gate electrode and the first threshold adjustment layer are provided between the bottom surface of the opening and the first electrode in a plan view of the substrate. The second gate electrode and the second threshold adjustment layer are provided between the bottom surface of the opening and the second electrode in a plan view of the substrate. A nitride semiconductor device according to any one of claims 10 to 13.

16. In a plan view of the substrate, a p-type fifth nitride semiconductor layer is provided above the semiconductor laminate at a position overlapping with the bottom surface of the opening, The present invention further comprises a third electrode provided above the fifth nitride semiconductor layer and set to the same potential as the source electrode, The nitride semiconductor device according to claim 15.

17. Both the first threshold adjustment layer and the second threshold adjustment layer are p-type nitride semiconductor layers. A nitride semiconductor device according to any one of claims 10 to 13.

18. The nitride semiconductor device can be divided into an active region and an inactive region in a plan view of the substrate. The first electrode and the second electrode are provided in the active region, The nitride semiconductor device is A first pad is provided in the inert region and is electrically connected to the first electrode, The system further comprises a second pad provided in the inert region and electrically connected to the second electrode, The first thick film portion, the first thin film portion, and the first threshold adjustment layer are all located between the first electrode and the first pad in a plan view of the substrate. The first threshold adjustment layer, in a plan view of the substrate, spans the first thin film portion and the first thick film portion between the first electrode and the first pad, The first thick film portion, the second thin film portion, and the second threshold adjustment layer are all located between the second electrode and the second pad in a plan view of the substrate. The second threshold adjustment layer, in a plan view of the substrate, spans the second thin film portion and the first thick film portion between the second electrode and the second pad. A nitride semiconductor device according to any one of claims 10 to 13.

19. circuit board and An n-type third nitride semiconductor layer is provided above the aforementioned substrate, A p-type fourth nitride semiconductor layer is provided above the third nitride semiconductor layer, A semiconductor laminate including a channel is provided so as to cover the inner surface of an opening that penetrates the fourth nitride semiconductor layer and reaches the third nitride semiconductor layer, and the area above the fourth nitride semiconductor layer, A first electrode and a second electrode are provided in contact with the semiconductor laminate, A threshold adjustment layer is provided between the first electrode and the second electrode, A gate electrode provided above the threshold adjustment layer, The substrate comprises a drain electrode provided below the substrate, The opening is provided between the first electrode and the second electrode in a plan view of the substrate. Both the first electrode and the second electrode are source electrodes that are electrically connected to each other. The semiconductor laminate is A first nitride semiconductor layer, The present invention includes a second nitride semiconductor layer provided above the first nitride semiconductor layer, The second nitride semiconductor layer is A first thin film portion located between the gate electrode and the first electrode in a plan view of the substrate, A second thin film portion located between the gate electrode and the second electrode in a plan view of the substrate, The substrate includes a first thick film portion located between the first thin film portion and the second thin film portion in a plan view, and which is thicker than either the first thin film portion or the second thin film portion. The threshold adjustment layer spans the first thin film portion and the first thick film portion in a plan view of the substrate, and spans the second thin film portion and the first thick film portion. The first electrode-side end of the threshold adjustment layer is located on the first thin film portion, The end of the threshold adjustment layer on the second electrode side is located on the second thin film portion. Nitride semiconductor devices.

20. The first electrode is provided on the first thin film portion, The second electrode is provided on the second thin film portion. The nitride semiconductor device according to claim 19.

21. The second nitride semiconductor layer is A second thick film portion is located between the first thin film portion and the first electrode in a plan view of the substrate, The substrate further includes a third thick film portion located between the second thin film portion and the second electrode in a plan view of the substrate, The nitride semiconductor device according to claim 19.

22. The first electrode is provided on the second thick film portion, The second electrode is provided on the third thick film portion. The nitride semiconductor device according to claim 21.

23. The second nitride semiconductor layer is In a plan view of the substrate, a first inclined portion is located between the first thin film portion and the first thick film portion, and its upper surface is inclined, The substrate further includes a third inclined portion located between the second thin film portion and the first thick film portion in a plan view, with an inclined upper surface. A nitride semiconductor device according to any one of claims 19 to 22.

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