Semiconductor equipment
The semiconductor device uses a guard ring and strategically placed diodes with optimized wiring to enhance resistance to ESD pulses and external noise, ensuring stable operation of internal circuits.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2024-11-06
- Publication Date
- 2026-05-19
AI Technical Summary
Semiconductor integrated circuits face challenges in providing adequate resistance to Electro-Static Discharge (ESD) pulses and external noise due to high integration and miniaturization, with existing protection elements being insufficient in preventing noise propagation to internal circuits.
The semiconductor device incorporates a guard ring surrounding the internal circuit, with multiple diodes positioned outside the guard ring in parallel and adjacent to power and ground pads, and optimized wiring widths and layouts to divert ESD pulses and external noise away from the internal circuit.
The configuration enhances resistance to ESD pulses and external noise, stabilizing the output signal and preventing significant fluctuations, thus protecting the internal circuit effectively.
Smart Images
Figure 2026081980000001_ABST
Abstract
Description
Technical Field
[0006] , [Figure 3] , [Figure 2] , [Figure 1]
[0001] This disclosure relates to a semiconductor device.
Background Art
[0002] Semiconductor integrated circuits often include protection elements such as diodes, for example, between a power line and a ground line, for protection against ESD [Electro-Static Discharge] pulses and further against external noise.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
[0004] [Summary] However, due to the high integration and miniaturization of semiconductor integrated circuits in recent years, strengthening the resistance to ESD pulses and external noise may be required.
[0005] The semiconductor device according to this disclosure includes, for example, an internal circuit configured to be connected between a power line and a ground line, a guard ring configured to surround the internal circuit in a plan view, a power pad disposed outside the guard ring in a plan view and configured to be connected to the power line, a ground pad disposed outside the guard ring in a plan view and configured to be connected to the ground line, and a plurality of first diodes disposed outside the guard ring in a plan view and configured to be connected in parallel between the power line and the ground line.
Brief Description of the Drawings
[0006] [Figure 1] FIG. 1 is an overall view of a semiconductor device. [Figure 2] [[ID= 46]]FIG. 2 is a circuit diagram of a comparative example. [Figure 3] FIG. 3 is a plan view of a comparative example. [Figure 4] Figure 4 shows the evaluation results of the comparative example. [Figure 5] Figure 5 is a circuit diagram of an embodiment. [Figure 6] Figure 6 is a plan view of the embodiment. [Figure 7] Figure 7 shows the wiring layout around the power pad and ground pad in the embodiment. [Figure 8] Figure 8 shows the wiring layout around the input pad in the embodiment. [Figure 9] Figure 9 shows the vertical structure of the guard ring in the embodiment. [Figure 10] Figure 10 shows the evaluation results of the embodiment.
[0007] [Detailed explanation] Figure 1 is an overall view of the semiconductor device 1. Package 100 contains the semiconductor device 1, a power terminal T1, a ground terminal T2, signal input terminals T3 and T4, a signal output terminal T5, and wires W1, W2, W3, W4, and W5. The semiconductor device 1 can be understood as a semiconductor chip. Parts of each terminal T1 to T5 are exposed to the outside of package 100.
[0008] The semiconductor device 1 includes a power pad 11, a ground pad 12, input pads 13 and 14, an output pad 15, an internal circuit 10, a power line L1, a ground line L2, signal input lines L3 and L4, and a signal output line L5.
[0009] The power pad 11 is connected to the power terminal T1 via wire W1. The ground pad 12 is connected to the ground terminal T2 via wire W2. The input pad 13 is connected to the signal input terminal T3 via wire W3. The input pad 14 is connected to the signal input terminal T4 via wire W4. The output pad 15 is connected to the signal output terminal T5 via wire W5.
[0010] A first power supply voltage VDD is applied to power supply terminal T1, and a second power supply voltage VSS is applied to ground terminal T2. The first power supply voltage VDD is higher than the second power supply voltage VSS. The second power supply voltage VSS may be 0V or any other voltage.
[0011] The first power terminal of the internal circuit 10 is connected to the power pad 11 via the power line L1. The second power terminal of the internal circuit 10 is connected to the ground pad 12 via the ground line L2. The non-inverting input terminal (+) of the internal circuit 10 is connected to the input pad 13 via the signal input line L3. The inverting input terminal (-) of the internal circuit 10 is connected to the input pad 14 via the signal input line L4. The output terminal of the internal circuit 10 is connected to the output pad 15 via the signal output line L5.
[0012] In the internal circuit 10, a first power supply voltage VDD is applied to the first power supply terminal, and a second power supply voltage VSS is applied to the second power supply terminal.
[0013] The internal circuit 10 may be, for example, an amplifier that amplifies the difference voltage between the positive-phase input signal INP received at the non-inverting input terminal (+) and the negative-phase input signal INN received at the inverting input terminal (-), and outputs an output signal OUT from the output terminal.
[0014] <Comparative Example> Before describing embodiments of this disclosure, we will now describe comparative examples for comparison. Describing these comparative examples will further clarify the issues that can be addressed by this disclosure.
[0015] Figure 2 is a circuit diagram of a comparative example of semiconductor device 1. In addition to the configuration in Figure 1, semiconductor device 1 includes diodes D1, D3, and D4, and transistors M1 and M2. Transistor M1 may be, for example, a P-channel type. Transistor M2 may be an N-channel type.
[0016] The cathode of diode D1 is connected to the power supply line L1, and the anode is connected to the ground line L2. The cathode of diode D3 is connected to the signal input line L3, and the anode is connected to the ground line L2. The cathode of diode D4 is connected to the signal input line L4, and the anode is connected to the ground line L2. Here, diodes D1, D3, and D4 have parasitic capacitances between their respective anodes and cathodes, and function as protection elements to protect the internal circuit 10 from ESD pulses or external noises.
[0017] The source of transistor M1 is connected to the power supply line L1, and the drain is connected to the drain of transistor M2 and the signal output line L5. The source of transistor M2 is connected to the ground line L2. Here, transistors M1 and M2 are the output stages of the internal circuit 10.
[0018] According to the configuration of the comparative example in FIG. 2, for example, when an ESD pulse or external noise is superimposed on the power supply pad 11, the internal circuit 10 can be protected by diode D1. Also, when an ESD pulse or external noise is superimposed on the input pads 13 and 14, the internal circuit 10 can be protected by diodes D3 and D4.
[0019] However, in the configuration of the comparative example in FIG. 2, only one diode is provided between the power supply line L1 and the ground line L2. With the high integration and miniaturization of semiconductor integrated circuits in recent years, stronger resistance to ESD pulses and external noises is required.
[0020] FIG. 3 is a plan view of a comparative example of the semiconductor device 1. The semiconductor device 1 includes a guard ring 20 in addition to the configuration of FIG. 2.
[0021] The guard ring 20 is formed so as to surround the internal circuit 10, the power supply pad 11, the ground pad 12, the input pads 13, 14, the output pad 15, and the diodes D1, D3, and D4. More specifically, the diode D1, the power supply pad 11, and the ground pad 12 are formed so as to be separated with the internal circuit 10 interposed therebetween.
[0022] As shown in the comparative example in Figure 3, the guard ring 20 surrounds the internal circuit 10, thereby suppressing the intrusion of ESD pulses or external noise.
[0023] However, in the comparative example configuration shown in Figure 3, not only the internal circuit 10 but also the power supply pad 11, ground pad 12, input pads 13 and 14, and output pad 15 are provided inside the guard ring 20. Therefore, the distance between each pad 11-15 and the internal circuit 10 is short. As a result, ESD pulses or external noise are more easily propagated to the internal circuit 10.
[0024] Figure 4 shows the evaluation results of the noise test for the comparative example. In this figure, the horizontal axis represents the frequency FRQ, and the vertical axis represents the variation value ΔOUT of the output signal OUT. In the configuration of the comparative example, the output signal OUT fluctuates significantly when ESD pulses or external noise are present.
[0025] <Embodiment> Figure 5 is a circuit diagram of an embodiment of semiconductor device 1. In addition to the circuit configuration of Figure 2, semiconductor device 1 in Figure 5 is equipped with a diode D2.
[0026] Diode D2 has its cathode connected to the power line L1 and its anode connected to the ground line L2. Diode D2 is installed in parallel with diode D1. Here, diode D2 functions as a protective element with parasitic capacitance, just like diode D1.
[0027] As shown in this configuration, by providing two diodes in parallel, the resistance to ESD pulses and external noise is enhanced compared to a configuration with only one diode, as in the comparative example shown in Figure 2.
[0028] Figure 6 is a plan view of an embodiment of semiconductor device 1. The semiconductor device 1 in Figure 6 includes a guard ring 20 in addition to the configuration in Figure 5. Compared to the configuration in Figure 3, the semiconductor device 1 in Figure 6 includes a diode D2 and the arrangement of each component is different.
[0029] The guard ring 20 is formed to surround the internal circuit 10. On the other hand, the power pad 11, ground pad 12, input pads 13, 14, output pad 15, and diodes D1, D2, D3, D4 are located outside the guard ring 20.
[0030] As shown in this configuration, by providing a guard ring 20 between each pad 11-15 and the internal circuit 10, the propagation of ESD pulses or external noise from each pad 11-15 to the internal circuit 10 can be reduced.
[0031] The semiconductor device 1 is a chip cut into a rectangular shape in a plan view, with an upper side 1a, a lower side 1b, a right side 1c, and a left side 1d.
[0032] The power pad 11, ground pad 12, output pad 15, and diodes D1 and D2 are positioned near the bottom edge 1b in Figure 6. More specifically, the area near the bottom edge 1b refers to the region between the guard ring 20 and the bottom edge 1b.
[0033] Diodes D1 and D2 are placed adjacent to each other. Specifically, being adjacent to each other means, for example, that they are in series when viewed from the left side 1d, and the distance between diodes D1 and D2 (w4) is shorter than the length of the side on the upper side 1a of the diode (D1a).
[0034] Diodes D1 and D2 are positioned adjacent to each other so as to overlap the ground pad 12 and the output pad 15, respectively. More specifically, "adjacent so as to overlap the ground pad 12 and the output pad 15" means that at least a portion of diode D1 or D2 is positioned so as to overlap the ground pad 12 and the output pad 15 in a vertical structure. Diodes D1 and D2 are also positioned near the power supply pad 11. "Near the power supply pad 11" means, for example, that the distance (w5) between diode D1 or D2 on the side closer to the power supply pad 11 and the power supply pad 11 is shorter than the length of the bottom edge 1b.
[0035] Diodes D1 and D2 may be placed between the power supply pad 11 and the ground pad 12.
[0036] As shown in this configuration, by placing diodes D1 and D2 near the power supply pad 11 and the ground pad 12, when an ESD pulse or external noise enters the circuit, it is possible to divert the ESD pulse or external noise to the protective elements, diodes D1 and D2, faster than it can propagate to the internal circuit 10.
[0037] The input pad 13 and diode D3 are located near the upper left corner of the semiconductor device 1 in Figure 6. Specifically, the area near the upper left corner refers to the region demarcated by the top edge 1a, the left edge 1d, and the guard ring 20.
[0038] The input pad 13 is positioned adjacent to the diode D3 so as to overlap it. More specifically, "adjacent to the diode D3" means that, in a vertical structure, at least a portion (the entirety in this figure) of the input pad 13 overlaps the diode D3.
[0039] The input pad 14 and diode D4 are located near the upper right corner of the semiconductor device 1 in Figure 6. Specifically, the area near the upper right corner refers to the region demarcated by the top edge 1a, the right edge 1c, and the guard ring 20.
[0040] The input pad 14 is positioned adjacent to the diode D4 so as to overlap it. More specifically, "adjacent to the diode D4" means that, in a vertical structure, at least a portion (the entirety in this figure) of the input pad 14 overlaps the diode D4.
[0041] The individual element sizes of diodes D1 and D2 may be larger than the individual element sizes of diodes D3 and D4.
[0042] Figure 7 shows the wiring layout around the power pad 11 and ground pad 12 in an embodiment of the semiconductor device 1. The semiconductor device 1 includes power lines L1a, L1b and ground lines L2a, L2b. Power lines L1a and L1b are subdivisions of the power line L1 described above. Ground lines L2a and L2b are subdivisions of the ground line L2 described above.
[0043] The power pad 11 is connected to an internal circuit 10 (not shown) via power line L1a. The power pad 11 is also connected to diodes D1 and D2 via power line L1b.
[0044] The grounding pad 12 is connected to an internal circuit 10 (not shown) via a grounding line L2a. The grounding pad 12 is also connected to diodes D1 and D2 via a grounding line L2b.
[0045] The wiring width w1a of power line L1a is set to be narrower than the wiring width w1b of power line L1b. The wiring width w1a may be, for example, 10 μm. The wiring width w1b may be, for example, 20 μm.
[0046] The wiring width w2a of the grounding line L2a is set to be narrower than the wiring width w2b of the grounding line L2b. The wiring width w2a may be, for example, 10 μm. The wiring width w2b may be, for example, 70 μm.
[0047] The wiring width w20 of the guard ring 20 is set to be thicker than the wiring width w1a and thinner than the wiring width w1b. The wiring width w20 may be, for example, 15 μm.
[0048] By changing the wiring width of the power lines L1a, L1b, ground lines L2a, L2b, and guard ring 20 in this way, ESD pulses or external noise can be directed to the thicker wire. Therefore, if ESD pulses or external noise enter from the power pad 11 and ground pad 12, it is possible to make it easier for the ESD pulses or external noise to flow to the diodes D1 and D2.
[0049] Here, the guard ring 20 has an open ring portion 21 in the region where it intersects with the power line L1a, and an open ring portion 22 in the region where it intersects with the ground line L2a.
[0050] The ring openings 21 and 22 are regions in the vertical structure through which the power line L1a and the ground line L2a pass from the outside to the inside of the guard ring 20. A detailed explanation of the vertical structure of the ring openings 21 and 22 will be given later.
[0051] Figure 8 shows the wiring layout around the input pad 13 in an embodiment of the semiconductor device 1. As previously described, the semiconductor device 1 includes a signal input line L3. The input pad 13 is connected to an internal circuit 10 (not shown) via the signal input line L3.
[0052] The wiring width w3 of the signal input line L3 is set to be narrower than the wiring width w1a of the power line L1a and the wiring width w2a of the power line L2a. The wiring width w3 may be, for example, 3 μm.
[0053] By designing the wiring width w3 in this way, a thinner wire can better prevent the intrusion of ESD pulses or external noise. Therefore, if ESD pulses or external noise enter from the input pad 13, it becomes more difficult for the ESD pulses or external noise to flow into the internal circuit 10.
[0054] Here, the guard ring 20 has an open section 23 in the region where it intersects with the signal input line L3.
[0055] The ring opening 23 is a region in the vertical structure through which the signal input line L3 passes from the outside to the inside of the guard ring 20. A detailed explanation of the vertical structure of the ring opening 23 will be given later.
[0056] Figure 9 shows the vertical structure of the input pad 13 and guard ring 20 in an embodiment of the semiconductor device 1.
[0057] The AA section (upper row) of Figure 9 shows the AA cross-section of Figure 8. The input pad 13 is formed on the surface layer of the diode D3, which consists of a P-type well P / W and an N-type region N+. The input pad 13 has multiple stacked metal layers. The multiple metal layers may be, for example, three layers: a 1st_AL layer, a 2nd_AL layer, and a TOP_AL layer.
[0058] The guard ring 20 is formed on a layer consisting of a P-type well P / W and P-type regions P+ and N-type regions N+. The guard ring 20 includes multiple stacked annular lines. Referring to the figure, the multiple annular lines may be formed on each of the multiple metal layers, for example, consisting of a 1st_AL layer, a 2nd_AL layer and a TOP_AL layer.
[0059] Here, the N-type region N+ and the P-type region p+ are connected to the 1st_AL layer, the 1st_AL layer is connected to the 2nd_AL layer, and the 2nd_AL layer is connected to the TOP_AL layer, respectively, by conductive vias.
[0060] The metal layer of the input pad 13 and the metal layer of the guard ring 20 are independent of each other.
[0061] The BB column (middle) in Figure 9 shows the BB cross-section of Figure 8. A signal input line L3 is connected to the input pad 13. The signal input line L3 is formed in the 2nd AL layer. In this figure, the metal layer of the signal input line L3 is provided so as to extend from the input pad 13, across the guard ring 20, to the internal circuit 10 (not shown). Here, the guard ring 20 is provided with a ring opening 23, which is a partial removal of the 2nd AL layer of the guard ring 20, in order to allow the metal layer of the signal input line L3 to pass through the internal circuit 10 (not shown).
[0062] Generally, the top layer, the TOP_AL layer, has a thicker film thickness. Therefore, the TOP_AL layer can be used primarily to reduce the wiring resistance of the guard ring 20. On the other hand, the bottom layer, the 1st_AL layer, plays the role of facilitating the escape of ESD pulses or external noise through contact with the P-type substrate. Therefore, it is desirable that the ring opening 23 for laying the signal input line L3 be provided by partially removing the 2nd_AL layer, which is not so critical in terms of wiring resistance.
[0063] The CC column (lower section) in Figure 9 shows the CC cross-section of Figure 8. The 1st_AL layer and TOP_AL layer of the guard ring 20 are provided in a continuous, uninterrupted manner, surrounding the internal circuit 10. In other words, the 1st_AL layer and TOP_AL layer of the guard ring 20 are formed in a closed ring shape. On the other hand, the 2nd_AL layer of the guard ring 20 is interrupted in the region of each ring opening (ring opening 23 in this figure). However, the 2nd_AL layer of the guard ring 20 is provided in a continuous, uninterrupted manner in the region other than each ring opening.
[0064] Thus, at least one of the multiple layers of annular lines forming the guard ring 20 is provided with at least one ring opening 21-23 where the ring is interrupted in a plan view. The power line L1a, the ground line L2a, and the signal lines L3, L4 are laid to connect each pad 11-14 to the internal circuit 10 through the ring opening.
[0065] With the configuration shown in Figure 9, even when each of the pads 11-14 is located on the outside of the guard ring 20, wiring connections to the internal circuit 10 are possible.
[0066] Figure 10 shows the evaluation results of an embodiment of semiconductor device 1. Figure 10 is a graph in which the horizontal axis represents frequency FRQ and the vertical axis represents the variation value ΔOUT of the output signal OUT. The solid line in the graph shows the evaluation results of an embodiment of semiconductor device 1, and the dotted line shows the evaluation results of a comparative example of semiconductor device 1.
[0067] This graph shows that, with the configuration of semiconductor device 1, the output signal OUT under the influence of ESD pulses or external noise is stable and does not fluctuate significantly compared to the comparative example.
[0068] As described above, with the embodiment of semiconductor device 1, further enhanced voltage resistance against ESD pulses or external noise becomes possible.
[0069] <Note> A note is provided regarding this disclosure in which specific configuration examples are shown in the embodiments described above.
[0070] (Note 1) An internal circuit (10) configured to be connected between a power line (L1) and a ground line (L2), A guard ring (20) is configured to surround the internal circuit (10) in a plan view, A power pad (11) is positioned outside the guard ring (20) in a plan view and is configured to be connected to the power line (L1), A grounding pad (12) is positioned outside the guard ring (20) in a plan view and is configured to be connected to the grounding line (L2), A plurality of first diodes (D1, D2) are arranged outside the guard ring (20) in a plan view and are configured to be connected in parallel between the power line (L1) and the ground line (L2), A semiconductor device (1) comprising the following:
[0071] (Note 2) The semiconductor device according to Appendix 1, further comprising input pads (13, 14) positioned outside the guard ring (20) in a plan view and configured to be connected to the internal circuit (10) via signal lines (L3, L4).
[0072] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein the plurality of first diodes (D1, D2) are arranged adjacent to each other.
[0073] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the plurality of first diodes (D1, D2) are arranged adjacent to the power supply pad (11) or the ground pad (12).
[0074] (Note 5) The semiconductor device according to any one of the appendices 1 to 4, wherein the power line (L1) includes a first power line (L1a) laid between the power pad (11) and the internal circuit (10), and a second power line (L1b) laid between the power pad (11) and the plurality of first diodes (D1, D2), and the wiring width (w1a) of the first power line (L1a) is narrower than the wiring width (w1b) of the second power line (L1b).
[0075] (Note 6) The semiconductor device as described in Appendix 5, wherein the wiring width of the guard ring (20) is thicker than the wiring width (w1a) of the first power line (L1a) and thinner than the wiring width (w1b) of the second power line (L1b).
[0076] (Note 7) The semiconductor device according to any one of the appendices 1 to 6, wherein the ground line (L2) includes a first ground line (L2a) laid between the ground pad (12) and the internal circuit (10), and a second ground line (L2b) laid between the ground pad (12) and the plurality of first diodes, and the wiring width (w2a) of the first ground line (L2a) is narrower than the wiring width (w2b) of the second ground line (L2b).
[0077] (Note 8) The semiconductor device described in Appendix 2, wherein the wiring width (w3) of the signal lines (L3, L4) is narrower than the wiring width of the power line (L1) and the ground line (L2).
[0078] (Note 9) The guard ring (20) includes multiple layers of annular lines formed in a laminated structure. At least one of the aforementioned multi-layered annular lines is provided with at least one annular opening (23) in which the ring is interrupted in a plan view. The semiconductor device as described in Appendix 2, wherein the power line (L1), the ground line (L2), and the signal line are each laid through the ring opening (23).
[0079] (Note 10) The semiconductor device as described in Appendix 2, wherein the internal circuit (10) is an amplifier configured to amplify an input signal received via the signal line and generate an output signal.
[0080] (Note 11) The semiconductor device according to Appendix 2, further comprising second diodes (D3, D4) positioned outside the guard ring (20) in a plan view and configured to be connected between the signal line and the ground line (L2).
[0081] (Note 12) The semiconductor device described in Appendix 11, wherein the element size of the first diode (D1, D2) is larger than the element size of the second diode (D3, D4). [Explanation of symbols]
[0082] 1. Semiconductor equipment (semiconductor chips) 1a Top edge 1b Bottom edge 1c Right side 1d Left side 10. Internal circuitry (amplifier) 11 Power Pad 12 Grounding pads 13, 14 Input pads 15 Output Pads 20 Guard Rings 21, 22, 23 Open ring part 100 packages D1, D2, D3, D4 diodes L1, L1a, L1b power lines L2, L2a, L2b grounding lines L3, L4 signal input lines L5 signal output line M1, M2 transistors N+ N-type region P / WP type well P+ P-type region T1 power terminal T2 ground terminal T3, T4 signal input terminals T5 signal output terminal W1~W5 Wire
Claims
1. An internal circuit configured to be connected between the power line and the ground line, A guard ring configured to surround the internal circuit in a plan view, A power pad is positioned outside the guard ring in a plan view and configured to be connected to the power line, A grounding pad is positioned outside the guard ring in a plan view and configured to be connected to the grounding line, A plurality of first diodes are arranged outside the guard ring in a plan view and are configured to be connected in parallel between the power line and the ground line, A semiconductor device equipped with the following features.
2. The semiconductor device according to claim 1, further comprising an input pad located outside the guard ring in a plan view and configured to be connected to the internal circuit via a signal line.
3. The semiconductor device according to claim 1, wherein the plurality of first diodes are arranged adjacent to one another.
4. The semiconductor device according to claim 1, wherein the plurality of first diodes are arranged adjacent to the power supply pad or the ground pad.
5. The semiconductor device according to claim 1, wherein the power line includes a first power line laid between the power pad and the internal circuit and a second power line laid between the power pad and the plurality of first diodes, and the wiring width of the first power line is narrower than the wiring width of the second power line.
6. The semiconductor device according to claim 5, wherein the wiring width of the guard ring is wider than the wiring width of the first power line and narrower than the wiring width of the second power line.
7. The semiconductor device according to claim 1, wherein the grounding line includes a first grounding line laid between the grounding pad and the internal circuit and a second grounding line laid between the grounding pad and the plurality of first diodes, and the wiring width of the first grounding line is narrower than the wiring width of the second grounding line.
8. The semiconductor device according to claim 2, wherein the wiring width of the signal line is narrower than the wiring width of the power line and the ground line.
9. The guard ring includes multiple layers of annular lines formed in a stacked manner. At least one of the aforementioned multiple layers of annular lines is provided with at least one annular opening where the ring is interrupted in a plan view. The semiconductor device according to claim 2, wherein the power line, the ground line, and the signal line are each laid through the ring-open portion.
10. The semiconductor device according to claim 2, wherein the internal circuit is an amplifier configured to amplify an input signal received via the signal line and generate an output signal.
11. The semiconductor device according to claim 2, further comprising a second diode positioned outside the guard ring in a plan view and configured to be connected between the signal line and the ground line.
12. The semiconductor device according to claim 11, wherein the element size of the first diode is larger than the element size of the second diode.