Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure comprising a substrate, a conductive layer, and a semiconductor element, which improves performance and heat dissipation. [Solution] In the semiconductor structure, the substrate 100 includes a first surface 100A', a second surface 100B opposite to the first surface, at least one insulating vacancy C extending from the first surface to the second surface, through holes TH penetrating the substrate, and a conductive layer 120 filling the through holes. The semiconductor element 102 is placed on the second surface and electrically connected to the conductive layer, and at least one insulating vacancy is distributed corresponding to the semiconductor element.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure for reducing the high-frequency coupling effect of semiconductor devices and a method for manufacturing the same.

Background Art

[0002] A high electron mobility transistor (HEMT), also known as a modulation-doped FET (MODFET), is a field-effect transistor. Unlike a metal-oxide-semiconductor field-effect transistor that uses a doped semiconductor directly for channel formation, a high electron mobility transistor forms a heterojunction using two materials with different energy gaps to provide a channel for carriers. As materials for forming high electron mobility transistors, ternary compound semiconductors such as gallium arsenide and aluminum gallium arsenide are commonly used. In recent years, GaN high electron mobility transistors have attracted attention due to their excellent high-frequency characteristics. Since high electron mobility transistors can operate at high frequencies, they are widely used in mobile phones, satellite TVs, radars, etc. However, in high electron mobility transistors, problems such as degradation of device performance due to high-frequency coupling effects frequently occur.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present invention provides a semiconductor structure having semiconductor devices and a method for manufacturing the same for reducing the high-frequency coupling effect of the semiconductor devices in the semiconductor structure.

Means for Solving the Problems

[0004] The present invention provides a semiconductor structure comprising a substrate, an insulating material, a conductive layer, and a semiconductor element. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface to the second surface, and through holes penetrating the substrate. The insulating material fills at least one insulating vacancy. The conductive layer fills the through holes. The semiconductor element is electrically connected to the conductive layer, and the insulating vacancies are distributed corresponding to the semiconductor element. In one embodiment of the present invention, the semiconductor element includes a transistor, the source of the transistor is grounded via the conductive layer, and the insulating vacancies are located beneath the channel layer of the transistor to reduce the high-frequency coupling effect of the channel layer. In one embodiment of the present invention, the source is in contact with the upper surface of the conductive layer via the bottom surface of a contact plug, and the area of ​​the upper surface of the conductive layer is greater than or equal to the area of ​​the bottom surface of the contact plug. In one embodiment of the present invention, the source is electrically connected to the conductive layer via a contact plug, and the bottom surface of the contact plug is in contact with the upper surface of the conductive layer. In one embodiment of the present invention, the insulating vacancies extend from the first surface to the second surface and penetrate the substrate. In one embodiment of the present invention, the width of the through-hole is less than or equal to the width of the insulating void. In one embodiment of the present invention, the width of the through-hole is greater than the width of the insulating void, and the depth of the insulating void is less than the thickness of the substrate. In one embodiment of the present invention, the semiconductor structure further includes a liner layer, the liner layer is disposed at least between the substrate and the conductive layer. In one embodiment of the present invention, the semiconductor structure further includes a support substrate, the conductive layer is bonded to the support substrate. In one embodiment of the present invention, the insulating material includes a thermally conductive dielectric material. In one embodiment of the present invention, at least one insulating void includes a microfluidic channel, and the insulating material includes a cooling fluid disposed within the microfluidic channel and a sealant that seals the cooling fluid within the microfluidic channel.

[0005] The present invention provides a semiconductor structure comprising a substrate, a first conductive layer, a second conductive layer, and a semiconductor element. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface to the second surface, and through holes penetrating the substrate. The first conductive layer fills at least one insulating vacancy. The second conductive layer fills the through holes, and the first and second conductive layers are electrically insulated from each other. The semiconductor element is placed on the second surface, the semiconductor element is electrically connected to the second conductive layer, and at least one insulating vacancy is distributed corresponding to the semiconductor element. In one embodiment of the present invention, the semiconductor element includes a transistor, the source of the transistor is grounded via the second conductive layer, the first conductive layer is electrically connected to a bias voltage different from the gate voltage to increase the breakdown voltage of the transistor, and at least one insulating vacancy is located beneath the channel layer of the transistor to reduce the high-frequency coupling effect of the channel layer. In one embodiment of the present invention, the first conductive layer and the second conductive layer are made of the same material.

[0006] The present invention provides a semiconductor structure comprising a substrate, a conductive layer, and a semiconductor element. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface to the second surface, and through holes penetrating the substrate. The conductive layer fills the through holes. The semiconductor element is placed on the second surface, the semiconductor element is electrically connected to the conductive layer, at least one insulating vacancy is distributed corresponding to the semiconductor element, the semiconductor element includes a semiconductor layer, and the semiconductor layer has doped regions distributed corresponding to at least one insulating vacancy. In one embodiment of the present invention, the semiconductor layer includes a buffer compound semiconductor layer and a channel layer located on the buffer compound semiconductor layer, and the doped regions are distributed within the buffer compound semiconductor layer. In one embodiment of the present invention, the doped regions include positive ion doped regions. In one embodiment of the present invention, the doped regions include negative ion doped regions. In one embodiment of the present invention, the semiconductor structure further includes a liner layer, the liner layer is located at least between the substrate and the conductive layer.

[0007] The present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: A substrate is provided, including a first surface and a second surface opposite to the first surface. A semiconductor element is formed on the second surface of the substrate. At least one insulating vacancy and a through-hole extending through the substrate are formed in the substrate, the insulating vacancy extending from the first surface to the second surface. An insulating material or a first conductive layer is formed in the insulating vacancy, or doped regions are formed in the semiconductor element via the insulating vacancy. A second conductive layer is formed in the through-hole, the semiconductor element is electrically connected to the second conductive layer, and the insulating vacancy is distributed corresponding to the semiconductor element. [Effects of the Invention]

[0008] Based on the above, in embodiments of the present invention, the high-frequency coupling effect of a semiconductor element can be effectively reduced through insulating vacancies formed on the substrate, thereby improving the performance of the semiconductor element. Furthermore, in embodiments of the present invention, the performance of the semiconductor element can be improved without significantly increasing process costs by manufacturing insulating vacancies and through-holes in the same process. In some embodiments, insulating material placed in the insulating vacancies contributes to improving the heat dissipation performance of the semiconductor element. In some embodiments, conductive layers placed in the insulating vacancies contribute to increasing the breakdown voltage of the semiconductor element. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic cross-sectional view of semiconductor structure manufacturing according to an embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view of semiconductor structure manufacturing according to an embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view of semiconductor structure manufacturing according to an embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view of semiconductor structure manufacturing according to an embodiment of the present invention. [Figure 5] This is a schematic cross-sectional view of semiconductor structure manufacturing according to an embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view of semiconductor structure manufacturing according to an embodiment of the present invention. [Figure 7] These are schematic cross-sectional and schematic perspective views of a semiconductor structure according to an embodiment of the present invention. [Figure 8] These are schematic cross-sectional and schematic perspective views of a semiconductor structure according to an embodiment of the present invention. [Figure 9] This is a schematic cross-sectional view of a liner layer, a conductive layer, and a contact plug in a semiconductor structure. [Figure 10] This is a schematic cross-sectional view of a liner layer, a conductive layer, and a contact plug in a semiconductor structure. [Figure 11] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 12] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 13] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 14] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 15] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 16] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 17] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 18] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 19] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 20] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 21] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Figure 22] This is a schematic cross-sectional view of a semiconductor structure according to a different embodiment of the present invention. [Modes for carrying out the invention]

[0010] Figures 1 to 6 are schematic cross-sectional views of semiconductor structure manufacturing according to embodiments of the present invention, and Figures 7 and 8 are schematic cross-sectional and perspective views of a semiconductor structure according to embodiments of the present invention.

[0011] Referring to Figure 1, a substrate 100 is provided. The substrate 100 has a first surface 100A and a second surface 100B (e.g., the upper surface) opposite to the first surface 100A (e.g., the bottom surface). In some embodiments, the material of the substrate 100 includes silicon or other suitable semiconductor materials. A semiconductor element 102 is formed on the second surface 100B of the substrate 100. Next, a bonding dielectric layer 104 is formed on the second surface 100B of the substrate 100 so as to cover the semiconductor element 102. A carrier substrate 106 is provided, and the substrate 100 on which the semiconductor element 102 and the bonding dielectric layer 104 are formed is bonded to the carrier substrate 106, and the semiconductor element 102 and the bonding dielectric layer 104 are disposed between the substrate 100 and the carrier substrate 106. In some embodiments, the material of the bonding dielectric layer 104 includes silicon oxide or other suitable dielectric materials. In this embodiment, the bonding dielectric layer 104 formed on the substrate 100 is directly bonded to the carrier substrate 106, and the semiconductor element 102 and the bonding dielectric layer 104 are disposed between the substrate 100 and the carrier substrate 106. In some embodiments, the material of the carrier substrate 106 includes silicon, glass, or other suitable semiconductor materials.

[0012] In this embodiment, the semiconductor element 102 includes a transistor. The transistor includes a gate 102G, a gate insulating layer 102GI, a source 102S, a drain 102D, and a channel layer 102C. The gate 102G, the source 102S, and the drain 102D are disposed on the channel layer 102C. The gate 102G and the channel layer 102C are separated by the gate insulating layer 102GI. The source 102S and the drain 102D are disposed on both sides of the gate 102G. Ohmic contacts are formed between the source 102S and the channel layer 102C and between the drain 102D and the channel layer 102C, respectively. In other embodiments, the gate insulating layer 102GI may not be included in the transistor. That is, the gate insulating layer 102GI is an arbitrary component in the transistor. In some embodiments, the transistor is formed on a substrate 100 provided with a buffer compound semiconductor layer 110, and the buffer compound semiconductor layer 110 is formed on the second surface 100B of the substrate 100. In some embodiments, the transistor further includes at least one protective layer 112, and the protective layer 112 covers the gate 102G, the source 102S, and the drain 102D. In some embodiments, the semiconductor element 102 includes a high electron mobility transistor (HEMT). The material of the channel layer 102C of the high electron mobility transistor includes GaN, AlGaN, InGaN, or other suitable semiconductor materials. The material of the buffer compound semiconductor layer 110 includes GaN, AlGaN, InGaN, or other suitable semiconductor materials. The material of the channel layer 102C and the material of the buffer compound semiconductor layer 110 may be the same or different.

[0013] In some embodiments, the transistor may further include a gate contact conductor 102GC, a source contact conductor 102SC, and a drain contact conductor 102DC. The gate contact conductor 102GC is located on the gate 102G and electrically connected to the gate 102G; the source contact conductor 102SC is located on the source 102S and electrically connected to the source 102S; and the drain contact conductor 102DC is located on the drain 102D and electrically connected to the drain 102D. Furthermore, the transistor may further include a contact plug CP. The source contact conductor 102SC extends laterally from the source 102S to the contact plug CP, which penetrates the protective layer 112, the gate insulating layer 102GI, and the buffer compound semiconductor layer 110 to contact the second surface 100B of the substrate 100. In other words, the source 102S is electrically connected to the contact plug CP via the source contact conductor 102SC.

[0014] Referring to Figure 2, the structure of Figure 1 is inverted so that the first surface 100A of the substrate 100 faces upward. Next, a thinning process is performed to reduce the thickness of the substrate 100. In this embodiment, the thinning process of the substrate 100 is performed on the first surface 100A of the substrate 100 such that the distance between the first surface 100A and the second surface 100B of the substrate 100 is reduced. In some embodiments, the thinning process of the substrate 100 includes chemical mechanical polishing (CMP), mechanical grinding, or a combination of the aforementioned processes. In this embodiment, the thickness of the substrate 100 after thinning is between 20 microns and 200 microns.

[0015] Referring to Figure 3, after thinning the substrate 100, a patterning process is performed to pattern the substrate 100. In this embodiment, the patterning process of the substrate 100 is performed on the thinned first surface 100A' of the substrate 100, simultaneously forming at least one insulating void C and a through hole TH within the substrate 100. The insulating void C extends from the first surface 100A' to the second surface 100B and penetrates the substrate 100, and the through hole TH extends from the first surface 100A' to the second surface 100B and penetrates the substrate 100. That is, the depth of the insulating void C and the depth of the through hole TH are substantially the same as the thickness of the thinned substrate 100. In this embodiment, the width of the through hole TH may be greater than or substantially equal to the width of the insulating void C.

[0016] As shown in Figure 3, the through-hole TH exposes the bottom surface of the contact plug CP and a portion of the bottom surface of the buffer compound semiconductor layer 110. The insulating vacancies C also expose a portion of the bottom surface of the buffer compound semiconductor layer 110 and are distributed beneath the semiconductor element 102. In this embodiment, the insulating vacancies C are located beneath the transistor gate 102G and the channel layer 102C, reducing the high-frequency coupling effect of the channel layer 102C.

[0017] Referring to Figure 4, the liner layer 114 is formed on the substrate 100. The liner layer 114 is distributed on the first surface 100A' of the substrate 100 and on the sidewalls used to define the insulating vacancies C and through-holes TH, but the liner layer 114 does not cover the bottom surface of the contact plug CP. For example, a dielectric material can be formed on the substrate 100 by atomic layer deposition (ALD), chemical vapor deposition, physical vapor deposition, etc. Next, the dielectric material in contact with the bottom surface of the contact plug CP is removed by etching to form the liner layer 114. In some embodiments, the liner layer 114 is in contact with a buffer compound semiconductor layer 110 exposed by the insulating vacancies C and through-holes TH. Furthermore, the material of the liner layer 114 includes silicon oxide or other suitable dielectric material.

[0018] Referring to Figure 5, a seed layer 116 is formed on the substrate 100. The seed layer 116 covers the liner layer 114. Since the liner layer 114 does not cover the bottom surface of the contact plug CP, the seed layer 116 is in contact with the bottom surface of the contact plug CP that is not covered by the liner layer 114. In some embodiments, the seed layer 116 is in contact with a buffer compound semiconductor layer 110 that is not covered by the liner layer 114. The seed layer 116 may be completely deposited on the liner layer 114 and the contact plug CP that is not covered by the liner layer 114, as well as on the bottom surface of the insulating vacancies C, via a sputtering process. Furthermore, the seed layer 116 may function as an electroplating seed layer required for subsequent electroplating processes and provide a barrier layer effect.

[0019] Next, a mask layer 118 is formed on the first surface 100A' of the substrate 100, covering the insulating vacancies C and the seed layer 116 located near the insulating vacancies C. In this embodiment, as shown in Figure 5, the mask layer 118 includes a patterned dry film having a specific pattern. Once the patterned dry film is attached to the seed layer 116, the patterned dry film can cover the insulating vacancies C, but does not fill them. In some other viable embodiments not shown, the mask layer 118 includes a patterned photoresist layer formed by a spin-coating process. Once the patterned photoresist layer is formed on the seed layer 116, the patterned photoresist layer can cover and fill the insulating vacancies C.

[0020] Referring to Figures 5 and 6, an electroplating process is performed to form a conductive layer 120 on the seed layer 116 that is not covered by the mask layer 118, so that the conductive layer 120 can fill the through holes TH. In this embodiment, the through holes TH are partially filled by the conductive layer 120. In other embodiments not shown, the through holes TH may be completely filled by the conductive layer 120. After the conductive layer 120 is formed, the mask layer 118 is removed to expose the portion of the seed layer 116 that is not covered by the conductive layer 120. The seed layer 116 that is not covered by the conductive layer 120 is then removed until a portion of the liner layer 114 is exposed. As shown in Figure 6, the liner layer 114 is positioned at least between the substrate 100 and the conductive layer 120. That is, the substrate 100 may be separated from the conductive layer 120 by the liner layer 114.

[0021] Source 102S is grounded via source contact conductor 102SC, conductive plug CP, and conductive layer 120. Compared to wire bonding, the wiring distance required to ground source 102S is reduced, thereby mitigating related problems such as parasitic inductance. The insulating vacancy C located beneath the transistor's channel layer 102C can reduce the high-frequency coupling effect of the channel layer 102C.

[0022] Referring to Figures 7 and 8, after the conductive layer 120 is formed, a support substrate 122 is provided and the conductive layer 120 formed on the substrate 100 is bonded to the support substrate 122. In this embodiment, the material of the support substrate 122 includes silicon, an organic carrier substrate, or other suitable semiconductor or encapsulating material. Next, the carrier substrate 106 is separated from the junction dielectric layer 104 and peeled off the carrier substrate 106 from the junction dielectric layer 104. As shown in Figure 8, insulating vacancies C placed between the support substrate 122 and the semiconductor element 102 can selectively pass a heat dissipation fluid 124 (e.g., cooling water or other cooling fluid with excellent heat dissipation properties) through, improving the overall heat dissipation performance of the semiconductor structure.

[0023] Figures 9 and 10 are schematic cross-sectional views of the liner layer, conductive layer, and contact plug in a semiconductor structure, respectively.

[0024] Referring to Figure 9, the liner layer 114 includes a first portion 114a covering the sidewall of the substrate 100 and a second portion 114b covering the first surface 100A' of the substrate 100. The first portion 114a is located within the through-hole TH, and the thickness L of the first portion 114a may be substantially equal to the thickness T of the second portion 114b. In this embodiment, the bottom surface of the contact plug CP is in contact with the top surface of the conductive layer 120, the size of the through-hole TH is larger than the size of the bottom surface of the contact plug CP, and the minimum size difference may be substantially equal to the thickness T of the second portion 114b. The area of ​​the top surface of the conductive layer 120 is substantially equal to the area of ​​the bottom surface of the contact plug CP. In this case, the liner layer 114 is in contact with the bottom surface of the contact plug CP, and the substrate 100 is not in contact with the contact plug CP. In some other embodiments, the area of ​​the top surface of the conductive layer 120 is larger than the area of ​​the bottom surface of the contact plug CP. In this case, the liner layer 114 is not in contact with the bottom surface of the contact plug CP.

[0025] Referring to Figure 10, the liner layer 114 includes a first portion 114a covering the sidewall of the substrate 100 and a second portion 114b covering the first surface 100A of the substrate 100. The first portion 114a is located within the through hole TH, and the thickness L of the first portion 114a is less than the thickness T of the second portion 114b, with the thickness L of the first portion 114a being approximately 5% of the thickness T of the second portion 114b. In this embodiment, the bottom surface of the contact plug CP is in contact with the top surface of the conductive layer 120, and the size of the through hole TH is greater than the size of the bottom surface of the contact plug CP. The minimum size difference may be equal to the thickness T of the second portion 114b. The area of ​​the top surface of the conductive layer 120 is substantially equal to the area of ​​the bottom surface of the contact plug CP. In this case, the liner layer 114 is in contact with the bottom surface of the contact plug CP, and the substrate 100 is not in contact with the contact plug CP. In some other embodiments, the area of ​​the top surface of the conductive layer 120 is greater than the area of ​​the bottom surface of the contact plug CP. In this case, the liner layer 114 does not come into contact with the bottom surface of the contact plug CP.

[0026] Figures 11 to 22 are schematic cross-sectional views of semiconductor structures according to different embodiments of the present invention.

[0027] Referring to Figures 7 and 11, the semiconductor structure shown in Figure 11 is similar to the semiconductor structure shown in Figure 7, but the difference is that the insulating vacancies C shown in Figure 11 are wider, so the width of the through-holes TH in the semiconductor structure is smaller than the width of the insulating vacancies C. In this embodiment, the insulating vacancies C are located beneath the gate 102G and channel layer 102C of the transistor to reduce the high-frequency coupling effect of the channel layer 102C.

[0028] Referring to Figures 7 and 12, the semiconductor structure shown in Figure 12 is similar to the semiconductor structure shown in Figure 7, but the difference is that the depth of the insulating vacancies C shown in Figure 12 is smaller than the thickness of the substrate 100. In other words, the insulating vacancies C extend from the first surface 100A' to the second surface 100B of the substrate 100, but the insulating vacancies C do not penetrate the substrate.

[0029] Referring to Figure 13, the semiconductor element 102 includes a shared drain 102D and multiple sources 102S. In some embodiments, the semiconductor element 102 employs a finger-like design for the drain 102D and sources 102S. There are multiple through-holes TH in the substrate 100, and multiple conductive layers 120 located within the through-holes TH are electrically connected to the corresponding sources 102S. In this embodiment, insulating vacancies C are located beneath the transistor gate 102G, drain 102D, source 102S, and channel layer 102C to reduce the high-frequency coupling effect of the channel layer 102C.

[0030] Referring to Figures 11 and 14, the semiconductor structure shown in Figure 14 is similar to the semiconductor structure shown in Figure 11, the difference being that the semiconductor structure shown in Figure 14 further includes a dielectric layer 126, which covers the conductive layer, the liner layer not covered by the conductive layer, and a portion of the semiconductor device region exposed by insulating vacancies. The dielectric layer 126 may be an organic adhesive material such as polyimide, benzocyclobutene (BCB), or other suitable dielectric layer material.

[0031] Referring to Figures 15 to 18, the semiconductor structures shown in Figures 15 to 18 are similar to the semiconductor structures shown in Figures 11 to 14. The difference is that the semiconductor structures in Figures 15 to 18 do not include the support substrate 122 bonded to the conductive layer 120.

[0032] Referring to Figure 19, the semiconductor structure of this embodiment includes a substrate 100. The substrate 100 has a first surface 100A and a second surface 100B (e.g., top surface) opposite to the first surface 100B (e.g., bottom surface). In some embodiments, the material of the substrate 100 includes silicon or other suitable semiconductor material. A semiconductor element 102 is formed on the second surface 100B of the substrate 100, and a junction dielectric layer 104 is formed on the second surface 100B of the substrate 100 so as to cover the semiconductor element 102. In this embodiment, the semiconductor element 102 includes a transistor. The transistor includes a gate 102G, a gate insulating layer 102GI, a source 102S, a drain 102D, and a channel layer 102C. The gate 102G, source 102S, and drain 102D are located on the channel 102C, and the gate 102G and the channel layer 102C are separated by the gate insulating layer 102GI. The source 102S and drain 102D are located on either side of the gate 102G, respectively, and ohmic contacts are formed between the source 102S and the channel layer 102C, and between the drain 102D and the channel layer 102C. In other embodiments, the gate insulating layer 102GI may not be included in the transistor. That is, the gate insulating layer 102GI in the transistor is an optional component. In some embodiments, the transistor is formed on a substrate 100 having a buffer compound semiconductor layer 110, the buffer compound semiconductor layer 110 being formed on a second surface 100B of the substrate 100. In some embodiments, the transistor further includes at least one protective layer 112, the protective layer 112 covering the gate 102G, source 102S, and drain 102. In some embodiments, the semiconductor element 102 includes a high electron mobility transistor (HEMT), the material of the channel layer 102C of the HEMT includes GaN, AlGaN, InGaN, or other suitable semiconductor material, and the material of the buffer compound semiconductor layer 110 includes GaN, AlGaN, InGaN, or other suitable semiconductor material, and the materials of the channel layer 102C and the buffer compound semiconductor layer 110 may be the same or different. In some embodiments, the material of the junction dielectric layer 104 includes silicon oxide or other suitable dielectric material.

[0033] In some embodiments, the transistor may further include a gate contact conductor 102GC, a source contact conductor 102SC, and a drain contact conductor 102DC. The gate contact conductor 102GC is located on the gate 102G and is electrically connected to the gate 102G. The source contact conductor 102SC is located on the source 102S and is electrically connected to the source 102S. Meanwhile, the drain contact conductor 102DC is located on the drain 102D and is electrically connected to the drain 102D. Furthermore, the transistor may further include a contact plug CP. The source contact conductor 102SC extends laterally from the source 102S to the contact plug CP, and the contact plug CP penetrates the protective layer 112, the gate insulating layer 102GI, and the buffer compound semiconductor layer 110 to further contact the second surface 100B of the substrate 100. In other words, the source 102S is electrically connected to the contact plug CP via the source contact conductor 102SC.

[0034] As shown in Figure 19, the semiconductor structure of this embodiment further includes an insulating material that fills the insulating vacancies C, the insulating material including a thermally conductive dielectric material 128 to enhance the heat dissipation effect of the semiconductor structure. In this embodiment, the thermally conductive dielectric material 128 is made of a material having high thermal conductivity and low electrical conductivity, such as diamond-like carbon (DLC), diamond, aluminum nitride (AlN), or hexagonal boron nitride (h-BN). As shown in Figure 19, the thermally conductive dielectric material 128 may completely fill the insulating vacancies C. In other possible embodiments, the thermally conductive dielectric material 128 may partially fill the insulating vacancies C.

[0035] In some other embodiments, the thermally conductive dielectric material 128 may fill other types of insulating vacancies C, such as insulating vacancies C penetrating the substrate 100 as shown in Figure 11.

[0036] Refer to Figures 13 and 20. The semiconductor structure shown in Figure 20 is similar to the semiconductor structure shown in Figure 13. The difference between the two is that the semiconductor structure in Figure 20 further includes a conductive layer 130, a portion of which is located within the insulating vacancies C, and the remaining portion of which is located outside the insulating vacancies C. In this embodiment, the conductive layer 130 is electrically connected to the bias voltage, which differs from the gate voltage and increases the breakdown voltage of the transistor. As shown in Figure 20, the conductive layer 130 may have the same film structure as the conductive layer 120, and the conductive layer 130 and the conductive layer 120 are electrically insulated from each other. For example, the material of the conductive layer 130 may be the same as or different from the material of the conductive layer 120, and the film structure of the conductive layer 130 may be the same as or different from the film structure of the conductive layer 120.

[0037] Refer to Figures 13 and 21. The semiconductor structure shown in Figure 21 is similar to the semiconductor structure shown in Figure 13. The difference between the two is that the insulating vacancies C in the substrate 100 in Figure 21 are in the shape of microfluidic channels. The semiconductor structure further includes an insulating material, which includes a cooling fluid 132 placed within the microfluidic channels and a sealant 134 that seals the cooling fluid 132 within the microfluidic channels. The microfluidic channels are located beneath the gate 102G and the gate contact conductor 102GC, thereby improving the heat dissipation effect in the area where the gate 102G and the gate contact conductor 102GC are located via the cooling fluid 132. For example, the cooling fluid 132 includes water or another fluid medium having heat dissipation properties, and the sealant 134 includes polyimide or another suitable sealing material.

[0038] Refer to Figures 13 and 22. The semiconductor structure shown in Figure 22 is similar to the semiconductor structure shown in Figure 13. The difference between the two is that the buffer compound semiconductor layer 110 in Figure 22 has doped regions 138 formed by the ion implantation process 136, and the doped regions 138 are distributed corresponding to insulating vacancies C. In the ion implantation process 136, the liner layer 114 can be used as a mask, so the doped regions 138 in the buffer compound semiconductor layer 110 are distributed only under the gate 102G and the gate contact conductor 102GC. In some embodiments, the ion implantation process 136 is a negative ion implantation process, and the doped regions 138 are negative ion doped regions for shifting the Fermi level upward to achieve operation in enhancement mode. In some other embodiments, the ion implantation step 136 is a positive ion implantation step, and the doped region 138 is a positive ion doped region to achieve the objective of shifting the Fermi level downward to increase the 2DEG concentration and reduce the channel resistance.

[0039] In summary, the above embodiment of the present invention makes it possible to shorten the wiring distance of the source ground without significantly increasing process costs, thereby reducing parasitic inductance and other related problems, and effectively reducing the high-frequency coupling effect of the channel layer. [Industrial applicability]

[0040] The semiconductor structure and manufacturing process of the present invention can be applied to semiconductor devices and methods for manufacturing semiconductor devices. [Explanation of Symbols]

[0041] 100: Circuit board 100A, 100A': First surface 100B: Second surface 102: Semiconductor devices 102G: Gate 102GC: Gate contact conductor 102GI: Gate Insulation Layer 102S: Source 102SC: Source contact conductor 102D: Drain 102DC: Drain contact conductor 102C: Channel layer 104: Junction dielectric layer 106: Carrier substrate 110: Buffer compound semiconductor layer 112: Protective layer 114: Liner layer 114a: Part 1 114b: Part 2 116: Seed layer 118: Mask layer 120: Conductive layer 122: Support substrate 124: Heat radiation fluid 126: Dielectric layer 128: Thermally conductive dielectric materials 130: Conductive layer 132: Cooling fluid 134: Sealant 136: Ion implantation process 138: Doping Area C: Insulating void CP: Contact Plug L, T: Thickness TH: Through hole

Claims

1. A substrate having a first surface, a second surface opposite to the first surface, at least one insulating void extending from the first surface to the second surface, and through holes penetrating the substrate, An insulating material to be filled into the insulating cavity, A conductive layer is filled into the through hole, The semiconductor element is disposed on the second surface, The semiconductor element is electrically connected to the conductive layer, and the insulating vacancies are distributed corresponding to the semiconductor element. Semiconductor structure.

2. The semiconductor device includes a transistor, The source of the transistor is grounded via the conductive layer. The insulating vacancies are located beneath the channel layer of the transistor to reduce the high-frequency coupling effect of the channel layer. The semiconductor structure according to claim 1.

3. The source contacts the upper surface of the conductive layer via the bottom surface of the contact plug. The area of ​​the upper surface of the conductive layer is greater than or equal to the area of ​​the bottom surface of the contact plug. The semiconductor structure according to claim 1.

4. The source is electrically connected to the conductive layer via a contact plug. The bottom surface of the contact plug is in contact with the upper surface of the conductive layer. The semiconductor structure according to claim 1.

5. The insulating void extends from the first surface to the second surface and penetrates the substrate. The semiconductor structure according to claim 1.

6. The width of the through-hole is less than or equal to the width of the insulating void. The semiconductor structure according to claim 5.

7. The width of the through-hole is greater than the width of the insulating void, and the depth of the insulating void is less than the thickness of the substrate. The semiconductor structure according to claim 1.

8. It further includes a liner layer, The liner layer is disposed at least between the substrate and the conductive layer. The semiconductor structure according to claim 1.

9. Further including a support substrate, The conductive layer is bonded to the support substrate. The semiconductor structure according to claim 1.

10. The insulating material includes a thermally conductive dielectric material. The semiconductor structure according to claim 1.

11. The insulating vacancy includes a microfluidic channel. The insulating material includes a cooling fluid disposed within the microfluidic channel and a sealant that seals the cooling fluid within the microfluidic channel. The semiconductor structure according to claim 1.

12. A substrate having a first surface, a second surface opposite to the first surface, at least one insulating void extending from the first surface to the second surface, and through holes penetrating the substrate, A first conductive layer is filled into the insulating void, A second conductive layer to be filled in the through hole, wherein the first conductive layer and the second conductive layer are electrically insulated from each other, A semiconductor element disposed on the second surface, wherein the semiconductor element is electrically connected to the second conductive layer, and the insulating vacancies are distributed corresponding to the semiconductor element, A semiconductor structure comprising the features described above.

13. The semiconductor device includes a transistor, The source of the transistor is grounded via the second conductive layer. The first conductive layer is electrically connected to a bias voltage different from the gate voltage, thereby increasing the breakdown voltage of the transistor. The insulating vacancies are located beneath the channel layer of the transistor to reduce the high-frequency coupling effect of the channel layer. The semiconductor structure according to claim 12.

14. The first conductive layer and the second conductive layer are made of the same material. The semiconductor structure according to claim 12.

15. A substrate having a first surface, a second surface opposite to the first surface, at least one insulating void extending from the first surface to the second surface, and through holes penetrating the substrate, A conductive layer is filled into the through hole, The semiconductor element is disposed on the second surface and electrically connected to the conductive layer, The insulating vacancies are distributed in accordance with the semiconductor element, the semiconductor element includes a semiconductor layer, and the semiconductor layer has doped regions distributed in accordance with at least one insulating vacancy. Semiconductor structure.

16. The semiconductor layer includes a buffer compound semiconductor layer and a channel layer located on the buffer compound semiconductor layer. The doped region is distributed within the buffer compound semiconductor layer. The semiconductor structure according to claim 15.

17. The doped region includes a positive ion doped region. The semiconductor structure according to claim 15.

18. The doped region includes a negative ion doped region. The semiconductor structure according to claim 15.

19. The material further includes a liner layer, the liner layer being located at least between the substrate and the conductive layer. The semiconductor structure according to claim 15.

20. To provide a substrate including a first surface and a second surface opposite to the first surface, Forming a semiconductor element on the second surface of the substrate, To form at least one insulating void and a through-hole penetrating the substrate in the substrate, Forming an insulating material or a first conductive layer in the insulating vacancy, or forming a doped region in the semiconductor element via the insulating vacancy, The method comprises forming a second conductive layer within the through-hole, The insulating void extends from the first surface to the second surface, The semiconductor element is electrically connected to the second conductive layer, and the insulating vacancies are distributed corresponding to the semiconductor element. A method for manufacturing semiconductor structures.

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