Memory system

Abstract

One embodiment aims to provide a memory system that can perform garbage collection efficiently. [Solution] According to one embodiment, a memory system having non-volatile memory and a controller is provided. The controller can manage the non-volatile memory in multiple management units with respect to garbage collection. The controller determines which of the multiple management units will be the destination for data to be moved by garbage collection, according to the usage rate of each of the multiple management units.

Description

Technical Field

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[0001] <000Q004>This embodiment relates to a memory system.

Background Art

[0002] A memory system having a non-volatile memory may manage the non-volatile memory in a plurality of management units. As data writing to the non-volatile memory progresses, management units including areas that are made inefficient by invalid data are generated. Therefore, garbage collection is performed, in which valid data is collected from the inefficient management units and rewritten to another management unit, and the inefficient areas in the original management unit are erased to make free areas. Garbage collection is desired to be performed efficiently.

Prior Art Documents

Patent Documents

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a memory system capable of efficiently performing garbage collection.

Means for Solving the Problems

[0005] According to one embodiment, a memory system is provided having non-volatile memory and a controller. The controller can manage the non-volatile memory in multiple management units with respect to garbage collection. The controller determines which of the multiple management units will be the destination for data to be moved by garbage collection, based on the usage rate of each of the multiple management units. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing the configuration of the memory system according to the first embodiment. [Figure 2] A diagram showing the configuration of the controller and non-volatile memory in the first embodiment. [Figure 3] A diagram showing the data structure of the block management table in the first embodiment. [Figure 4] A flowchart illustrating the general operation of the memory system according to the first embodiment. [Figure 5] A flowchart illustrating the garbage collection (GC) target search process for a memory system according to the first embodiment. [Figure 6] A diagram illustrating a use case for the GC target search process of a memory system according to the first embodiment. [Figure 7] A diagram illustrating a use case for the GC target search process of a memory system according to the first embodiment. [Figure 8] A diagram showing the configuration of the controller and non-volatile memory in the second embodiment. [Figure 9] A diagram showing the block management table in the second embodiment. [Figure 10] A diagram illustrating a use case for the GC target search process of a memory system according to the second embodiment. [Figure 11] A diagram illustrating a use case for the GC target search process of a memory system according to the second embodiment. [Figure 12] A diagram showing the configuration of the controller and non-volatile memory in the third embodiment. [Figure 13]A diagram showing the block management table in the third embodiment. [Figure 14] A diagram illustrating a use case for the GC target search process of a memory system according to the third embodiment. [Figure 15] A diagram illustrating a use case for the GC target search process of a memory system according to the third embodiment. [Modes for carrying out the invention]

[0007] The memory system according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0008] (First Embodiment) The memory system according to the first embodiment has non-volatile memory including multiple management units. Garbage collection is performed by collecting valid data from a management unit that includes an area that has become inefficient due to the writing of a lot of invalid data and rewriting it to another management unit, thereby erasing the inefficient area in the original management unit and creating a free area. The data movement by garbage collection described later refers to, for example, copying valid data contained in the source block to another block and erasing the data contained in the source block.

[0009] In the first embodiment, the memory system, which erases the data that was copied from it, is equipped with features to efficiently perform garbage collection.

[0010] The memory system 1 can be configured as shown in Figure 1. Figure 1 is a diagram showing the configuration of the memory system 1.

[0011] The memory system 1 can be connected to the host 100 via the host channel HCH and can function as a storage medium for the host 100. The memory system 1 is, for example, an SSD (Solid State Drive), eMMC, or memory card. The host 100 may be a terminal such as a personal computer or the CPU of a terminal. The host channel HCH may be a wired communication path.

[0012] The memory system 1 includes a controller 2, a non-volatile memory 3, and a buffer memory 4. The controller 2 can be connected to the host 100 via the HCH (host channel). The controller 2 is connected to the non-volatile memory 3 via channel 1 (CH1). Channel CH1 includes a plurality of signal lines. The controller 2 is connected to the buffer memory through channel 2 (CH2). Channel CH2 includes one or more signal lines.

[0013] The controller 2 comprehensively controls each part of the memory system 1. The controller 2 can be implemented as a controller package including, for example, a SoC (System-on-a-Chip). The controller 2 has a host interface (host IF) 21, a processor 22, a buffer memory 23, a buffer interface (buffer IF) 25, and a memory interface (memory IF) 26.

[0014] The host interface 21 can be connected to the host 100 via the host channel HCH. The host interface 21 receives command / data from the host 100 and transmits response / data to the host 100.

[0015] The processor 22 comprehensively controls each part of the controller 2. The processor 22 may be implemented as a CPU (Central Processing Unit) or the like. The processor 22 controls the write process, which writes data to the non-volatile memory 3 in response to write commands received at the host interface 21. The processor 22 controls the read process, which reads data from the non-volatile memory 3 in response to read commands received at the host interface 21. The processor 22 controls the erase process, which deletes data from the non-volatile memory 3.

[0016] The buffer memory 23 is a volatile memory such as SRAM (Static Random Access Memory), and can be used as a work area by the controller 2. The buffer memory 23 temporarily stores data related to write and read operations, data for internal processes such as garbage collection, and management information such as logical-physical address translation information, which will be described later.

[0017] The buffer interface 25 performs interface operations with respect to the buffer memory 4 under the control of the processor 22. The buffer interface 25 can transfer data related to write and read operations, data from internal processes such as garbage collection, and management information such as logical-physical address translation information to and from the buffer memory 4.

[0018] Buffer memory 4 is a volatile memory such as DRAM (Dynamic Random Access Memory) and can be used as a work area by controller 2. Buffer memory 4 temporarily stores data related to write and read operations, data for internal processes such as garbage collection, and management information such as logical-physical address translation information.

[0019] The memory interface 26 performs interface operations with respect to the non-volatile memory 3 under the control of the processor 22. The memory interface 26 can transfer data related to write and read operations, data from internal processes such as garbage collection, and management information such as logical-physical address translation information to and from the non-volatile memory 3.

[0020] The non-volatile memory 3 may be, for example, NAND flash memory, ReRAM (Resistance Random Access Memory), PRAM (Phase change RAM), MRAM (Magnetoresistive Random Access Memory), or FeRAM (Ferroelectric Random Access Memory). The following explanation will focus on the case where the non-volatile memory 3 is NAND flash memory.

[0021] The non-volatile memory 3 is allocated multiple media blocks by the controller 2. Some of the media blocks are allocated to the management information storage area 31, and the remaining (most) media blocks are allocated to the storage area 32. Each media block contains multiple media pages. The storage area 32 is where data requested to be written from the host 100 is stored, and the management information storage area 31 is where management information from the controller 2 is stored.

[0022] The non-volatile memory 3 includes multiple memory chips 5_0 to 5_7, as shown in Figure 2. Figure 2 shows the configuration of the controller 2 and the non-volatile memory 3. Note that the number of memory chips 5 included in the non-volatile memory 3 is not limited to the 8 shown in Figure 2, but may be 7 or less, or 9 or more.

[0023] Controller 2 is connected to multiple memory chips 5_0 to 5_7 via channel CH1.

[0024] Within each memory chip 5, a physical page is a unit that allows for simultaneous write / read access of data. Multiple physical pages, which allow for parallel, nearly simultaneous write / read access, may constitute a single media page that serves as the data recording area.

[0025] A physical block is the smallest access unit composed of multiple physical pages, where data can be erased independently. A single media block, which is a data block, may be composed of multiple physical blocks that can be erased in parallel and almost simultaneously.

[0026] Each physical block has multiple memory cells. Each memory cell is capable of multi-level storage. If each memory cell in a group of memory cells connected to the same word line in each physical block can store n bits of information, that group of memory cells is treated as n physical pages.

[0027] For example, when a memory cell is used in SLC mode (n=1), the threshold voltage distribution of the memory cell contains two states (small regions) ST0 to ST1 within the range where the threshold voltage is controlled.

[0028] When the memory cell is used in MLC mode (n=2), the threshold voltage distribution of the memory cell contains four states ST0 to ST3 within the range where the threshold voltage is controlled.

[0029] When memory cells are used in TLC mode (n=3), the threshold voltage distribution of the memory cells contains eight states ST0 to ST7 within the range where the threshold voltage is controlled.

[0030] When memory cells are used in QLC mode (n=4), the threshold voltage distribution of the memory cells contains 16 states ST0 to ST15 within the range where the threshold voltage is controlled.

[0031] When the memory cell is used in PLC mode (n=5), the threshold voltage distribution of the memory cell contains 32 states ST0 to ST31 within the range in which the threshold voltage is controlled.

[0032] In the following, we will simply refer to media blocks as "blocks" and media pages as "pages."

[0033] This section explains the management of physical and logical addresses in non-volatile memory 3. A physical address is an address that indicates a storage location within non-volatile memory 3. This storage location is also called a physical storage location. Physical addresses are also called Physical Block Addresses (PBA) or Memory Block Addresses (MBA). Logical-physical address translation information is a table that manages the correspondence between logical addresses and physical addresses. Logical-physical address translation information manages the correspondence between logical addresses and physical addresses on a page-by-page basis, for example.

[0034] Data can only be written to one page of a single memory cell once per program / erase cycle (P / E cycle), and no further writes are permitted until the data is erased. Therefore, controller 2 writes update data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous data corresponding to that logical address is stored. Controller 2 then invalidates the previous data by updating the logical-physical address translation information to associate this logical address with this different physical memory location. Data referenced by the logical-physical address translation information (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address is called invalid data. Valid data is data that may be read by host 100 later. Invalid data is data that can no longer be read by host 100.

[0035] Garbage collection by controller 2 will be described below. When performing garbage collection, controller 2 may manage the non-volatile memory 3 in units of memory chips 5.

[0036] For example, controller 2 may determine a management unit from among multiple management units whose free capacity is less than or equal to the threshold Cth as the source of data to be moved by garbage collection. Free capacity refers to the amount of invalid data within the management unit. For example, controller 2 may determine a management unit from among multiple management units whose number of free blocks is less than or equal to the threshold Nth as the source of data to be moved by garbage collection. A free block is a block in which all the data written to it is invalid data. Controller 2 may also manage the free capacity by converting it to the number of free blocks converted to TLC mode.

[0037] Controller 2 may determine, among multiple management units, that management unit whose used capacity is equal to or greater than the threshold Ctha as the source of data to be moved by garbage collection. Used capacity refers to the amount of valid data within the management unit. For example, Controller 2 may determine, among multiple management units, that management unit whose number of used blocks is equal to or greater than the threshold Ntha as the source of data to be moved by garbage collection. Used blocks are blocks in which the written data contains valid data. Controller 2 may manage used capacity using the number of used blocks converted to TLC mode.

[0038] Controller 2 may determine which of the multiple management units will be the destination for data to be moved by garbage collection, based on the utilization rate of each of the multiple management units. In this embodiment, Controller 2 determines the management unit with the lowest utilization rate among the multiple management units as the destination for data to be moved by garbage collection.

[0039] Controller 2 may manage the number of user-available blocks in each memory chip 5 as the maximum number of user blocks. Controller 2 may also manage the maximum number of user blocks as the number of blocks converted to TLC mode.

[0040] Controller 2 may manage the number of blocks used in each memory chip 5 as the number of blocks used. Controller 2 may also manage the number of blocks used as the number of blocks converted to TLC mode.

[0041] Controller 2 manages the percentage of blocks used in each memory chip 5 as the utilization rate. The utilization rate is calculated using the number of blocks used and the maximum number of user blocks. For example, Controller 2 may calculate the utilization rate by dividing the number of blocks used by the maximum number of user blocks.

[0042] Controller 2 may perform garbage collection using a block management table 33 as shown in Figure 3. The block management table 33 is stored in the management information storage area 31. Figure 3 shows the data structure of the block management table 33.

[0043] The block management table 33 includes a chip identifier column 331, a maximum user block count column 332, and a used block count column 333. In the block management table 33, the identifier, maximum user block count, and used block count of memory chip 5 are associated with multiple memory chips 5_0 to 5_7. The chip identifier column 331 records the identifier of memory chip 5. The maximum user block count column 332 records the maximum number of user blocks for memory chip 5. The used block count column 333 records the number of blocks used by memory chip 5.

[0044] Controller 2 can determine the maximum number of user blocks and the number of blocks used for each memory chip 5 corresponding to an identifier by referring to the block management table 33. Controller 5 can determine the utilization rate of each memory chip 5 by referring to the block management table 33.

[0045] For memory chip 5_0 with chip identifier "0", the maximum number of user blocks is "SN1" and the number of blocks used is "BN1". From this, the utilization rate of memory chip 5_0 can be calculated as (BN1) / (SN1).

[0046] For memory chip 5_1 with chip identifier "1", the maximum number of user blocks is "SN2" and the number of blocks used is "BN2". From this, the utilization rate of memory chip 5_1 can be calculated as (BN2) / (SN2).

[0047] For memory chip 5_7 with chip identifier "7", the maximum number of user blocks is "SN8" and the number of blocks used is "BN8". From this, the utilization rate of memory chip 5_7 can be calculated as (BN8) / (SN8).

[0048] As shown in Figure 1, the block management table 33 is stored in the management information storage area 31 of the non-volatile memory 3. The controller 2 may read the block management table 33 from the management information storage area 31 and store it in the buffer memory 4 when the memory system 1 is started up, etc.

[0049] Controller 2 updates the block management table 33 on the buffer memory 4 at a predetermined timing. This predetermined timing is, for example, the timing when write / erase access to the storage area 32 of the non-volatile memory 3 occurs.

[0050] Controller 2 may write the block management table 33 back from buffer memory 4 to management information storage area 31 at a predetermined timing to make it non-volatile. The predetermined timing may be a periodic timing based on the passage of time, or it may be the timing of the shutdown of memory system 1.

[0051] Next, we will explain the general operation of memory system 1 regarding garbage collection using Figure 4. Figure 4 is a flowchart illustrating the general operation of memory system 1.

[0052] In memory system 1, controller 2 determines whether there is a management unit among multiple management units that has a number of free blocks smaller than the threshold Nth (S1). The threshold Nth is a value determined by considering the margin of free blocks required to prevent data loss in the management unit. The threshold Nth may be determined experimentally in advance before the memory system 1 is shipped. A management unit is, for example, one of several memory chips 5_0 to 5_7. Multiple management units are multiple memory chips 5_0 to 5_7.

[0053] Controller 2 refers to the block management table 33 and calculates the number of available blocks by subtracting the number of used blocks from the maximum number of user blocks. Controller 2 compares the calculated number of available blocks with the threshold Nth to determine whether there is a management unit with a number of available blocks smaller than the threshold Nth.

[0054] Controller 2 terminates the process shown in this flowchart if there are no management units with a number of free blocks smaller than the threshold Nth (No in S1).

[0055] Controller 2 performs a GC source search process (S2) to find the management unit that will be the source of data movement (GC source) by garbage collection if there is a management unit with a number of free blocks smaller than the threshold Nth (Yes in S1).

[0056] Controller 2 may decide to use a management unit with a number of free blocks equal to or less than the threshold Nth as the source for garbage collection, instead of a management unit with a number of free blocks equal to or less than the threshold Nth. If there are two or more management units among multiple management units that have a number of free blocks equal to or less than the threshold Nth, Controller 2 may decide to use the management unit with the smaller number of free blocks among the two or more management units as the source for garbage collection.

[0057] Controller 2 performs a GC destination search process (S3) to find a management unit that will be the destination for data to be moved by garbage collection (GC destination). For example, Controller 2 determines which management unit will be the GC destination from among multiple management units based on the utilization rate of each of the multiple management units. For example, Controller 2 determines the management unit with the lowest utilization rate among multiple management units as the GC destination.

[0058] Controller 2 performs garbage collection (GC) (S4). Controller 2 collects valid data from inefficient blocks in the management unit discovered in S2 and rewrites it to the management unit discovered in S3. Controller 2 erases the inefficient blocks in the management unit discovered in S2, making them free blocks.

[0059] Next, the GC target search process (S3) will be explained using Figure 5. Figure 5 is a flowchart of the GC target search process for memory system 1. Figure 5 illustrates the case where the multiple management units targeted for GC target search are multiple memory chips 5_0 to 5_7.

[0060] In memory system 1, controller 2 sets initial values ​​for parameters for executing the GC target search process. These parameters include the minimum utilization rate and the GC target chip identifier. The minimum utilization rate is a parameter used to determine whether the utilization rate of memory chip 5 is at its minimum. The GC target chip identifier is a parameter used to identify the memory chip to be used for garbage collection.

[0061] Controller 2 sets the minimum utilization to the initial value "0xFFFF" and the GC target chip identifier to the initial value "0".

[0062] Controller 2 performs the loop processing from S13 to S15. Controller 2 may use a processing chip identifier as a parameter to manage the loop processing from S13 to S15. Controller 2 sets the initial value of the processing chip identifier to "0" (S12) and starts the loop processing from S13 to S15.

[0063] Controller 2 determines whether the utilization rate of the memory chip 5 to be processed is less than the minimum utilization rate (S13).

[0064] If the utilization rate of the memory chip 5 to be processed is above the minimum utilization rate (No in S13), the controller 2 determines that the memory chip 5 to be processed is unsuitable as a garbage collection target and proceeds to S15.

[0065] If the utilization rate of the memory chip 5 to be processed is less than the minimum utilization rate (Yes in S13), the controller 2 considers the memory chip 5 to be a suitable garbage collection target and updates the minimum utilization rate parameter and the garbage collection target chip identifier parameter (S14). In other words, the controller 2 sets the minimum utilization rate value to the utilization rate of the memory chip 5 to be processed and sets the garbage collection target chip identifier to the chip identifier of the memory chip 5 to be processed.

[0066] Controller 2 increments the value of the processing chip identifier (S15). After S15, processing returns to S13.

[0067] The loop from S13 to S15 is repeated until the processing chip identifier reaches 7. Once the processing chip identifier reaches 7, steps S13 to S16 are executed for memory chip 5_7 with chip identifier "7", and then processing is terminated.

[0068] As shown in Figure 5, the identifier of the memory chip 5 with the lowest utilization rate among multiple memory chips 5_0 to 5_7 is set as the GC target chip identifier. As a result, the memory chip 5 corresponding to the identifier set in the GC target chip identifier is selected as the memory chip to be garbage collected. This suppresses the occurrence of memory chips 5 with excessively high utilization rates and equalizes the utilization rates (e.g., block utilization) of multiple memory chips 5_0 to 5_7.

[0069] Next, the use cases for the GC target search process of memory system 1 will be explained using Figures 6 and 7. Figures 6 and 7 are diagrams showing the use cases for the GC target search process of memory system 1, respectively.

[0070] Figure 6 is a table showing the maximum number of user blocks for each memory chip, and how the usage rate and number of blocks used change with the number of garbage collection cycles.

[0071] In the "pre-GC" state shown in Figure 6, the number of free blocks for multiple memory chips 5_0, 5_1, 5_2, 5_3, 5_4, 5_5, 5_6, and 5_7 are 3680-3630=50, 3866-3520=346, 3866-3530=336, 3867-3520=347, 3867-3520=347, 3680-3500=180, 3867-3510=357, and 3867-3520=347, respectively.

[0072] Among the multiple memory chips 5_0 to 5_7, memory chips 5_0 and 5_5, which have a number of free blocks smaller than the threshold Nth (for example, Nth=300), are selected as the garbage collector (GC) source, specifically memory chip 5_0, which has the fewest free blocks.

[0073] As shown in "Before GC", when garbage collection is not being performed, the utilization rates of multiple memory chips 5_0, 5_1, 5_2, 5_3, 5_4, 5_5, 5_6, and 5_7 are 98.64%, 91.05%, 91.31%, 91.03%, 91.03%, 95.11%, 90.77%, and 91.03%, respectively.

[0074] Of the multiple memory chips 5_0 to 5_7, the memory chip 5_6 with the lowest usage rate is selected as the garbage collector (GC) target.

[0075] Controller 2 collects valid data from the inefficient blocks of memory chip 5_0 and rewrites it to memory chip 5_6. Controller 2 erases the inefficient blocks in memory chip 5_0, making them free blocks. Free blocks are also called empty blocks.

[0076] As a result, the number of blocks used and the utilization rate of multiple memory chips will be in the state of having undergone one garbage collection (GC), as indicated by "GC 1 time". In this state, the utilization rates of multiple memory chips 5_0, 5_1, 5_2, 5_3, 5_4, 5_5, 5_6, and 5_7 are 98.61%, 91.05%, 91.31%, 91.03%, 91.03%, 95.11%, 90.79%, and 91.03%, respectively.

[0077] Before garbage collection (GC) is performed, the difference between the maximum and minimum utilization rates of multiple memory chips is 98.64 - 90.77 = 7.87 (%). After one GC has been performed, the difference between the maximum and minimum utilization rates of multiple memory chips is 98.61 - 90.79 = 7.82 (%).

[0078] In other words, it can be seen that one garbage collection cycle reduces the difference between the maximum and minimum usage rates across multiple memory chips 5_0 to 5_7, thus leveling out the usage rates.

[0079] As shown in "GC10 times", with GC performed 10 times, the utilization rates of multiple memory chips 5_0, 5_1, 5_2, 5_3, 5_4, 5_5, 5_6, and 5_7 are 98.37%, 91.05%, 91.31%, 91.03%, 91.03%, 95.11%, 91.03%, and 91.03%, respectively.

[0080] With 10 garbage collection cycles performed, the difference between the maximum and minimum utilization rates of multiple memory chips is 98.37 - 91.03 = 7.34 (%).

[0081] In other words, by having controller 2 perform garbage collection 10 times, the difference between the maximum and minimum utilization rates of multiple memory chips 5_0 to 5_7 is further reduced, and the utilization rates are further leveled out.

[0082] Figure 7 shows the usage status of multiple memory chips when the number of GC cycles is further increased in this embodiment. Figure 7 shows the usage status of each memory chip 5_0 to 5_7 as a bar graph. In Figure 7, the vertical axis represents the number of blocks, and the horizontal axis represents the chip identifier. As the number of GC cycles is increased, for example, as shown in Figure 7, the usage rate of multiple memory chips 5_0 to 5_7 can become 92%, which is almost equal.

[0083] The "320" area in memory chips 5_0 and 5_5 is inaccessible as a bad block BB. A bad block BB is a block that is unusable due to reasons such as the bit error rate exceeding a predetermined value. In memory chips 5_0 and 5_5, the maximum number of user blocks is "3680" in each case, which is the total number of blocks minus the number of bad blocks "320".

[0084] The area labeled "134" in memory chips 5_1 and 5_2 is made inaccessible as part of the management information storage area 31 (see Figure 1). The management information storage area 31 contains multiple memory cells used in SLC mode. In memory chips 5_1 and 5_2, the maximum number of user blocks is "3866" in each case, excluding the number of blocks "134" in the management information storage area from the total number of blocks.

[0085] The area labeled "133" in memory chips 5_3, 5_4, 5_6, and 5_7 is made inaccessible as part of the management information storage area 31 (see Figure 1). In memory chips 5_3, 5_4, 5_6, and 5_7, the maximum number of user blocks is "3867" in each case, excluding the "133" blocks in the management information storage area from the total number of blocks.

[0086] The areas indicated by dot hatching in each memory chip 5_0 to 5_7 correspond to the number of blocks used. The areas in white on each memory chip 5_0 to 5_7 correspond to the number of free blocks. Of the white areas on each memory chip 5_0 to 5_7, the portion above the dotted line corresponds to the threshold Nth for the number of free blocks required for garbage collection (GC) to be triggered. As shown in Figure 7, in this embodiment, the number of blocks between the area indicated by dot hatching and the dotted line representing the threshold is equal, and each of the multiple memory chips has an equal number of free blocks relative to each other. In other words, each of the multiple memory chips has an equal margin of blocks before GC is triggered. This makes it possible to equalize the frequency of GC triggers among the multiple memory chips 5_0 to 5_7.

[0087] In other words, by using utilization rate as the criterion for determining the GC target, memory chip 5 with a large number of bad blocks will be less likely to be selected as the GC target even if it has a small number of used blocks, because of its high utilization rate. This reduces the frequency of GC activation. Furthermore, memory chip 5 with few bad blocks will be more likely to be selected as the GC target even if it has a large number of used blocks, because of its low utilization rate. As a result, it is possible to suppress the increase in the number of write / erase cycles for each memory chip 5, thereby extending the product lifespan.

[0088] As described above, in the first embodiment, in the memory system 1, the controller 2 determines which of the multiple management units will be the destination for data to be moved by garbage collection, according to the utilization rate of each of the multiple management units. This allows the utilization rate of each of the multiple management units to be equalized, the frequency of garbage collection activation to be equalized among the multiple management units, and garbage collection to be performed efficiently. As a result, the number of write / erase cycles can be equalized among the multiple management units, and the degree of wear on each of the multiple management units can be homogenized, thereby extending the lifespan of the memory system 1.

[0089] Furthermore, in the first embodiment, when garbage collection is performed in the memory system 1, the controller can manage the non-volatile memory 3 on a unit of memory chips 5. That is, the controller 2 determines which memory chip 5 will be the destination for data to be moved by garbage collection, based on the usage rate of each of the multiple memory chips 5. This allows the usage rate of each memory chip 5 to be equalized among the multiple memory chips 5, the frequency of garbage collection activation to be equalized among the multiple memory chips 5, and garbage collection to be performed efficiently. As a result, the number of write / erase cycles can be equalized among the multiple memory chips 5, and the degree of wear on the multiple memory chips 5 can be homogenized, thus extending the lifespan of the memory system 1.

[0090] Controller 2 may perform garbage collection based on the page usage rate of each management unit instead of based on the block usage rate of each management unit. Controller 2 may also use pages as management units instead of blocks.

[0091] The controller 2 may manage the number of user-available pages in each memory chip 5 as the maximum number of pages.

[0092] Controller 2 may manage the number of pages being used in each memory chip 5 as the number of pages used. A used page is a page that contains valid data for the data being written to it.

[0093] Controller 2 may manage the percentage of pages being used in each memory chip 5 as the utilization rate. The utilization rate is calculated using the number of pages used and the maximum number of pages. For example, Controller 2 may calculate the utilization rate by dividing the number of pages used by the maximum number of pages.

[0094] Controller 2 may perform garbage collection using block management table 33', in which the maximum number of user blocks and the number of blocks used in block management table 33 shown in Figure 3 have been replaced with the maximum number of pages and the number of pages used.

[0095] In S1 shown in Figure 4, the controller 2 may determine whether there is a management unit among the multiple management units that has a number of free pages smaller than the threshold PNth. The threshold PNth is a value determined by considering the margin of free pages required to prevent data loss in the management unit. The threshold PNth can be experimentally determined in advance before the memory system 1 is shipped.

[0096] Alternatively, in S1 shown in Figure 4, the controller 2 may determine whether there is a management unit among the multiple management units whose number of used blocks exceeds the threshold Ntha. The threshold Ntha is a value determined considering the margin of the number of used blocks that prevents data loss in the management unit. The threshold Ntha can be experimentally determined in advance before the memory system 1 is shipped.

[0097] Alternatively, in S1 shown in Figure 4, the controller 2 may determine whether there is a management unit among the multiple management units whose number of used pages exceeds the threshold PNtha. The threshold PNtha is a value determined considering the margin of the number of used pages that prevents data loss in the management unit. The threshold PNtha can be experimentally determined in advance before the memory system 1 is shipped.

[0098] Alternatively, in S1 shown in Figure 4, the controller 2 may determine whether or not there is a management unit among the multiple management units whose utilization rate exceeds the threshold Rth. The threshold Rth can be determined experimentally in advance, taking into account the utilization rate margin at which data loss does not occur in the management unit.

[0099] (Second embodiment) Next, a description will be given of the memory system 1i according to the second embodiment. The following description will focus on the differences from the first embodiment.

[0100] In the first embodiment, garbage collection using a memory chip as the management unit is illustrated, while in the second embodiment, garbage collection using a parallel processing unit within a memory chip as the management unit is illustrated.

[0101] In the non-volatile memory 3i of the memory system 1i, each memory chip 5 may include multiple memory areas 6 that can be processed in parallel with each other within the memory chip 5, as shown in Figure 8. Figure 8 is a diagram showing the configuration of the controller 2i and the non-volatile memory 3i in the second embodiment.

[0102] The non-volatile memory 3i has multiple memory chips 5_0, 5_1. Figure 8 illustrates a configuration in which the non-volatile memory 3i has two memory chips 5_0, 5_1, but the number of memory chips 5 in the non-volatile memory 3i may be three or more.

[0103] Memory chip 5_0 contains multiple memory areas 6_0 to 6_3. These memory areas 6_0 to 6_3 are units that can be processed in parallel within memory chip 5_0. Controller 2i can access these memory areas 6_0 to 6_3 in parallel. Each memory area 6 is also called a plane.

[0104] Figure 8 illustrates a configuration in which memory chip 5_0 has four memory areas 6_0 to 6_3, but the number of memory areas 6 on memory chip 5_0 may be 2 to 3 or 5 or more.

[0105] Memory chip 5_1 contains multiple memory areas 6_4 to 6_7. These memory areas 6_4 to 6_7 are units that can be processed in parallel within memory chip 5_1. Controller 2i can access these memory areas 6_4 to 6_7 in memory chip 5_0 in parallel. Each memory area 6 is also called a plane.

[0106] Figure 8 illustrates a configuration in which the memory chip 5_1 has four memory areas 6_4 to 6_7, but the number of memory areas 6 on the memory chip 5_1 may be 2 to 3 or 5 or more.

[0107] The controller 2i can manage non-volatile memory 3i in units of multiple memory areas 6_0 to 6_7 for garbage collection.

[0108] Controller 2i may perform garbage collection using a block management table 33i, as shown in Figure 9, instead of the block management table 33 (see Figure 3). Figure 9 shows the data structure of the block management table 33i.

[0109] The block management table 33i associates the identifier of memory area 6 with the maximum number of user blocks and the number of blocks used for multiple memory areas 6_0 to 6_7. The block management table 33i has a memory area identifier field 331i instead of a chip identifier field 331 (see Figure 3). The memory area identifier field 331i records the identifier of memory area 6. In all other respects, it is the same as the block management table 33 of the first embodiment.

[0110] By referring to the block management table 33i, the maximum number of user blocks and the number of used blocks corresponding to the identifier of memory area 6 can be determined, and the utilization rate can be calculated from these.

[0111] For memory area 6_0 with memory area identifier "0", we can see that the maximum number of user blocks is "SN11" and the number of used blocks is "BN11". From this, the utilization rate can be calculated as (BN11) / (SN11).

[0112] For memory area 6_1 with memory area identifier "1", we can see that the maximum number of user blocks is "SN12" and the number of used blocks is "BN12". From this, the utilization rate can be calculated as (BN12) / (SN12).

[0113] For memory area 6_7 with memory area identifier "7", we can see that the maximum number of user blocks is "SN18" and the number of used blocks is "BN18". From this, the utilization rate can be calculated as (BN18) / (SN18).

[0114] The operation of the memory system 1i in relation to garbage collection is the same as in the explanations of Figures 4 and 5, but with "memory chip" replaced by "memory area".

[0115] Furthermore, the use case for the GC target search process of the memory system 1i differs from the first embodiment in the following respects, as shown in Figures 10 and 11. Figures 10 and 11 are diagrams showing the use cases for the GC target search process of the memory system 1i according to the second embodiment, respectively.

[0116] In the "pre-GC" state shown in Figure 10, the number of free blocks in multiple memory areas 6_0, 6_1, 6_2, 6_3, 6_4, 6_5, 6_6, and 6_7 are 900-880=20, 933-815=118, 933-815=118, 934-815=119, 934-815=119, 900-800=100, 934-805=129, and 934-810=124, respectively.

[0117] Of the multiple memory areas 6_0 to 6_7, memory area 6_0, which has a number of free blocks smaller than the threshold Nth (for example, Nth=100), is selected as the source for garbage collection.

[0118] As shown in "Before GC", when garbage collection is not performed, the usage rates of multiple memory areas 6_0, 6_1, 6_2, 6_3, 6_4, 6_5, 6_6, and 6_7 are 97.78%, 87.35%, 87.35%, 87.26%, 87.26%, 88.89%, 86.19%, and 86.72%, respectively.

[0119] Of the multiple memory areas 6_0 to 6_7, the memory area 6_6 with the lowest usage rate is determined to be the garbage collector.

[0120] Controller 2i collects valid data from the inefficient blocks in memory area 6_0 and rewrites it to memory area 6_6. Controller 2i erases the inefficient blocks in memory area 6_0, making them free blocks.

[0121] By repeating the same process five times, the state of "GC 5 times" is reached. In this state, the usage rates of multiple memory areas 6_0, 6_1, 6_2, 6_3, 6_4, 6_5, 6_6, and 6_7 are 97.22%, 87.35%, 87.35%, 87.26%, 87.26%, 88.89%, 86.72%, and 86.72%, respectively.

[0122] The difference between the maximum and minimum usage rates in the "before GC" state is 97.78 - 86.19 = 11.59 (%). As shown in "5 GCs", the difference between the maximum and minimum usage rates in the state where GC has been performed 5 times is 97.22 - 86.72 = 10.5 (%).

[0123] In other words, it can be seen that when controller 2i performs garbage collection five times, the difference between the maximum and minimum usage rates in multiple memory areas 6_0 to 6_7 decreases, and the usage rates are leveled out.

[0124] As garbage collection (GC) is performed further, the utilization rates of multiple memory areas 6_0 to 6_7 can become almost uniform at 92%, as shown in Figure 11. Figure 11 shows the utilization status of each memory area 6_0 to 6_7 as a bar graph. In Figure 11, the vertical axis represents the number of blocks, and the horizontal axis represents the memory area identifier.

[0125] The "100" areas in memory areas 6_0 and 6_5 are inaccessible as bad blocks (BB). In memory areas 6_0 and 6_5, the maximum number of user blocks is "900" (100 bad blocks) from the total number of blocks.

[0126] The area "67" in memory areas 6_1 and 6_2 is made inaccessible as part of the management information storage area 31 (see Figure 1). In memory areas 6_1 and 6_2, the maximum number of user blocks is "933" in each case, excluding the number of blocks "67" in the management information storage area from the total number of blocks.

[0127] The "66" area in memory areas 6_3, 6_4, 6_6, and 6_7 is made inaccessible as part of the management information storage area 31 (see Figure 1). In memory areas 6_3, 6_4, 6_6, and 6_7, the maximum number of user blocks is "934" in each case, excluding the "66" blocks in the management information storage area from the total number of blocks.

[0128] The areas indicated by dot hatching in each memory area 6_0 to 6_7 correspond to the number of used blocks. The areas in white within each memory area 6_0 to 6_7 correspond to the number of free blocks. Of the white areas within each memory area 6_0 to 6_7, the portion above the dotted line corresponds to the threshold Nth for the number of free blocks required to trigger garbage collection (GC). As shown in Figure 11, in this embodiment, the number of blocks between the areas indicated by dot hatching and the dotted line representing the threshold is equal, indicating that the margin of blocks before GC is triggered is also equal. This allows the frequency of GC to be equalized across multiple memory areas 6_0 to 6_7.

[0129] In other words, by using utilization rate as the criterion for determining the GC target, memory area 6 with a large number of bad blocks will be less likely to be selected as the GC target even if the number of used blocks is small, because of its high utilization rate. This reduces the frequency of GC activation. Furthermore, memory area 6 with few bad blocks will be more likely to be selected as the GC target even if the number of used blocks is large, because of its low utilization rate. As a result, it is possible to suppress the increase in write / erase cycles in each memory area 6, thereby extending the product lifespan.

[0130] As described above, in the second embodiment, in the memory system 1i, the controller 2i can manage the non-volatile memory 3i in parallel processing units within the memory chip 5 with respect to garbage collection. That is, the controller 2i determines which memory area 6 will be the destination for data moved by garbage collection from among the multiple memory areas 6, according to the usage rate of each of the multiple memory areas 6. This makes it possible to equalize the usage rate of each of the multiple memory areas 6, equalize the frequency of garbage collection activation among the multiple memory areas 6, and perform garbage collection efficiently. As a result, the number of write / erase cycles can be equalized among the multiple memory areas 6, and the degree of fatigue of each of the multiple memory areas 6 can be homogenized, thus extending the lifespan of the memory system 1i.

[0131] (Third embodiment) Next, a description will be given of the memory system 1j according to the third embodiment. The following description will focus on the differences from the first and second embodiments.

[0132] In the first embodiment, garbage collection with a memory chip 5 as the management unit is illustrated; in the second embodiment, garbage collection with a parallel processing unit within the memory chip 5 as the management unit is illustrated; and in the third embodiment, garbage collection with a parallel processing unit spanning two or more memory chips 5 as the management unit is illustrated.

[0133] In the memory system 1j, the non-volatile memory 3j may include multiple POS7 that are able to process each other in parallel and each spans two or more memory chips 5, as shown in Figure 12. Figure 12 shows the configuration of the controller 2j and the non-volatile memory 3j in the third embodiment.

[0134] The non-volatile memory 3j has multiple memory chips 5_0 to 5_3. Figure 12 illustrates a configuration in which the non-volatile memory 3j has four memory chips 5_0 to 5_3, but the number of memory chips 5 in the non-volatile memory 3j may be two to three, or five or more.

[0135] Memory chip 5_0 contains multiple memory areas 6_0 to 6_3. Memory chip 5_1 contains multiple memory areas 6_4 to 6_7. Memory chip 5_2 contains multiple memory areas 6_0 to 6_3. Memory chip 5_3 contains multiple memory areas 6_4 to 6_7.

[0136] The non-volatile memory 3j contains multiple POS7_0 to 7_7 units. These multiple POS7_0 to 7_7 units are units that can be processed in parallel with each other. The controller 2j can access multiple POS7_0 to 7_3 units in parallel. Each POS7 is also called a bank. Figure 12 illustrates a configuration in which the non-volatile memory 3j has eight POS7_0 to 7_3 units, but the number of POS7 units in the non-volatile memory 3j can be 2 to 7, or 9 or more.

[0137] POS7_0 is a parallel processing unit that spans memory chip 5_0 and memory chip 5_2. POS7_0 includes memory area 6_0 of memory chip 5_0 and memory area 6_0 of memory chip 5_2.

[0138] POS7_1 is a parallel processing unit that spans memory chip 5_0 and memory chip 5_2. POS7_1 includes memory area 6_1 of memory chip 5_0 and memory area 6_1 of memory chip 5_2.

[0139] POS7_2 is a parallel processing unit that spans memory chip 5_0 and memory chip 5_2. POS7_2 includes memory area 6_2 of memory chip 5_0 and memory area 6_2 of memory chip 5_2.

[0140] POS7_3 is a parallel processing unit that spans memory chip 5_0 and memory chip 5_2. POS7_3 includes memory area 6_3 of memory chip 5_0 and memory area 6_3 of memory chip 5_2.

[0141] POS7_4 is a parallel processing unit that spans memory chip 5_1 and memory chip 5_3. POS7_4 includes memory area 6_4 of memory chip 5_1 and memory area 6_4 of memory chip 5_3.

[0142] POS7_5 is a parallel processing unit that spans memory chip 5_1 and memory chip 5_3. POS7_5 includes memory area 6_5 of memory chip 5_1 and memory area 6_5 of memory chip 5_3.

[0143] POS7_6 is a parallel processing unit that spans memory chip 5_1 and memory chip 5_3. POS7_6 includes memory area 6_6 of memory chip 5_1 and memory area 6_6 of memory chip 5_3.

[0144] POS7_7 is a parallel processing unit that spans memory chip 5_1 and memory chip 5_3. POS7_7 includes memory area 6_7 of memory chip 5_1 and memory area 6_7 of memory chip 5_3.

[0145] Controller 2j can manage non-volatile memory 3j in units of multiple POS7_0 to 7_7 for garbage collection.

[0146] Controller 2j may perform garbage collection using a block management table 33j as shown in Figure 13, instead of the block management table 33 (see Figure 3). Figure 13 shows the data structure of the block management table 33j.

[0147] The block management table 33j associates the POS7 identifier, the maximum number of user blocks, and the number of blocks used for multiple POS7_0 to 7_7. The block management table 33j has a POS identifier field 331j instead of a chip identifier field 331 (see Figure 3). The POS7 identifier is recorded in the POS identifier field 331j. In all other respects, it is the same as the block management table 33 of the first embodiment.

[0148] By referring to the block management table 33j, it is possible to determine the maximum number of user blocks and the number of blocks used corresponding to the POS7 identifier, and from these, the utilization rate can be calculated.

[0149] For POS7_0 with POS identifier "0", we can see that the maximum number of user blocks is "SN21" and the number of blocks used is "BN21". From this, the utilization rate can be calculated as (BN21) / (SN21).

[0150] For POS7_1 with POS identifier "1", we can see that the maximum number of user blocks is "SN22" and the number of blocks used is "BN22". From this, the utilization rate can be calculated as (BN22) / (SN22).

[0151] For POS7_7 with POS identifier "7", we can see that the maximum number of user blocks is "SN28" and the number of blocks used is "BN28". From this, the utilization rate can be calculated as (BN28) / (SN28).

[0152] The operation of memory system 1j regarding garbage collection is the same as in the explanations of Figures 4 and 5, but with "memory chip" replaced by "POS".

[0153] Furthermore, the use case for the GC target search process of memory system 1j differs from the first embodiment in the following respects, as shown in Figures 14 and 15. Figures 14 and 15 are diagrams showing the use case for the GC target search process of memory system 1j according to the third embodiment, respectively.

[0154] In the "pre-GC" state shown in Figure 10, the number of free blocks for multiple POS7_0, 7_1, 7_2, 7_3, 7_4, 7_5, 7_6, and 7_7 are 1688-1640=48, 1762-1610=152, 1762-1610=152, 1763-1610=153, 1763-1610=153, 1688-1580=108, 1763-1590=173, and 1763-1600=163.

[0155] Among the multiple POS7_0~7_7 blocks, POS7_0 with a number of free blocks smaller than a threshold (e.g., 100) is selected as the garbage collector.

[0156] As shown in "Before GC", when GC is not being performed, the usage rates of multiple POS7_0, 7_1, 7_2, 7_3, 7_4, 7_5, 7_6, and 7_7 are 97.16%, 91.37%, 91.37%, 91.32%, 91.32%, 93.60%, 90.19%, and 90.75%, respectively.

[0157] Of the multiple POS7_0 to 7_7 entries, POS7_6, which has the lowest usage rate, is selected as the garbage collector.

[0158] Controller 2j collects valid data from the inefficient blocks in POS7_0 and rewrites it to POS7_6. Controller 2j erases the inefficient blocks in POS7_0 and makes them free blocks.

[0159] By repeating the same process 10 times, the system will have undergone 10 garbage collection cycles, as indicated by "GC10 times". In this state, the usage rates of multiple POS7_0, 7_1, 7_2, 7_3, 7_4, 7_5, 7_6, and 7_7 are 96.56%, 91.37%, 91.37%, 91.32%, 91.32%, 93.60%, 90.75%, and 90.75%, respectively.

[0160] The difference between the maximum and minimum utilization when no garbage collection (GC) is performed is 97.16 - 90.19 = 6.97 (%). The difference between the maximum and minimum utilization when GC has been performed 10 times is 96.56 - 90.75 = 5.81 (%).

[0161] In other words, it can be seen that when controller 2j performs garbage collection 10 times, the difference between the maximum and minimum utilization rates for multiple POS7_0 to 7_7 decreases, and the utilization rates are leveled out.

[0162] As garbage collection (GC) is performed further, the usage rates of multiple POS7_0~7_7 can become almost equal at 92%, as shown in Figure 15. Figure 15 shows the usage status of each POS7_0~7_7 as a bar graph. In Figure 15, the vertical axis represents the number of blocks, and the horizontal axis represents the POS identifier.

[0163] The "142" area in POS7_0 and 7_5 is inaccessible as a bad block BB. In POS7_0 and 7_5, the maximum number of user blocks is "1688" in each case, excluding the bad block count of "100" from the total number of blocks.

[0164] The area of ​​"68" in POS7_1 and 7_2 is inaccessible as part of the management information storage area 31 (see Figure 1). In POS7_1 and 7_2, the maximum number of user blocks is "1762" in each case, excluding the "68" blocks in the management information storage area from the total number of blocks.

[0165] The area "67" in POS7_3, 7_4, 7_6, and 7_7 is inaccessible as part of the management information storage area 31 (see Figure 1). In POS7_3, 7_4, 7_6, and 7_7, the maximum number of user blocks is "1763" in each case, excluding the number of blocks "67" in the management information storage area from the total number of blocks.

[0166] The areas indicated by dot hatching in each POS7_0 to 7_7 correspond to the number of used blocks. The areas in white in each POS7_0 to 7_7 correspond to the number of free blocks. Of the white areas in each POS7_0 to 7_7, the portion above the dotted line corresponds to the threshold Nth for the number of free blocks required to trigger garbage collection (GC). As shown in Figure 15, in this embodiment, the number of blocks between the areas indicated by dot hatching and the dotted line representing the threshold is equal, indicating that the margin of blocks before GC is triggered is also equal. This allows the frequency of GC to be equalized across multiple POS7_0 to 7_7.

[0167] In other words, by using utilization rate as the criterion for determining the garbage collection target, POS7 blocks with a high number of bad blocks are less likely to be selected for garbage collection even if they have a low number of used blocks, because their utilization rate is high. This reduces the frequency of garbage collection. Furthermore, POS7 blocks with few bad blocks are more likely to be selected for garbage collection even if they have a high number of used blocks, because their utilization rate is low. Therefore, it is possible to suppress the increase in write / erase cycles in POS7 blocks, thereby extending the product lifespan.

[0168] As described above, in the third embodiment, in the memory system 1j, the controller 2j determines which of the multiple POS7s will be the destination for data to be moved by garbage collection, according to the usage rate of each of the multiple POS7s. This equalizes the usage rate of each of the multiple POS7s and equalizes the frequency of garbage collection activation among the multiple POS7s. As a result, the number of write / erase operations can be equalized among the multiple POS7s and the degree of wear on each of the multiple POS7s can be homogenized, thus extending the lifespan of the memory system 1j.

[0169] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0170] 1,1i,1j Memory system, 2,2i,2j Controller, 3,3i,3j Non-volatile memory, 5 Memory chip, 6 Memory area, 7 POS.

Claims

1. Non-volatile memory containing multiple management units, A controller capable of managing the aforementioned multiple management units, which determines which of the multiple management units will be the destination for data to be moved by garbage collection, according to the usage rate of each of the aforementioned multiple management units. A memory system equipped with this feature.

2. The aforementioned controller, The usage rate of each of the aforementioned multiple management units is calculated using the number of blocks used and the maximum number of user data blocks. The management unit with the smallest utilization rate among the aforementioned multiple management units is determined as the destination for data to be moved by garbage collection. The memory system according to claim 1.

3. The non-volatile memory has multiple chips, and the controller manages each of the multiple chips as one of the multiple management units. The memory system according to claim 1.

4. The aforementioned non-volatile memory has multiple chips, The controller manages the multiple parallel processing units within the chip as the multiple management units. The memory system according to claim 1.

5. The aforementioned non-volatile memory has multiple chips, The controller manages multiple parallel processing units spanning two or more chips as the multiple management units. The memory system according to claim 1.

6. The controller determines, among the plurality of management units, the management unit whose free data capacity is below a first threshold as the source of data to be moved by garbage collection. The memory system according to claim 1.

7. The controller determines, among the plurality of management units, the management unit whose amount of used data exceeds a second threshold as the source of data to be moved by garbage collection. The memory system according to claim 1.

8. The controller refers to a table containing the maximum number of user data blocks and the number of blocks used for each of the multiple management units, and calculates the utilization rate. The memory system according to claim 2.

9. The controller updates the table each time it accesses the non-volatile memory, and stores the updated table in the non-volatile memory at first time intervals. The memory system according to claim 8.

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