Semiconductor laminate, semiconductor device, and method for manufacturing a semiconductor device

Abstract

To improve the protective effect on the surface of the nitride semiconductor layer during annealing, i.e., the effect of suppressing nitrogen detachment, compared to conventional methods. [Solution] A semiconductor laminate (100) that is subjected to annealing during the manufacturing process of a semiconductor device comprises a nitride semiconductor layer (101) containing a dopant and a protective layer (103) covering the main surface (112) of the nitride semiconductor layer. The protective layer is provided to suppress the detachment of nitrogen from the nitride semiconductor layer due to annealing. In this disclosure, the protective layer does not contain oxygen as a constituent element and is formed to have a higher oxygen barrier property than the aluminum nitride layer in preventing the action of oxygen on the main surface.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor laminate, a semiconductor device, and a method for manufacturing a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a method for manufacturing a p-type group III nitride semiconductor by ion-implanting magnesium (Mg) into a group III nitride semiconductor. Specifically, the manufacturing method described in Patent Document 1 includes a through-film formation step, an ion implantation step, a step of removing all the through-films, a protective film formation step, an annealing step, and a step of removing the protective film.

[0003] The through-film formation step is a step of forming a through-film on a semiconductor layer made of a group III nitride semiconductor to adjust the implantation amount and the position of the implantation peak of p-type impurities in the next step. The ion implantation step is a step of ion-implanting p-type impurities by controlling the implantation energy so that the implantation peak is in the through-film from above the through-film and forming an ion implantation region in the semiconductor layer.

[0004] The protective film formation step is a step of forming a protective film on the semiconductor layer to prevent the release of nitrogen due to annealing in the next step. In Patent Document 1, the protective film can be made of, for example, aluminum nitride (AlN), silicon nitride (SiN), silicon oxide (SiO2), aluminum oxide (Al2O3), etc. The annealing step is a step of activating p-type impurities by heat treatment to make the ion implantation region a p-type region.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In this regard, the inventors have diligently researched and found that there is still room for improvement in the conventional technology regarding the protective effect on the surface of the nitride semiconductor layer during annealing, that is, the effect of suppressing nitrogen detachment. This disclosure has been made in view of the circumstances exemplified above. [Means for solving the problem]

[0007] The semiconductor laminate (100) described in claim 1 is A nitride semiconductor layer (101) containing a dopant, A protective layer (103) covering the main surface (112) of the nitride semiconductor layer, Equipped with, The protective layer does not contain oxygen as a constituent element and is formed to have a higher oxygen barrier property than the aluminum nitride layer in preventing the action of oxygen on the main surface. The semiconductor laminate (100) described in claim 7 is A nitride semiconductor layer (101) containing a dopant, A protective layer (103) covering the nitride semiconductor layer, Equipped with, The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer is a semiconductor laminate made of the material described in i) or ii) below; i) The protective layer includes a gallium nitride layer; ii) The protective layer comprises a carbon film (131) and a cap layer (132) superimposed on the carbon film, wherein the cap layer is made of a compound semiconductor material. The semiconductor device (1) described in claim 8 is A semiconductor layer (2) containing a nitride semiconductor, The electrode (5) formed on the main surface (22) side of the semiconductor layer, Equipped with, The surface roughness Ra of the main surface is 5 nm or less. The method for manufacturing the semiconductor device (1) according to claim 10 is: The protective layer formation involves covering the main surface (112) of the ion-implanted nitride semiconductor layer (101) with a protective layer (103), and The nitride semiconductor layer is heat-treated while being protected by the protective layer, in an annealing process, Includes, In forming the protective layer, the protective layer is formed such that it does not contain oxygen as a constituent element and has a higher oxygen barrier property than the aluminum nitride layer in preventing the action of oxygen on the main surface.

[0008] In addition, each element in the application documents may be denoted by a reference numeral in parentheses. In this case, the reference numeral is merely an example of the correspondence between the element and the specific configuration described in the embodiments described later. Therefore, this disclosure is not limited in any way by the inclusion of reference numerals. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view showing a schematic configuration of a semiconductor device according to one embodiment of the present disclosure. [Figure 2] This is a cross-sectional view showing the schematic configuration of a semiconductor stack according to the first embodiment of this disclosure. [Figure 3] This figure shows a portion of the manufacturing flow corresponding to the overview of the semiconductor device manufacturing method shown in Figure 1. [Figure 4] This is a cross-sectional view showing the schematic configuration of a semiconductor laminate according to the second embodiment of this disclosure. [Figure 5] This is a cross-sectional view showing the schematic configuration of a semiconductor laminate according to the third embodiment of this disclosure. [Modes for carrying out the invention]

[0010] (Embodiment) Hereinafter, embodiments of the present disclosure will be described with reference to the drawings as appropriate. Note that the following embodiments, their modifications, and the descriptions of the drawings related thereto are schematic or simplified for the purpose of briefly explaining the content of the present disclosure. Therefore, the content of the present disclosure is not limited thereby. Needless to say, it is not always the case that the description of the drawings and the specific device configuration actually manufactured and sold coincide. That is, unless the applicant explicitly limits it during the application process of this application, the present disclosure should not be construed in a limited manner by the description of the drawings and the description of the configuration, its functions, or operations described below corresponding thereto.

[0011] (Semiconductor device) First, referring to FIG. 1, the schematic configuration of a semiconductor device 1 according to an embodiment of the present disclosure will be described. Such a semiconductor device 1 includes a semiconductor layer 2, a substrate 3, a drain electrode 4, a source electrode 5, and an insulating gate 6.

[0012] For the sake of simplicity of illustration and description, a right-handed XYZ coordinate system as shown in FIG. 1 is set. The Z-axis direction is referred to as the "vertical direction", and any direction in the XY plane is referred to as the "in-plane direction". However, it is needless to say that the concept of the "vertical direction" or "up" and "down" in this case is based on the vertical direction in the drawing and does not necessarily correspond to the direction of the gravitational action in the manufacturing process or the usage situation of the semiconductor device 1.

[0013] The semiconductor layer 2 is a compound semiconductor layer containing a nitride semiconductor and has a pair of main surfaces, a lower surface 21 and an upper surface 22. The "main surface" is a surface orthogonal to the thickness direction in a layered or plate-like object and can also be referred to as the "main face". The semiconductor layer 2 is provided such that the lower surface 21 contacts the substrate 3. The substrate 3 is a portion that functions as a drain region and contains a high concentration of an n-type dopant, and is in ohmic contact with the drain electrode 4.

[0014] In this embodiment, the semiconductor layer 2 is made of gallium nitride and / or aluminum gallium nitride and is formed on the substrate 3 using a crystal growth technique. The semiconductor layer 2 has a drift region 24 including a JFET region 23, a body region 25, a source region 26, and a body contact region 27.

[0015] The JFET region 23 is a part of the n-type drift region 24 and is formed in a convex shape upward so as to contact the insulating gate 6 by reaching the upper surface 22. The layered portion of the drift region 24 other than the JFET region 23 is provided in the lower portion in the vertical direction of the semiconductor layer 2 so as to contact the substrate 3.

[0016] The body region 25 is provided so as to contact the layered portion of the drift region 24 other than the JFET region 23. A part of the body region 25 close to the JFET region 23 in the in-plane direction is formed in a convex shape upward so as to contact the insulating gate 6 by reaching the upper surface 22. The body region 25 contains a p-type dopant (such as magnesium, etc.).

[0017] The source region 26 and the body contact region 27 are provided so as to contact the layered portion of the body region 25 other than the portion formed in a convex shape upward. That is, the source region 26 and the body contact region 27 are formed so as to reach the upper surface 22.

[0018] The source region 26 is provided so as to contact the insulating gate 6 at a position adjacent to the portion of the body region 25 formed in a convex shape upward in the in-plane direction. The source region 26 contains an n-type dopant at a higher concentration than the drift region 24.

[0019] The body contact region 27 is located adjacent to the source region 26 in the in-plane direction. The body contact region 27 contains a higher concentration of p-type dopant than the body region 25. The body contact region 27 is in ohmic contact with the source electrode 5 formed on the upper surface 22 side.

[0020] In this embodiment, the insulated gate 6 has a so-called planar structure. Specifically, the insulated gate 6 has an insulating film 61 and a gate electrode 62. The insulating film 61 is formed as a flat film on the upper surface 22. The gate electrode 62 is provided as a flat layer or film so as to face the JFET region 23, the upwardly convex portion of the body region 25, and the source region 26 with the insulating film 61 in between.

[0021] As described above, the general configuration of the semiconductor device 1 is the same as that of the applicant of the present application, as stated in the prior application, Japanese Patent Publication No. 2024-64553. However, in the semiconductor device 1 according to this embodiment, the surface roughness Ra of the upper surface 22 is 5 nm or less. Such smoothness of the upper surface 22 can be achieved in the manufacturing process of the semiconductor device 1 by using the semiconductor laminate 100 shown in Figure 2.

[0022] The following describes the schematic configuration of the semiconductor laminate 100 according to this embodiment and the schematic of the method for manufacturing the semiconductor device 1 using it, with reference to Figure 2. Note that the right-handed XYZ coordinate system in Figure 2 is shown to be consistent with the right-handed XYZ coordinate system shown in Figure 1. The same applies to Figures 4 and 5, which correspond to other embodiments described later.

[0023] (Semiconductor laminate: First embodiment) As shown in Figure 2, the semiconductor laminate 100 according to this embodiment comprises a nitride semiconductor layer 101, a support substrate 102, and a protective layer 103. The nitride semiconductor layer 101, which is made of gallium nitride and / or aluminum gallium nitride, corresponds to the semiconductor layer 2 shown in Figure 1, that is, the compound semiconductor layer that forms the basis of the drift region 24 to the body contact region 27, and is formed to include an n-type dopant.

[0024] The nitride semiconductor layer 101 is formed by crystal growth on the support substrate 102. That is, the support substrate 102 is provided so as to be in contact with the first main surface 111, which is the lower main surface of the nitride semiconductor layer 101. The first main surface 111 is the surface corresponding to the lower surface 21 in Figure 1. The support substrate 102 corresponds to the substrate 3 shown in Figure 1 and contains a higher concentration of n-type dopant than the nitride semiconductor layer 101.

[0025] The protective layer 103 is provided to cover the second main surface 112, which is the upper main surface of the nitride semiconductor layer 101. The second main surface 112 corresponds to the upper surface 22 in Figure 1. In this embodiment, the protective layer 103 is also provided to cover the support substrate 102. That is, the protective layer 103 is provided to cover both the upper and lower surfaces of the laminate of the nitride semiconductor layer 101 and the support substrate 102.

[0026] The protective layer 103 is made of a material that does not contain oxygen as a constituent element. The material constituting the protective layer 103 can be selected from nitrides, carbides, and high-melting-point metals. Preferably, the protective layer 103 is formed to have a higher oxygen barrier property than the aluminum nitride layer, which prevents the action of oxygen on the second main surface 112. Nitrides include at least one of aluminum, gallium, scandium, boron, indium, etc. Carbides may be elemental carbon or compounds containing tantalum, silicon, etc. High-melting-point metals may be at least one of tantalum, molybdenum, nickel, titanium, copper, iridium, platinum, palladium, ruthenium, chromium, hafnium, tungsten, etc., or compounds thereof.

[0027] In this embodiment, the protective layer 103 has a configuration as a single layer of gallium nitride. Specifically, the bonding surface 130, which is the main surface of the protective layer 103, is formed as a flat gallium nitride substrate with a surface roughness Ra of approximately 5 nm or less. The substrate-like protective layer 103 is provided such that the mirror-finished bonding surface 130 is in close contact with the surface of the second main surface 112 and the support substrate 102.

[0028] (Manufacturing method) Figure 3 shows a part of the manufacturing process of the semiconductor device 1 according to this embodiment. Note that the first to fifth steps P1 to P5 shown in Figure 3 are merely a selection of the entire manufacturing process. Therefore, this does not rule out the possibility of other steps (such as the removal of the protective layer 103) being inserted before, after, or in between these steps.

[0029] First, in the first step P1, a nitride semiconductor layer 101 is grown from the upper surface of the support substrate 102, containing an n-type dopant. This forms a nitride semiconductor layer 101 of the desired thickness on the support substrate 102.

[0030] Next, in the second step P2, ion implantation technology is used to implant p-type and n-type dopants into predetermined regions in the upper part of the nitride semiconductor layer 101 (i.e., the part on the second main surface 112 side). This forms the ion implantation regions that will become the body region 25, source region 26, and body contact region 27 shown in Figure 1.

[0031] Next, in the third step P3, protective layers 103 are formed on the upper and lower surfaces of the laminate of the nitride semiconductor layer 101 and the support substrate 102. As is well known, the protective layer 103 is intended to suppress surface roughness that occurs on the surface of the nitride semiconductor layer 101, particularly on the second main surface 112 on the side not bonded to the support substrate 102, due to nitrogen detachment from the nitride semiconductor layer 101 during the subsequent annealing process. This forms the semiconductor laminate 100 shown in Figure 2.

[0032] The protective layer 103 may be formed using crystal growth technology, but as described above, it can be easily carried out by using a method of closely adhering the protective layer 103 as a flat protective substrate having a mirror-finished bonding surface 130. The formation of the protective layer 103 on the support substrate 102 side may be omitted as appropriate. That is, only the protective layer 103 covering the second main surface 112 of the nitride semiconductor layer 101 may be provided.

[0033] Next, in the fourth step P4, annealing, i.e., heat treatment for activating the ion implantation region, is performed. This effectively activates the implanted dopant, particularly the p-type dopant magnesium, and forms the body region 25, source region 26, and body contact region 27 shown in Figure 1. After annealing, the protective layer 103 is removed.

[0034] Then, in the fifth step P5, the drain electrode 4, source electrode 5, and insulating gate 6 are formed. Since the techniques for forming these are already well known at the time of filing this application, a detailed explanation is omitted. In this way, the semiconductor device 1 shown in Figure 1 can be manufactured.

[0035] (effect) The effects achieved by this embodiment will be explained below in comparison with the prior art.

[0036] In the prior art, a widely known technique involves using aluminum nitride as the material constituting the protective layer 103. However, in the prior art, there was still room for improvement regarding the protective effect on the surface of the nitride semiconductor layer 101 during annealing, that is, the effect of suppressing nitrogen detachment. Specifically, it was extremely difficult to almost completely suppress the generation of pits on the surface of the nitride semiconductor layer 101 with protection using an aluminum nitride layer.

[0037] More specifically, for example, if the aluminum nitride layer is thickened, cracks will occur during high-temperature heat treatment due to the difference in lattice constants between it and the constituent material of the nitride semiconductor layer 101 (e.g., gallium nitride). On the other hand, if the layer is made thinner to avoid such cracks, the nitrogen detachment suppression effect decreases, resulting in the generation of a large number of pits.

[0038] In this regard, the inventors, through diligent research, discovered that oxygen was influencing the surface roughness of the nitride semiconductor layer 101. Specifically, when the annealing conditions in which pits partially occurred (i.e., aluminum nitride layer thickness, atmospheric gas pressure, temperature, and time) were changed from a nitrogen atmosphere to a nitrogen atmosphere mixed with a certain amount of oxygen, pits occurred across the entire surface.

[0039] Therefore, the inventor focused on the oxygen barrier properties that prevent oxygen from acting on the surface of the nitride semiconductor layer 101. Specifically, the inventor found that by forming a protective layer 103 such that its oxygen barrier properties are higher than those of the aluminum nitride layer, pit formation can be suppressed more effectively than in the conventional method. The protective layer 103 is preferably formed from the material described above, which does not contain oxygen as a constituent element.

[0040] In this embodiment, the nitride semiconductor layer 101 is made of gallium nitride and / or aluminum gallium nitride. In this case, by making the protective layer 103 include a gallium nitride layer, it is possible to minimize the impact on the nitride semiconductor layer 101 and suppress device performance degradation very well. Furthermore, for example, it has been confirmed that a good surface condition of the nitride semiconductor layer 101 can be obtained even when annealing is performed under a pressure atmosphere exceeding atmospheric pressure (e.g., about 1400°C and 1 GPa) using a gallium nitride substrate as the protective layer 103. In addition, by lowering the surface roughness of the bonding surface 130, which is the main surface facing the nitride semiconductor layer 101 on the substrate-like protective layer 103, the adhesion of the protective layer 103 can be improved, thereby effectively suppressing the influence of oxygen in the atmospheric gas.

[0041] (Semiconductor laminate: Second embodiment) A second embodiment of this disclosure will be described below. In the following description of the second embodiment, i.e., this embodiment, the differences from the first embodiment described above will be mainly explained. In addition, parts that are the same or equivalent to each other in the first embodiment and this embodiment are denoted by the same reference numerals. Therefore, in the following description of this embodiment, with respect to components that have the same reference numerals as in the first embodiment, the description in the first embodiment may be appropriately referred to unless there is a technical inconsistency or additional explanation to be provided. The same applies to the third embodiment described later.

[0042] Figure 4 shows a schematic configuration of the semiconductor laminate 100 according to this embodiment. As shown in Figure 4, in this embodiment, the semiconductor laminate 100 further comprises an additional protective layer 104 made of aluminum nitride in addition to the protective layer 103.

[0043] The additional protective layer 104 is provided between the nitride semiconductor layer 101 and the protective layer 103. That is, the additional protective layer 104 is formed on the second main surface 112. The protective layer 103 is formed to cover the additional protective layer 104. In other words, this embodiment corresponds to the conventional technology in which the nitride semiconductor layer 101 is protected by an aluminum nitride layer, with the addition of the protective layer 103 according to this disclosure. The additional protective layer 104 may also be provided between the support substrate 102 and the protective layer 103.

[0044] When the nitride semiconductor layer 101 is made of gallium nitride and / or aluminum gallium nitride, the reactivity between the constituent materials of the nitride semiconductor layer 101 and aluminum nitride is low. Therefore, it is possible to minimize the impact on the nitride semiconductor layer 101 and suppress device performance degradation very well. Furthermore, by using a two-layer structure of protective layer 103 and additional protective layer 104, it is possible to effectively suppress the influence of atmospheric gas during annealing and effectively suppress the decrease in oxygen barrier properties due to the decomposition of the materials constituting the protective layer 103 and additional protective layer 104.

[0045] The protective layer 103 may be a silicon carbide layer instead of a gallium nitride layer. Similar effects can be achieved with this configuration as well.

[0046] (Semiconductor laminate: Third embodiment) A third embodiment of this disclosure will now be described. As shown in Figure 5, in this embodiment, the protective layer 103 has a carbon film 131 and a capping layer 132. In addition to the protective layer 103, the semiconductor laminate 100 may further include an additional protective layer 104 made of aluminum nitride.

[0047] The carbon film 131 is a carbon sputtered film provided to cover the second main surface 112, and is located inside the cap layer 132, i.e., on the nitride semiconductor layer 101 side. The cap layer 132 is the outermost layer of the protective layer 103 and is provided to be superimposed on the carbon film 131. The cap layer 132 is formed of a compound semiconductor material such as silicon carbide. With this configuration, even better heat resistance and oxygen barrier properties can be achieved. Furthermore, when a substrate-shaped cap layer 132 is used, the surface roughness of the bonding surface 130, which is the main surface facing the nitride semiconductor layer 101, can be reduced to improve adhesion, thereby effectively suppressing the influence of oxygen in the atmospheric gas.

[0048] (modified version) This disclosure is not limited to the embodiments described above. Therefore, the embodiments can be modified as appropriate. Representative modifications are described below. In the following description of modifications, the differences from the embodiments will be mainly described. In addition, parts that are the same or equivalent to each other in the embodiments and modifications are denoted by the same reference numerals. Therefore, in the following description of modifications, with respect to components that have the same reference numerals as in the embodiments, the descriptions in the embodiments can be appropriately referenced unless there is a technical inconsistency or additional explanation to be provided.

[0049] This disclosure is not limited to the shapes and structures specifically disclosed in the embodiments described above. That is, for example, the semiconductor device 1 may have a so-called trench gate type structure. Also, the protective layer 103 may have a multilayer structure of three or more layers. Specifically, for example, the protective layer 103 shown in Figures 2 and 4, and the cap layer 132 shown in Figure 5 may have a multilayer structure. In the case of a multilayer structure, each layer may be made of the same material but with different component ratios, or it may be made of different materials.

[0050] The protective layer 103 does not contain oxygen as a constituent element, but this does not mean that it contains absolutely no oxygen, and does not rule out the possibility of it being present at the level of impurities.

[0051] It goes without saying that the elements constituting the above embodiments are not necessarily essential unless explicitly stated to be particularly essential or considered to be fundamentally essential. Furthermore, when numerical values ​​such as the number, quantity, or range of components are mentioned, this disclosure is not limited to those specific numerical values ​​unless explicitly stated to be particularly essential or considered to be fundamentally limited to those specific numerical values. Similarly, when the shape, orientation, positional relationship, etc., of components are mentioned, this disclosure is not limited to those shape, orientation, positional relationship, etc., unless explicitly stated to be particularly essential or considered to be fundamentally limited to those specific shape, orientation, positional relationship, etc.

[0052] Modifications are not limited to the examples given above. That is, for example, multiple embodiments other than those exemplified above can be combined with each other, as long as they do not technically contradict each other. Similarly, multiple modifications can be combined with each other, as long as they do not technically contradict each other.

[0053] (Disclosure perspective) As is evident from the above description of embodiments and modifications, this specification discloses at least the following:

[0054] [Perspective 1-1] A semiconductor laminate (100), A nitride semiconductor layer (101) containing a dopant, A protective layer (103) covering the main surface (112) of the nitride semiconductor layer, Equipped with, The protective layer does not contain oxygen as a constituent element and is formed such that its oxygen barrier properties, which prevent the action of oxygen on the main surface, are higher than those of the aluminum nitride layer. Semiconductor laminate. [Perspective 1-2] The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer includes a gallium nitride layer. The semiconductor laminate described in perspective 1-1. [Perspectives 1-3] The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The aforementioned protective layer is Carbon film (131) and, A cap layer (132) superimposed on the carbon film, Includes, The aforementioned cap layer is made of a compound semiconductor material. A semiconductor laminate as described in perspective 1-1 or 1-2. [Perspectives 1-4] The aforementioned cap layer is made of silicon carbide. A semiconductor laminate as described in perspectives 1-3. [Perspectives 1-5] The system further comprises an additional protective layer (104) provided between the nitride semiconductor layer and the protective layer, The aforementioned additional protective layer is made of aluminum nitride. A semiconductor laminate described in any one of the following points 1-1 to 1-4. [Perspectives 1-6] The surface roughness Ra of the substrate surface (130) constituting the protective layer is 5 nm or less. A semiconductor laminate described in any one of the following points 1-1 to 1-5.

[0055] [Perspective 2-1] A semiconductor laminate (100), A nitride semiconductor layer (101) containing a dopant, A protective layer (103) covering the nitride semiconductor layer, Equipped with, The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer is a semiconductor laminate made of the material described in i) or ii) below; i) The protective layer includes a gallium nitride layer; ii) The protective layer comprises a carbon film (131) and a cap layer (132) superimposed on the carbon film, wherein the cap layer is made of a compound semiconductor material. [Perspective 2-2] The aforementioned cap layer is made of silicon carbide. The semiconductor laminate described in perspective 2-1. [Perspective 2-3] The system further comprises an additional protective layer (104) provided between the nitride semiconductor layer and the protective layer, The aforementioned additional protective layer is made of aluminum nitride. A semiconductor laminate as described in perspective 2-1 or 2-2. [Perspective 2-4] The surface roughness Ra of the substrate surface (130) constituting the protective layer is 5 nm or less. A semiconductor laminate described in any one of the following perspectives 2-1 to 2-3.

[0056] [Perspective 3-1] Semiconductor device (1), A semiconductor layer (2) containing a nitride semiconductor, The electrode (5) formed on the main surface (22) side of the semiconductor layer, Equipped with, The surface roughness Ra of the main surface is 5 nm or less. Semiconductor equipment. [Perspective 3-2] The semiconductor layer is made of gallium nitride or aluminum gallium nitride, and regions (25, 27) containing a p-type dopant are formed therein. Semiconductor device as described in perspective 3-1.

[0057] [Perspective 4-1] A method for manufacturing a semiconductor device (1), The protective layer formation involves covering the main surface (112) of the ion-implanted nitride semiconductor layer (101) with a protective layer (103), and The nitride semiconductor layer is heat-treated while being protected by the protective layer, in an annealing process, Includes, In forming the protective layer, the protective layer is formed such that it does not contain oxygen as a constituent element and has a higher oxygen barrier property than the aluminum nitride layer in preventing the action of oxygen on the main surface. A method for manufacturing a semiconductor device. [Perspective 4-2] The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer includes a gallium nitride layer. A method for manufacturing a semiconductor laminate as described in Perspective 4-1. [Perspective 4-3] The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. In forming the aforementioned protective layer, A carbon film (131) is formed to cover the main surface. A cap layer (132) made of a compound semiconductor material is placed on the carbon film. A method for manufacturing a semiconductor laminate according to viewpoint 4-1 or viewpoint 4-2. [Perspective 4-4] The aforementioned cap layer is made of silicon carbide. A method for manufacturing a semiconductor laminate as described in Perspective 4-3. [Perspectives 4-5] In forming the aforementioned protective layer, An additional protective layer (104) made of aluminum nitride is formed on the main surface. The protective layer is formed so as to cover the additional protective layer. A method for manufacturing a semiconductor laminate as described in any one of the viewpoints 4-1 to 4-4. [Perspective 4-6] The aforementioned annealing is performed under a pressure atmosphere exceeding atmospheric pressure. A method for manufacturing a semiconductor laminate as described in any one of the viewpoints 4-1 to 4-5. [Perspective 4-7] The surface roughness Ra of the substrate surface (130) constituting the protective layer is 5 nm or less. A method for manufacturing a semiconductor laminate as described in any one of the views 4-1 to 4-6. [Explanation of Symbols]

[0058] 10 Sliding member 11 Base material 111 Coating surface (outermost surface of the substrate) 112 Aluminum oxide coating 12 Solid lubricant film 121 Sliding surface

Claims

1. A semiconductor laminate (100), A nitride semiconductor layer (101) containing a dopant, A protective layer (103) covering the main surface (112) of the nitride semiconductor layer, Equipped with, The protective layer does not contain oxygen as a constituent element and is formed such that its oxygen barrier properties, which prevent the action of oxygen on the main surface, are higher than those of the aluminum nitride layer. Semiconductor laminate.

2. The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer includes a gallium nitride layer. The semiconductor laminate according to claim 1.

3. The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The aforementioned protective layer is Carbon film (131) and, A cap layer (132) superimposed on the carbon film, Includes, The aforementioned cap layer is made of a compound semiconductor material. The semiconductor laminate according to claim 1.

4. The aforementioned cap layer is made of silicon carbide. The semiconductor laminate according to claim 3.

5. The system further comprises an additional protective layer (104) provided between the nitride semiconductor layer and the protective layer, The aforementioned additional protective layer is made of aluminum nitride. The semiconductor laminate according to claim 1 or 2.

6. The surface roughness Ra of the surface (130) of the substrate constituting the protective layer is 5 nm or less. The semiconductor laminate according to claim 1 or 2.

7. A semiconductor laminate (100), A nitride semiconductor layer (101) containing a dopant, A protective layer (103) covering the nitride semiconductor layer, Equipped with, The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer is a semiconductor laminate made of the material described in i) or ii) below; i) The protective layer includes a gallium nitride layer; ii) The protective layer comprises a carbon film (131) and a cap layer (132) superimposed on the carbon film, wherein the cap layer is made of a compound semiconductor material.

8. Semiconductor device (1), A semiconductor layer (2) containing a nitride semiconductor, The electrode (5) formed on the main surface (22) side of the semiconductor layer, Equipped with, The surface roughness Ra of the main surface is 5 nm or less. Semiconductor equipment.

9. The semiconductor layer is made of gallium nitride or aluminum gallium nitride, and regions (25, 27) containing a p-type dopant are formed therein. The semiconductor device according to claim 8.

10. A method for manufacturing a semiconductor device (1), The protective layer formation involves covering the main surface (112) of the ion-implanted nitride semiconductor layer (101) with a protective layer (103), The nitride semiconductor layer is heat-treated while being protected by the protective layer, in an annealing process, Includes, In forming the protective layer, the protective layer is formed such that it does not contain oxygen as a constituent element and has a higher oxygen barrier property than the aluminum nitride layer in preventing the action of oxygen on the main surface. A method for manufacturing a semiconductor device.

11. The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. The protective layer includes a gallium nitride layer. A method for manufacturing a semiconductor laminate according to claim 10.

12. The nitride semiconductor layer is made of gallium nitride or aluminum gallium nitride. In forming the aforementioned protective layer, A carbon film (131) is formed to cover the main surface. A cap layer (132) made of a compound semiconductor material is placed on the carbon film. A method for manufacturing a semiconductor laminate according to claim 10.

13. The aforementioned cap layer is made of silicon carbide. A method for manufacturing a semiconductor laminate according to claim 12.

14. In forming the aforementioned protective layer, An additional protective layer (104) made of aluminum nitride is formed on the main surface. The protective layer is formed so as to cover the additional protective layer. A method for manufacturing a semiconductor laminate according to claim 10 or 11.

15. The aforementioned annealing is performed under a pressure atmosphere exceeding atmospheric pressure. A method for manufacturing a semiconductor laminate according to claim 10 or 11.

16. The surface roughness Ra of the surface (130) of the substrate constituting the protective layer is 5 nm or less. A method for manufacturing a semiconductor laminate according to claim 10 or 11.

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