Printed circuit board

Abstract

The present invention provides a printed circuit board that facilitates the formation of fine circuits, ensures size uniformity, provides partially protruding pads, and improves reliability issues related to the pads. [Solution] This disclosure relates to a printed circuit board comprising: a first insulating body; a plurality of first wiring layers disposed on or within the first insulating body; and a plurality of first via layers disposed within the first insulating body and connected to one or more of the plurality of first wiring layers, wherein the uppermost of the plurality of first wiring layers includes an embedded pattern embedded on the upper side of the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body, a protruding pattern is disposed on the embedded pattern, and the thickness of the embedded pattern is thinner than the thickness of the wiring pattern included in at least one of the remaining first wiring layers excluding the uppermost first wiring layer.

Description

Technical Field

[0001] The present disclosure relates to a printed circuit board.

Background Art

[0002] Due to the increasing performance of semiconductor chips such as the AP of smartphones, the CPU for servers, and AI accelerators, the demand for package substrates including high-density circuits is expanding. As a result, the bump pitch is decreasing, and higher multi-layers and larger areas are required. Also, in order to cope with the increasing input / output terminals, the technology for realizing fine circuits has become important.

Summary of the Invention

Problems to be Solved by the Invention

[0003] One of the various objectives of the present disclosure is to provide a printed circuit board that can be easily formed with fine circuits, can provide partially protruding pads with ensured size uniformity, and can improve reliability issues regarding the pads.

Means for Solving the Problems

[0004] One of the various solutions proposed in the present disclosure is to form a protruding pattern on the outermost embedded pattern of a coreless substrate to provide pads, and at this time, form the outermost embedded pattern relatively thinly to realize pads with desired dimensions.

[0005] For example, a printed circuit board according to one example includes a first insulating body, a plurality of first wiring layers disposed on or within the first insulating body, and a plurality of first via layers disposed within the first insulating body and connected to one or more of the plurality of first wiring layers, wherein the uppermost of the plurality of first wiring layers includes an embedded pattern embedded on the upper side of the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body, a protruding pattern is disposed on the embedded pattern, and the thickness of the embedded pattern may be thinner than the thickness of the wiring pattern included in at least one of the remaining first wiring layers excluding the uppermost first wiring layer.

[0006] For example, a printed circuit board according to one example includes a plurality of insulating layers, a plurality of wiring layers each disposed on or within the plurality of insulating layers, a plurality of via layers each disposed within the plurality of insulating layers and connected to one or more of the plurality of insulating layers, and a pattern layer disposed on the outermost wiring layer among the plurality of wiring layers and in direct contact with the outermost wiring layer, wherein the outermost wiring layer is embedded in the outermost insulating layer such that one side is exposed from one side of the outermost insulating layer among the plurality of insulating layers, and the thickness of the outermost wiring layer may be thinner than the thickness of each of the remaining wiring layers among the plurality of wiring layers. [Effects of the Invention]

[0007] One of the various effects of this disclosure is the ability to provide a printed circuit board that facilitates the formation of fine circuits, provides partially protruding pads with ensured size uniformity, and improves reliability issues with respect to the pads. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram illustrating an example of an electronic equipment system. [Figure 2]This is a schematic cross-sectional view showing an example of a printed circuit board. [Figure 3] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Figure 4] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Figure 5] Figure 2 is a schematic cross-sectional view showing an example of the manufacturing process of a printed circuit board. [Modes for carrying out the invention]

[0009] The following description of this disclosure will be made with reference to the attached drawings. The shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0010] Figure 1 is a block diagram illustrating an example of an electronic equipment system.

[0011] Referring to the drawing, the electronic device 1000 houses a main board 1010. The main board 1010 is physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040, etc. These are also coupled with other electronic components, which will be described later, to form various signal lines 1090.

[0012] Chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with each other. Chip-related components 1020 can also be in the form of a package containing the aforementioned chips and electronic components.

[0013] Network-related component 1030 includes, but is not limited to, any other wireless and wired protocols designated as Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth®, 3G, 4G, 5G, and later. It may also include any other numerous wireless or wired standards or protocols. Furthermore, network-related component 1030 can be combined with chip-related component 1020.

[0014] Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCCs (low-temperature co-firing ceramics), EMI (electromagnetic interference) filters, and MLCCs (multi-layer ceramic capacitors). However, they are not limited to these, and may also include passive elements in the form of chip components used for various other applications. Furthermore, other components 1040 can be combined with chip-related components 1020 and / or network-related components 1030.

[0015] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the main board 1010, or not connected. Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited to these, and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (e.g., hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. In addition, depending on the type of electronic device 1000, it may also include other electronic components used for various purposes.

[0016] Electronic device 1000 can be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smartwatch, automobile, server, etc. However, it is not limited to these, and can also be any other electronic device that processes data.

[0017] Figure 2 is a schematic cross-sectional view showing an example of a printed circuit board.

[0018] Referring to the drawings, an example printed circuit board 100A may include a first insulating body 111, a plurality of first wiring layers 112 arranged on or within the first insulating body 111, and a plurality of first via layers 113 arranged within the first insulating body 111 and connected to one or more of the plurality of first wiring layers 112. The uppermost of the plurality of first wiring layers 112 may include an embedded pattern M1 embedded on the upper side of the first insulating body 111 such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body 111. A pattern layer 115 including a protruding pattern M2 may be arranged on the uppermost first wiring layer 112 including the embedded pattern M1. The thickness of the embedded pattern M1 may be thinner than the thickness of the wiring pattern included in at least one of the remaining first wiring layers 112 excluding the uppermost first wiring layer 112. For example, the thickness of the uppermost first wiring layer 112 may be thinner than the thickness of each of the remaining first wiring layers 112.

[0019] As described above, the printed circuit board 100A according to this example can have a coreless structure, and the first wiring layer 112 located on the uppermost side can include an embedded trace substrate (ETS) type embedded pattern M1. Therefore, it is possible to easily realize fine circuits and reduce the overall thickness of the board. In addition, a protruding pattern M2 can be separately formed and arranged on the embedded pattern M1. In this case, the embedded pattern M1 and the protruding pattern M2 can be directly connected and / or in contact with each other, and as a result, a partially protruding pad including them can be provided. This makes it possible to provide a partially protruding pad with size uniformity, thereby improving the mounting quality of semiconductor chips and the like that mounted on the pad. Furthermore, when forming the protruding pattern M2, it is not necessary to expose a part of the embedded pattern M1 and form a partially protruding pad in the process of plasma etching the uppermost side of the first insulating body 111. In the case of such plasma etching, side effects such as crevice formation may occur, but this can be prevented by forming the protruding pattern M2. Therefore, the mounting reliability of semiconductor chips and the like mounted on the pad can be ensured. Furthermore, by forming the uppermost first wiring layer 112, which includes the embedded pattern M1, relatively thinner than the other first wiring layers 112, the overall thickness of the pad can be controlled, and the pad can be formed to a desired dimension.

[0020] On the other hand, the thickness of the pattern layer 115, which includes the protruding pattern M2, may be thinner than the thickness of the uppermost first wiring layer 112, which includes the embedded pattern M1. For example, the thickness of a partially protruding pad provided by the embedded pattern M1 and the protruding pattern M2 being in direct contact and / or connected to each other may be substantially the same as the thickness of a wiring pattern included in at least one of the remaining first wiring layers 112. For example, the sum of the thickness of the outermost first wiring layer 112 and the thickness of the pattern layer 115 may be substantially the same as the thickness of each of the remaining first wiring layers 112. For example, the thickness of the embedded pattern M1 may be about 10 μm, the thickness of the protruding pattern M2 may be about 4 μm, and therefore the thickness of the pad provided through them may be about 14 μm. Also, the wiring patterns included in each of the remaining first wiring layers 112 may be substantially identical to each other, with a thickness of about 14 μm. For example, the thickness of the embedded pattern M1 may be about 65% to 75% of the thickness of the wiring pattern included in at least one of the remaining first wiring layers 112, and the thickness of the protruding pattern M2 may be about 25% to 35% of the thickness of the wiring pattern included in at least one of the remaining first wiring layers 112. This makes it easy to control the thickness of the partially protruding pad provided via the embedded pattern M1 and the protruding pattern M2 within an appropriate range.

[0021] On one hand, the upper surface of the uppermost first wiring layer 112 including the embedded pattern M1 and the upper surface of the first insulating body 111 can be substantially coplanar with each other. For example, the uppermost first wiring layer 112 can be formed in an ETS (Embedded Trace Substrate) type, and even so, as in the process described later, the first wiring layer 112 disposed on the uppermost side can be protected during the etching process of the copper foil by a barrier layer containing nickel (Ni) or the like. Therefore, it is possible to prevent the occurrence of a recess step on the exposed surface of the first wiring layer 112 disposed on the uppermost side. In this case, when forming the pattern layer 115 including the protruding pattern M2 on the first wiring layer 112 disposed on the uppermost side including the embedded pattern M1, a flat surface can be provided, so that the pattern layer 115 including the protruding pattern M2 can be formed with a finer pitch, and the reliability can be further improved.

[0022] On the other hand, the uppermost first wiring layer 112 including the embedded pattern M1 may not include a separate seed layer for plating. For example, since the first wiring layer 112 disposed on the uppermost side can be formed in an ETS (Embedded Trace Substrate) type, the metal layer of the carrier can be used as the seed layer and the metal layer of the carrier can be removed, similar to the process described later. Also, the pattern layer 115 including the protruding pattern M2 may not include a separate seed layer for plating. For example, since the protruding pattern M2 can be formed by plating based on the embedded pattern M1, similar to the process described later, a separate seed layer may not be present between the protruding pattern M2 and the embedded pattern M1. In this case, the process can be more simplified, and undercuts and the like that may occur during the etching process of the seed layer can be prevented. However, it is not limited to this, and a separate seed layer may be formed when forming the pattern layer 115 including the embedded pattern M1 as needed. Separately from this, other first wiring layers 112 can include a seed layer. For example, they can be formed respectively in the seed layer formation and the plating process based thereon.

[0023] On the one hand, the width of the embedded pattern M1 and the protruding pattern M2 in the cross-section can be substantially the same as each other. Therefore, the side surfaces of the embedded pattern M1 and the protruding pattern M2 can have almost no step. In this case, it can be easier to provide a pad that protrudes partially with a desired dimension, and it can also be easier to ensure size uniformity. However, it is not limited to this, and if necessary, the width of the protruding pattern M2 in the cross-section may be narrower than the width of the embedded pattern M1 in the cross-section.

[0024] Referring to the drawings, a printed circuit board 100A according to an example may further include a second insulating body 121 disposed below the first insulating body 111, one or more second wiring layers 122 respectively disposed on or within the second insulating body 121, and one or more second via layers 123 respectively disposed within the second insulating body 121 and connected to one or more of the one or more second wiring layers 122. The plurality of first wiring layers 112 and the one or more second wiring layers 122 can be electrically connected to each other. At this time, the second insulating body 121 can include an insulating material different from the insulating material included in the first insulating body 111. For example, the second insulating body 121 can include an insulating material having a higher elastic modulus than the insulating material included in the first insulating body 121. In this case, it can be effective for warpage control. The second insulating body 121 can include an insulating material further including glass fibers in addition to the insulating resin and the inorganic filler, for example, prepreg. Also, the first insulating body 111 can include an insulating resin and an inorganic filler, but can include an insulating material that does not include glass fibers, for example, Ajinomoto Build-up Film (ABF). However, the material is not necessarily limited to this.

[0025] On the other hand, the connecting vias included in each of the multiple first via layers 113 and one or more second via layers 123 may have sides that are substantially tapered in the same direction in cross-section. For example, the connecting vias included in each of the multiple first via layers 113 and one or more second via layers 123 may have sides that are substantially tapered in cross-section, with the width of the upper end being narrower than the width of the lower end. As described above, since the first wiring sections 111, 112, and 113 can be formed on the carrier using the ETS method, and the second wiring sections 121, 122, and 123 can be formed on the first wiring sections 111, 112, and 113 using the coreless method, the multiple first via layers 113 and one or more second via layers 123 can have such a tapered structure.

[0026] Referring to the drawings, the printed circuit board 100A according to one example may further include a passivation layer 141 located below the second insulating body 121, having multiple openings that expose at least a portion of the lowest second wiring layer 122 among one or more second wiring layers 122. For example, the printed circuit board 100A according to one example may be a semiconductor package substrate or an interposer substrate, and may be mounted on a main board or other package substrate.

[0027] The components of a printed circuit board 100A, as an example, will be described in more detail below with reference to the drawings.

[0028] The first and second insulating bodies 111 and 121 may each contain an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may contain inorganic fillers, organic fillers and / or glass fibers together with these insulating resins. For example, the first insulating body 111 may contain an insulating material containing an insulating resin and an inorganic filler, such as Ajinomoto Build-Up Film (ABF), but is not limited thereto, and may also contain a photosensitive insulating material (PID), etc. The second insulating body 121 may contain an insulating material containing an insulating resin, an inorganic filler and glass fibers, such as a prepreg, but is not limited thereto. The first and second insulating bodies 111 and 121 may each contain one or more insulating layers or multiple insulating layers, and these insulating layers may have distinct boundaries or be integrated with each other with indistinct boundaries. The first and second insulating bodies 111 and 121 may contain multiple insulating layers from an overall perspective. In this case, the outermost insulating layer among the multiple insulating layers may have a partially protruding pad including the embedded pattern M1 and protruding pattern M2 described above. This outermost insulating layer contains insulating resin and inorganic filler, but does not necessarily contain glass fibers. Furthermore, the outermost insulating layer, which is located on the opposite side of the lamination direction from the outermost insulating layer described above, may contain insulating resin, inorganic filler, and glass fibers.

[0029] The first and second wiring layers 112, 122 and the pattern layer 115 can each contain metals. These metals can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the remaining parts of the first and second wiring layers 112, 122, excluding the uppermost first wiring layer 112, can each contain chemical copper formed by electroless plating as a seed layer, and electroplated copper formed by electroplating based on this can be included as a pattern plating layer. However, the invention is not limited to this, and the remaining parts of the first and second wiring layers 112, 122, excluding the uppermost first wiring layer 112, may each contain a titanium (Ti) layer and a copper (Cu) layer, etc., formed by sputtering as seed layers. The uppermost first wiring layer 112 and the pattern layer 115 can each contain electroplated copper formed by electroplating as a pattern plating layer. For example, the embedded pattern M1 and the protruding pattern M2 may each include electroplated copper as a pattern plating layer. The first and second wiring layers 112, 122 and the pattern layer 115 can each perform various functions depending on the design. For example, the first and second wiring layers 112, 122 and the pattern layer 115 may each include signal transmission patterns, power transmission patterns, ground transmission patterns, etc. On the other hand, these patterns can have various pattern forms such as lines, traces, planes, pads, and lands. The first and second wiring layers 112, 122 may each consist of one or more layers.

[0030] The first and second via layers 113 and 123 can each contain a metal. The metal can include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. For example, the first and second via layers 113 and 123 can each contain chemical copper formed by electroless plating as a seed layer, and electrocopper formed by electroplating based on this as a pattern plating layer. However, the first and second via layers 113 and 123 may each contain a titanium (Ti) layer and a copper (Cu) layer formed by sputtering as seed layers. The first and second via layers 113 and 123 can each perform various functions depending on the design. For example, the first and second via layers 113 and 123 can each contain a signal transmission via, a power transmission via, a ground transmission via, and so on. On the other hand, the connecting vias included in the first and second via layers 113 and 123, respectively, may have substantially tapered sides in cross-section, where the width of the upper end is narrower than the width of the lower end. There may be multiple connecting vias included in the first and second via layers 113 and 123, respectively. The connecting vias included in the first and second via layers 113 and 123, respectively, may have a fill-plated via structure, but are not limited to this, and may also have a conformally plated via structure.

[0031] The passivation layer 141 may include an organic insulating material. The organic insulating material may be a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or may include an inorganic filler and / or organic filler together with the resin. For example, the organic insulating material may be, but is not limited to, Ajinomoto build-up film (ABF), photosensitive insulating material (PUD), solder resist (SR), etc. The passivation layer 141 may have a plurality of openings that each expose at least a portion of the bottommost second wiring layer 122. At least a portion of the bottommost second wiring layer 122 exposed through each of the plurality of openings may be of the SMD (Solder Mask Defined) and / or NSMD (Non Solder Mask Defined) type.

[0032] Figures 3 to 5 are schematic cross-sectional views illustrating an example of the manufacturing process of the printed circuit board shown in Figure 2.

[0033] Referring to Figure 3, first, a carrier 210 can be prepared. The carrier 210 may include a core material 211 and a plurality of metal layers 212, 213 arranged on both sides of the core material 211. The core material 211 may be, but is not limited to, an organic insulating material with excellent rigidity containing insulating resin, inorganic filler, and glass fiber, and may also be an inorganic insulating material such as glass, ceramic, or silicon. The plurality of metal layers 212, 213 may each contain copper (Cu), but is not limited to, and may contain other metals. Next, a barrier layer 221 can be formed on the metal layer 213. The barrier layer 221 may contain nickel (Ni), but is not limited to, and may contain other metals different from those in the metal layer 213. Next, a first wiring layer 112 including an embedded pattern M1 can be formed on the barrier layer 221. For example, a dry film 231 can be formed on the barrier layer 221, patterned in a photolithography process, and then electroplating or the like can be performed on the patterned openings of the dry film 231 to form an ETS (Embedded Trace Substrate) pattern in the M1 layer. Next, the dry film 231 can be removed in a peeling process, and the first insulating layer constituting the first insulating body 111 can be formed in a lamination process. In addition, via holes that expose at least a portion of the embedded pattern M1 can be formed in the first insulating layer constituting the first insulating body 111 by laser processing. Next, a first wiring layer 112 can be further formed on the first insulating layer constituting the first insulating body 111 using a circuit formation process such as SAP (Semi Additive Process), and a first via layer 113 can be formed in the via holes.

[0034] Referring to Figure 4, next, a build-up process or coreless process can be performed by repeatedly performing the lamination process, via hole processing, and circuit formation process described above to form the first insulating body 111, a plurality of first wiring layers 112, and a plurality of first via layers 113. A second insulating body 121, one or more second wiring layers 122, and one or more second via layers 123 can also be formed. Furthermore, a passivation layer 141 can be formed in a coating process or lamination process. Next, the laminate manufactured from the carrier 210 can be separated. For example, the plurality of metal layers 212 and 213 of the carrier 210 can be separated from each other. At this time, the metal layer 213 and the barrier layer 221 may remain in the laminate. On the other hand, since laminates can be formed on both sides of the carrier 210, multiple laminates can be obtained after separation. The laminates can be inverted vertically as needed.

[0035] Referring to Figure 5, the metal layer 213 and the barrier layer 221 can then be removed sequentially. The metal layer 213 and the barrier layer 221 can be removed in their respective etching processes, and the barrier layer 221 can not be etched during the etching process of the metal layer 213. Thus, the outermost first wiring layer 112, for example, the uppermost first wiring layer 112 including the embedded pattern M1, can be protected. Thus, the upper surface of the uppermost first wiring layer 112 including the embedded pattern M1 can be substantially coplane with the upper surface of the first insulating body 111. Next, a protruding pattern M2 can be directly formed on the embedded pattern M1 to form a partially protruding pad. For example, a dry film 232 can be formed on the first insulating body 111, the dry film 232 can be patterned to create an opening that exposes the embedded pattern M1, and the opening can be filled to a desired thickness by electroplating to form a pattern layer 115 including the protruding pattern M2. For example, the pattern layer 115 including the protruding pattern M2 can be formed in an SAP (Semi Additive Process) process. Next, the dry film 232 can be removed in the peeling process.

[0036] Through a series of processes, the printed circuit board 100A according to the example described above can be manufactured. Other details may be substantially the same as those described for the printed circuit board 100A according to the example described above.

[0037] In this disclosure, the expression "cover" can include not only covering the entire surface but also covering at least a portion of it, and can include not only direct covering but also indirect covering. Similarly, the expression "fill" can include not only completely filling the surface but also filling at least a portion of it, and can also include roughly filling the surface. For example, this can include cases where there are some gaps or voids. Furthermore, the expression "enclose" can include not only completely enclosing the surface but also partially enclosing or roughly enclosing it. Moreover, "expose" can include not only completely exposing the surface but also partially exposing it, and exposure can mean exposing the surface to other surfaces in which the surface is embedded. For example, an opening exposing a pad can mean exposing the pad from a resist layer, and a surface treatment layer or the like may be further placed on the exposed pad.

[0038] In this disclosure, the determination can be made including process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, substantially coplane means not only when it is perfectly coplane, but also when it is approximately coplane. Similarly, substantially having a specific shape means not only when it is exactly that shape, but also when it is approximately that shape. Furthermore, substantially identical insulating materials can mean not only when they are completely identical insulating materials, but also when they are of the same type. Therefore, the composition of the insulating materials may be substantially the same, but their specific composition ratios may differ slightly.

[0039] In this disclosure, "cross-sectional" can mean the cross-sectional shape when the object is cut vertically, or the cross-sectional shape when the object is viewed from the side. "Planar" can mean the planar shape when the object is cut horizontally, or the planar shape when the object is viewed from the top or bottom.

[0040] In this disclosure, terms such as "lower side," "bottom," and "bottom surface" are used for convenience to mean the downward direction relative to the cross-section of the drawing, while terms such as "upper side," "top," and "top surface" are used to mean the opposite direction. However, this is merely a definition of direction for explanatory purposes, and the scope of the claims is not specifically limited by such descriptions of direction, and the concepts of "upper" and "lower" can change at any time.

[0041] In this disclosure, the term "connected" includes not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" includes both physically connected and non-connected cases. In addition, expressions such as "first," "second," etc., are used to distinguish one component from another and do not limit the order and / or importance of those components. In some cases, without departing from the scope of the rights, the first component may be named the second component, and similarly, the second component may be named the first component.

[0042] In this disclosure, thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness, etc., can be measured using a scanning microscope or optical microscope, based on a cross-section obtained by polishing or cutting the printed circuit board. The cut cross-section can be a vertical or horizontal cross-section, and the values ​​can be measured based on the required cut cross-section. For example, the width of the upper and / or lower ends of a via can be measured on a cross-section obtained by cutting the central axis of the via. In this case, if the values ​​are not constant, the values ​​can be determined by taking the average of the values ​​measured at any five points.

[0043] The expression "example" as used in this disclosure does not mean that each embodiment is identical to the others, but is provided to highlight and illustrate the unique and distinct features of each embodiment. However, the examples presented above do not preclude their implementation in combination with features of other examples. For example, even if a matter described in one example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that contradicts or inconsistes with that matter.

[0044] The terms used in this disclosure are for illustrative purposes only and are not intended to limit the disclosure. Where otherwise, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0045] 1000 electronic equipment 1010 Mainboard 1020 Chip-related components 1030 Network-related components 1040 Other parts 1050 Camera 1060 Antenna 1070 Display 1080 Battery 1090 signal line 100A Printed Circuit Board 111, 121 Insulating body 112, 122 wiring layer 113, 123 via layers 115 pattern layers 141 Passivation Layer M1 Embedding Pattern M2 protruding pattern 210 carriers 211 Core material 212, 213 metal layer 221 Barrier layer 231, 232 Dry film

Claims

1. First insulating body and A plurality of first wiring layers are disposed on or inside the first insulating body, It includes a plurality of first via layers, each disposed within the first insulating body and each connected to one or more of the plurality of first wiring layers, The uppermost of the plurality of first wiring layers includes an embedded pattern embedded on the upper side of the first insulating body such that at least a portion of its upper surface is exposed from the upper surface of the first insulating body. A protruding pattern is arranged on the aforementioned embedded pattern. A printed circuit board in which the thickness of the embedded pattern is thinner than the thickness of a wiring pattern included in at least one of the remaining first wiring layers, excluding the uppermost first wiring layer.

2. The printed circuit board according to claim 1, wherein the thickness of the protruding pattern is thinner than the thickness of the embedded pattern.

3. The printed circuit board according to claim 2, wherein the embedded pattern and the protruding pattern are directly connected to each other.

4. The embedded pattern and the protruding pattern are directly connected to each other to provide a pad. The printed circuit board according to claim 3, wherein the thickness of the pad is substantially the same as the thickness of the wiring pattern included in at least one of the remaining first wiring layers, excluding the uppermost first wiring layer.

5. The thickness of the embedded pattern is 65% to 75% of the thickness of the wiring pattern included in at least one of the remaining first wiring layers, excluding the uppermost first wiring layer. The printed circuit board according to claim 3, wherein the thickness of the protruding pattern is 25% to 35% of the thickness of a wiring pattern included in at least one of the remaining first wiring layers, excluding the uppermost first wiring layer.

6. The printed circuit board according to claim 1, wherein the embedded pattern and the first insulating body have substantially coplane upper surfaces.

7. The printed circuit board according to claim 1, wherein the protruding pattern has substantially the same width in cross-section as the embedded pattern.

8. The remaining first wiring layers, excluding the uppermost first wiring layer, each include a seed layer. The printed circuit board according to claim 1, wherein the embedded pattern and the protruding pattern each do not include a seed layer.

9. A second insulating body is positioned below the first insulating body, One or more second wiring layers are disposed on or inside the second insulating body, The invention further includes one or more second via layers, each of which is disposed within the second insulating body and connected to one or more of the one or more second wiring layers, The plurality of first wiring layers and the one or more second wiring layers are electrically connected to each other. The printed circuit board according to claim 1, wherein the second insulating body includes an insulating material different from that of the first insulating body.

10. The printed circuit board according to claim 9, wherein the second insulating body includes an insulating material having a greater elastic modulus than the insulating material included in the first insulating body.

11. The printed circuit board according to claim 9, wherein each of the connecting vias included in the plurality of first and second via layers has substantially tapered sides in cross-section, with the width of the upper end being narrower than the width of the lower end.

12. The printed circuit board according to claim 9, further comprising a passivation layer disposed below the second insulating body and having a plurality of openings that expose at least a portion of the third wiring layer, which is the lowest of the one or more third wiring layers.

13. Multiple insulating layers, A plurality of wiring layers, each disposed on or within the plurality of insulating layers, A plurality of via layers, each disposed within the plurality of insulating layers and connected to one or more of the plurality of insulating layers, The pattern layer includes a pattern layer that is placed on the outermost wiring layer among the plurality of wiring layers and is in direct contact with the outermost wiring layer, The outermost wiring layer is embedded in the outermost insulating layer such that one side is exposed from one side of the outermost insulating layer among the plurality of insulating layers. A printed circuit board in which the thickness of the outermost wiring layer is thinner than the thickness of each of the remaining wiring layers among the plurality of wiring layers.

14. The printed circuit board according to claim 13, wherein the thickness of the pattern layer is thinner than the thickness of the outermost wiring layer.

15. The printed circuit board according to claim 13, wherein one surface of the outermost wiring layer is substantially coplane with one surface of the outermost insulating layer.

16. The printed circuit board according to claim 13, wherein each of the multiple via layers has connecting vias that are substantially tapered in the same direction in cross-section.

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