Functional safety test circuits and methods, neural network processors and storage media

Abstract

This application discloses functional safety test circuits and methods, neural network processors, and storage media, relating to the field of functional safety technology. [Solution] The functional safety test circuit includes a configurator for generating and outputting configuration information for testing an integrated circuit under test; a plurality of test data generators for generating and outputting first test data corresponding to each of the plurality of test data generators based on the configuration information; an integrated circuit under test for processing the plurality of first test data and acquiring and outputting a plurality of second test data; and a first comparator for comparing the consistency of the plurality of second test data and acquiring a first test result of the integrated circuit under test.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to functional safety test circuits and methods, devices, and storage media.

Background Art

[0002] Currently, functional safety (FuSa) tests are mainly performed on integrated circuits by means of parity check methods. When performing a FuSa test on the integrated circuit by means of the parity check method, in order to detect a possible failure occurring in the line used for data transmission by the transmission data with a parity bit added, it is necessary to add a parity bit to the transmission data in the integrated circuit. However, the parity check method can only detect whether an abnormality has occurred in the line used for data transmission in the integrated circuit, and cannot detect whether a failure has occurred in the arithmetic circuit that performs logical operations on the transmission data in the integrated circuit. Therefore, when the integrated circuit includes an arithmetic circuit, it is often difficult to meet the expected functional safety standards by performing a FuSa test by the parity check method. In addition, when performing a FuSa test on an integrated circuit by means of the parity check method, it is necessary to add a parity bit to the transmission data, which results in a large area overhead of the integrated circuit and high power consumption for data transmission.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The current functional safety test circuit cannot meet the expected functional safety standards, has high power consumption for data transmission, and has a large area overhead of the circuit.

Means for Solving the Problems

[0004] To solve the above technical problems, this disclosure provides a functional safety test circuit comprising: a configurator used to generate and output configuration information for testing an integrated circuit under test; a plurality of test data generators coupled with the configurator and used to generate and output first test data corresponding to each of the plurality of test data generators based on the configuration information; an integrated circuit under test coupled with the plurality of test data generators and used to process the plurality of first test data and acquire and output a plurality of second test data; and a first comparator coupled with the integrated circuit under test and used to compare the consistency of the plurality of second test data and acquire a first test result of the integrated circuit under test.

[0005] A second aspect of this disclosure provides a functional safety testing method for an integrated circuit, comprising the steps of: generating configuration information for testing an integrated circuit under test using a configurator; generating first test data corresponding to each of the multiple test data generators based on the configuration information using a plurality of test data generators; processing the plurality of first test data using the integrated circuit under test to obtain a plurality of second test data; and comparing the consistency of the plurality of second test data using a first comparator to obtain a first test result for the integrated circuit under test.

[0006] A third aspect of this disclosure provides a neural network processor comprising at least one functional safety test circuit of the first aspect described above.

[0007] A fourth aspect of this disclosure provides an electronic device including a memory for storing executable instructions for a processor, and a processor used to read and execute executable instructions from the memory to implement the functional safety test method for an integrated circuit of the second aspect.

[0008] A fifth aspect of the present disclosure provides a computer-readable storage medium which, when executed by a processor, stores a computer program for performing the functional safety test method of the integrated circuit of the second aspect described above. [Effects of the Invention]

[0009] The functional safety test circuit provided by the embodiments of this disclosure can perform processing on multiple first test data using only the integrated circuit under test, determine the first test result of the integrated circuit under test based on the consistency of the acquired multiple second test data, and realize FuSa testing of the circuits in the integrated circuit under test. When performing functional safety testing on the integrated circuit under test, the functional safety test circuit provided by this disclosure not only meets the expected functional safety standards but also reduces the area overhead of the integrated circuit and lowers the power consumption of data transmission because it does not require adding parity bits to the transmission data of the integrated circuit under test. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram of a functional safety test circuit that provides FuSa protection using a parity check scheme provided in one exemplary embodiment of the present disclosure. [Figure 2] This is a schematic diagram of a functional safety test circuit provided by one exemplary embodiment of the present disclosure. [Figure 3] This is a schematic diagram of another functional safety test circuit provided by one exemplary embodiment of the present disclosure. [Figure 4] This is a schematic diagram of yet another functional safety test circuit provided by one exemplary embodiment of the present disclosure. [Figure 5] This is a schematic diagram of yet another functional safety test circuit provided by one exemplary embodiment of the present disclosure. [Figure 6] This is a schematic diagram of yet another functional safety test circuit provided by one exemplary embodiment of the present disclosure. [Figure 7]This is a flowchart illustrating the implementation of a functional safety test method for an integrated circuit provided by one exemplary embodiment of the present disclosure. [Figure 8] This is a flowchart illustrating the implementation of a functional safety test method for another integrated circuit provided by one exemplary embodiment of the present disclosure. [Figure 9] This is a flowchart illustrating the implementation of yet another functional safety test method for an integrated circuit provided by one exemplary embodiment of the present disclosure. [Figure 10] This is a flowchart illustrating the implementation of yet another functional safety test method for an integrated circuit provided by one exemplary embodiment of the present disclosure. [Figure 11] This is a schematic diagram of a neural network processor provided by one exemplary embodiment of the present disclosure. [Figure 12] This is a schematic diagram of an electronic device provided by one exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0011] To illustrate this disclosure, exemplary embodiments of this disclosure will be described in detail below with reference to the drawings. Clearly, the embodiments described are only some of the embodiments of this disclosure, not all embodiments, and it should be understood that this disclosure is not limited to exemplary embodiments.

[0012] It should be noted that the relative arrangements of parts and steps, formulas, and numerical values ​​described in these embodiments do not limit the scope of this disclosure unless specifically stated otherwise.

[0013] Summary of this application In the field of integrated circuits, the FuSa mechanism is an important technical means of ensuring that integrated circuit systems (e.g., System on Chip, SOC) operate safely and reliably. Typically, different FuSa test schemes can be employed for circuits with different functions and characteristics in an integrated circuit system.

[0014] In the related art, for integrated circuits with relatively simple logic, a relatively large number of arithmetic circuits, and a relatively large circuit area, the FuSa test is mainly performed by a parity check method. Taking the case where the integrated circuit is a tensor core in a neural network processor as an example, when performing the FuSa test on the tensor core by the parity check method, it is necessary to add a parity bit to the transmission data when the tensor core actually operates, and detect whether there is a fault in the line used for data transmission based on the transmission data with the parity bit added, thereby realizing the FuSa test for the tensor core.

[0015] FIG. 1 is a schematic structural diagram of a functional safety test circuit for performing a FuSa test by a parity check method provided by one exemplary embodiment of the present disclosure. The functional safety test circuit 10 is used to perform a FuSa test on the tensor core 11. As shown in FIG. 1, the functional safety test circuit 10 may include a first arithmetic circuit 101, an encoder 103, a decoder 104, and a second arithmetic circuit 102 that are sequentially connected. Here, the tensor core 11 includes the first arithmetic circuit 101 and the second arithmetic circuit 102. The encoder 103 and the decoder 104 are detection circuits installed between the first arithmetic circuit 101 and the second arithmetic circuit 102 when performing the FuSa test on the tensor core 11.

[0016] The process of performing the FuSa test on the tensor core 11 by the parity check method will be described below.

[0017] First, the encoder 103 adds a parity bit to the output signal SIG_0 of the first arithmetic circuit 101, obtains an encoded signal SIG_1, and outputs it. Then, the decoder 104 performs decoding on the encoded signal SIG_1, obtains a decoded signal SIG_2, and outputs it to the second arithmetic circuit 102. The second arithmetic circuit 102 performs corresponding arithmetic processing on the decoded signal SIG_2, obtains an arithmetic signal SIG_3, and outputs it.

[0018] When performing the FuSa test on the tensor calculation core 11, the decoder 104 can also calculate the number of logical values "1" in the received encoded signal SIG_1 to determine the parity of the received SIG_1, and based on the consistency between the parity represented by the number of logical values "1" and the parity represented by the parity bit, determine whether an abnormality occurs when transmitting the encoded signal SIG_1 between the first arithmetic circuit 101 and the second arithmetic circuit 102, thereby realizing the FuSa test for the first arithmetic circuit 101 and the second arithmetic circuit 102.

[0019] When another arithmetic circuit is further coupled to the subsequent stage of the second arithmetic circuit 102, an encoder and a decoder sequentially coupled between the second arithmetic circuit 102 and the other arithmetic circuit can be installed. Similarly, in order to realize the FuSa test for the second arithmetic circuit 102 and the other arithmetic circuit, the encoder and the decoder perform decoding processing and encoding processing on the arithmetic signal SIG_3 sequentially.

[0020] When performing the FuSa test on the tensor calculation core using the above parity check method, it is only possible to detect whether there is an abnormality in the line used for data transmission in the tensor calculation core, and it is impossible to detect whether there is an abnormality in the arithmetic circuit in the tensor calculation core, and it is impossible to perform the FuSa test on all the circuits in the entire tensor calculation core, so the expected functional safety standard is not reached. Also, the encoded signal is a signal after adding a parity bit to the transmission data, and since the bit width is larger than the transmission data, in order to transmit the encoded signal via the line between the arithmetic circuits, it is necessary to increase the line area between the arithmetic circuits, which will increase the area overhead of the integrated circuit. At the same time, when transmitting the encoded signal after adding a parity bit via the line between the arithmetic circuits, a larger power consumption for data transmission also occurs.

[0021] Based on the above technical challenges, an embodiment of the present disclosure provides a functional safety test circuit in which a configurator generates configuration information for performing a functional safety test on an integrated circuit under test, a plurality of test data generators then generate a plurality of first test data based on the configuration information, the integrated circuit under test then processes the plurality of first test data to obtain a plurality of second test data, and finally, a first comparator compares the consistency of the plurality of second test data to obtain a first test result for the integrated circuit under test.

[0022] In this way, the integrated circuit under test processes multiple first test data, and based on the consistency of the acquired multiple second test data, the first test result of the integrated circuit under test is determined, thereby enabling FuSa testing of the integrated circuit under test. The functional safety test circuit provided by this disclosure not only enables the expected functional safety standards to be met when performing functional safety testing on the integrated circuit under test, but also reduces the area overhead of the integrated circuit and the power consumption of data transmission because it does not require the addition of parity bits to the transmission data of the integrated circuit under test.

[0023] Example circuit Figure 2 is a schematic diagram of a functional safety test circuit provided in one exemplary embodiment of the present disclosure. As shown in Figure 2, the functional safety test circuit 20 includes a configurator 201, a plurality of test data generators 202, an integrated circuit under test 203, and a first comparator 204.

[0024] Here, the configurator 201 is used to generate and output configuration information for testing the integrated circuit 203 under test, the multiple test data generators 202 are coupled with the configurator 201 and are used to generate and output first test data corresponding to each of the multiple test data generators 202 based on the configuration information, the integrated circuit 203 under test is coupled with the multiple test data generators 202 and is used to process the multiple first test data and obtain and output multiple second test data, and the first comparator 204 is coupled with the integrated circuit 203 under test and is used to compare the consistency of the multiple second test data and obtain the first test result of the integrated circuit 203 under test.

[0025] For example, the configurator 201 may be an Address Generation Unit (AGU) for instruction analysis and control on an in-vehicle SOC. The configurator 201 may also include a control input terminal and a configuration output terminal. The control input terminal of the configurator 201 is used to receive test instructions output by the compiler. In response to the test instructions, the configurator 201 is used to generate configuration information for performing functional safety tests on the integrated circuit 203 under test, and to output this configuration information via the configuration output terminal.

[0026] In some embodiments, the configuration information may include instructions for configuring the test data generator 202 to generate test data, and the type of instructions included in the configuration information relates to a test scheme for performing functional safety tests on the integrated circuit 203 under test.

[0027] For example, a test method for performing functional safety testing on the integrated circuit 203 under test may include random data testing and preset data testing. If the test method is random data testing, the configuration information includes a test start command and a test end command. If the test method is preset data testing, i.e., if the test is performed using fixed test data, the configuration information includes not only a test start command and a test end command, but also control commands for controlling the test data generator 202 to generate the preset test data. The embodiments of this disclosure do not limit the specific content of the configuration information, and the following embodiments provide an illustrative explanation using the example that the configuration information includes a test start command and a test end command.

[0028] Exemplary, depending on the differences in the test scheme, the multiple test data generators 202 may include at least one type of data generator. In some examples, the multiple test data generators 202 may include multiple random data generators and may also include multiple preset data generators.

[0029] A random data generator is used to generate random test data, which is uncontrollable and unknown test data. Therefore, a random data generator can generate different test data at different times in response to a test start command.

[0030] A preset data generator is used to generate preset test data, which is test data corresponding to control commands. Therefore, a preset data generator can generate preset test data corresponding to each control command in response to a test start command and different control commands.

[0031] In some other examples, the multiple test data generators 202 may include at least one random data generator and at least one preset data generator. The types of data generators included in the multiple test data generators 202 are related to the circuit structure of the integrated circuit 203 under test.

[0032] For example, if the integrated circuit 203 under test includes multiple data processing circuits, and each data processing circuit includes multiple identical data processing sub-circuits, then FuSa testing can be performed on the integrated circuit 203 under test using the same test data, or FuSa testing can be performed on the integrated circuit 203 under test using different test data. Therefore, the multiple test data generators 202 may be random data generators or preset data generators.

[0033] Furthermore, for example, if the integrated circuit 203 under test includes multiple data processing circuits, and at least some of these data processing circuits include different data processing sub-circuits, then the only option is to use the same test data to perform FuSa testing on the integrated circuit 203 under test. Therefore, the multiple test data generators 202 may be preset data generators.

[0034] The number of test data generators 202 is related to the circuit structure of the integrated circuit 203 under test. In some examples, the number of test data generators 202 corresponds to the number of data input terminals included in the integrated circuit 203 under test. For example, if the integrated circuit 203 under test includes three data input terminals, then the test data generators 202 include three test data generators 202. Taking the test data generators 202 as random data generators, the test data generators 202 may include a first random data generator, a second random data generator, and a third random data generator.

[0035] For example, each of the multiple test data generators 202 includes a configuration input terminal and a data output terminal. The configuration input terminals of the test data generators 202 are all connected to the configuration output terminals of the configurator 201.

[0036] Let's take the example where the test data generator 202 is a random data generator and the configuration information includes a test start command. In some examples, the test data generator 202 receives a test start command output from the configurator 201, generates random test data in response to the test start command, and outputs the random test data via the data output terminal. In this case, the first test data corresponding to the test data generator 202 is random test data.

[0037] For example, the test data generator 202 is a preset data generator, and the configuration information includes a test start command and a control command for generating preset test data. In some other examples, the test data generator 202 receives the test start command and control command output from the configurator 201, generates preset test data corresponding to the control command in response to the test start command and control command, and outputs the preset test data via the data output terminal. In this case, the first test data corresponding to the test data generator 202 is the preset test data.

[0038] Exemplary, the first test data may be a test sequence comprising multiple first and second levels. In some examples, the first level may be a logical low level "0" and the second level may be a logical high level "1", and in some other examples, the first level may be a logical high level "1" and the second level may be a logical low level "0". The embodiments of this disclosure do not limit the specific levels of the first and second levels. The embodiments of this disclosure provide an illustrative explanation using the example that the first level is a logical low level "0" and the second level is a logical high level "1".

[0039] In some cases, to cover many possibilities and improve the accuracy of the test, the first test data may be a test sequence where the number of high-low level inversions is greater than the preset number. For example, if the preset number is 5, and one inversion is defined as inverting from low level 0 to high level 1 and then again from high level 1 to low level 0, then the first test data may be 010110001001110011110000.

[0040] In some cases, the first test data can correspond to the type of test data generator 202. If the type of test data generator 202 is a random data generator, the first test data is a random test sequence and may also be called random test data. If the type of test data generator 202 is a preset data generator, the first test data is a preset test sequence and may also be called preset test data.

[0041] The first test data generated by each of the multiple test data generators 202 may be the same or different. The embodiments of this disclosure do not limit the consistency of the first test data generated by each test data generator 202. The embodiments of this disclosure provide an illustrative example of the case where the first test data generated by each test data generator 202 is different.

[0042] In some examples, if each test data generator 202 is a random data generator, the first test data generated by each test data generator 202 may be different. In some other examples, if each test data generator 202 is a preset data generator and each test data generator 202 receives and responds to the same control command, each test data generator 202 will generate the same first test data.

[0043] In embodiments of this disclosure, the integrated circuit 203 under test may be any integrated circuit in the SOC that has relatively simple logic, a relatively large number of arithmetic circuits, and a relatively large area. In some examples, the integrated circuit 203 under test may be an integrated circuit other than the neural network processor on the SOC. For example, the integrated circuit 203 under test may be a tensor computation core other than the neural network processor of the SOC. In some other examples, the integrated circuit 203 under test may be an integrated circuit within the neural network processor of the SOC, for example, the integrated circuit 203 under test may be a tensor computation core within the neural network processor of the SOC. Embodiments of this disclosure provide an illustrative description using the example that the integrated circuit 203 under test is a tensor computation core within the neural network processor of the SOC.

[0044] The data input terminal of the integrated circuit 203 under test is connected to the data output terminals of multiple test data generators 202, and is used to receive the first test data output by each test data generator 202 and to acquire multiple first test data.

[0045] Exemplary, the configurator 201 further includes a control output terminal. The configurator 201 is also used to generate circuit control signals to control the integrated circuit 203 under test to perform corresponding data processing based on the test instructions output by the compiler, and to output the circuit control signals via the control output terminal.

[0046] The integrated circuit 203 under test further includes a control signal input terminal. This control signal input terminal is coupled to the control output terminal of the configurator 201 and is used to receive circuit control signals. The integrated circuit 203 under test is used to sequentially perform pre-processing, arithmetic operations, and post-processing on a plurality of first test data in response to the circuit control signals, and to acquire a plurality of second test data.

[0047] For example, the number of first comparators 204 may be one or more, and the number of first comparators 204 is related to the number of second test data. In some examples, the number of first comparators 204 is half the number of second test data. For example, if the number of second test data is 64, then the number of first comparators 204 is 32.

[0048] Let's take the example where there are 64 sets of secondary test data and 32 first comparators 204. The 64 sets of secondary test data can be divided into pairs of two, yielding 32 sets of secondary test data. These 32 comparators can then perform a consistency comparison on each of the 32 sets of secondary test data, yielding 32 first comparison results. Furthermore, these 32 first comparison results can be determined as the first test results for the integrated circuit 203 under test.

[0049] In some examples, if the first level indicates that a set of test data being compared is the same, and the second level indicates that a set of test data being compared is different, then the first test result of the integrated circuit 203 under test can be determined to be a pass if all 32 first comparison results are at the first level, and the first test result of the integrated circuit 203 under test can be determined to be a fail if at least one of the 32 first comparison results is at the second level.

[0050] In some other examples, if the first level indicates that a set of test data being compared is different, and the second level indicates that a set of test data being compared is the same, then the first test result of the integrated circuit 203 under test can be determined to be a test failure when at least one of the 32 first comparison results contains the first level, and the first test result of the integrated circuit 203 under test can be determined to be a test pass when all 32 first comparison results are at the second level. The specific implementations of the first and second levels have already been described in the preamble, so the embodiments of this disclosure will not be described here.

[0051] The functional safety test circuit provided by the embodiments of this disclosure can process multiple first test data sets using only the integrated circuit under test, determine the first test result of the integrated circuit under test based on the consistency of the acquired multiple second test data sets, and realize FuSa protection for the circuits in the integrated circuit under test. The functional safety test circuit provided by this disclosure can not only achieve the expected functional safety standards when performing functional safety testing on the integrated circuit under test, but also reduce the area overhead of the integrated circuit and the power consumption of data transmission because it does not require adding parity bits to the transmitted data of the integrated circuit under test.

[0052] The configuration information relates to the test method of the integrated circuit 203 under test, and the test method of the integrated circuit 203 under test relates to the circuit structure of the integrated circuit 203 under test. Therefore, the configurator 201 can generate different configuration information for integrated circuits 203 under test having different structures. Furthermore, the test data generator 202 can generate corresponding first test data in response to different configuration information.

[0053] In some embodiments of this disclosure, the first test data may include random test data or preset test data. The test data generator 202 is used to generate random test data in response to configuration information including first subconfiguration information corresponding to random data tests, or the test data generator 202 is used to generate preset test data in response to configuration information including second subconfiguration information corresponding to preset data tests.

[0054] For example, if the test method used to perform functional safety testing on the integrated circuit 203 under test is a random data test, the first subconfiguration information may include instructions for configuring the test data generator 202 to generate random test data. For instance, the first subconfiguration information may include a test start instruction and a test end instruction.

[0055] If the test method used to perform functional safety testing on the integrated circuit 203 under test is a preset data test, the second subconfiguration information may include instructions for configuring the test data generator 202 to generate preset test data. For example, the second subconfiguration information may include a test start instruction, a test end instruction, and control instructions for controlling the test data generator 202 to generate preset test data.

[0056] In the functional safety test circuit provided by the embodiments of this disclosure, if the configuration information includes first sub-configuration information corresponding to random test data, the test data generator can generate corresponding random test data for performing random data testing on the integrated circuit under test, thereby meeting the actual test needs for performing random data testing on the integrated circuit under test based on random test data and performing functional safety testing on the integrated circuit under test. If the configuration information includes second sub-configuration information corresponding to preset data testing, the test data generator can generate corresponding preset test data for performing preset data testing on the integrated circuit under test, thereby meeting the actual test needs for performing preset data testing on the integrated circuit under test based on preset test data and performing functional safety testing on the integrated circuit under test.

[0057] In some other embodiments of this disclosure, if the test method for performing a functional safety test on the integrated circuit 203 under test is a preset data test, the functional safety test circuit 20 does not need to include a configurator 201 and a plurality of test data generators 202. The method by which the functional safety test circuit 20 acquires the first test data may include first writing the preset test data of the integrated circuit 203 under test to a preset storage area, and then, when performing a functional safety test on the integrated circuit 203 under test, reading the preset test data from the preset storage area via an external bus. In this way, the area overhead of the integrated circuit under test can be reduced.

[0058] Let's take the example that the integrated circuit 203 under test is a tensor computation core in the neural network processor of the SOC. The integrated circuit 203 under test may include multiple first data conversion circuits, an arithmetic logic circuit, and a second data conversion circuit. Here, the multiple first data conversion circuits can be used to preprocess multiple first test data and obtain and output the multiple preprocessed first test data. The arithmetic logic circuit can be used to perform arithmetic operations on the multiple preprocessed first test data and obtain multiple arithmetic operation data. The second data conversion circuit can be used to postprocess multiple arithmetic operation data and obtain multiple second test data.

[0059] As shown in Figure 3, based on the embodiment shown in Figure 2 above, the integrated circuit 203 under test can include a plurality of first data conversion circuits 2031, an arithmetic logic circuit 2032, and a second data conversion circuit 2033.

[0060] Here, the data input terminals of the multiple first data conversion circuits 2031 are the data input terminals of the integrated circuit 203 under test, each data input terminal of the first data conversion circuit 2031 is coupled to the data output terminals of the multiple test data generators 202, and the data output terminals of the multiple first data conversion circuits 2031 are coupled to the data input terminals of the arithmetic logic circuit 2032.

[0061] Multiple first data conversion circuits 2031 are used to perform first data conversion on multiple first test data, and to acquire and output multiple first converted data.

[0062] The data output terminal of the arithmetic logic circuit 2032 is connected to the data input terminal of the second data conversion circuit 2033. The arithmetic logic circuit 2032 is used to receive multiple first-converted data, perform arithmetic operations on the multiple first-converted data, and obtain and output multiple arithmetic operation data.

[0063] The data output terminal of the second data conversion circuit 2033 is the data output terminal of the integrated circuit 203 under test and is coupled to the first comparator 204. The second data conversion circuit 2033 is used to perform a second data conversion on multiple arithmetic operation data and to acquire and output multiple second test data.

[0064] For example, the first data transformation can correspond to the preprocessing described above, and the first data transformation may include processes such as data structure or data format transformation, data retiming, and data selection. The first transformed data may be data obtained after processing such as data structure or data format transformation, data tapping, and data selection has been performed on multiple first test data. The purpose of performing the first data transformation process on the first test data is to transform the first test data into data that matches the input request of the arithmetic logic circuit 2032, so the first transformed data matches the input request of the arithmetic logic circuit 2032.

[0065] Exemplary, as shown in Figure 3, each of the multiple first data conversion circuits 2031 may include multiple parallel-connected first data conversion subcircuits, and the data input terminal of each first data conversion subcircuit in the multiple first data conversion subcircuits is coupled to the data output terminals of multiple test data generators 202. In some examples, each first data conversion subcircuit in the first data conversion circuit 2031 can simultaneously receive multiple first test data output by multiple test data generators 202 and process the multiple first test data simultaneously. For example, each first data conversion subcircuit can receive multiple first test data, perform processing such as data structure or data format conversion, data tapping, and data selection on the multiple first test data, and be used to obtain first converted data that matches the input request of the arithmetic logic circuit 2032. Furthermore, multiple first converted data can be obtained through the first data conversion circuit 2031.

[0066] In the embodiments of this disclosure, the number of first data conversion circuits 2031 and the number of first data conversion subcircuits in each first data conversion circuit 2031 are related to the circuit structure of the integrated circuit 203 under test.

[0067] In some examples, the number of multiple first data conversion circuits 2031 corresponds to the number of data input terminals included in the integrated circuit 203 under test. Here, one data input terminal can receive data corresponding to one set of data sources. For example, if the integrated circuit 203 under test receives data from three sets of data sources, i.e., if the integrated circuit 203 under test includes three data input terminals, then the number of multiple first data conversion circuits 2031 is three. Embodiments of this disclosure do not limit the number of multiple first data conversion circuits 2031. The following embodiments illustrate the case where the number of multiple first data conversion circuits 2031 is three.

[0068] In some other examples, the number of first data conversion subcircuits in each first data conversion circuit 2031 corresponds to the degree of parallelism of the integrated circuit 203 under test, where parallelism refers to the number of corresponding data that the integrated circuit 203 under test can process simultaneously. For example, if the integrated circuit under test can process 8 data simultaneously, the first data conversion circuit 2031 may contain 8 first data conversion subcircuits. Alternatively, for example, if the integrated circuit under test can process 32 data simultaneously, the first data conversion circuit 2031 may contain 32 first data conversion subcircuits. Embodiments of this disclosure do not limit the number of first data conversion subcircuits in the first data conversion circuit 2031. The embodiments of this disclosure illustrate, for example, that there are three first data conversion circuits 2031, of which the first data conversion circuit 2031a includes eight first data conversion subcircuits, the first data conversion circuit 2031b includes 32 second data conversion subcircuits, and the first data conversion circuit 2031c includes eight third data conversion subcircuits.

[0069] For example, each of the multiple first data conversion circuits 2031 includes a control signal terminal, which is coupled to the control output terminal of the configurator 201.

[0070] For example, the first data conversion circuit 2031a includes a first control signal terminal, which is coupled to the control output terminal of the configurator 201. The circuit control signal output by the configurator 201 may include a first control signal corresponding to the first data conversion circuit 2031a. The first data conversion circuit 2031a receives a first control signal and, in response to the first control signal, selects multiple first data conversion subcircuits from the eight first data conversion subcircuits included in the first data conversion circuit 2031a to perform processing such as data structure or data format conversion, data tapping, and data selection on multiple first test data, and is used to obtain multiple first converted data.

[0071] Exemplary, the arithmetic logic circuit 2032 may be an arithmetic logic unit (ALU) and may include multiple adders, multiple multipliers, multiple saturation logic circuits, and multiple shift logic circuits.

[0072] In some examples, the arithmetic logic circuit 2032 further includes a control signal terminal, which is coupled to the control output terminal of the configurator 201. Correspondingly, the circuit control signal output by the configurator 201 may include a second control signal corresponding to the arithmetic logic circuit 2032. The arithmetic logic circuit 2032 receives the second control signal and, in response to the second control signal, selects at least one adder, at least one multiplier, at least one saturation logic circuit, and at least one shift logic circuit within the arithmetic logic circuit 2032 to perform arithmetic operations on a plurality of first transformed data and is used to obtain a plurality of arithmetic operation data.

[0073] For example, the second data transformation process may also be called post-processing, and the second data transformation is similar to the first data transformation, and the second data transformation may also include processes such as data structure or data format transformation, data tapping, and data selection. The second transformed data may be data obtained after processing such as data structure or data format transformation, data tapping, and data selection has been performed on the arithmetic operation data. The purpose of performing the second data transformation process on the arithmetic operation data in this disclosure is to transform the arithmetic operation data into data that matches the input requirements of the downstream circuit of the integrated circuit 203 under test, so the second transformed data matches the input requirements of the downstream circuit of the integrated circuit 203 under test.

[0074] Similar to the first data conversion circuit 2031, the second data conversion circuit 2033 may include multiple fourth data conversion subcircuits. The data input terminal of each fourth data conversion subcircuit is coupled to the data output terminal of the arithmetic logic circuit 2032. The fourth data conversion subcircuit receives arithmetic operation data, performs processing on the arithmetic operation data such as data structure or data format conversion, and is used to obtain second test data that matches the input requirements of the downstream circuit of the integrated circuit 203 under test.

[0075] In some examples, the second data conversion circuit 2033 may further include a control signal terminal, which is coupled to the configurator 201. Correspondingly, the circuit control signal output by the configurator 201 may include a third control signal corresponding to the second data conversion circuit 2032. The second data conversion circuit 2033 receives the third control signal and, in response to the third control signal, selects at least one fourth data conversion subcircuit from a plurality of fourth data conversion subcircuits included in the second data conversion circuit 2033. The selected at least one fourth data conversion subcircuit performs processing on multiple arithmetic operation data, such as data structure or data format conversion, data tapping, and data selection, and is used to obtain multiple second test data.

[0076] In the functional safety test circuit provided by the embodiments of this disclosure, multiple first data conversions can be performed on multiple first test data by multiple first data conversion circuits, thereby obtaining multiple first converted data suitable for processing by arithmetic logic circuits. By performing arithmetic operations on the multiple first converted data by arithmetic logic circuits, data calculation processing on the first test data can be realized. Furthermore, by performing second data conversions on multiple arithmetic calculation data by second data conversion circuits, multiple second test data suitable for data processing by subsequent circuits can be obtained. This enables functional safety testing of the integrated circuit under test.

[0077] In some embodiments of this disclosure, the arithmetic logic circuit 2032 may include at least one logic operation circuit, and the number of logic operation circuits included in the arithmetic logic circuit 2032 and the function of each logic operation circuit are related to the function and design of the integrated circuit 203 under test. The embodiments of this disclosure do not limit the number and function of logic operation circuits included in the arithmetic logic circuit 2032. The embodiments of this disclosure provide illustrative descriptions, for example, in which the arithmetic logic circuit 2032 includes a first logic operation circuit and a second logic operation circuit.

[0078] As shown in Figure 4, based on the embodiment shown in Figure 3 above, the arithmetic logic circuit 2032 includes a first logic operation circuit 401 and a second logic operation circuit 402.

[0079] The data input terminal of the first logic operation circuit 401 is the data input terminal of the arithmetic logic circuit 2032 and is connected to the data output terminals of multiple first data conversion circuits 2031, and the data output terminal of the first logic operation circuit 401 is connected to the data input terminal of the second logic operation circuit 402. The first logic operation circuit 401 is used to perform a first logic operation on multiple first conversion data and to obtain and output multiple first operation data.

[0080] The data output terminal of the second logic operation circuit 402 is the data output terminal of the arithmetic logic circuit 2032 and is connected to the data input terminal of the second data conversion circuit 2033. The second logic operation circuit 402 is used to perform second logic operation processing on multiple first operation data and to obtain and output multiple arithmetic operation data.

[0081] Exemplary, the first logic circuit 401 may include multiple adders and / or multiple multipliers having the same calculation logic. For example, the first logic circuit 401 may include 4k (thousand) adders and 4k multipliers. Alternatively, for example, the first logic circuit 401 may include 8k adders and 8k multipliers. Correspondingly, the first logic circuit 401 can be used to perform addition and multiplication operations on multiple first transformation data and to obtain multiple first operation data.

[0082] In some examples, the first logic circuit 401 includes a first control signal sub-terminal, which is coupled to the configurator 201. Correspondingly, the second control signal may include a first sub-control signal corresponding to the first logic circuit 401. The first logic circuit 401 is used to receive the first sub-control signal, select at least one adder and at least one multiplier in response to the first sub-control signal, perform addition and multiplication operations on a plurality of first transformation data, and obtain a plurality of first operation data.

[0083] Similarly, the second logic operation circuit 402 may be a logic matrix containing multiple identical logic circuits. Each logic circuit in the logic matrix can receive one first operation data output by the first logic operation circuit 401, and perform operations such as addition, saturation, shifting, quantization, and table lookup on the first operation data to obtain arithmetic operation data.

[0084] In some examples, the second logic circuit 402 includes a second control signal sub-terminal, which is coupled to the configurator 201. Correspondingly, the second control signal may include a second sub-control signal corresponding to the second logic circuit 402. The second logic circuit 402 is used to receive the second sub-control signal and, in response to the second sub-control signal, perform at least one operation from among the operations such as addition, saturation, shift, quantization, and table lookup on each of the multiple first operation data, in order to obtain arithmetic operation data.

[0085] Because each logic circuit in the second logic circuit 402 has fuzzy operations such as saturation and quantization, when determining the first test result of the integrated circuit 203 under test based on the consistency of the second test data corresponding to the multiple arithmetic operation data output by the second logic circuit 402, it is not possible to cover all failures in the preceding circuits of the second logic circuit 402 in the integrated circuit 203 under test. In other words, it is not possible to cover all failures of the multiple test data generators 202 and the first logic circuit 401, and the test coverage for the integrated circuit 203 under test can only reach 90%, not 100%. To improve the test coverage of the integrated circuit under test, in the embodiment of this disclosure, when multiple first operation data are input to the second logic circuit 402, a second comparator can be installed at the output terminal of the first logic circuit 401, and the second comparator compares the consistency of the multiple first operation data output by the first logic circuit 401 to realize detection of the preceding circuits of the second logic circuit 402.

[0086] As shown in Figure 5, based on the embodiment shown in Figure 4 above, the functional safety test circuit 20 further includes a second comparator 205.

[0087] The comparison data input terminal of the second comparator 205 is coupled to the output terminal of the first logic circuit 401. The second comparator 205 is used to compare the consistency of multiple first calculation data and to obtain a second test result of the integrated circuit under test.

[0088] Similar to the first comparator 204, the second comparator 205 also includes at least one comparator, and the number of comparators in the second comparator 205 is related to the amount of data of the multiple first calculation data. The embodiments of this disclosure omit a description of the implementation of the second comparator 205.

[0089] For example, the second test result of the integrated circuit 203 under test can correspond to the test result of the pre-processor circuit of the second logic operation circuit 402 in the integrated circuit 203 under test, and can be determined based on the consistency of multiple first operation data. In some examples, if multiple first operation data match, it is determined that the test of the pre-processor circuit of the second logic operation circuit 402 has passed. In some other examples, if multiple first operation data do not match, it is determined that the test of the pre-processor circuit of the second logic operation circuit 402 has failed.

[0090] Let's take an example where the number of first calculation data is 64, and the second comparator 205 contains 32 comparators. These 64 first calculation data can be divided into pairs of two first calculation data to obtain 32 pairs of first calculation data. Furthermore, by comparing the consistency of these 32 pairs of first calculation data using the 32 second comparators 205, that is, by comparing one pair of first calculation data with one comparator, 32 second comparison results can be obtained. These 32 second comparison results can then be determined as the second test results of the integrated circuit 203 under test. Since the second comparison results are similar to the realization of the first comparison results, the embodiments of this disclosure omit a description of the second comparison results.

[0091] If all 32 second comparison results are the same, for example, if all 32 second comparison results are either Level 1 or Level 2, the second test result of the integrated circuit 203 under test is determined to be a pass. If there are different second comparison results among the 32, for example, if the 32 second comparison results include one Level 1 and 31 Level 2, the second test result of the integrated circuit 203 under test is determined to be a fail.

[0092] The functional safety test circuit provided by the embodiments of this disclosure compares the consistency of multiple first arithmetic data using a second comparator and obtains a second test result for the integrated circuit under test. In this way, detection of the preceding circuit of the second logic arithmetic circuit in the integrated circuit under test can be achieved, and the test coverage of the integrated circuit under test can be improved.

[0093] In some embodiments of the present disclosure, the second comparator 205 is further used to determine expected data corresponding to preset test data in response to the first test data being preset test data, to compare the consistency between the first calculated data and the expected data, and to obtain a second test result, or to compare the consistency of multiple first calculated data in response to the first test data being random test data, and to obtain a second test result.

[0094] Exemplary, the expected data may be the data output by the first logic circuit 401 when preset test data is input to the integrated circuit 203 under test. In some examples, the expected data can be determined by inference based on the circuit structure of the integrated circuit 203 under test. In some other examples, the expected data can be determined by testing the integrated circuit 203 under test. The embodiments of this disclosure do not limit the method of acquiring the expected data, and the embodiments of this disclosure exemplify the example of inferring the expected data based on the circuit structure of the integrated circuit 203 under test.

[0095] In the embodiments of this disclosure, when performing a functional safety test on the integrated circuit 203 under test using preset test data, the second comparator 205 compares the data output by the first logic circuit 401 with the expected data for consistency, thereby obtaining a second test result for the integrated circuit 203 under test. This enables accurate functional safety detection of the preceding circuit of the second logic circuit 402 based on the second test result.

[0096] In the embodiments of this disclosure, when performing a functional safety test on the integrated circuit 203 under test using random test data, the second comparator 205 can directly compare the consistency of the data output by the first logic circuit 401 to obtain a second test result for the integrated circuit 203 under test. This enables accurate detection of the preceding circuit of the second logic circuit 402 based on the second test result.

[0097] As shown in Figure 6, based on the embodiment shown in Figure 3 above, the integrated circuit 203 under test further includes a Pipelining Register Unit 2034.

[0098] The data input terminal of the pipeline register unit 2034 is connected to the data output terminal of the arithmetic logic circuit 2032, and the output terminal of the pipeline register unit 2034 is connected to the data input terminal of the second data conversion circuit 2033. The pipeline register unit 2034 is used to perform temporary storage processing on multiple arithmetic operation data and to output the multiple arithmetic operation data after temporary storage processing.

[0099] In response to this, the second data conversion circuit 2033 receives multiple arithmetic operation data after temporary storage processing, performs a second data conversion process on the multiple arithmetic operation data after temporary storage processing, obtains multiple second test data, and is used to output multiple second test data to the first comparator 204.

[0100] Exemplary, the pipeline register unit 2034 may include at least one register. The number of registers in the pipeline register unit 2034 is related to the timing requirements of the integrated circuit under test, and the embodiments of this disclosure do not limit the number of registers.

[0101] The functional safety test circuit provided by the embodiments of this disclosure can perform temporary storage processing on multiple arithmetic operation data using a pipeline register unit, adjust the timing of the multiple arithmetic operation data, and ensure the timing accuracy of the integrated circuit under test.

[0102] Exemplary Method Figure 7 is a flowchart showing the implementation of a functional safety test method for an integrated circuit provided in one exemplary embodiment of the present disclosure. This functional safety test method can be applied to the functional safety test circuit described above to implement a functional safety test on the integrated circuit under test. As shown in Figure 7, the functional safety test method may include the following steps 701 to 704.

[0103] In step 701, the configurator generates configuration information for testing the integrated circuit under test.

[0104] In step 702, multiple test data generators generate first test data corresponding to each of the multiple test data generators based on the configuration information.

[0105] In step 703, the integrated circuit under test processes multiple first test data points and obtains multiple second test data points.

[0106] In step 704, the first comparator compares the consistency of multiple second test data to obtain the first test result for the integrated circuit under test.

[0107] In some embodiments, the first test data includes random test data or preset test data. Taking the first test data as an example, step 702 specifically includes generating random test data using a test data generator in response to first subconfiguration information corresponding to a random data test. Taking the first test data as an example, step 702 specifically includes generating preset test data using a test data generator in response to second subconfiguration information corresponding to a preset data test.

[0108] In some embodiments, the integrated circuit under test includes a plurality of first data conversion circuits, an arithmetic logic circuit, and a second data conversion circuit. As shown in Figure 8, based on the embodiment shown in Figure 7 above, step 703 may include the following steps 7031 to 7033.

[0109] In step 7031, multiple first data conversion circuits perform first data conversion on multiple first test data, and multiple first converted data are acquired and output.

[0110] In step 7032, an arithmetic logic circuit performs arithmetic operations on multiple first-converted data, and obtains and outputs multiple arithmetic operation data.

[0111] In step 7033, the second data conversion circuit performs a second data conversion on multiple arithmetic operation data, and acquires and outputs multiple second test data.

[0112] In some embodiments, the arithmetic logic circuit includes a first logic operation circuit and a second logic operation circuit. As shown in Figure 9, based on the embodiment shown in Figure 8 above, step 7032 may include the following steps 801 and 802.

[0113] In step 801, the first logic operation circuit performs the first logic operation on multiple first transformation data to obtain multiple first operation data.

[0114] In step 802, the second logic circuit performs second logic operations on multiple first operation data to obtain multiple arithmetic operation data.

[0115] In some embodiments, the functional safety test circuit further includes a second comparator. As shown in Figure 10, based on the embodiment shown in Figure 9 above, the functional safety test method may further include the following step 803.

[0116] In step 803, the second comparator compares the consistency of multiple first calculation data to obtain the second test result for the integrated circuit under test.

[0117] In some embodiments, step 803 specifically includes determining expected data corresponding to the preset test data in response to the first test data being preset test data using a second comparator, comparing the consistency between the first calculated data and the expected data, and obtaining a second test result, or comparing the consistency between multiple first calculated data in response to the first test data being random test data using a second comparator, and obtaining a second test result.

[0118] In some examples, the integrated circuit under test further includes a pipelined register unit. As shown in Figure 10, step 7033 specifically includes performing temporary storage processing on multiple arithmetic operation data using the pipelined register unit, outputting the multiple arithmetic operation data after temporary storage processing, performing a second data conversion process on the multiple arithmetic operation data after temporary storage processing using a second data conversion circuit, obtaining multiple second test data, and outputting the multiple second test data to the first comparator.

[0119] Regarding the functional safety test method for the integrated circuit in the above-described embodiment, the specific methods of each execution step and the corresponding beneficial effects have already been described in detail in the corresponding embodiment of the functional safety test circuit portion described above. Therefore, the corresponding execution methods and beneficial technical effects of the above-described exemplary circuit portion can be referenced, and the explanation is omitted here.

[0120] In some embodiments of this disclosure, if a system-on-a-chip (SOC) neural network processor includes multiple tensor computing cores, the neural network processor includes a corresponding number of functional safety test circuits.

[0121] Figure 11 is a schematic diagram of a neural network processor provided by one exemplary embodiment of the present disclosure. As shown in Figure 11, the neural network processor 110 includes at least one functional safety test circuit 20 shown in Figure 2.

[0122] Exemplary electronic device Figure 12 is a schematic diagram of an electronic device provided in one exemplary embodiment of the present disclosure, the electronic device 120 including one or more processors 1201 and memory 1202, as shown in Figure 12.

[0123] The processor 1201 may be a central processing unit (CPU) or another form of processing unit having data processing capability and / or instruction execution capability, and can control other components in the electronic device 120 to perform a desired function.

[0124] Memory 1202 may include one or more computer program products, including various forms of computer-readable storage media such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or fast cache memory (cache). Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be stored in the computer-readable storage media, and the processor 1201 can execute the computer program instructions to implement the functional safety test methods and / or other desired functions of the integrated circuits of each embodiment of the present disclosure described above.

[0125] In one example, the electronic device 120 may further include an input device 1203 and an output device 1204, and these components are connected to each other via a bus system and / or other forms of connection mechanisms (not shown).

[0126] Naturally, for the sake of simplification, Figure 12 shows only some of the components of the electronic device 120 relevant to this disclosure, and components such as buses and input / output interfaces are omitted. Beyond this, the electronic device 120 may include any other appropriate components depending on the specific application.

[0127] Exemplary computer program products and computer-readable storage media Embodiments of the present disclosure may also include, in addition to the methods and apparatus described above, computer program products that, when executed by a processor, cause the processor to perform steps in the functional safety testing methods of the various embodiments of the present disclosure described in the “Exemplary Methods” section above.

[0128] Computer program products can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and common procedural programming languages ​​such as the C language or similar programming languages, to create program code for performing the operations of the embodiments of this disclosure. The program code may run entirely on a user computing device, partially on a user computing device, as a standalone software package, partially on a user computing device, partially on a remote computing device, or entirely on a remote computing device or server.

[0129] In addition, embodiments of the present disclosure may further include a computer-readable storage medium storing computer program instructions that, when executed by a processor, cause the processor to perform steps in the functional safety testing methods of the various embodiments of the present disclosure described in the “Exemplary Methods” portion of this specification.

[0130] The computer-readable storage medium may employ any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0131] While the basic principles of this disclosure have been explained above with reference to specific examples, the advantages, advantages, and effects mentioned in this disclosure are merely illustrative and not limiting, and it is not assumed that these advantages, advantages, and effects must be present in each example of this disclosure. Furthermore, the specific details disclosed above are merely illustrative and intended to facilitate understanding, and are not limiting, nor do they imply that this disclosure must be implemented in the specific details described above.

[0132] Those skilled in the art can make various modifications and variations to this disclosure without departing from the spirit and scope of the application. Thus, if such modifications and variations of the application fall within the scope of the claims of this disclosure and the equivalent art, this disclosure is intended to include such modifications and variations.

Claims

1. A configurator used to generate configuration information for testing an integrated circuit under test and to output said configuration information, Multiple test data generators, which are coupled with the configurator and used to generate and output first test data corresponding to each of the multiple test data generators based on the configuration information, The integrated circuit under test, which is coupled with multiple test data generators and used to process multiple first test data and acquire and output multiple second test data, A functional safety test circuit comprising: a first comparator coupled to the integrated circuit under test, used to compare the consistency of a plurality of second test data and to obtain a first test result of the integrated circuit under test.

2. The aforementioned test data generator is In response to the fact that the configuration information includes first sub-configuration information corresponding to a random data test, random test data is generated. In response to the fact that the aforementioned configuration information includes a second sub-configuration information corresponding to a preset data test, it is used to generate preset test data. Herein, the first test data includes the random test data or the preset test data, as described in claim 1, for the functional safety test circuit.

3. The integrated circuit under test is, Multiple first data conversion circuits used to perform a first data conversion on multiple first test data and to acquire and output multiple first converted data, An arithmetic logic circuit, which is coupled with multiple first data conversion circuits and used to perform arithmetic operations on multiple first converted data and to acquire and output multiple arithmetic operation data, The functional safety test circuit according to claim 1, comprising: a second data conversion circuit coupled with the arithmetic logic circuit and used to perform a second data conversion on a plurality of arithmetic operation data and to acquire and output a plurality of the second test data.

4. The aforementioned arithmetic logic circuit is A first logic operation circuit used to perform a first logic operation on a plurality of the aforementioned first conversion data and to obtain a plurality of first operation data, The functional safety test circuit according to claim 3, further comprising a second logic operation circuit used to perform a second logic operation on a plurality of first calculation data and to obtain a plurality of arithmetic calculation data.

5. The aforementioned functional safety test circuit is The functional safety test circuit according to claim 4, further comprising a second comparator coupled with the first logic circuit and used to compare the consistency of a plurality of the first calculation data and to obtain a second test result of the integrated circuit under test.

6. The second comparator is, In response to the first test data being preset test data, the expected data corresponding to the preset test data is determined, the consistency between the first calculation data and the expected data is compared, the second test result is obtained, or A functional safety test circuit according to claim 5, used to compare the consistency of a plurality of first calculation data in response to the fact that the first test data is random test data, and to obtain the second test result.

7. The integrated circuit under test is, A pipeline register unit is coupled to the arithmetic logic circuit and the second data conversion circuit, respectively, and is used to perform temporary storage processing on a plurality of arithmetic operation data and to output the plurality of arithmetic operation data after temporary storage processing. The functional safety test circuit according to claim 3, further comprising: a second data conversion circuit used to perform a second data conversion process on a plurality of arithmetic calculation data after temporary storage processing, and to acquire and output a plurality of the second test data.

8. The steps include: generating configuration information for testing the integrated circuit under test using a configurator; A step of generating first test data corresponding to each of the test data generators in the plurality of test data generators based on the configuration information using a plurality of test data generators, The steps include: processing a plurality of first test data using the integrated circuit under test and obtaining a plurality of second test data; A functional safety test method for an integrated circuit, performed by a functional safety test circuit, comprising the steps of: comparing the consistency of a plurality of second test data using a first comparator to obtain a first test result for the integrated circuit under test.

9. A neural network processor comprising at least one functional safety test circuit as described in any one of claims 1 to 7.

10. Memory for storing instructions that the processor can execute, An electronic device comprising: a processor used to read and execute the executable instructions from the memory, thereby realizing the functional safety test method for an integrated circuit described in claim 8.

11. A computer-readable storage medium storing a computer program that, when executed by a processor, performs the functional safety test method for an integrated circuit described in claim 8.

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