Semiconductor substrates, semiconductor devices, electronic equipment

Abstract

This invention provides a GaN-based semiconductor layer obtained by the ELO method, which includes low-defect regions where linear defects are not detected on dissimilar substrates. [Solution] The invention comprises a different type of substrate (1), a mask layer (6) having an opening (KS) and a mask portion (5), a seed portion (3S) overlapping the opening, and a semiconductor layer (8) containing a GaN-based semiconductor disposed on the seed portion and the mask portion. The upper surface of the effective portion (YS) of the semiconductor layer includes at least one low-defect region (AL) having a size of 10 μm in a first direction along the width direction of the opening and 10 μm in a second direction perpendicular to the first direction, and linear defects are not measured by the CL method in the low-defect region (AL).

Description

[Technical Field]

[0001] This invention relates to semiconductor substrates, semiconductor devices, and electronic devices. [Background technology]

[0002] Semiconductor devices using GaN (gallium nitride) generally have higher power conversion efficiency than semiconductor devices made of Si (silicon). As a result, GaN-based semiconductor devices have lower power loss than Si-based semiconductor devices, and therefore are expected to have energy-saving effects. Conventionally, research has been conducted on techniques for forming GaN-based semiconductor elements in order to manufacture semiconductor devices using GaN. For example, Patent Document 1 discloses a method for forming a GaN-based semiconductor layer on a GaN-based substrate or a dissimilar substrate (e.g., a sapphire substrate) using the ELO (Epitaxial Lateral Overgrowth) method. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2013-251304 [Overview of the project]

[0004] The semiconductor substrate according to this disclosure comprises a main substrate with a lattice constant different from that of a GaN-based semiconductor, a mask layer located above the main substrate and having an opening and a mask portion, a seed portion that overlaps with the opening in a plan view, and a semiconductor layer containing a GaN-based semiconductor disposed on the seed portion and the mask portion, wherein the semiconductor layer includes an effective portion located between the opening and the center of the mask portion in a plan view, and the upper surface of the effective portion includes at least one low-defect region having a size of 10 μm in a first direction along the width direction of the opening and a size of 10 μm in a second direction perpendicular to the first direction, wherein linear defects are not measured by the CL method in the low-defect region. [Brief explanation of the drawing]

[0005] [Figure 1] These are a plan view and a cross-sectional view showing the configuration of the semiconductor substrate according to this embodiment. [Figure 2] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 3] This is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. [Figure 4] These are a plan view and a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. [Figure 5] These are a plan view and a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. [Figure 6] This is a cross-sectional view showing the element isolation process according to this embodiment. [Figure 7] This is a plan view showing the element isolation process according to this embodiment. [Figure 8] This is a cross-sectional view showing another example of the element isolation process. [Figure 9] This is a cross-sectional view showing another example of the element isolation process. [Figure 10] This is a cross-sectional view showing the process of element delamination. [Figure 11] This is a cross-sectional view showing another example of the element delamination process. [Figure 12] This is a schematic diagram showing the configuration of the electronic device according to this embodiment. [Figure 13] This is a schematic diagram showing an alternative configuration of the electronic device according to this embodiment. [Figure 14] This is a cross-sectional view showing an example of lateral growth of a semiconductor layer. [Figure 15] These are plan views and schematic diagrams illustrating the evaluation of this semiconductor substrate (a configuration in which the ELO semiconductor layer has an edge surface on the mask). [Figure 16] These are plan views and schematic diagrams illustrating the evaluation of this semiconductor substrate (a configuration in which the ELO semiconductor layer has an edge surface on the mask). [Figure 17] These are plan views and schematic diagrams illustrating the evaluation of this semiconductor substrate (a configuration in which the ELO semiconductor layer has an edge surface on the mask). [Figure 18]It is a plan view and a schematic diagram showing an evaluation of this semiconductor substrate (a configuration in which the ELO semiconductor layer has an edge surface on a mask). [Figure 19] It is a plan view and a schematic diagram showing an evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer does not have an edge surface on a mask. [Figure 20] It is a plan view and a schematic diagram showing an evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer does not have an edge surface on a mask. [Figure 21] It is a plan view and a schematic diagram showing an evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer does not have an edge surface on a mask. [Figure 22] It is a plan view and a schematic diagram showing an evaluation of an integrated semiconductor substrate in which the ELO semiconductor layer does not have an edge surface on a mask. [Figure 23] It is a CL image of the ELO semiconductor layer 8 of the semiconductor substrate 10 (the main substrate is a silicon substrate). [Figure 24] It is a CL image of the ELO semiconductor layer 8 of the semiconductor substrate 10 (the main substrate is a sapphire substrate). [Figure 25] It is a CL image of the back surface (peeling surface) of the ELO semiconductor layer of the semiconductor substrate 10. [Figure 26] It is a CL image of the surface of the GaN layer in the reference example. [Figure 27] It is a CL image of the surface of the GaN layer in the reference example. [Figure 28] It is a CL image of the surface of the GaN layer in the reference example. [Figure 29] It is a CL image of the back surface (peeling surface) of the GaN layer formed by the ELO method in the reference example. [Figure 30] It is a CL image of the back surface (peeling surface) of the GaN layer formed by the ELO method in the reference example. [Figure 31] It is a cross-sectional view showing the configuration of the semiconductor substrate of Example 1. [Figure 32] It is a cross-sectional view showing an example of semiconductor layer peeling in Example 1. [Figure 33] It is a cross-sectional view showing the configuration of the semiconductor substrate of Example 2. [Figure 34]This is a cross-sectional view showing the configuration of the semiconductor substrate in Example 3. [Figure 35] This is a cross-sectional view showing the configuration of the semiconductor substrate in Example 4. [Figure 36] This is a cross-sectional view showing an application example of Example 4. [Figure 37] This is a cross-sectional view showing the configuration of Example 5. [Figure 38] This is a cross-sectional view showing the configuration of Embodiment 6. [Figure 39] This is a cross-sectional view showing an alternative configuration of Example 6. [Figure 40] This block diagram shows an example configuration of semiconductor substrate manufacturing equipment. [Modes for carrying out the invention]

[0006] (Semiconductor substrate) Figure 1 is a plan view and a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figure 1, the semiconductor substrate 10 (semiconductor wafer) according to this embodiment includes a main substrate 1, a base layer 4 formed on the main substrate 1 and including a seed portion 3S, a mask layer 6 formed on the base layer 4 and having an opening KS and a mask portion 5 that overlap with the seed portion 3S in a plan view, and a semiconductor layer 8 containing a nitride semiconductor (e.g., a GaN-based semiconductor) disposed on the seed portion 3S and the mask portion 5. The base layer 4 may be the base portion 4, the mask layer 6 may be the mask 6 (mask pattern), and the semiconductor layer 8 may be the semiconductor portion 8.

[0007] The opening KS of the mask layer 4 may be tapered (a shape that narrows in width towards the base layer 4). In this case, the width of the opening KS and the width of the mask portion 5 can be expressed with respect to the upper surface of the mask layer. However, it is not limited to this.

[0008] Nitride semiconductors can be represented, for example, as AlxGayInzN (0≦x≦1;0≦y≦1;0≦z≦1;x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The semiconductor layer 8 may be doped (e.g., n-type including a donor) or undoped. A semiconductor substrate means a substrate containing a nitride semiconductor (e.g., a GaN-based semiconductor), and the material of the main substrate 1 may be a semiconductor or a non-semiconductor. The main substrate 1 and the underlay layer 4 together are sometimes called a base substrate, and the main substrate 1, the underlay layer 4, and the mask layer 6 together are sometimes called a template substrate 7.

[0009] The semiconductor layer 8 is formed by the ELO (Epitaxial Lateral Overgrowth) method, starting from the seed portion 3S exposed from the aperture KS. For this reason, the semiconductor layer 8 is sometimes referred to as the ELO semiconductor layer 8. The thickness direction of the semiconductor layer 8 is the Z direction (of the GaN crystal). <0001> The direction is (direction). The opening KS has a longitudinal shape, and its width direction is the X direction (the <11-20> direction of the GaN crystal).

[0010] Figure 2 is a cross-sectional view showing an alternative configuration of the semiconductor substrate according to this embodiment. As shown in Figure 2, the semiconductor substrate 10 may also be configured in which the main substrate 1, underlayer 4, mask layer 6, semiconductor layer 8, and functional layer 9 are provided in this order.

[0011] In the semiconductor substrate 10, multiple layers are stacked on the main substrate, and the stacking direction can be set to "upward." Also, viewing the semiconductor substrate 10 with a line of sight parallel to the normal direction of the semiconductor substrate 10 can be called a "planar view."

[0012] (Main board) The main substrate 1 can be a heterogeneous substrate having a different lattice constant from the GaN-based semiconductor. Examples of heterogeneous substrates include silicon (Si) substrates, sapphire (Al2O3) substrates, silicon carbide (SiC) substrates, and ScAlMgO4 substrates. The plane orientation of the main substrate 1 is, for example, the (111) plane for a silicon substrate, the (0001) plane for a sapphire substrate, and the 6H-SiC(0001) plane for a SiC substrate. These are examples, and any substrate and plane orientation that can grow the semiconductor layer 8 by the ELO method is acceptable. The main substrate may also be a self-supporting substrate (for example, a wafer cut from a bulk crystal).

[0013] (base layer) As the base layer 4, a buffer layer 2 (e.g., an AlN layer) and a seed layer 3 (e.g., a GaN-based semiconductor) can be provided in order from the main substrate side. The buffer layer 2 is a melting suppression layer that can reduce the direct contact and melting of the main substrate 1 and the seed layer 3. It also has the effect of improving the crystallinity of the seed layer 3. The AlN layer is formed to a thickness of about 10 nm to 5 μm using, for example, the MOCVD method. For example, if a main substrate 1 that does not melt with the seed layer 3, which is a GaN-based semiconductor, is used, it is also possible to omit the buffer layer 2. When a silicon substrate or the like is used for the main substrate 1, it melts with the GaN-based semiconductor seed layer, so melting is reduced by providing a buffer layer 2 such as an AlN layer.

[0014] For example, an AlGaN layer can be used for the seed layer 3. The seed layer 3 includes a seed portion 3S that overlaps with the opening KS of the mask layer 6. As the seed layer 3, a graded layer can be used in which the Al composition approaches GaN in a graded manner. For example, the graded layer consists of, in order from the AlN layer side, the first layer being Al 0.7 Ga 0.3 N layer and the second layer, Al 0.3 Ga 0.7This is a laminate with an N layer. In this case, the composition ratio of Ga in the second layer (Al:Ga:N=0.3:0.7:1) (0.7 / 2=0.35) is greater than the composition ratio of Ga in the first layer (Al:Ga:N=0.7:0.3:1) (0.3 / 2=0.15). The graded layer can be easily formed by the MOCVD method and may consist of three or more layers. By using a graded layer as the seed layer 3, stress from the main substrate 1, which is a different type of substrate, can be relieved. The seed layer 3 may include a GaN layer. In this case, the seed layer 3 may be a single GaN layer, or the top layer of the graded layer which is the seed layer 3 may be a GaN layer. The base layer 4 may consist of only one of the buffer layer 2 and the seed layer 3. Furthermore, a self-supporting SiC substrate (for example, a single-crystal wafer cut from a bulk crystal) can be used as the main substrate 1, and a mask layer 6 can be formed on the SiC substrate without forming an underlayer, thereby creating a template substrate.

[0015] (Mask layer) The mask layer 6 has a mask portion 5 and an opening KS formed therein. The opening KS has the function of a growth initiation opening that exposes the seed layer 3 and starts the growth of the semiconductor layer 8, and the mask portion 5 may have the function of a selective growth mask that grows the semiconductor layer 8 laterally. The opening KS is a portion of the mask layer 6 (mask pattern 6) where the mask portion 5 is not present (unformed portion) and does not need to be surrounded by the mask portion 5.

[0016] As the mask layer 6, inorganic insulating films such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and titanium nitride (TiNx) can be used. For example, a silicon oxide film with a thickness of approximately 50 nm to 4 μm (for example, approximately 100 nm to 2 μm) is formed over the entire substrate layer 4 using a sputtering method, and a resist is applied to the entire surface of the silicon oxide film. Then, the resist is patterned using a photolithography method to form a resist with stripe-shaped openings. Subsequently, a portion of the silicon oxide film is removed using a wet etchant such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF) to form openings KS, and the resist is removed by organic cleaning to form a mask layer 6 having openings KS and mask portions 5. It is also possible to form the mask portions over the entire substrate surface using a photolithography method, then apply and pattern a resist to remove the resist in the areas that will become openings KS, and then form the openings KS using a dry etching method.

[0017] The apertures KS have a longitudinal shape, and multiple apertures KS are arranged periodically with a first period in the a-axis direction (first direction X) of the ELO semiconductor layer 8.

[0018] The width of the aperture KS should be approximately 0.1 μm to 20 μm. The smaller the width of the aperture KS, the fewer the number of through-dislocations propagating from the aperture KS to the ELO semiconductor layer 8. Furthermore, the peeling of the ELO semiconductor layer 8 in subsequent processes becomes easier. In addition, the area of ​​the effective portion with fewer surface defects can be increased.

[0019] The mask layer 6 can also be a multilayer film containing the above-mentioned materials, for example, a multilayer film containing a silicon oxide film and a silicon nitride film.

[0020] (Deposition of ELO semiconductor layer) A GaN-based semiconductor layer is formed as the semiconductor layer 8 (ELO semiconductor layer 8) by the ELO method. The ELO semiconductor layer 8 is composed of GaN, and the seed portion 3S may also contain GaN. For example, a template substrate 7 including the main substrate 1, underlayer 4, and mask layer 6 is introduced into an MOCVD apparatus, and a GaN layer is deposited on the template substrate 7. As an example of ELO deposition conditions, the substrate temperature: 1120°C, growth pressure: 50kPa, TMG (trimethylgallium): 22sccm, NH3: 15slm, and V / III = 6000 (ratio of the amount of Group V raw material supplied to the amount of Group III raw material supplied) can be used.

[0021] In the deposition of the semiconductor layer 8, it is preferable to reduce the interaction between the semiconductor layer 8 and the mask portion 5 and maintain a state in which the semiconductor layer 8 and the mask portion 5 are in contact by van der Waals forces. In other words, the semiconductor layer 8 and the mask portion 5 are in contact mainly by van der Waals forces.

[0022] Adjacent ELO semiconductor layers 8 grown from adjacent openings KS may be made to meet each other, or they may not meet each other, forming a gap near the center of the mask portion 5. If they are made to meet, a flat surface can be formed across the entire substrate. If they are not made to meet, the stress (compressive stress or tensile stress) that occurs when a main substrate 1 made of a material different from the nitride semiconductor is used can be more effectively relieved by the gap, and the occurrence of defects and cracks can be effectively suppressed.

[0023] (Shape of the ELO semiconductor layer) The semiconductor layer 8 has an effective portion YS (the portion that constitutes the device in a later process) located between the aperture KS and the center 5C of the mask portion in a plan view. Of the semiconductor layer 8, the portion located on the seed portion 3S (the portion with many through-dislocations) becomes an ineffective portion NS. That is, the semiconductor layer 8 includes an effective portion YS with relatively few through-dislocations and an ineffective portion NS with relatively many through-dislocations. The ineffective portion NS is a dislocation inheritance portion and has more through-dislocations than the effective portion YS (dislocation non-inheritance portion), but it may be used as part of the device. For example, if the functional layer 9 includes an active layer, the portion of the active layer where electrons and holes combine (light-emitting portion) can be provided so as to overlap with the effective portion YS in a plan view. N-type electrodes (cathodes), etc., may be provided so as to overlap with the ineffective portion NS in a plan view.

[0024] Threading dislocations are in the thickness direction of the ELO semiconductor layer 8. <0001> These are dislocations (defects) that extend from the bottom surface or interior of the semiconductor layer 8 to its surface or surface layer along the direction (Z direction). Threading dislocations can be observed by performing a CL (Cathode luminescence) measurement on the surface (parallel to the c-plane) of the semiconductor layer 8.

[0025] The semiconductor layer 8 in Figure 1 has an edge surface (side surface) 8E near the center of the mask portion 5 and does not associate with the semiconductor layer 8 grown from the adjacent seed portion 3S. When the c-plane ELO semiconductor layer 8 is formed in an island shape, the side surface of the ELO semiconductor layer 8 is typically formed by a <1-10α> plane (α is any integer), a <11-2β> plane (β is any integer), or a crystallographically equivalent plane. That is, the edge surface 8E of the semiconductor layer 8 may have a slanted surface (facet).

[0026] In this way, the semiconductor layers 8 that grow laterally in opposite directions from two adjacent seed portions 3S do not come into contact (meet) on the mask portion 5, and have a gap GP, which reduces the internal stress of the semiconductor layers 8. This reduces cracks and defects that occur in the semiconductor layers 8. This effect is particularly effective in this embodiment where the main substrate 1 is a different type of substrate. The width of the gap GP is preferably 4 μm or less, and more preferably 3 μm or less.

[0027] The semiconductor layer 8 may be an n-type GaN-based semiconductor (for example, silicon as a donor). When a functional layer 9 including, for example, a p-type semiconductor layer is formed above the semiconductor layer 8 (see Figure 2), if the semiconductor layer 8 has silicon or oxygen as an n-type dopant, the p-type dopant (magnesium, etc.) may be compensated for. This phenomenon can be significantly reduced by keeping the width of the gap GP within the above range.

[0028] Figure 3 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. When forming the functional layer 9, edge growth 9G (corners) may occur as shown in Figure 3. For example, this occurs when the functional layer 9 includes an AlGaN layer. Edge growth can be 10 μm or more in width and about 200-300 nm in height, which can be an obstacle to subsequent processes. However, by keeping the width of the gap GP within the above range, edge growth 9G can be significantly reduced (for example, to 100 nm or less).

[0029] Figures 4 and 5 are a plan view and a cross-sectional view, respectively, showing an alternative configuration of the semiconductor substrate according to this embodiment. The semiconductor layer 8 in Figure 4 has a configuration in which semiconductor layers grown laterally in opposite directions from two adjacent seed portions 3S meet and are integrated near the center 5C of the mask portion. In this configuration, by appropriately setting the film deposition conditions of the ELO semiconductor layer 8, the width of the mask portion 5, etc., a hollow portion 8C may be formed near the center 5C of the mask portion, which is the meeting point, as shown in Figure 5. The shape of the hollow portion 8C is wider on the mask portion 5 side (for example, a cone shape or teardrop shape in cross-section). In this case, the semiconductor layer 8 has a portion (non-effective portion NS) that overlaps with the hollow portion 8C in a plan view. That is, the semiconductor layer 8 has an effective portion YS and a non-effective portion NS adjacent to the effective portion YS.

[0030] The silicon oxide, silicon nitride, and silicon oxynitride films used as materials for the mask layer 6 have smaller coefficients of thermal expansion compared to GaN-based semiconductors. Therefore, when the ELO semiconductor layer 8, which is assembled at around 1000°C, is cooled to room temperature, cracks may occur in the ELO semiconductor layer 8 due to the difference in coefficients of thermal expansion. The hollow portion 8C has the effect of significantly reducing the internal stress of the semiconductor layer 8, thus effectively reducing the occurrence of such cracks. Furthermore, the surface of the semiconductor layer 8 may have a depression 8D in the portion above the hollow portion 8C. This depression 8D also has the effect of relaxing the internal stress of the semiconductor layer 8.

[0031] (Functional layer) The semiconductor substrate 10 in Figure 2 includes a functional layer 9 on a semiconductor layer 8. The functional layer 9 includes, for example, at least one of a GaN-based n-type semiconductor layer, a GaN-based undoped semiconductor layer, a GaN-based p-type semiconductor layer, a conductive layer, and an insulating layer. Any film deposition method may be used for the GaN-based semiconductor layer of the functional layer 9. The functional layer 9 may also be a compound semiconductor layer (compound semiconductor portion). The compound semiconductor layer may also be a nitride semiconductor layer (nitride semiconductor portion), in which case the nitride semiconductor layer may include a p-type layer and an active layer (e.g., an emissive layer), or the nitride semiconductor layer may include an n-type layer, an active layer, and a p-type layer.

[0032] The functional layer 9 may, but is not limited to, a semiconductor device (e.g., an LED or laser) together with the semiconductor layer 8. For example, only a GaN-based n-type semiconductor layer may be provided.

[0033] (Element isolation on a semiconductor substrate) Figure 6 is a cross-sectional view showing the element isolation process according to this embodiment. Figure 7 is a plan view showing the element isolation process according to this embodiment. As shown in Figure 6, in the semiconductor substrate 10, the region AK that overlaps with the aperture KS in a plan view is removed using vapor phase etching down to the underlying layer 4.

[0034] In this process, a portion of the underlayer 4, mask layer 6, semiconductor layer 8, and functional layer 9 are removed, and the underlayer 4 and mask portion 5 are exposed in the trench TR (element isolation groove) formed after removal. It is desirable that the opening width of the trench TR be larger than the opening KS of the mask layer. Through the element isolation process, the element portion DS can be separated from the semiconductor substrate 10. At this stage, the element portion DS is van der Waals coupled to the mask portion 5 of the template substrate and is part of the semiconductor substrate 10.

[0035] As shown in Figure 7, the trench TR can be formed in a grid shape (lattice pattern) in a plan view. In this case, one element DS may be included in the region enclosed by adjacent horizontal trenches (extending in the X direction) and adjacent vertical trenches (extending in the Y direction).

[0036] Vapor-phase etching is performed using a general photolithography method. After etching is complete, it is necessary to remove the photoresist that served as the mask for vapor-phase etching. However, if organic cleaning is performed using weak ultrasound, there is little risk of the element part DS peeling off from the mask part 5.

[0037] Figure 8 is a cross-sectional view showing another example of the element isolation process. As shown in Figure 8, the region of the semiconductor substrate 10 that overlaps with the aperture KS and the region that overlaps with the gap GP in a plan view may be removed down to the underlayer 4 using vapor phase etching. This eliminates the meandering of the semiconductor layer 8 in the second direction (the longitudinal direction of the aperture KS, the Y direction), and a uniformly shaped element portion DS can be obtained.

[0038] Figure 9 is a cross-sectional view showing another example of the element isolation process. As shown in Figure 9, the region of the semiconductor substrate 10 that overlaps with the aperture KS in a plan view and the region that overlaps with the central part of the mask 5 (non-effective part NS) can be removed down to the underlayer 4 using vapor phase etching.

[0039] (Removal of elements from the template substrate) Figure 10 is a cross-sectional view showing the device peeling process. Since the semiconductor layer 8 and the mask portion 5 are bonded by van der Waals forces (weak forces), as shown in Figure 10, the functional layer 9 can be easily peeled off the device portion DS from the template substrate by pulling up the functional layer 9 with an attractive force (adhesion, suction, electrostatic force, etc.) from a stamping device ST, etc., thereby forming the semiconductor device 20. Direct peeling from the mask portion 5 using a viscoelastic elastomer stamp, electrostatic adhesive stamp, etc., offers significant advantages in terms of cost and throughput. However, if the mask portion 5 and the semiconductor layer 8 are adhered, peeling becomes difficult, so reducing such adhesion is of great importance (described later). After bringing the viscoelastic elastomer stamp, electrostatic adhesive stamp, etc. into contact with the semiconductor layer 8, vibrations such as ultrasonic vibrations may be applied. These vibrations make it even easier to peel the semiconductor layer 8 from the mask portion 5.

[0040] Figure 11 is a cross-sectional view showing another example of the device removal process. As shown in Figure 11, the mask portion 5 may be wet-etched to a state where the device portion DS of the semiconductor layer 8 is connected only to the seed layer 3, and then the device portion DS may be mechanically removed from the template substrate 7 using tape TP or the like. In this case, since it is not necessary to etch the opening KS, a large semiconductor device 20 can be formed. This removal method has the advantage that the device separation process can be omitted when the semiconductor layer 8 is of the separate type (when it has an edge surface on the mask portion). When the semiconductor layer 8 is of the integrated type (when it does not have an edge surface on the mask portion), it is sufficient to form a groove for etchant flow (down to the underlying layer), which has the advantage of making device removal easy.

[0041] (Semiconductor devices) As shown in Figures 10 and 11, the element portion DS peeled off from the template substrate 7 functions as a semiconductor device 20. Specific examples of semiconductor devices 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high-electron-mobility transistors).

[0042] (electronic equipment) Figure 12 is a schematic diagram showing the configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 12 includes a semiconductor device 20 including a semiconductor layer 8 and a functional layer 9, a drive substrate 23 on which the semiconductor device 20 is mounted, and a control circuit 25 for controlling the drive substrate 23. Figure 13 is a schematic diagram showing an alternative configuration of the electronic device according to this embodiment. The electronic device 30 in Figure 13 includes a semiconductor substrate 10 including a semiconductor layer 8 and a functional layer 9, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 25 for controlling the drive substrate 23. In this case, the main substrate 1 may be a light-transmitting substrate (for example, a sapphire substrate).

[0043] Examples of electronic devices include display devices, laser emitters (including Fabry-Perot type and surface-emitting type), measuring devices, lighting devices, communication devices, information processing devices, and power control devices.

[0044] (Void on the back surface of the ELO semiconductor layer) The following describes the back surface (interface with the mask portion 5) of the ELO semiconductor layer 8 on the semiconductor substrate 10.

[0045] When using different substrates and widening the mask portion 5, voids may form on the back surface of the ELO semiconductor layer 8. These voids can cause surface defects in the ELO semiconductor layer 8 (for example, they can be the starting point for defects when stress is applied to the semiconductor layer 8), leading to deterioration of the characteristics and reduced reliability of the device formed on the ELO semiconductor layer 8. In this embodiment, by increasing the lateral deposition rate and reducing the interaction between the ELO semiconductor layer 8 and the mask portion 5, the surface morphology of the mask portion 5 is improved, and as a result, voids on the back surface of the ELO semiconductor layer 8 and adhesion to the mask portion 5 are successfully reduced.

[0046] Specifically, to reduce the degradation of the mask portion 5, the lateral deposition rate is increased, and the mask portion 5 is quickly covered with a laterally grown film (ELO semiconductor layer 8). In MOCVD, if the lateral deposition rate is small, the mask portion 5 will be exposed to hydrogen and nitrogen at high temperatures for a long time, which can lead to evaporation and decomposition of the mask portion 5, potentially causing deterioration of the surface morphology, the occurrence of pinholes, and the formation of pits.

[0047] The method for increasing the lateral film deposition rate is as follows: First, a longitudinal growth layer growing in the c-axis direction is formed on the seed portion exposed from the opening KS of the mask layer 6, and then a lateral growth layer growing in the a-axis direction is formed. In this case, by setting the thickness of the longitudinal growth layer to 10 μm or less, preferably 5 μm or less, and more preferably 3 μm or less, the thickness of the lateral growth layer can be kept low, thereby increasing the lateral film deposition rate.

[0048] Figure 14 is a cross-sectional view showing an example of lateral growth of a semiconductor layer. As shown in Figure 14, it is desirable to form an initial growth layer SL on a seed portion 3S that overlaps with the opening KS, and then grow the semiconductor layer 8 laterally from the initial growth layer SL. The initial growth layer SL serves as the starting point for the lateral growth of the semiconductor layer 8. In the deposition of the semiconductor layer 8, it is preferable to stop the deposition of the initial growth layer SL just before the edge of the initial growth layer SL rides up onto the upper surface of the mask portion 5 (when it is in contact with the upper edge of the side surface of the mask portion 5), or immediately after it rides up onto the upper surface of the mask portion 5 (i.e., at this timing, switch the ELO deposition conditions from c-axis deposition conditions to a-axis deposition conditions). In this way, since lateral deposition is performed from a state in which the initial growth layer SL is slightly protruding from the mask portion 5, the consumption of material for growth in the thickness direction of the semiconductor layer 8 is reduced, and the semiconductor layer 8 can be effectively grown laterally at high speed. The initial growth layer SL can be formed to a thickness of 50 nm to 5.0 μm (for example, 80 nm to 2 μm). The thickness of the initial growth layer SL may be 500 nm or less.

[0049] As shown in Figure 14, by growing the semiconductor layer 8 laterally after depositing the initial growth layer SL, it is possible to increase the number of non-penetrating dislocations within the effective region YS (reducing the penetration dislocation density on the surface of the effective region YS). Furthermore, it is possible to control the distribution of impurity concentrations (e.g., silicon, oxygen) within the effective region YS. By appropriately controlling the conditions during the deposition of the semiconductor layer 8, it is possible to control the growth of the semiconductor layer 8 in the Z direction (c-axis direction) or the X direction (a-axis direction).

[0050] For the effective portion YS of the semiconductor layer 8 shown in Figure 14, the ratio of the size W1 in the X direction (first direction) to the thickness d1 (W1 / d1) can be, for example, 2.0 or more. Using the method in Figure 14, W1 / d1 can be 1.5 or more, 2.0 or more, 4.0 or more, 5.0 or more, 7.0 or more, or 10.0 or more. It has been found that setting W1 / d1 to 1.5 or more facilitates the splitting process shown in Figure 7. In addition, the internal stress of the semiconductor layer 8 is reduced, and substrate warping is reduced. The aspect ratio of the semiconductor layer 8 (ratio of size in the X direction to thickness = WL / d1) can be 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more. Furthermore, by using the method shown in Figure 14, the ratio of the size WL of the semiconductor layer 8 in the X direction to the width WK of the aperture KS (WL / WK) can be set to 3.5 or more, 5.0 or more, 6.0 or more, 8.0 or more, 10 or more, 15 or more, 20 or more, 30 or more, or 50 or more, thereby increasing the ratio of the effective area. The semiconductor layer 8 shown in Figure 14 can be a nitride semiconductor crystal (for example, a GaN crystal, an AlGaN crystal, an InGaN crystal, or an InAlGaN crystal).

[0051] Non-penetrating dislocations are dislocations observed at CL in a cross-section made of a plane parallel to the c-axis (a plane parallel to the thickness direction), and are mainly base plane (c-plane) dislocations. The plane parallel to the c-axis may be a plane parallel to the (1-100) plane (a plane whose normal is in the Y direction) or a plane parallel to the (11-20) plane (a plane whose normal is in the X direction).

[0052] The non-penetrating dislocation density of the effective portion YS of semiconductor layer 8 is greater than the penetrating dislocation density of the effective portion YS. In other words, the effective portion YS of semiconductor layer 8 can be described as a GaN-based crystal (GaN-based layer) in which the non-penetrating dislocation density is greater than the penetrating dislocation density. In this case, the non-penetrating dislocation density can be 10 times or more, for example, 20 times or more, than the penetrating dislocation density. The penetrating dislocation density is, for example, 5 × 10⁻⁶ 6 [pcs / cm 2 The following can be achieved: The width (length in the X direction) of the effective portion (GaN-based crystal) can be, for example, 10 μm or more. The effective portion (GaN-based crystal) can also have a longitudinal shape in which the size in the Y direction (m-axis direction) is larger than the size in the X direction (a-axis direction). For the effective portion (GaN-based crystal), the non-penetrating dislocation density of the cross-section made by a plane parallel to the (11-20) plane may be greater than the non-penetrating dislocation density of the cross-section made by a plane parallel to the (1-100) plane. Furthermore, since the effective portion (GaN-based crystal) is formed by lateral growth (X direction), with respect to the X direction, the concentration of impurities (atoms contained in the mask layer 6, such as silicon and oxygen) can be lower at the other end, which is at the end of the growth stage, than at the other end, which is at the beginning of the growth stage.

[0053] The quality of the mask portion 5 (uniformity of thickness, film quality, etc.) is affected by the surface flatness, crystallinity, and material of the underlying layer on which the mask portion 5 is formed. If there are defects in the underlying layer, the reaction between the mask portion 5 and the underlying layer will proceed from those defects, degrading the quality of the mask portion 5. As a result, the reaction between the mask portion 5 and the ELO semiconductor layer 8 deposited on top of it is accelerated, and voids may occur on the back surface of the ELO semiconductor (the interface with the mask portion 5). In the ELO method, film deposition proceeds from both sides of the mask portion 5 toward the center, so voids are more likely to occur in the parts closer to the center (parts where the time until film deposition is longer).

[0054] Regarding the deposition temperature of the ELO semiconductor layer 8, temperatures of 1150°C or lower are preferable to high temperatures exceeding 1200°C. Formation of the ELO semiconductor layer 8 is possible even at low temperatures below 1000°C, and this is even more preferable from the viewpoint of reducing mutual reactions. In such low-temperature deposition, it has been found that when trimethylgallium (TMG) is used as the gallium raw material, the raw material is not sufficiently decomposed, and more gallium atoms and carbon atoms are incorporated into the ELO semiconductor layer 8 than usual. This is thought to be because in the ELO method, deposition in the a-axis direction is fast, while deposition in the c-axis direction is slow, so more is incorporated during c-plane deposition.

[0055] It has been found that carbon incorporated into the ELO semiconductor film reduces reactions with the mask portion 5, reduces mutual reactions with the mask portion 5, and does not cause adhesion with the mask portion 5. Therefore, in low-temperature deposition of the ELO semiconductor layer 8, by reducing the supply of ammonia and deposition at a low V / III (<1000) level, the ELO semiconductor layer 8 can incorporate carbon elements from the raw materials or the chamber atmosphere, thereby reducing reactions with the mask portion 5. In this case, the semiconductor layer 8 will have a carbon-containing structure.

[0056] Furthermore, for low-temperature film deposition below 1000°C, it is preferable to use triethylgallium (TEG) as the gallium raw material gas. Compared to TMG, TEG allows for more efficient decomposition of organic raw materials at low temperatures, thus increasing the lateral film deposition rate.

[0057] An InGaN layer may be formed as the ELO semiconductor layer 8. Lateral deposition of the InGaN layer is performed at a low temperature, for example, below 1000°C. This is because at high temperatures, the vapor pressure of indium increases, preventing it from being effectively incorporated into the film. Lowering the deposition temperature reduces the interaction between the mask portion 5 and the InGaN layer. Additionally, the InGaN layer has the effect of being less reactive with the mask portion 5 than the GaN layer. It is desirable that the indium is incorporated into the InGaN layer at an In composition level of 1% or more, as this further reduces the reactivity with the mask portion 5. Triethylgallium (TEG) is preferably used as the gallium source gas.

[0058] Since the interaction between the mask portion 5 and the ELO semiconductor layer 8 is triggered by a combination of various factors, the above-mentioned measures may be combined.

[0059] By suppressing the generation of voids on the back surface of the ELO semiconductor layer 8, linear defects on the surface (front layer) of the ELO semiconductor layer 8 can be reduced. The m-plane of the ELO semiconductor layer 8 is vulnerable to stress and prone to defects. These linear defects are thought to be caused by crystal slip along the m-plane. In a specific cross-section parallel to the c-plane, dislocations extending in the m-axis direction (presumably mixed dislocations combining edge dislocations and helical dislocations) may be observed as linear defects, but it is sufficient if the linear defects disappear (are not observed) in a cross-section cut at the surface layer (parallel to the c-plane) rather than this specific cross-section.

[0060] (Adhesion on the back surface of the ELO semiconductor layer) When using different substrates and widening the mask portion 5, adhesion between the back surface of the ELO semiconductor layer 8 and the mask portion 5 may occur. If this adhesion is present, the stress generated by the difference in thermal expansion coefficients between the ELO semiconductor layer 8 and the different substrate becomes difficult to relieve, leading to surface defects. It also worsens the peeling yield when peeling the ELO semiconductor layer 8 from the template substrate 7.

[0061] In this embodiment, adhesion between the ELO semiconductor layer 8 and the mask portion 5 is reduced by reducing the interaction between the ELO semiconductor layer 8 and the mask portion 5. Specifically, the material and thickness of the mask portion 5 are optimized, and the film density of the mask portion 5 is increased. If the film density of the mask portion 5 is low, the film will evaporate quickly or the etching rate will be high when the film is deposited at high temperature and in a hydrogen atmosphere in the MOCVD apparatus. When the ELO semiconductor layer 8 grows laterally and covers such a mask portion 5, the mask portion 5 and the ELO semiconductor layer 8 will adhere to each other. This is thought to be because a reaction layer is formed in which the mask portion 5 and the ELO semiconductor layer 8 mix, causing the ELO semiconductor layer 8 to adhere to the mask portion 5.

[0062] When the ELO semiconductor layer 8 and the mask portion 5 adhere to each other, an intermediate layer (a layer in which the mask portion 5 and the semiconductor layer 8 react or mix) is formed on the back surface of the ELO semiconductor layer 8. This intermediate layer (adhesion layer) is not removed even when the mask portion 5 is removed using an etchant such as hydrofluoric acid, and remains on the back surface of the ELO semiconductor layer 8. Therefore, when an intermediate layer is formed, the surface morphology of the back surface of the ELO semiconductor layer 8 after peeling from the template substrate 7 deteriorates. For samples with little adhesion, the arithmetic mean surface roughness Ra measured by AFM (Atomic Force Microscope) is 10 nm or less, and preferably around 1 nm. For samples with a large adhesion effect, the Ra was around 13 nm. By measuring the surface roughness of the back surface of the ELO semiconductor layer 8 with AFM using the peeling method described later (see Example 1), the state of adhesion can be determined.

[0063] (Preferred configuration of the mask layer) The mask layer is the aforementioned silicon oxide film (SiO x In addition to the above, examples include single-layer films or multi-layer films consisting of one or more of the following: titanium nitride film (TiN, etc.), silicon nitride film (SiN, etc.), silicon oxynitride film (SiON), and high-melting-point metal film.

[0064] The mask portion 5 may be a silicon nitride film or a silicon oxynitride film. While silicon oxide films may decompose and evaporate in small amounts during the formation of the ELO semiconductor layer 8 and be incorporated into the ELO semiconductor layer 8, silicon nitride films and silicon oxynitride films have the advantage of being less prone to decomposition and evaporation at high temperatures. Furthermore, even when a silicon oxide film, which is common in the ELO method, is used as the mask layer, the interaction between the mask portion 5 and the ELO semiconductor layer 8 can be effectively reduced by optimizing the film formation conditions for the mask layer and the ELO semiconductor layer 8.

[0065] Therefore, the mask layer may be a single layer of silicon nitride or silicon oxynitride, or a multilayer film in which a silicon oxide film and a silicon nitride film are formed in that order on the underlying layer, or a multilayer film in which a silicon nitride film and a silicon oxide film are formed in that order on the underlying layer, or a multilayer film in which a silicon nitride film, a silicon oxide film and a silicon nitride film are formed in that order on the underlying layer.

[0066] Any abnormalities in the mask portion 5, such as pinholes, may be eliminated by performing organic cleaning after film formation and then reintroducing the film-forming apparatus to form the same type of film again. Alternatively, a general silicon oxide film may be used, and a high-quality mask layer may be formed using the re-formation method described above.

[0067] (Evaluation of this semiconductor substrate) The evaluation of the semiconductor substrate 10 is described below. Figures 15 to 18 are plan views and schematic diagrams showing the evaluation of this semiconductor substrate (a configuration in which the ELO semiconductor layer has an edge surface on the mask). The back surface of the semiconductor layer 8 (the interface surface 8R with the mask) can be evaluated in the state of the interface surface in contact with the mask 5, or the semiconductor layer 8 can be peeled off from the mask 5 and the peeled surface can be evaluated. In this case, the semiconductor layer 8 can be peeled off by removing the mask 5 by wet etching or the like (if the semiconductor layer 8 is an integrated type, pre-etching down to the base layer 4 may be performed).

[0068] For the semiconductor substrate 10, the surface of the ELO semiconductor layer 8 was measured using the cathodoluminescence (CL) method. The results showed that the upper surface 8F of the effective area YS contained at least one low-defect region AL having a size of 10 μm in the first direction X (a-axis direction) along the width direction of the opening KS and a size of 10 μm in the second direction Y (m-axis direction) perpendicular to the first direction. No linear defects (linear defects oblique to the first direction X, thought to be caused by m-plane slip) were measured in the low-defect region AL (see Figure 15, evaluation criterion 1). More specifically, the upper surface of the effective area YS contained multiple low-defect regions AL aligned in the first direction X and multiple low-defect regions AL aligned in the second direction Y (see Figure 15, evaluation criterion 2). The size of the effective area YS in the first direction was larger than the width of the opening KS (see Figure 15, evaluation criterion 3).

[0069] The effective portion YS had a first region A1 with a size of 10 μm in the first direction X and 10 μm in the second direction Y at the interface 8R with the mask portion 5, and a second region A2 with the same size as the first region A1, located closer to the center of the mask portion 5 than the first region A1, and having a distance PT from the center 5C of the mask portion 5 that was 30% or less of the width of the mask portion 5. When the effective portion YS was peeled off from the mask portion 5, the first region A1 and the second region A2 were observed with AFM, and the number of recesses with a major axis of 0.1 [μm] or more in the first region A1 was less than or equal to the number of recesses with a major axis of 0.1 [μm] or more in the second region A2 (see Figure 16, evaluation criterion 4). In addition, the major axis of the recesses present in the first region A1 was 1 μm or less (hereinafter, evaluation criterion 5).

[0070] Furthermore, regarding the effective portion YS before peeling from the mask portion 5, cross-sectional observation of the first region A1 and the second region A2 was performed using AFM. The results showed that the number of voids with a major axis of 0.1 [μm] or more in the first region A1 was less than or equal to the number of voids with a major axis of 0.1 [μm] or more in the second region A2 (see Figure 16, evaluation criterion 6).

[0071] The effective portion YS had a third region A3 with dimensions of 10 μm in the first direction X and 10 μm in the second direction Y at the interface 8R with the mask portion 5, and a fourth region A4 with the same dimensions but located closer to the center of the mask portion 5 than the third region A3. When the effective portion YS was peeled from the mask portion 5 and the first region A3 and second region A4 were observed with AFM, the adhesion area of ​​the third region A3 was smaller than the adhesion area of ​​the fourth region A4 (see Figure 17, evaluation criterion 7). Furthermore, the third region A3 was a non-adherent region in which substantially no adhesion to the mask portion 5 was observed (hereinafter, evaluation criterion 8). The fourth region A4 was located at a position where the distance PT from the center 5C of the mask portion was 30% or less of the width of the mask portion 5.

[0072] The effective part YS includes a first part P1 and a second part P2 that is farther from the opening KS than the first part P1 and has a distance KT from the opening KS of 10 μm or more. When the first part P1 is peeled off from the mask part 5, the surface roughness (Ra) of the peeling surface F1 is taken as the first surface roughness, and when the second part P2 is peeled off from the mask part 5, the surface roughness (Ra) of the peeling surface F2 is taken as the second surface roughness. The first surface roughness was less than or equal to the second surface roughness (see Fig. 18, Evaluation Criteria 9). Here, the arithmetic mean roughness (Ra) for a 5 μm × 5 μm range of each peeling surface was extracted from a part of the roughness curve measured by AFM using the reference length, and the uneven state of that section could be represented by the average value. Furthermore, the value of the ratio of the second surface roughness to the first surface roughness was 1.0 to 10 (Evaluation Criteria 10). Furthermore, when the effective part YS was peeled off from the mask part 5, the peeling surface (including F1 and F2) included a flat region having a size of 10 μm in the first direction and 10 μm in the second direction and no recesses with a major diameter of 0.1 [μm] or more (Evaluation Criteria 11). Also, the second surface roughness was less than 10 [nm] (Evaluation Criteria 12). Also, in a plan view, the first part P1 was adjacent to the opening KS, and the distance PT between the second part P2 and the center 5C of the mask part was 30% or less of the width of the mask part 5 (Evaluation Criteria 13). Also, taking the area ratio of the recesses with a major diameter of 0.1 μm or more included in the peeling surface F1 of the first part P1 to the peeling surface as the first recess occupancy ratio, and the area ratio of the recesses with a major diameter of 0.1 μm or more included in the peeling surface F2 of the second part to the peeling surface as the second recess occupancy ratio, the first recess occupancy ratio was less than or equal to the second recess occupancy ratio (Evaluation Criteria 14). Here, recesses (void regions) were measured by AFM for a 5 μm × 5 μm range of each peeling surface, and the major diameter, occupancy ratio, etc. could be obtained.

[0073] Also, the impurity concentration on the peeling surface F1 of the first part P1 was higher than the impurity concentration on the peeling surface F2 of the second part P2 (Evaluation Criteria 15).

[0074] Furthermore, the through - dislocation density on the upper surface 8R of the effective part YS was 5 × 10 6 [pieces / cm 2 or less (Evaluation Criteria 16).

[0075] As described above, in order to reduce surface defects in the semiconductor layer 8, it is important to reduce adhesion with the mask portion 5 to relieve stress, and to reduce the generation of voids that cause surface defects (m-plane slip).

[0076] The crystallinity of the ELO semiconductor layer 8 growing laterally on the mask 5 from the opening KS of the mask 5 is extremely high. In the semiconductor substrate 10, by reducing the interaction between the mask portion 5 and the semiconductor layer 8, voids and adhesions occurring on the back surface of the semiconductor layer 8 are reduced, and stress from the main substrate 1 is effectively relieved. As a result, it can be seen that defects occurring in the effective portion YS are confined within the semiconductor layer 8 without penetrating to the surface.

[0077] Figures 19 to 22 are plan views and schematic diagrams illustrating the evaluation of a semiconductor substrate with a different configuration (an integrated type where the ELO semiconductor layer does not have an edge surface on the mask). In this case as well, it was found that the evaluation criteria 1 to 16 were met.

[0078] Figure 23 is a cathodoluminescence (CL) image of the ELO semiconductor layer 8 of a semiconductor substrate 10 (main substrate is a silicon substrate). No dark spots or dark lines are observed in the effective area YS. Only in the non-effective area NS are there 10 threading dislocations resulting from the difference in lattice constants between the silicon substrate and GaN. 19 / cm 2 It exists to some extent.

[0079] Figure 24 shows a cathodoluminescence (CL) image of the ELO semiconductor layer 8 of semiconductor substrate 10 (main substrate is a sapphire substrate). Because the ELO semiconductor layer 8 is mechanically exfoliated from the template substrate, the non-effective area NS is slightly damaged, and the exfoliated surface is not flat, so the CL image is slightly distorted. However, in the effective area YS, no scotomas or dark lines, which are penetrating dislocations, are observed, or a low dislocation density is achieved.

[0080] Figure 25 is a CL image of the back surface (exfoliation surface) of the ELO semiconductor layer of the semiconductor substrate 10. It can be seen that there are no voids or adhesions in the effective area YS.

[0081] (Example of ELO film deposition) Figure 26 shows a CL image of the GaN layer surface in a reference example. In this reference example, sapphire is used as the main substrate, and the GaN layer is deposited by the ELO method. On the aperture, there are scotomas (10) which are high-density threading dislocations. 18 ~10 19 / cm 2 Both scotoma and dark lines are present. Furthermore, scotoma and dark lines are observed on the mask area, although the density is lower than on the aperture. Figure 27 shows a CL image of the GaN layer surface in a reference example. In this reference example, silicon is used as the main substrate, and the GaN layer is deposited by the ELO method. Above the opening, 10 19 / cm 2 A certain degree of scotoma was observed, and dark lines were also observed on the masked area.

[0082] Figure 28 shows a CL image of the back surface of the GaN layer in a reference example. In this reference example, silicon was used as the main substrate, and the GaN layer was deposited by the ELO method. Numerous voids are observed at the edges of the mask area.

[0083] Figure 29 is an optical microscope image of the back surface (exfoliation surface) of the GaN layer of a reference example film deposited by the ELO method. The adhesion NL (reaction layer) between the mask and the GaN layer can be seen. If such a GaN layer is mechanically peeled off from the mask (for example, using a diamond pen), the GaN layer and the mask will peel off together from the template substrate, as shown in the peeling region NA of Figure 30.

[0084] The example shows that simply using the ELO method does not eliminate voids and adhesions, nor does it significantly reduce surface defects on the mask. Regarding dark lines (linear defects), their occurrence has a wide-ranging impact, so reducing them is of great significance.

[0085] (Example 1) Figure 31 is a cross-sectional view showing the configuration of the semiconductor substrate of Example 1. A silicon substrate having a (111) plane was used as the main substrate 1. The buffer layer 2 of the underlayer 4 was an AlN layer (for example, 30 nm). The seed layer 3 of the underlayer 4 was the first layer Al 0.6 Ga 0.4 A graded layer was formed in the following order: an N layer (e.g., 300 nm) and a second GaN layer (e.g., 1-2 μm). That is, the composition ratio of Ga in the second layer (Ga:N=1:1) (1 / 2=0.5) is greater than the composition ratio of Ga in the first layer (Al:Ga:N=0.6:0.4:1) (0.6 / 2=0.3).

[0086] The mask layer 6 used a laminate in which a silicon oxide film (SiO2) and a silicon nitride film (SiN) were formed in that order. The thickness of the silicon oxide film was, for example, 0.3 μm, and the thickness of the silicon nitride film was, for example, 70 nm. Plasma chemical vapor deposition (CVD) was used to deposit both the silicon oxide film and the silicon nitride film.

[0087] The semiconductor layer 8 was a GaN layer, and ELO deposition was performed using an MOCVD apparatus. First, the ELO semiconductor layer 8 was selectively grown on the surface of the seed layer 3 (the second GaN layer) exposed in the opening KS, and then subsequently grown laterally on the mask portion 5. At this time, growth was stopped before the semiconductor layers growing laterally from both sides on the mask portion 5 met. The width of the gap GP at this time was 2 μm.

[0088] The width WM of the mask portion 5 was 50 μm, the width of the aperture KS was 5 μm, the width WL of the ELO semiconductor layer 8 was 53 μm, and the width (size in the X direction) of the effective portion YS was 24 μm. The thickness of the ELO semiconductor layer 8 was 5 μm, and the aspect ratio of the ELO semiconductor layer 8 was 53 μm / 5 μm = 10.6, achieving a very high aspect ratio.

[0089] When the semiconductor substrate 10 obtained in Example 1 was evaluated, it was found that the above-mentioned evaluation criteria 1 to 16 were met.

[0090] The semiconductor layer 8 can be peeled off during back surface evaluation as follows. For example, if the mask layer 6 is formed of a silicon oxide film, nitride film, or oxynitride film, the semiconductor substrate 10 that has undergone the device isolation process (see Figures 8 and 9) can be immersed in hydrofluoric acid etchant for 10 to 60 minutes. This dissolves the mask layer 6 in the etchant, allowing the semiconductor layer 8 to be peeled off from the template substrate 7.

[0091] As an alternative delamination method, as shown in Figure 32, the semiconductor substrate 10 may be immersed in a hydrofluoric acid etchant to dissolve the mask layer 6, and then an adhesive tape (for example, an adhesive dicing tape used when dicing semiconductor wafers) may be attached to the surface of the semiconductor layer 8. The semiconductor substrate 10 with the adhesive tape attached may then be lowered to a low temperature using a Peltier element. In this case, the adhesive tape, which generally has a larger coefficient of thermal expansion than the semiconductor, will shrink significantly, applying stress to the semiconductor layer 8. Since the semiconductor layer 8 is bonded to the template substrate 7 only within the opening KS, and the mask portion 5 has been removed, the stress from the adhesive tape is effectively applied to the bond with the template substrate 7, allowing the bond to be mechanically cleaved or destroyed. In other words, the bond does not need to be removed by dry etching.

[0092] (Example 2) Figure 33 is a cross-sectional view showing the configuration of the semiconductor substrate of Example 2. In Example 2, an integrated ELO semiconductor layer 8 without an edge surface was adopted on the mask portion 5. The width of the mask portion 5 is 50 μm, and the width of the opening KS is 5 μm. From the viewpoint of relaxing film stress, the height of the hollow portion 8C is preferably 1 μm or more. The width of the bottom surface of the hollow portion 8C is also preferably 1 μm or more, and more preferably 2 μm or more.

[0093] When the semiconductor substrate 10 obtained in Example 2 was evaluated, it was found that the above-mentioned evaluation criteria 1 to 16 were met.

[0094] (Example 3) Figure 34 is a cross-sectional view showing the configuration of the semiconductor substrate of Example 3. In Example 3, the aperture width KS is 700 nm with a width of 1 μm or less, and the width of the mask portion 5 is 100 μm. In Example 3, the width of the effective portion YS can be made wider, making it suitable for high-power laser semiconductor elements (ridge width of about 40 μm), etc. Figure 34 shows a structure in which the semiconductor layer 8 has an edge surface on the mask portion 5, but an integrated type without an edge on the mask portion 5 is also acceptable.

[0095] When the semiconductor substrate 10 obtained in Example 3 was evaluated, it was found that the above-mentioned evaluation criteria 1 to 16 were met.

[0096] (Example 4) Figure 35 is a cross-sectional view showing the configuration of Example 4. In Example 4, a functional layer 9 constituting an LED is deposited on a semiconductor layer 8. The semiconductor layer 8 is an n-type semiconductor doped with, for example, silicon. The functional layer 9 includes, in order from the bottom layer, an active layer 34, an electron blocking layer 35, and a GaN-based p-type semiconductor layer 36. The active layer 34 is MQW (Multi-Quantum Well) and includes an InGaN layer and a GaN layer. The electron blocking layer 35 is, for example, an AlGaN layer. The GaN-based p-type semiconductor layer 36 is, for example, a GaN layer. The anode 38 is formed to be in contact with the GaN-based p-type semiconductor layer 36, and the cathode 39 is formed to be in contact with the semiconductor layer 8.

[0097] Voids on the back surface of the semiconductor layer cause surface defects (linear defects), degrading the characteristics of the semiconductor device. Furthermore, if the semiconductor device is a light-emitting element, voids on the back surface of the semiconductor layer reduce the in-plane uniformity of the emitted light. In Example 6, an element portion (light-emitting portion) DS is formed on the ELO semiconductor layer 8, and this can be peeled off to obtain the semiconductor device 20, which is a light-emitting element, thus improving these problems. Specifically, no defects were observed in the light-emitting region of the semiconductor device 20.

[0098] Figure 36 is a cross-sectional view showing an application example of Embodiment 4. Embodiment 4 allows for the creation of a red micro-LED 20R, a green micro-LED 20G, and a blue micro-LED 20B. By mounting these on a drive substrate (TFT substrate) 23, a micro-LED display 30D (electronic device) can be constructed. As an example, the red micro-LED 20R, green micro-LED 20G, and blue micro-LED 20B are mounted on multiple pixel circuits 27 of the drive substrate 23 via a conductive resin 24 (for example, an anisotropic conductive resin), and then a control circuit 25 and a driver circuit 29 are mounted on the drive substrate 23. A portion of the driver circuit 29 may be included in the drive substrate 23.

[0099] (Example 5) Figure 37 is a cross-sectional view showing the configuration of Example 5. In Example 5, a functional layer 9 constituting a semiconductor laser is deposited on a semiconductor layer 8. The functional layer 9 includes, in order from the bottom layer, an n-type optical cladding layer 41, an n-type optical guide layer 42, an active layer 43, an electron blocking layer 44, a p-type optical guide layer 45, a p-type optical cladding layer 46, and a GaN-based p-type semiconductor layer 47. InGaN layers can be used for each guide layer 42-45. GaN layers or AlGaN layers can be used for each cladding layer 41-46. The anode 48 is formed to be in contact with the GaN-based p-type semiconductor layer 47.

[0100] In Example 5, as shown in Figure 37, the cathode 49 is formed on the back surface of the semiconductor layer 8 after the element portion DS is peeled off. Therefore, the quality of the back surface of the semiconductor layer 8 affects the device characteristics.

[0101] (Example 6) Figure 38 is a cross-sectional view showing the configuration of Example 6. Figure 39 is a cross-sectional view showing an alternative configuration of Example 6. In Example 6, a sapphire substrate with a textured surface is used as the main substrate 1. The underlayer 4 has a buffer layer 2 and a seed layer 3. The semiconductor layer 8 may have an edge surface on the mask 5 (Figure 38) or be an integrated type without an edge surface on the mask (Figure 39). In Example 6, a GaN layer with a (20-21) plane can be deposited on the main substrate 1 as the underlayer 4. In this case, the ELO semiconductor layer 8 becomes the (20-21) plane, which is the crystal main plane, in the underlayer 4, and a semipolar ELO semiconductor layer 8 can be obtained. By providing a functional layer for lasers and LEDs on the semipolar plane, there are advantages such as a lower piezoelectric field and a higher probability of electron-hole recombination in the active layer. Note that by using a sapphire substrate with a textured surface, a GaN layer with a (11-22) plane can also be deposited on the main substrate 1 as the underlayer 4.

[0102] (manufacturing equipment) The method for manufacturing the semiconductor substrate 10 includes at least the step of forming a semiconductor layer 8 on a template substrate 7 using the ELO method. It may also include the step of forming a base layer 4 and a mask layer 6 on a main substrate 1.

[0103] The semiconductor substrate 10 can be manufactured, for example, using the semiconductor substrate manufacturing apparatus shown in Figure 40. The semiconductor substrate manufacturing apparatus 70 includes at least a semiconductor layer formation unit 71 that performs the process of forming a semiconductor layer 8 on a template substrate 7 using the ELO method, and a control unit 72 that controls the semiconductor layer formation unit 71. The semiconductor layer formation unit 71 may include an MOCVD apparatus, and the control unit 72 may include a processor and memory. The control unit 72 may be configured to control the semiconductor layer formation unit 71 by executing a program stored in, for example, an internal memory, a communication device, or an accessible network, and this program and the recording medium on which this program is stored are also included in this embodiment. The semiconductor substrate manufacturing apparatus 70 may include a template substrate formation unit that performs the process of forming an underlayer 4 and a mask layer 6 on a main substrate 1, a functional layer formation unit that performs the process of forming a functional layer 9 on the semiconductor layer 8, and so on. Furthermore, a semiconductor device manufacturing apparatus that performs the process of element delamination can also be configured. The semiconductor device manufacturing apparatus may perform the process of element isolation. The semiconductor device manufacturing apparatus may include the semiconductor substrate manufacturing apparatus 70.

[0104] (Additional items) The inventions described in this disclosure have been explained above based on the drawings and embodiments. However, the inventions described in this disclosure are not limited to the embodiments described above. That is, the inventions described in this disclosure can be modified in various ways within the scope shown in this disclosure, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the inventions described in this disclosure. In other words, it should be noted that it is easy for those skilled in the art to make various modifications or alterations based on this disclosure. Furthermore, it should be noted that these modifications or alterations are included in the scope of this disclosure. [Explanation of Symbols]

[0105] 1 Main board 2 buffer layers 3. Seed Layer 3S Seed Section 4 Base layer 5 Mask section 6 Mask Layers 8 Semiconductor layer 9 Functional Layers 10 Semiconductor substrates 20 Semiconductor Devices 30 Electronic equipment 70 Semiconductor substrate manufacturing equipment KS opening YS Effective Section

Claims

1. A main substrate having a lattice constant different from that of a GaN-based semiconductor, and a template substrate having a seed portion and a non-seed portion located above the main substrate, A semiconductor layer comprising a GaN-based semiconductor having a first crystalline portion located above the seed portion and a second crystalline portion located above the non-seed portion, The second crystal portion has a first region having a width of 10 [μm] in a first direction along the width direction of the seed portion, and a second region located further away from the first crystal portion compared to the first region. A semiconductor substrate in which, when the semiconductor layer is peeled off from the template substrate, the number of recesses with a major axis of 0.1 [μm] or more in the first region is less than the number of recesses with a major axis of 0.1 [μm] or more in the second region.

2. The semiconductor substrate according to claim 1, wherein the major axis of the recess in the first region is 1 [μm] or less.

3. The template substrate comprises a mask portion which is the non-seed portion and a portion where the seed portion is exposed. Having a mask pattern including an opening, The second crystal portion is located between the opening and the center of the mask portion in a plan view. The semiconductor substrate according to claim 1.

4. In a plan view, the first region is adjacent to the opening, and the second region and the The semiconductor according to claim 3, wherein the distance from the center of the mask portion is 30% or less of the width of the mask portion. Body substrate.

5. The semiconductor substrate according to any one of claims 1 to 4, wherein the first direction is the <11-20> direction of the semiconductor layer.

6. The semiconductor substrate according to any one of claims 1 to 4, wherein the second crystal portion has a longitudinal shape with the second direction perpendicular to the first direction as its longitudinal direction.

7. The semiconductor substrate according to claim 6, wherein the end of the second crystal portion located on the seed portion side has a higher concentration of impurities compared to the end located away from the seed portion with respect to the first direction.

8. The penetration dislocation density on the upper surface of the second crystal portion is 5 × 10 ６ [pcs / cm ２ The semiconductor substrate according to any one of claims 1 to 4, wherein the semiconductor substrate is as follows:

9. A layer above the main substrate contains a sheet containing group III atoms other than Ga, Ga, and nitrogen atoms. Including the top layer, The seed portion includes a first layer on the main substrate side and a second layer above the first layer. The composition ratio of Ga in the second layer is greater than the composition ratio of Ga in the first layer. A semiconductor substrate according to any one of claims 1 to 4.

10. The semiconductor layer is provided on the semiconductor layer, according to any one of claims 1 to 4. Conductive substrate.

11. A semiconductor device comprising the semiconductor layer and functional layer described in claim 1.

12. An electronic device comprising the semiconductor device described in claim 11.

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