Cache-based memory access tracking

Abstract

The present invention provides a device, method, non-temporary computer-readable storage medium, and memory tracking circuit that reduce processing overhead and improve performance. [Solution] The device 100 for executing a software program comprises a processing unit 101, a plurality of memory components, each connected to the processing unit and mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit, and at least one memory tracking circuit connected to the processing unit and at least one memory component. In each of a plurality of iterations, the memory tracking circuit responds to the reception of a memory access command from the processing unit, updates at least one of a plurality of statistical counters, and provides one or more of the plurality of statistical counters to a memory management component in order to map the application memory of the software program to the memory component.

Description

Technical Field

[0001] The present disclosure relates to a computerized device, and more particularly, but not limited to, a computerized device having two or more memory components.

Background Art

[0002] For the sake of brevity, hereinafter, the term "system" is used to mean a computerized system, and these terms are used interchangeably.

[0003] There are numerous metrics for measuring the performance of a computerized system, such as throughput, i.e., the amount of tasks executed within an identified time interval, and latency, i.e., the amount of time a task is delayed before being executed. For example, improving the performance of a system by increasing the throughput of the system and, additionally or alternatively, reducing the latency of the system depends, among other factors, on the amount of computer resources available within the system and how well the various components of the system work together. For example, reducing latency when accessing memory and, additionally or alternatively, increasing the throughput of memory access can improve the performance of the system.

[0004] Memory components with relatively higher performance access characteristics, such as low-latency memory components, or high-throughput memory components, such as static RAM (SRAM), are typically more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). To balance system cost and performance, it is customary to design a system's memory using two or more types of memory components. Some common system designs organize multiple memory components in multiple layers of memory, where smaller, faster layers overshadow larger, slower layers, acting as a cache to the larger layers. In some designs, there is a hierarchy of layers, with only the largest layer available for use by software programs, i.e., addressable using the application memory address of the software program, while the other layers in the hierarchy act as a hierarchical cache.

[0005] Some other system designs make all layers of memory addressable using the application memory addresses of software programs. In such systems, the system's performance is affected by the distribution of the software program's application memory among multiple layers of memory, i.e., among one or more memory components of the system. When the software program's application memory comprises multiple application memory areas, performance can be improved if frequently accessed application memory areas are stored in one or more high-performance memory components, while lower-performance memory components are used to store less frequently accessed application memory areas.

[0006] The term non-uniform memory access (NUMA) refers to a computerized system with two or more memory components, where several characteristics of memory access from processing units to memory components, such as latency and, additionally or alternatively, throughput, depend on the system topology, for example, the location of the memory components relative to the processing units. Similar to the systems described above, in a system with NUMA, the system's performance may be affected by the distribution of application memory of software programs among one or more memory components. [Overview of the project] [Means for solving the problem]

[0007] This disclosure includes a description of apparatus and methods for tracking memory access and managing memory. In some embodiments described herein, one or more memory tracking circuits are used to update at least one of a plurality of statistical counters in response to receiving a memory access command from a processing unit. Furthermore, in such embodiments, one or more memory tracking circuits are configured to provide one or more of a plurality of statistical counters to a memory management component for the purpose of mapping the application memory of a software program to a plurality of memory components connected to a processing unit. Updating at least one statistical counter using one or more memory tracking circuits reduces the amount of processing overhead required from the processing unit to track memory access and to manage the allocation of the application memory of a software program to a plurality of memory components, thereby improving the performance of the apparatus.

[0008] The above and other objectives are achieved by the features of the independent claims. Further implementations are evident from the dependent claims, description, and figures.

[0009] According to a first embodiment, the apparatus for executing a software program comprises a processing unit, at least one memory component, each connected to the processing unit and mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit, and at least one memory tracking circuit connected to the processing unit and the at least one memory component, wherein the at least one memory tracking circuit is configured to update at least one of a plurality of statistical counters in response to receiving a memory access command from the processing unit in each iteration of a plurality of iterations, and to provide one or more of the plurality of statistical counters to a memory management component for the purpose of mapping the application memory of the software program to the at least one memory component.

[0010] According to a second aspect, a method for managing memory in a device for executing one or more software programs includes, in each of a plurality of iterations, the steps of updating at least one statistical counter among a plurality of statistical counters in response to receiving a memory access command from a processing unit by at least one memory tracking circuit connected to a processing unit and at least one memory component connected to the processing unit, each of the at least one memory component being mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit; and providing one or more of the plurality of statistical counters to a memory management component for the purpose of mapping the application memory of a software program to at least one memory component.

[0011] According to a third aspect, a software program product for memory management comprises a non-temporary computer-readable storage medium and a program instruction for receiving one or more of a plurality of statistical counters from a processing unit and at least one memory tracking circuit connected to at least one memory component connected to the processing unit, in each of one or more management iterations, for the purpose of mapping the application memory of the software program to at least one memory component, wherein each of the at least one memory component is mapped to at least one range of memory addresses from a plurality of memory address ranges of the processing unit. According to a third aspect, the program instruction is executed from the non-temporary computer-readable storage medium by at least one computerized processor.

[0012] According to a fourth aspect, a method for a memory management component includes, in each management iteration of one or more management iterations, receiving one or more statistical counters from a processing unit and at least one memory tracking circuit connected to at least one memory component connected to the processing unit, for the purpose of mapping the application memory of a software program to at least one memory component, wherein each of the at least one memory component is mapped to at least one range of memory addresses from a plurality of memory address ranges of the processing unit.

[0013] According to a fifth aspect, a memory tracking circuit comprising a plurality of statistical counters comprises a high access counter, a low access counter, and a plurality of range access counters. According to a fifth aspect, when the memory tracking circuit is connected to a processing unit and to at least one memory component, each of which is connected to the processing unit and mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit, and each of the plurality of range access counters is associated with one of the plurality of memory address ranges, in each iteration of a plurality of iterations, in response to receiving a memory access command from the processing unit, the memory tracking circuit is configured to: identify a memory address in a memory access command; identify a memory address range among the plurality of memory address ranges, wherein the memory address range contains a memory address; increment each range access counter associated with the memory address range; increment the high access counter when each range access counter exceeds a high access threshold; and provide one or more of the plurality of statistical counters to a memory management component for the purpose of mapping the application memory of a software program to at least one memory component.

[0014] In one implementation of the first and second embodiments, the multiple statistical counters include at least one watermark counter selected from a group consisting of high-access counters and low-access counters, and at least one of a plurality of range access counters, each associated with one of a plurality of memory address ranges. Using at least one watermark counter in addition to the plurality of range access counters reduces the amount of access to the plurality of range access counters, thereby reducing the amount of computing resources required for memory management compared to a method that accesses all of the plurality of range access counters. In some cases, at least one other of the plurality of statistical counters is implemented in at least one memory tracking circuit. Implementing statistical counters in a memory tracking circuit reduces the amount of computing resources required to track one or more memory accesses compared to a method that implements statistical counters in a page table of an operating system executed by a processing unit that runs a software program. In some cases, at least one yet another of the plurality of statistical counters is implemented in a cache memory component connected to one or more of at least one memory components. In some cases, at least one yet another of the plurality of statistical counters is implemented in one of at least one memory components.

[0015] In other implementations of the first and second embodiments, updating at least one statistical counter includes identifying a memory address in a memory access command, identifying a memory address range among a plurality of memory address ranges, the memory address range that contains a memory address, incrementing each range access counter, and incrementing the high access counter when each range access counter exceeds a high access threshold. Incrementing the high access counter when each range access counter associated with a memory address range exceeds a high access threshold reduces the amount of access to multiple range access counters and reduces the amount of computing resources required for memory management compared to a method of accessing all of the multiple range access counters. In some cases, providing one or more statistical counters to a memory management component includes providing at least one watermark counter and providing at least one range access counter among a plurality of range access counters in response to a request from the memory management component. In some cases, the memory management component is configured to perform another analysis comprising at least one watermark counter and send a request to at least one memory tracking circuit to provide at least one range access counter according to another result of that other analysis. Providing one or more statistical counters from at least one memory tracking circuit to a memory management component in two or more steps, and according to the execution of another analysis thereof, includes reducing the amount of access to multiple range access counters, reducing the amount of computing resources required for memory management compared to a method of accessing all multiple range access counters, and reducing processing time, processing complexity, and the amount of access to at least one memory tracking circuit. In some cases, the memory management component is further configured to set at least one of a low access threshold and a high access threshold within at least one memory tracking circuit.In some cases, the memory management component sets at least one of a low access threshold and a high access threshold within at least one memory tracking circuit, according to yet another result of yet another analysis comprising one or more statistical counters. Setting a low access threshold, and additionally or alternatively, a high access threshold, improves the accuracy of the high access counters and low access counters, and improves the accuracy of the memory mapping calculated according to one or more statistical counters.

[0016] In further implementations of the first and second embodiments, at least one memory tracking circuit is configured to update at least one statistical counter and to provide one or more of a plurality of statistical counters while the processing unit is executing the software program. Updating at least one statistical counter and providing one or more statistical counters while the processing unit is executing the software program allows for runtime changes to the memory mapping of the software program's application memory while the software program is running, thereby improving system performance.

[0017] In further implementations of the first and second embodiments, at least one memory tracking circuit comprises a plurality of local tracking circuits. In some cases, each of the plurality of local tracking circuits is connected to a processing unit and to one or more memory components of at least one memory component, and each of the plurality of local tracking circuits updates at least one statistical counter in response to receiving a memory access command when at least one memory address range of a plurality of memory address ranges associated with one or more memory components connected to the local tracking circuit comprises a local memory address which is a memory address in a memory address command. The use of multiple local tracking circuits enhances the usability of the method described herein in systems where at least one memory component is topologically separated from each other.

[0018] In further implementations of the first and second embodiments, the application memory of a software program comprises a plurality of application memory areas, each stored in one of at least one memory component, and the mapping of application memory by a memory management component includes performing an analysis comprising one or more statistical counters, and in response to the results of the analysis, moving at least one of the plurality of application memory areas from one of the at least one memory component to another of the at least one memory component. In some cases, a memory mapping component maps the application memory while a processing unit executes the software program. Moving application memory areas from one memory component to another while a processing unit executes the software program reduces the overall amount of latency of the multiple memory accesses performed while the software program is executed, and, in addition or alternatively, increases the overall bandwidth of the multiple memory accesses, thereby improving the performance of the device executing the software program. Performing an analysis that includes one or more statistical counters improves the accuracy of the analysis results, and moving at least one application memory area according to the analysis results improves the performance of the device running the software program, compared to other methods of selecting memory areas that do not include one or more statistical counters collected while the processing unit runs the software program, such as using static analysis of the software program.

[0019] Further implementations of the first and second embodiments include a memory tracking circuit that performs a plurality of iterations, each of which includes updating at least one statistical counter in each of one or more management iterations; providing one or more statistical counters to a memory management component; and resetting one or more of the plurality of statistical counters.

[0020] In further implementations of the first and second embodiments, the memory management component comprises software objects executed by the processing unit. In some cases, the memory management component comprises a memory management circuit connected to at least one memory tracking circuit and at least one memory component. Using a memory management circuit reduces the amount of computing resources of the processing unit required for memory management and reduces the impact of memory management on the performance of the device running the software program.

[0021] In further implementations of the first and second embodiments, the processing unit is configured to run an operating system. In some cases, the operating system addresses at least one memory component using a plurality of operating system memory pages, each having one page size of an identified set of page sizes, and at least one identified memory address range among the plurality of memory address ranges has a range size that is not equal to any of the page sizes of the set of page sizes. Tracking memory address ranges that have a range size that is not equal to any of the page sizes of the operating system's set of page sizes improves the accuracy of the analysis of one or more statistical counters and, therefore, improves the performance of the device running the software program.

[0022] In one implementation of the fourth embodiment, the group of statistical counters comprises at least one of a high-access counter, a low-access counter, and a group of range-access counters, each associated with one of a group of memory address ranges. Optionally, the step of receiving one or more statistical counters includes the step of receiving at least one of the high-access counters and the low-access counters. Optionally, the method further includes the step of performing an analysis comprising at least one of the low-access counters and the high-access counters, and sending a request to at least one memory tracking circuit to provide at least one range-access counter according to the results of the other analysis.

[0023] Other systems, methods, features, and advantages of this disclosure will be apparent to those skilled in the art upon consideration of the following drawings and detailed description. All such additional systems, methods, features, and advantages are intended to be contained within this description, within the scope of this disclosure, and protected by the appended claims.

[0024] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as those generally understood by those skilled in the art in the field relating to the implementation. Methods and materials similar to or equivalent to those described herein may be used in the implementation or testing of the implementation, but exemplary methods and / or materials are described below. In case of any inconsistency, this specification, including definitions, will take precedence. Furthermore, materials, methods, and examples are illustrative and not necessarily intended to be limiting.

[0025] Several embodiments are described herein, merely as examples, with reference to the accompanying drawings. A particular emphasis is placed upon the drawings, with reference to the drawings in particular, that the details shown are illustrative and for illustrative purposes only. In this regard, the description, as interpreted in conjunction with the drawings, will make it clear to those skilled in the art how the embodiments may be carried out.

[0026] In the drawings, it is as follows.

Brief Description of the Drawings

[0027] [Figure 1] It is a schematic block diagram of an exemplary apparatus according to some embodiments. [Figure 2] It is a schematic block diagram of another exemplary apparatus according to some embodiments. [Figure 3] It is a schematic block diagram of an exemplary address mapping according to some embodiments. [Figure 4] It is a flowchart schematically representing any flow of operations for managing memory according to some embodiments. [Figure 5] It is a flowchart schematically representing any flow of operations for updating a statistical counter according to some embodiments. [Figure 6] It is a flowchart schematically representing any flow of operations for memory management according to some embodiments. [Figure 7] It is a sequence diagram of any flow of operations according to some embodiments. [Figure 8] It is a schematic block diagram of an exemplary memory mapping according to some embodiments. [Figure 9] It is a schematic block diagram of another exemplary memory mapping according to some embodiments.

Modes for Carrying Out the Invention

[0028] As used herein, the term “processing unit” refers to any type of programmable or non-programmable circuit configured to perform the operations described below. A processing unit may comprise hardware and software. For example, a processing unit may comprise one or more processors and temporary or non-temporary memory for carrying programs that cause the processing unit to perform their respective operations when the programs are executed by one or more processors.

[0029] Furthermore, as used herein, the term “physical address” means an address used by a processing unit in a memory access request to access a memory component. Furthermore, as used herein, the term “application address” means an address used in an application. An application address may be a virtual address, in which case it is necessary to translate the application address to a physical address for the purpose of accessing one or more memory components. As used herein, the term “memory mapping” refers to mapping the application memory address of a software program to a physical address in a memory access request sent by a processing unit. Such mapping may be used to translate an application address to a physical address that identifies a location in a memory component where application data or instructions are stored.

[0030] Furthermore, as used herein, the terms “memory access request” and “memory access command” are both used interchangeably to mean a request to access a memory component for the purpose of reading from the memory component and writing to the memory component as an addition or replacement. A memory access request may be generated when executing a computer instruction of a software program that includes a memory access computer instruction.

[0031] Furthermore, as used herein, the terms “range of memory addresses” and “range of memory addresses” are both used interchangeably to mean a range of memory addresses.

[0032] To improve system performance, some systems track access to one or more memory components in order to allocate each of multiple application memory areas to one or more memory components connected to the processing unit. Some existing tracking methods maintain access counters in a page table used to map application addresses to physical addresses. Such methods require updating the counters in the page table each time memory is accessed. Furthermore, analyzing multiple counters in the page table requires merging counters for multiple virtual pages mapped to a common physical page. Some methods further require sorting multiple counters to categorize page table entries, for example, to identify page table entries describing high-access application memory areas. Such methods reduce system performance because they require computing resources from the processing unit.

[0033] In some other methods of tracking memory access, the processing unit maintains multiple counters stored in one or more memory components. In systems implementing such methods, each memory access request from the processing unit requires two accesses from the processing unit to memory: one to update the counters and the other to access the data in memory, thus reducing the effective memory throughput (i.e., access to the application memory area).

[0034] To reduce the amount of computing resources used by a processing unit to track multiple memory accesses, the Disclosure proposes, in some embodiments described herein, the use of one or more memory management circuits connected to the processing unit and one or more memory components to update at least one of a plurality of statistical counters in response to the reception of memory access commands from the processing unit. In some cases, the statistical counter indicates a plurality of memory access commands. For example, when the processing unit has a plurality of memory address ranges, and each of one or more memory components is mapped to one or more of the plurality of memory address ranges, the statistical counter may be a range access counter associated with the memory address range, indicating the amount of time the memory address range is accessed in a plurality of memory access commands. In some cases, the statistical counter indicates an amount of range access counters that meet an identified criterion. For example, the statistical counter may be a watermark counter, indicating an amount of range access counters that exceed a high access threshold, where the high access threshold indicates an amount of access to a memory address range considered high. Alternatively, the watermark counter may indicate an amount of range access counters that are below a low access threshold, where the low access threshold indicates another amount of access to a memory address range considered low. In some cases, a statistics counter indicates the number of memory access commands received from the processing unit. In some cases, one or more processing circuits receive memory access commands in each of several iterations and update at least one of several statistics counters in each of several iterations. Updating at least one statistics counter using one or more processing circuits reduces the amount of resources used by the processing unit to track multiple memory accesses, for example, by reducing the number of memory accesses performed by the processing unit and, as an addition or replacement, by reducing the amount of processor cycles used by the processing unit to compute memory mappings.Reducing the amount of computing resources used by processing units improves system performance when running software programs, for example, by increasing throughput and, in addition or alternatively, by reducing latency when performing one or more tasks of the software program.

[0035] In some cases, at least one of several statistical counters is implemented within one or more memory tracking circuits, further reducing the amount of access to one or more memory components, and thus improving system performance.

[0036] Furthermore, in some embodiments, the disclosure proposes that one or more memory tracking circuits provide a memory management component with one or more statistical counters for the purpose of mapping the application memory of a software program to one or more memory components. In some cases, the memory management component performs analysis of one or more statistical counters for the purpose of mapping application memory. In some cases, the memory management component comprises software objects executed by a processing unit. In some cases, the memory management component comprises other circuits, possibly connected to one or more memory tracking circuits and one or more memory components. Providing one or more statistical counters to the memory management component makes it possible to improve system performance by moving one or more application memory areas of a software program from one or more memory components to another of the one or more memory components. For example, a range access counter for a range of memory addresses exceeding a high access threshold may indicate that that range of memory addresses is accessed frequently, and the application memory area of ​​multiple application memory areas referenced by that range of memory addresses should be stored in a memory component that has relatively higher performance access characteristics, e.g., low latency, and, in addition or alternatively, high throughput. Similarly, a range access counter for another range of memory addresses that falls below a low access threshold may indicate that that other range of memory addresses is rarely accessed, and that other application memory area among several application memory areas referenced by that other range of memory addresses should be stored in another memory component with relatively lower performance access characteristics, such as higher latency and, additionally or alternatively, lower throughput, rather than a memory component with relatively higher performance access characteristics.In some cases, memory mapping components map application memory while the processing unit executes a software program, and in some cases, move one or more application memory areas while the processing unit executes a software program.

[0037] In some embodiments described herein, at least one memory component is a plurality of memory components comprising at least two memory components. In some cases, one or more memory tracking circuits comprise a plurality of local tracking circuits, such that each of the plurality of local tracking circuits is connected to one or more of the plurality of memory components. In some cases, each local tracking circuit is connected to a subset of the plurality of memory components, such that a local tracking circuit is not connected to at least one of the plurality of memory components. In some cases, each local tracking circuit updates at least one statistical counter according to one or more memory components connected to it, i.e., in response to the receipt of a memory access command, when at least one of a plurality of memory address ranges associated with one or more memory components connected to the local tracking circuit comprises a local memory address in a memory address command. When a processing unit is connected to at least one memory component via a host memory controller, the local tracking circuits connected to at least one memory component are, in some cases, further connected to the host memory controller.

[0038] In some cases, when one or more memory tracking circuits provide one or more statistical counters to a memory management component, the one or more statistical counters include one or more watermark counters. In some cases, the memory management component performs another analysis of one or more watermark counters, and according to the results of that other analysis, the memory management component sends a request to one or more memory tracking circuits to provide, in some cases, at least one range access counter. For example, the memory management component may request at least one range access counter only when the results of that other analysis indicate that a high watermark counter exceeds an identified threshold. In this example, it is not necessary to move the memory area as long as the amount of ranges receiving high access is below the threshold. This requires fewer computing resources compared to some other methods that require reading all multiple range access counters to identify whether it is not necessary to move the memory area. In another example, the memory management component may request one or more range access counters until it receives an amount of range access counters that exceeds a high watermark threshold equal to a high watermark counter. In this example, identifying all memory areas receiving high access rates can be achieved without reading all multiple memory counters, requiring fewer computing resources than some other methods that do not use watermark counters.

[0039] When a processing unit executes an operating system, the operating system may address multiple memory components using multiple operating system memory pages. It is customary not to use an arbitrary page size for multiple operating system memory pages; that is, each of the multiple operating system memory pages has one page size from an identified set of page sizes. When memory access tracking is performed using the operating system's page table, the granularity of the memory access tracking follows the respective page sizes of each of the multiple operating system memory pages. In some embodiments described herein, at least one identified memory address range among multiple memory address ranges has a range size that is not equal to any of the page sizes in the set of page sizes. Tracking multiple memory access commands according to multiple memory address ranges using one or more memory tracking circuits allows tracking multiple memory access commands at a granularity different from the operating system's page size, improving the accuracy of memory mapping calculated according to multiple statistical counters compared to memory mapping calculated when tracking follows the operating system's page size, and thus improving the accuracy of the allocation of multiple application memory areas to one or more memory components, thereby improving system performance.

[0040] Before describing in detail at least one embodiment, it should be understood that the embodiment is not necessarily limited in its application to the details of configuration and arrangement of components and / or methods described below, and / or shown in the drawings and / or examples. Other embodiments are possible or can be carried out in various ways.

[0041] Embodiments may be systems, methods, and / or computer program products. A computer program product may include a computer-readable storage medium (or more mediums) having computer-readable program instructions thereon for causing a processor to perform an aspect of the embodiment.

[0042] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any preferred combination thereof. A non-exhaustive list of more specific examples of computer-readable storage mediums includes, namely, portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital multipurpose disks (DVDs), memory sticks, floppy disks, and any preferred combination thereof. The computer-readable storage mediums used herein should not be interpreted as being transient signals in themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0043] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmitters, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives computer-readable program instructions from the network and transfers them for storage in a computer-readable storage medium within the respective computing / processing device.

[0044] The computer-readable program instructions for performing the operation of the embodiments may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code that is natively compiled or just-in-time (JIT) compiled, written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, Java, object-oriented Fortran, interpreted programming languages ​​such as JavaScript, Python, and traditional procedural programming languages ​​such as the C programming language, Fortran, or similar programming languages. The computer-readable program instructions may run entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (for example, via the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute a computer-readable program instruction by utilizing state information of the computer-readable program instruction to personalize the electronic circuit in order to perform an aspect of the embodiment.

[0045] The aspects of the embodiments will be described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to the embodiments. It will be understood that each block in the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0046] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a dedicated computer, or other programmable data processing device to create a machine, such that the instructions executed via the computer or other programmable data processing device processor create means for performing a function / operation specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can instruct a computer, a programmable data processing device, and / or other device to function in a particular way, such that the computer-readable storage medium having the instructions stored therein comprises a product containing instructions that perform a mode of function / operation specified in one or more blocks of a flowchart and / or block diagram.

[0047] Computer-readable program instructions may also be loaded onto a computer, another programmable device, or another device to create a process performed by the computer, another programmable device, or another device, so that a series of operational steps are executed on the computer, another programmable device, or another device, causing the instructions executed on the computer, another programmable device, or another device to perform a function / operation specified in one or more blocks of a flowchart and / or block diagram.

[0048] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products in various embodiments. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions mentioned in a block may be performed in a different order than those mentioned in the diagram. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or they may be executed in reverse order. It should also be noted that each block in a block diagram and / or flowchart, as well as any combination of blocks in a block diagram and / or flowchart, may be implemented by a dedicated hardware-based system that performs a specified function or operation, or a combination of dedicated hardware and computer instructions.

[0049] Next, Figure 1 is shown, which illustrates a schematic block diagram of an exemplary apparatus 100 according to several embodiments. In such embodiments, the processing unit 101 is connected to at least one memory component 120.

[0050] For brevity, the term “memory component 120” will hereafter be used to mean “at least one memory component 120,” and these terms will be used interchangeably. In some cases, memory component 120 comprises one memory component, for example, memory component 120C. In some cases, memory component 120 comprises two or more memory components, for example, memory component 120A, memory component 120B, and memory component 120C. The memory components may be random access memory (RAM) components, for example, SRAM components or DRAM components. Other examples of memory components include read-only memory (ROM) components, electrically erasable programmable ROM (EEPROM), and non-volatile RAM (NVRAM). In some cases, one or more of the memory components 120 are electrically coupled to the processing unit 101. In some cases, one or more of the memory components 120 are connected to the processing unit 101 via a host memory controller (not shown).

[0051] In some cases, one or more of the memory components 120 are cache memory components of the processing unit 101. In some cases, one or more of the memory components 120 are connected to another cache memory component (not shown) further connected to the processing unit 101.

[0052] In some cases, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory component 120.

[0053] Next, see also Figure 2, which shows a schematic block diagram of another exemplary apparatus 200 according to several embodiments. In such embodiments, one or more memory tracking circuits 130 comprise a plurality of local tracking circuits 201, for example, comprising local tracking circuits 201A and local tracking circuits 201B. In some cases, each of the plurality of local tracking circuits 201 is connected to one or more of the memory components 120. In some cases, each of the plurality of local tracking circuits is connected to a subset of the memory components 120, such that each of the plurality of local tracking circuits 201 is not connected to at least one of the memory components 120. In this example, local tracking circuit 201A is connected to memory components 120A and 120B, but not to memory component 120C. Furthermore, in this example, local tracking circuit 201B is connected to memory component 120C, but not to memory components 120A and 120B. In some cases, each of the plurality of local tracking circuits 201 is connected to exactly one of the memory components 120.

[0054] Next, Figure 1 is referred to again. In some cases, each of the memory components 120 is mapped to at least one range of memory addresses among multiple memory address ranges of the processing unit 101.

[0055] Next, see also Figure 3, which shows a schematic block diagram of an exemplary address mapping 300 according to several embodiments. In this example, the memory component 120A is mapped to memory address ranges 301A, 301B, and 301C, among a plurality of memory address ranges 301. Therefore, when the processing unit 101 accesses a memory address in one of the memory address ranges 301A, 301B, and 301C, the processing unit 101 accesses the memory component.

[0056] Similarly, memory component 120B is mapped to memory address range 301D among the multiple memory address ranges 301, and memory component 120C is mapped to memory address ranges 301E and 301F among the multiple memory address ranges 301.

[0057] In some cases, the processing unit 101 executes an operating system that addresses the memory component 120 using multiple operating system memory pages. In some cases, each of the multiple operating system memory pages has a page size that is one of the page sizes in an identified set of page sizes. In some cases, at least one of the multiple memory address ranges 301 has a size that is not an element of the identified set of page sizes.

[0058] Next, Figure 1 is referenced again. In some cases, one or more memory tracking circuits 130 are connected to the memory management component 110. In some cases, the memory management component 110 comprises software objects executed by the processing unit 101. In some cases, the memory management component 110 comprises memory management circuits further connected to the processing unit 101 and the memory component 120.

[0059] To track memory access commands and manage memory, any of the following methods may be implemented by system 100 or system 200 in some embodiments.

[0060] Next, see also Figure 4, which shows a flowchart schematically representing an arbitrary flow of operation 400 for managing memory according to several embodiments. In such embodiments, in 401, one or more memory tracking circuits 130 receive a memory access command from the processing unit 101, which includes a memory address. In some cases, the memory address is in one of a plurality of memory address ranges 301. For example, when the memory address is in the memory address range 301E, the memory address is the local memory address of memory component 120C. In this example, the memory address range 301E includes the local memory address of memory component 120C, which is the memory address in the memory access command. In some cases, the processing unit 101 sends a memory access command when executing a software program, possibly for the purpose of accessing the application memory of the software program.

[0061] In 410, one or more memory tracking circuits 130 may update at least one of a plurality of statistical counters. The plurality of statistical counters may comprise a plurality of range access counters, each associated with one of a plurality of memory address ranges 301. The plurality of statistical counters may comprise one or more watermark counters, each associated with a frequency of access to a memory component. A watermark counter may indicate the amount of a memory access range accessed at a frequency associated with the watermark counter. A watermark counter may be a high access counter indicating a range access counter among a plurality of range access counters that exceeds a high access threshold, indicating frequent access to each memory component associated with a range access counter that exceeds a high access threshold. For example, a range access counter for memory address range 301F that exceeds a high access threshold may indicate frequent access to memory component 120C associated with memory address range 301F. Another example of a watermark counter is a low access counter indicating a range access counter among a plurality of range access counters that exceeds a low access threshold. There may be three or more watermark counters, each associated with one of a plurality of access frequencies to a memory component. Each of the three or more watermark counters may be associated with an access threshold that indicates the frequency of access associated with it, i.e., it indicates the amount of range access counters among multiple range access counters that exceed the threshold associated with the watermark counter.

[0062] In some cases, at least one of the multiple statistical counters is implemented in one or more memory tracking circuits 130. In some cases, at least one other of the multiple statistical counters is implemented in one of the memory components 120. In some cases, one of the memory components implementing at least one other statistical counter is the cache memory component of the processing unit 101. In some cases, at least one other of the multiple statistical counters is implemented in another cache memory component connected to one or more of the memory components 120.

[0063] Next, see also Figure 5, which shows a flowchart schematically representing an arbitrary flow of operation 500 for updating statistical counters according to several embodiments. In such embodiments, in 501, one or more memory tracking circuits 130 identify a memory address in a memory access command received in 401. In 502, one or more memory tracking circuits 130 optionally identify a memory address range from a plurality of memory address ranges 301, the memory address range comprising a memory address. For example, a memory command may comprise a memory address within the memory address range 301F. In this example, one or more memory tracking circuits 130 identify the memory address range 301F. Optionally, in 510, one or more memory tracking circuits 130 increment each of a plurality of range access counters associated with the memory address range 301F. When one or more memory tracking circuits 130 include a plurality of local tracking circuits 201, and at least one of a plurality of memory address ranges 301 associated with one or more memory components connected to a local tracking circuit contains the memory address of a memory access command, each of the plurality of local tracking circuits 201 updates at least one statistical counter. For example, when a local tracking circuit 201B identifies that the memory address of a memory access command is within the range of memory addresses 301F associated with a memory component 120C connected to a local tracking circuit 201B, the local tracking circuit 201B may update one or more statistical counters.

[0064] In step 520, one or more memory tracking circuits 130 optionally determine whether each range access counter associated with the memory address range 301F exceeds the low access threshold, and in step 521, one or more memory tracking circuits 130 optionally decrement the low access counter according to the determination that each range access counter associated with the memory address range 301F exceeds the low access threshold. In step 530, one or more memory tracking circuits 130 optionally determine whether each range access counter associated with the memory address range 301F exceeds the high access threshold, and in step 531, one or more memory tracking circuits 130 optionally increment the high access counter according to the determination that each range access counter associated with the memory address range 301F exceeds the high access threshold. When one or more watermark counters comprise three or more watermark counters, one or more tracking circuits 130 may, for each of the three or more watermark counters, determine whether each range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, and, according to the determination that each range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, one or more memory tracking circuits 130 may, increment the watermark counter.

[0065] Next, Figure 4 is referred to again. In some cases, one or more memory tracking circuits 130 perform 401 and 410 while the processing unit 101 executes the software program. In some cases, one or more memory tracking circuits 130 repeat 401 and 410 in each of a plurality of iterations.

[0066] In 420, one or more memory tracking circuits 130 may optionally provide one or more of a plurality of statistical counters to the memory management component 110 for the purpose of mapping the application memory of a software program to the memory component 120. Optionally, one or more memory tracking circuits 130 provide one or more statistical counters while the processing unit 101 executes the software program. Optionally, the memory mapping component 110 maps the application memory to the memory component 120 while the processing unit 101 executes the software program.

[0067] Next, see also Figure 6, which shows an arbitrary flow of operation 600 for memory management according to several embodiments. In such embodiments, in 601, the memory management component 110 performs an analysis of one or more statistical counters. The following are exemplary, non-essential methods for performing the analysis.

[0068] Next, see also Figure 7, which shows a sequence diagram of an arbitrary flow of operation 700 according to several embodiments. In such embodiments, in 701, one or more memory tracking circuits 130 provide one or more watermark counters to the memory management component 110. In some cases, one or more memory tracking circuits 130 provide in 701 a subset of one or more watermark counters, for example, just one of one or more watermark counters. In some cases, one or more watermark counters include high access counters. In some cases, one or more watermark counters include low access counters. In 702, one or more memory tracking circuits 130 perform another analysis comprising one or more watermark counters. According to the results of that other analysis, in 710, the memory management component 110 sends a request to one or more memory tracking circuits 130 to provide, in some cases, in 710, at least one range access counter from a plurality of range access counters. For example, if the result of the alternative analysis indicates that the watermark counter exceeds a frequency threshold, the memory mapping component may require at least one range access counter to identify which of several memory address ranges is accessed most frequently. On the other hand, if the result of the alternative analysis indicates that the watermark counter does not exceed a frequency threshold, the memory mapping component 110 may refuse to perform the alternative analysis and refuse to modify the mapping of the software program's application memory. The alternative analysis may, for example, use one of one or more watermark counters when only one watermark counter is implemented. The alternative analysis may use two or more of one or more watermark counters. If one or more watermark counters include at least one of a low access counter and a high access counter, the alternative analysis may, in some cases, include at least one of a low access counter and a high access counter.

[0069] In response to receiving a request from the memory management component 110, in 711, one or more memory tracking circuits 130 optionally send at least one range access counter to the memory management component 110. In some cases, 710 and 711 are repeated in multiple read iterations. In some cases, in 711, one or more memory tracking circuits 130 send one range access counter to the memory management component 110, causing the memory management component 110 to access one or more range access counters one by one. In some cases, in each execution of 711, one or more memory tracking circuits 130 send a subset of multiple range access counters to the memory management component 110. In some cases, the management component 110 refuses to execute 710 by identifying a termination condition, for example, receiving an amount of range access counters that exceeds a threshold equal to the value of the watermark counter provided in 701.

[0070] Next, see also Figure 6. The memory management component 110 may, depending on the results of the analysis performed in 601, perform one or more memory management tasks, such as mapping the application memory of a software program. Another example of a memory management task is setting up one or more memory tracking circuits 130.

[0071] Next, see also Figure 8, which shows schematic block diagrams of exemplary memory mappings 800 according to several embodiments. In some cases, the application memory of a software program comprises a plurality of application memory areas 801, including, for example, memory application area 801A, memory application area 801B, and memory application area 801C. In some cases, each of the plurality of memory application areas is stored in one of the memory components 120. For example, application memory area 801A may be stored in memory component 120A, application memory area 801B may be stored in memory component 120B, and application memory area 801C may be stored in memory component 120C.

[0072] Next, Figure 6 is referenced again. In 610, in response to the analysis performed in 601 (for example, using method 700), the memory management component 110 may move one or more application memory areas from among the multiple application memory areas 801 from one of the memory components 120 to another of the memory components 120.

[0073] Next, see also Figure 9, which shows a schematic block diagram of another exemplary memory mapping 900 according to several embodiments. In this example, for example, if memory component 120C has higher performance access characteristics than memory component 120A, and the analysis results show high-frequency access to application memory area 801A, the analysis results may cause the memory management component 110 to move application memory area 801A from memory component 120A to memory component 120C. In some cases, the memory management component 110 updates the mapping between application memory and one or more of the multiple memory address ranges 301 in the page table of the operating system executed by the processing unit 101, for example.

[0074] Next, Figure 7 is referred to again. In 721, the memory management component 110 optionally sets one or more watermark thresholds in one or more memory tracking circuits 130, for example, a high watermark threshold or a low watermark threshold. Optionally, in 720, the memory management component 110 performs yet another analysis of one or more statistical counters and performs 721 according to yet another result of the yet another analysis. For example, when a memory component with high-performance access characteristics is not being fully utilized, the memory management component 110 may lower the high watermark threshold. Similarly, when a memory component with high-performance access characteristics is being heavily utilized, the memory management component 110 may raise the high watermark threshold.

[0075] Next, Figure 4 is referred to again. At 430, one or more memory tracking circuits 130 may, in some cases, reset one or more other counters among a plurality of statistical counters. For example, one or more memory tracking circuits 130 may reset statistical counters after providing them to the memory management component 110 at 420. Resetting a counter may mean setting the counter to 0. Resetting a counter may mean setting the counter to an initial value. For example, a low access counter may start with a value equal to the amount of memory components in the memory component 120 and be decremented at 521 for each range access counter that exceeds the low watermark threshold.

[0076] In some cases, one or more memory tracking circuits 130 repeat, in each of a plurality of management iterations, the execution of a plurality of iterations including 401 and 410, the provision of one or more statistical counters in 420, and the resetting of one or more other counters.

[0077] While descriptions of various embodiments are presented for illustrative purposes, they are not exhaustive or limiting to the embodiments disclosed. Many variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments described. The terms used herein have been selected to best describe the principles of the embodiments, practical applications, or technological improvements over technologies found in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

[0078] During the term of this patent application, it is anticipated that many related memory tracking circuits will be developed, and the scope of the term "memory tracking circuit" is intended to a priori include all such new technologies.

[0079] As used herein, the term "about" refers to a range of ±10%.

[0080] The terms "comprises," "comprising," "includes," "including," and "having," and their cognates, all mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of."

[0081] The phrase "consisting essentially of" means that a composition or method may include additional components and / or steps, but only if the additional components and / or steps do not substantially alter the basic and novel properties of the claimed composition or method.

[0082] As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly indicates otherwise. For example, the terms "a compound" or "at least one compound" may include multiple compounds, including mixtures thereof.

[0083] The term “exemplary” is used herein to mean “acting as an example, case, or illustration.” Any embodiment described as “exemplary” should not necessarily be construed as being preferable or advantageous to other embodiments, and / or that should not be excluded from incorporating features from other embodiments.

[0084] The term "optionally" is used herein to mean "provided in some embodiments but not in other embodiments." Any particular embodiment may include more than a few "optional" features, provided that such features do not conflict.

[0085] Throughout this application, various embodiments may be presented in scope form. It should be understood that scope descriptions are for convenience and conciseness only and should not be interpreted as inflexible limitations on the scope of the embodiments. Therefore, scope descriptions should be considered to specifically disclose all possible partial ranges, as well as the individual numbers within those ranges. For example, a scope description such as 1 to 6 should be considered to specifically disclose partial ranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0086] Whenever a numerical range is indicated herein, it is intended to include any of the aforementioned digits (fractions or integers) within the indicated range. The phrases “ranging / ranges between” and “ranging / ranges from” the first indicator to “to” the second indicator are used interchangeably herein and are intended to include the first and second indicated numbers, as well as all fractions and integers between them.

[0087] For clarity, it should be understood that some features of an embodiment described in the context of a separate embodiment may also be provided in combination in a single embodiment. Conversely, for brevity, various features of an embodiment described in the context of a single embodiment may also be provided separately, in any preferred partial combination, or as suitable in any other described embodiment. Some features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiment is inoperable without those elements.

[0088] While embodiments have been described in conjunction with their specific embodiments, it is evident that many alternative, modified, and variant forms will be apparent to those skilled in the art. Therefore, it is intended to encompass all such alternative, modified, and variant forms that fall within the spirit and broad scope of the appended claims.

[0089] It is the applicant's intention that all publications, patents, and patent applications referenced herein should be incorporated herein by reference in their entirety, as if each individual publication, patent, or patent application were specifically and individually referred to as being incorporated herein by reference. Furthermore, no citation or identification of any reference in this application should be construed as an acknowledgment that such reference is available as prior art to the present invention. Section headings should not necessarily be construed as limitations insofar as they are used. Furthermore, any priority documents of this application should be incorporated herein by reference in their entirety. [Explanation of Symbols]

[0090] 100, 200 devices, systems 101 Processing Unit 110 Memory management components, memory mapping components, management components 120, 120A, 120B, 120C Memory Components 130 memory tracking circuit, tracking circuit 201, 201A, 201B Local Tracking Circuit 300 Address Mapping 301 Memory address range 301A, 301B, 301C, 301D, 301E, 301F Memory address range 800, 900 memory mapping 801 Application Memory Area 801A, 801B, 801C: Memory application area, application memory area

Claims

1. A device for executing a software program, Processing unit and Each is connected to the processing unit and comprises at least one memory component mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit, The processing unit and at least one memory tracking circuit connected to the at least one memory component The at least one memory tracking circuit is provided In each of the multiple iterations, in response to receiving a memory access command from the processing unit, at least one of the multiple statistical counters is updated. For the purpose of mapping the application memory of the software program to the at least one memory component, the memory management component is provided with one or more of the plurality of statistical counters. A device configured to perform the following actions.

2. The aforementioned multiple statistical counters At least one watermark counter selected from a group consisting of high-access counters and low-access counters, and Multiple range access counters associated with one of the aforementioned multiple memory address ranges The apparatus according to claim 1, comprising at least one of the following.

3. The apparatus according to claim 1 or 2, wherein at least one of the plurality of statistical counters is implemented within the at least one memory tracking circuit.

4. The apparatus according to any one of claims 1 to 3, wherein at least one or other of the plurality of statistical counters is implemented in a cache memory component connected to one or more of the at least one memory components.

5. The apparatus according to any one of claims 1 to 4, wherein at least one of the plurality of statistical counters is implemented in one of the at least one memory component.

6. The at least one memory tracking circuit comprises a plurality of local tracking circuits, Each of the plurality of local tracking circuits is connected to the processing unit and to one or more of the memory components among the at least one memory component, The apparatus according to any one of claims 1 to 5, wherein each of the plurality of local tracking circuits updates the at least one statistical counter in response to receiving a memory access command when at least one of the plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit comprises a local memory address which is a memory address in a memory address command.

7. The application memory of the software program comprises a plurality of application memory areas, each of which is stored in one of the at least one memory component. The mapping of the application memory by the memory management component is Performing an analysis using the one or more statistical counters described above, In response to the results of the above analysis, move at least one of the plurality of application memory areas from one of the at least one memory component to another of the at least one memory component. The apparatus according to any one of claims 1 to 6, including the apparatus described in any one of claims 1 to 6.

8. The apparatus according to claim 7, wherein the memory mapping component maps the application memory while the processing unit executes the software program.

9. The at least one memory tracking circuit, In each of the 1 or more control iterations, Performing the plurality of iterations, which includes updating at least one of the statistical counters, The memory management component is provided with the one or more statistical counters, Resetting one or more of the aforementioned statistical counters The apparatus according to any one of claims 1 to 8, further configured to perform the following:

10. Updating the aforementioned at least one statistical counter is Identifying the memory address in the aforementioned memory access command, Identifying a memory address range among the plurality of memory address ranges, wherein the memory address range includes the memory address; Incrementing each of the range access counters associated with the memory address range, When each of the aforementioned range access counters exceeds the high access threshold, the high access counter is incremented. The apparatus according to any one of claims 2 to 9, including the apparatus described in any one of claims 2 to 9.

11. The memory management component is provided with one or more statistical counters. To provide the aforementioned at least one watermark counter, In response to a request from the memory management component, provide at least one of the multiple range access counters. Includes, The memory management component, Performing another analysis with at least one watermark counter, In accordance with another result of the aforementioned other analysis, a request is sent to the at least one memory tracking circuit to provide the at least one range access counter. The apparatus according to claim 10, configured to perform the following:

12. The apparatus according to claim 10 or 11, wherein the memory management component is further configured to set at least one of the low access threshold and the high access threshold within the at least one memory tracking circuit.

13. The apparatus according to claim 12, wherein the memory management component sets at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit according to yet another result of yet another analysis comprising one or more statistical counters.

14. The apparatus according to any one of claims 1 to 13, wherein the at least one memory tracking circuit is configured to update the at least one statistical counter and to provide one or more of the plurality of statistical counters while the processing unit executes the software program.

15. The apparatus according to any one of claims 1 to 14, wherein the memory management component comprises a software object executed by the processing unit.

16. The apparatus according to any one of claims 1 to 14, wherein the memory management component comprises the at least one memory tracking circuit and a memory management circuit connected to the at least one memory component.

17. The processing unit is configured to run an operating system, The operating system addresses the at least one memory component using a plurality of operating system memory pages, each having one page size from an identified set of page sizes. The apparatus according to any one of claims 1 to 16, wherein at least one identified memory address range among the plurality of memory address ranges has a range size that is not equal to any of the page sizes of the set of page sizes.

18. A method for managing memory in a device for running one or more software programs, In each of a plurality of iterations, the processing unit and at least one memory tracking circuit connected to at least one memory component connected to the processing unit update at least one of a plurality of statistical counters in response to receiving a memory access command from the processing unit, wherein each of the at least one memory component is mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit. The steps include providing a memory management component with one or more of the plurality of statistical counters for the purpose of mapping the application memory of a software program to the at least one memory component, and Methods that include...

19. A method for memory management components, Steps of receiving one or more statistical counters in each management iteration of one or more management iterations from a processing unit and at least one memory tracking circuit connected to at least one memory component connected to the processing unit, for the purpose of mapping the application memory of a software program to the at least one memory component, wherein each of the at least one memory component is mapped to at least one range of memory addresses from a plurality of memory address ranges of the processing unit. Methods that include...

20. The plurality of statistical counters comprises at least one of a high access counter, a low access counter, and a plurality of range access counters, each associated with one of the plurality of memory address ranges. The step of receiving one or more statistical counters includes the step of receiving at least one of the high access counter and the low access counter, The method described above is The steps include performing an analysis that includes at least one of the low-access counter and the high-access counter, The steps include sending a request to the at least one memory tracking circuit to provide the at least one range access counter, in accordance with the results of other analyses, and The method according to claim 19, further comprising:

21. A software program product for memory management, Non-temporary computer-readable storage medium and In each of one or more management iterations, a program instruction for receiving one or more statistical counters from a processing unit and at least one memory tracking circuit connected to at least one memory component connected to the processing unit, for the purpose of mapping the application memory of a software program to the at least one memory component, wherein each of the at least one memory component is mapped to at least one range of memory addresses from a plurality of memory address ranges of the processing unit, and Equipped with, A software program product in which the program instructions are executed by at least one computerized processor from the non-temporary computer-readable storage medium.

22. A memory tracking circuit comprising multiple statistical counters, wherein the multiple statistical counters are High access counter and Low access counter and Multiple range access counters and Equipped with, When the memory tracking circuit is connected to a processing unit and to at least one memory component, each of which is connected to the processing unit and mapped to at least one range of memory addresses among a plurality of memory address ranges of the processing unit, and when each of the plurality of range access counters is associated with one of the plurality of memory address ranges, In each of the multiple iterations, in response to receiving a memory access command from the processing unit, Identifying the memory address in the aforementioned memory access command, Identifying a memory address range among the plurality of memory address ranges, wherein the memory address range includes the memory address; Incrementing each of the range access counters associated with the memory address range, When each of the aforementioned range access counters exceeds the high access threshold, the high access counter is incremented. For the purpose of mapping the application memory of the software program to the at least one memory component, the memory management component is provided with one or more of the plurality of statistical counters. A memory tracking circuit configured to perform the following actions.

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